ncr53c9xvar.h revision 1.30.2.8
1 /* $NetBSD: ncr53c9xvar.h,v 1.30.2.8 2003/01/07 21:34:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_IC_NCR53C9XVAR_H_ 41 #define _DEV_IC_NCR53C9XVAR_H_ 42 43 /* 44 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. All advertising materials mentioning features or use of this software 55 * must display the following acknowledgement: 56 * This product includes software developed by Peter Galbavy. 57 * 4. The name of the author may not be used to endorse or promote products 58 * derived from this software without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 61 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 62 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 63 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 64 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 65 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 66 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 67 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 68 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 69 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* Set this to 1 for normal debug, or 2 for per-target tracing. */ 73 /* #define NCR53C9X_DEBUG 1 */ 74 75 /* Wide or differential can have 16 targets */ 76 #define NCR_NLUN 8 77 78 #define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */ 79 #define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */ 80 81 #define FREQTOCCF(freq) (((freq + 4) / 5)) 82 83 /* 84 * NCR 53c9x variants. Note, these values are used as indexes into 85 * a table; don't modify them unless you know what you're doing. 86 */ 87 #define NCR_VARIANT_ESP100 0 88 #define NCR_VARIANT_ESP100A 1 89 #define NCR_VARIANT_ESP200 2 90 #define NCR_VARIANT_NCR53C94 3 91 #define NCR_VARIANT_NCR53C96 4 92 #define NCR_VARIANT_ESP406 5 93 #define NCR_VARIANT_FAS408 6 94 #define NCR_VARIANT_FAS216 7 95 #define NCR_VARIANT_AM53C974 8 96 #define NCR_VARIANT_FAS366 9 97 #define NCR_VARIANT_NCR53C90_86C01 10 98 #define NCR_VARIANT_MAX 11 99 100 /* 101 * ECB. Holds additional information for each SCSI command Comments: We 102 * need a separate scsi command block because we may need to overwrite it 103 * with a request sense command. Basicly, we refrain from fiddling with 104 * the scsipi_xfer struct (except do the expected updating of return values). 105 * We'll generally update: xs->{flags,resid,error,sense,status} and 106 * occasionally xs->retries. 107 */ 108 struct ncr53c9x_ecb { 109 TAILQ_ENTRY(ncr53c9x_ecb) chain; 110 struct scsipi_xfer *xs; /* SCSI xfer ctrl block from above */ 111 int flags; 112 #define ECB_ALLOC 0x01 113 #define ECB_READY 0x02 114 #define ECB_SENSE 0x04 115 #define ECB_ABORT 0x40 116 #define ECB_RESET 0x80 117 #define ECB_TENTATIVE_DONE 0x100 118 int timeout; 119 120 struct { 121 u_char msg[3]; /* Selection Id msg and tags */ 122 struct scsi_generic cmd; /* SCSI command block */ 123 } cmd; 124 char *daddr; /* Saved data pointer */ 125 int clen; /* Size of command in cmd.cmd */ 126 int dleft; /* Residue */ 127 u_char stat; /* SCSI status byte */ 128 u_char tag[2]; /* TAG bytes */ 129 u_char pad[1]; 130 131 #if NCR53C9X_DEBUG > 1 132 char trace[1000]; 133 #endif 134 }; 135 #if NCR53C9X_DEBUG > 1 136 #define ECB_TRACE(ecb, msg, a, b) do { \ 137 const char *f = "[" msg "]"; \ 138 int n = strlen((ecb)->trace); \ 139 if (n < (sizeof((ecb)->trace)-100)) \ 140 sprintf((ecb)->trace + n, f, a, b); \ 141 } while(0) 142 #else 143 #define ECB_TRACE(ecb, msg, a, b) 144 #endif 145 146 /* 147 * Some info about each (possible) target and LUN on the SCSI bus. 148 * 149 * SCSI I and II devices can have up to 8 LUNs, each with up to 256 150 * outstanding tags. SCSI III devices have 64-bit LUN identifiers 151 * that can be sparsely allocated. 152 * 153 * Since SCSI II devices can have up to 8 LUNs, we use an array 154 * of 8 pointers to ncr53c9x_linfo structures for fast lookup. 155 * Longer LUNs need to traverse the linked list. 156 */ 157 158 struct ncr53c9x_linfo { 159 int64_t lun; 160 LIST_ENTRY(ncr53c9x_linfo) link; 161 time_t last_used; 162 unsigned char used; /* # slots in use */ 163 unsigned char avail; /* where to start scanning */ 164 unsigned char busy; 165 struct ncr53c9x_ecb *untagged; 166 struct ncr53c9x_ecb *queued[256]; 167 }; 168 169 struct ncr53c9x_tinfo { 170 int cmds; /* # of commands processed */ 171 int dconns; /* # of disconnects */ 172 int touts; /* # of timeouts */ 173 int perrs; /* # of parity errors */ 174 int senses; /* # of request sense commands sent */ 175 u_char flags; 176 #define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */ 177 #define T_SYNCMODE 0x08 /* SYNC mode has been negotiated */ 178 #define T_SYNCHOFF 0x10 /* SYNC mode for is permanently off */ 179 #define T_RSELECTOFF 0x20 /* RE-SELECT mode is off */ 180 #define T_TAG 0x40 /* Turn on TAG QUEUEs */ 181 #define T_WIDE 0x80 /* Negotiate wide options */ 182 #define T_WDTRSENT 0x04 /* WDTR message has been sent to */ 183 u_char period; /* Period suggestion */ 184 u_char offset; /* Offset suggestion */ 185 u_char cfg3; /* per target config 3 */ 186 u_char nextag; /* Next available tag */ 187 u_char width; /* width suggesion */ 188 LIST_HEAD(lun_list, ncr53c9x_linfo) luns; 189 struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */ 190 }; 191 192 /* Look up a lun in a tinfo */ 193 #define TINFO_LUN(t, l) ( \ 194 (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \ 195 ? ((t)->lun[(l)]) \ 196 : ncr53c9x_lunsearch((t), (int64_t)(l)) \ 197 ) 198 199 /* Register a linenumber (for debugging) */ 200 #define LOGLINE(p) 201 202 #define NCR_SHOWECBS 0x01 203 #define NCR_SHOWINTS 0x02 204 #define NCR_SHOWCMDS 0x04 205 #define NCR_SHOWMISC 0x08 206 #define NCR_SHOWTRAC 0x10 207 #define NCR_SHOWSTART 0x20 208 #define NCR_SHOWPHASE 0x40 209 #define NCR_SHOWDMA 0x80 210 #define NCR_SHOWCCMDS 0x100 211 #define NCR_SHOWMSGS 0x200 212 213 #ifdef NCR53C9X_DEBUG 214 extern int ncr53c9x_debug; 215 #define NCR_ECBS(str) \ 216 do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0) 217 #define NCR_MISC(str) \ 218 do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0) 219 #define NCR_INTS(str) \ 220 do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0) 221 #define NCR_TRACE(str) \ 222 do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0) 223 #define NCR_CMDS(str) \ 224 do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0) 225 #define NCR_START(str) \ 226 do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0) 227 #define NCR_PHASE(str) \ 228 do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0) 229 #define NCR_DMA(str) \ 230 do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0) 231 #define NCR_MSGS(str) \ 232 do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0) 233 #else 234 #define NCR_ECBS(str) 235 #define NCR_MISC(str) 236 #define NCR_INTS(str) 237 #define NCR_TRACE(str) 238 #define NCR_CMDS(str) 239 #define NCR_START(str) 240 #define NCR_PHASE(str) 241 #define NCR_DMA(str) 242 #define NCR_MSGS(str) 243 #endif 244 245 #define NCR_MAX_MSG_LEN 8 246 247 struct ncr53c9x_softc; 248 249 /* 250 * Function switch used as glue to MD code. 251 */ 252 struct ncr53c9x_glue { 253 /* Mandatory entry points. */ 254 u_char (*gl_read_reg)(struct ncr53c9x_softc *, int); 255 void (*gl_write_reg)(struct ncr53c9x_softc *, int, u_char); 256 int (*gl_dma_isintr)(struct ncr53c9x_softc *); 257 void (*gl_dma_reset)(struct ncr53c9x_softc *); 258 int (*gl_dma_intr)(struct ncr53c9x_softc *); 259 int (*gl_dma_setup)(struct ncr53c9x_softc *, 260 caddr_t *, size_t *, int, size_t *); 261 void (*gl_dma_go)(struct ncr53c9x_softc *); 262 void (*gl_dma_stop)(struct ncr53c9x_softc *); 263 int (*gl_dma_isactive)(struct ncr53c9x_softc *); 264 265 /* Optional entry points. */ 266 void (*gl_clear_latched_intr)(struct ncr53c9x_softc *); 267 }; 268 269 struct ncr53c9x_softc { 270 struct device sc_dev; /* us as a device */ 271 272 struct evcnt sc_intrcnt; /* intr count */ 273 struct scsipi_adapter sc_adapter; /* out scsipi adapter */ 274 struct scsipi_channel sc_channel; /* our scsipi channel */ 275 struct device *sc_child; /* attached scsibus, if any */ 276 struct callout sc_watchdog; /* periodic timer */ 277 278 struct ncr53c9x_glue *sc_glue; /* glue to MD code */ 279 280 int sc_cfflags; /* Copy of config flags */ 281 282 /* register defaults */ 283 u_char sc_cfg1; /* Config 1 */ 284 u_char sc_cfg2; /* Config 2, not ESP100 */ 285 u_char sc_cfg3; /* Config 3, ESP200,FAS */ 286 u_char sc_cfg3_fscsi; /* Chip-specific FSCSI bit */ 287 u_char sc_cfg4; /* Config 4, only ESP200 */ 288 u_char sc_cfg5; /* Config 5, only ESP200 */ 289 u_char sc_ccf; /* Clock Conversion */ 290 u_char sc_timeout; 291 292 /* register copies, see espreadregs() */ 293 u_char sc_espintr; 294 u_char sc_espstat; 295 u_char sc_espstep; 296 u_char sc_espstat2; 297 u_char sc_espfflags; 298 299 /* Lists of command blocks */ 300 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) 301 ready_list; 302 303 struct ncr53c9x_ecb *sc_nexus; /* Current command */ 304 int sc_ntarg; 305 struct ncr53c9x_tinfo *sc_tinfo; 306 307 /* Data about the current nexus (updated for every cmd switch) */ 308 caddr_t sc_dp; /* Current data pointer */ 309 ssize_t sc_dleft; /* Data left to transfer */ 310 311 /* Adapter state */ 312 int sc_phase; /* Copy of what bus phase we are in */ 313 int sc_prevphase; /* Copy of what bus phase we were in */ 314 u_char sc_state; /* State applicable to the adapter */ 315 u_char sc_flags; /* See below */ 316 u_char sc_selid; 317 u_char sc_lastcmd; 318 319 /* Message stuff */ 320 u_short sc_msgify; /* IDENTIFY message associated with this nexus */ 321 u_short sc_msgout; /* What message is on its way out? */ 322 u_short sc_msgpriq; /* One or more messages to send (encoded) */ 323 u_short sc_msgoutq; /* What messages have been sent so far? */ 324 325 u_char *sc_omess; /* MSGOUT buffer */ 326 caddr_t sc_omp; /* Message pointer (for multibyte messages) */ 327 size_t sc_omlen; 328 u_char *sc_imess; /* MSGIN buffer */ 329 caddr_t sc_imp; /* Message pointer (for multibyte messages) */ 330 size_t sc_imlen; 331 332 caddr_t sc_cmdp; /* Command pointer (for DMAed commands) */ 333 size_t sc_cmdlen; /* Size of command in transit */ 334 335 /* Hardware attributes */ 336 int sc_freq; /* SCSI bus frequency in MHz */ 337 int sc_id; /* Our SCSI id */ 338 int sc_rev; /* Chip revision */ 339 int sc_features; /* Chip features */ 340 int sc_minsync; /* Minimum sync period / 4 */ 341 int sc_maxxfer; /* Maximum transfer size */ 342 }; 343 344 /* values for sc_state */ 345 #define NCR_IDLE 1 /* waiting for something to do */ 346 #define NCR_SELECTING 2 /* SCSI command is arbiting */ 347 #define NCR_RESELECTED 3 /* Has been reselected */ 348 #define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */ 349 #define NCR_CONNECTED 5 /* Actively using the SCSI bus */ 350 #define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */ 351 #define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */ 352 #define NCR_CLEANING 8 353 #define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */ 354 355 /* values for sc_flags */ 356 #define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */ 357 #define NCR_ABORTING 0x02 /* Bailing out */ 358 #define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */ 359 #define NCR_SYNCHNEGO 0x08 /* Synch negotiation in progress. */ 360 #define NCR_ICCS 0x10 /* Expect status phase results */ 361 #define NCR_WAITI 0x20 /* Waiting for non-DMA data to arrive */ 362 #define NCR_ATN 0x40 /* ATN asserted */ 363 #define NCR_EXPECT_ILLCMD 0x80 /* Expect Illegal Command Interrupt */ 364 365 /* values for sc_features */ 366 #define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */ 367 #define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */ 368 #define NCR_F_DMASELECT 0x04 /* can do dmaselect */ 369 #define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */ 370 371 /* values for sc_msgout */ 372 #define SEND_DEV_RESET 0x0001 373 #define SEND_PARITY_ERROR 0x0002 374 #define SEND_INIT_DET_ERR 0x0004 375 #define SEND_REJECT 0x0008 376 #define SEND_IDENTIFY 0x0010 377 #define SEND_ABORT 0x0020 378 #define SEND_WDTR 0x0040 379 #define SEND_SDTR 0x0080 380 #define SEND_TAG 0x0100 381 382 /* SCSI Status codes */ 383 #define ST_MASK 0x3e /* bit 0,6,7 is reserved */ 384 385 /* phase bits */ 386 #define IOI 0x01 387 #define CDI 0x02 388 #define MSGI 0x04 389 390 /* Information transfer phases */ 391 #define DATA_OUT_PHASE (0) 392 #define DATA_IN_PHASE (IOI) 393 #define COMMAND_PHASE (CDI) 394 #define STATUS_PHASE (CDI|IOI) 395 #define MESSAGE_OUT_PHASE (MSGI|CDI) 396 #define MESSAGE_IN_PHASE (MSGI|CDI|IOI) 397 398 #define PHASE_MASK (MSGI|CDI|IOI) 399 400 /* Some pseudo phases for getphase()*/ 401 #define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */ 402 #define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */ 403 #define PSEUDO_PHASE 0x100 /* "pseudo" bit */ 404 405 /* 406 * Macros to read and write the chip's registers. 407 */ 408 #define NCR_READ_REG(sc, reg) \ 409 (*(sc)->sc_glue->gl_read_reg)((sc), (reg)) 410 #define NCR_WRITE_REG(sc, reg, val) \ 411 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val)) 412 413 #ifdef NCR53C9X_DEBUG 414 #define NCRCMD(sc, cmd) do { \ 415 if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \ 416 printf("<CMD:0x%x %d>", (unsigned)cmd, __LINE__); \ 417 sc->sc_lastcmd = cmd; \ 418 NCR_WRITE_REG(sc, NCR_CMD, cmd); \ 419 } while (0) 420 #else 421 #define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd) 422 #endif 423 424 /* 425 * DMA macros for NCR53c9x 426 */ 427 #define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc)) 428 #define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc)) 429 #define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc)) 430 #define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \ 431 (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize)) 432 #define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc)) 433 #define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc)) 434 435 /* 436 * Macro to convert the chip register Clock Per Byte value to 437 * Sunchronous Transfer Period. 438 */ 439 #define ncr53c9x_cpb2stp(sc, cpb) \ 440 ((250 * (cpb)) / (sc)->sc_freq) 441 442 void ncr53c9x_attach __P((struct ncr53c9x_softc *)); 443 int ncr53c9x_detach __P((struct ncr53c9x_softc *, int)); 444 void ncr53c9x_scsipi_request __P((struct scsipi_channel *chan, 445 scsipi_adapter_req_t req, void *)); 446 void ncr53c9x_reset __P((struct ncr53c9x_softc *)); 447 int ncr53c9x_intr __P((void *)); 448 void ncr53c9x_init __P((struct ncr53c9x_softc *, int)); 449 450 #endif /* _DEV_IC_NCR53C9XVAR_H_ */ 451
Indexes created Thu Oct 23 22:10:10 GMT 2025