ncr53c9xvar.h revision 1.36
1 /* $NetBSD: ncr53c9xvar.h,v 1.36 2002/08/26 05:14:47 petrov Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Peter Galbavy. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* Set this to 1 for normal debug, or 2 for per-target tracing. */ 70 #define NCR53C9X_DEBUG 1 71 72 /* Wide or differential can have 16 targets */ 73 #define NCR_NTARG 8 74 #define NCR_NLUN 8 75 76 #define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */ 77 #define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */ 78 79 #define FREQTOCCF(freq) (((freq + 4) / 5)) 80 81 /* 82 * NCR 53c9x variants. Note, these values are used as indexes into 83 * a table; don't modify them unless you know what you're doing. 84 */ 85 #define NCR_VARIANT_ESP100 0 86 #define NCR_VARIANT_ESP100A 1 87 #define NCR_VARIANT_ESP200 2 88 #define NCR_VARIANT_NCR53C94 3 89 #define NCR_VARIANT_NCR53C96 4 90 #define NCR_VARIANT_ESP406 5 91 #define NCR_VARIANT_FAS408 6 92 #define NCR_VARIANT_FAS216 7 93 #define NCR_VARIANT_AM53C974 8 94 #define NCR_VARIANT_FAS366 9 95 #define NCR_VARIANT_NCR53C90_86C01 10 96 #define NCR_VARIANT_MAX 11 97 98 /* 99 * ECB. Holds additional information for each SCSI command Comments: We 100 * need a separate scsi command block because we may need to overwrite it 101 * with a request sense command. Basicly, we refrain from fiddling with 102 * the scsipi_xfer struct (except do the expected updating of return values). 103 * We'll generally update: xs->{flags,resid,error,sense,status} and 104 * occasionally xs->retries. 105 */ 106 struct ncr53c9x_ecb { 107 TAILQ_ENTRY(ncr53c9x_ecb) chain; 108 struct scsipi_xfer *xs; /* SCSI xfer ctrl block from above */ 109 int flags; 110 #define ECB_ALLOC 0x01 111 #define ECB_READY 0x02 112 #define ECB_SENSE 0x04 113 #define ECB_ABORT 0x40 114 #define ECB_RESET 0x80 115 #define ECB_TENTATIVE_DONE 0x100 116 int timeout; 117 118 struct { 119 u_char msg[3]; /* Selection Id msg and tags */ 120 struct scsi_generic cmd; /* SCSI command block */ 121 } cmd; 122 char *daddr; /* Saved data pointer */ 123 int clen; /* Size of command in cmd.cmd */ 124 int dleft; /* Residue */ 125 u_char stat; /* SCSI status byte */ 126 u_char tag[2]; /* TAG bytes */ 127 u_char pad[1]; 128 129 #if NCR53C9X_DEBUG > 1 130 char trace[1000]; 131 #endif 132 }; 133 #if NCR53C9X_DEBUG > 1 134 #define ECB_TRACE(ecb, msg, a, b) do { \ 135 const char *f = "[" msg "]"; \ 136 int n = strlen((ecb)->trace); \ 137 if (n < (sizeof((ecb)->trace)-100)) \ 138 sprintf((ecb)->trace + n, f, a, b); \ 139 } while(0) 140 #else 141 #define ECB_TRACE(ecb, msg, a, b) 142 #endif 143 144 /* 145 * Some info about each (possible) target and LUN on the SCSI bus. 146 * 147 * SCSI I and II devices can have up to 8 LUNs, each with up to 256 148 * outstanding tags. SCSI III devices have 64-bit LUN identifiers 149 * that can be sparsely allocated. 150 * 151 * Since SCSI II devices can have up to 8 LUNs, we use an array 152 * of 8 pointers to ncr53c9x_linfo structures for fast lookup. 153 * Longer LUNs need to traverse the linked list. 154 */ 155 156 struct ncr53c9x_linfo { 157 int64_t lun; 158 LIST_ENTRY(ncr53c9x_linfo) link; 159 time_t last_used; 160 unsigned char used; /* # slots in use */ 161 unsigned char avail; /* where to start scanning */ 162 unsigned char busy; 163 struct ncr53c9x_ecb *untagged; 164 struct ncr53c9x_ecb *queued[256]; 165 }; 166 167 struct ncr53c9x_tinfo { 168 int cmds; /* # of commands processed */ 169 int dconns; /* # of disconnects */ 170 int touts; /* # of timeouts */ 171 int perrs; /* # of parity errors */ 172 int senses; /* # of request sense commands sent */ 173 u_char flags; 174 #define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */ 175 #define T_SYNCMODE 0x08 /* SYNC mode has been negotiated */ 176 #define T_SYNCHOFF 0x10 /* SYNC mode for is permanently off */ 177 #define T_RSELECTOFF 0x20 /* RE-SELECT mode is off */ 178 #define T_TAG 0x40 /* Turn on TAG QUEUEs */ 179 #define T_WIDE 0x80 /* Negotiate wide options */ 180 u_char period; /* Period suggestion */ 181 u_char offset; /* Offset suggestion */ 182 u_char cfg3; /* per target config 3 */ 183 u_char nextag; /* Next available tag */ 184 u_char width; /* width suggesion */ 185 LIST_HEAD(lun_list, ncr53c9x_linfo) luns; 186 struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */ 187 }; 188 189 /* Look up a lun in a tinfo */ 190 #define TINFO_LUN(t, l) ( \ 191 (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \ 192 ? ((t)->lun[(l)]) \ 193 : ncr53c9x_lunsearch((t), (int64_t)(l)) \ 194 ) 195 196 /* Register a linenumber (for debugging) */ 197 #define LOGLINE(p) 198 199 #define NCR_SHOWECBS 0x01 200 #define NCR_SHOWINTS 0x02 201 #define NCR_SHOWCMDS 0x04 202 #define NCR_SHOWMISC 0x08 203 #define NCR_SHOWTRAC 0x10 204 #define NCR_SHOWSTART 0x20 205 #define NCR_SHOWPHASE 0x40 206 #define NCR_SHOWDMA 0x80 207 #define NCR_SHOWCCMDS 0x100 208 #define NCR_SHOWMSGS 0x200 209 210 #ifdef NCR53C9X_DEBUG 211 extern int ncr53c9x_debug; 212 #define NCR_ECBS(str) \ 213 do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0) 214 #define NCR_MISC(str) \ 215 do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0) 216 #define NCR_INTS(str) \ 217 do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0) 218 #define NCR_TRACE(str) \ 219 do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0) 220 #define NCR_CMDS(str) \ 221 do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0) 222 #define NCR_START(str) \ 223 do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0) 224 #define NCR_PHASE(str) \ 225 do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0) 226 #define NCR_DMA(str) \ 227 do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0) 228 #define NCR_MSGS(str) \ 229 do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0) 230 #else 231 #define NCR_ECBS(str) 232 #define NCR_MISC(str) 233 #define NCR_INTS(str) 234 #define NCR_TRACE(str) 235 #define NCR_CMDS(str) 236 #define NCR_START(str) 237 #define NCR_PHASE(str) 238 #define NCR_DMA(str) 239 #define NCR_MSGS(str) 240 #endif 241 242 #define NCR_MAX_MSG_LEN 8 243 244 struct ncr53c9x_softc; 245 246 /* 247 * Function switch used as glue to MD code. 248 */ 249 struct ncr53c9x_glue { 250 /* Mandatory entry points. */ 251 u_char (*gl_read_reg)(struct ncr53c9x_softc *, int); 252 void (*gl_write_reg)(struct ncr53c9x_softc *, int, u_char); 253 int (*gl_dma_isintr)(struct ncr53c9x_softc *); 254 void (*gl_dma_reset)(struct ncr53c9x_softc *); 255 int (*gl_dma_intr)(struct ncr53c9x_softc *); 256 int (*gl_dma_setup)(struct ncr53c9x_softc *, 257 caddr_t *, size_t *, int, size_t *); 258 void (*gl_dma_go)(struct ncr53c9x_softc *); 259 void (*gl_dma_stop)(struct ncr53c9x_softc *); 260 int (*gl_dma_isactive)(struct ncr53c9x_softc *); 261 262 /* Optional entry points. */ 263 void (*gl_clear_latched_intr)(struct ncr53c9x_softc *); 264 }; 265 266 struct ncr53c9x_softc { 267 struct device sc_dev; /* us as a device */ 268 269 struct evcnt sc_intrcnt; /* intr count */ 270 struct scsipi_adapter sc_adapter; /* out scsipi adapter */ 271 struct scsipi_channel sc_channel; /* our scsipi channel */ 272 struct device *sc_child; /* attached scsibus, if any */ 273 struct callout sc_watchdog; /* periodic timer */ 274 275 struct ncr53c9x_glue *sc_glue; /* glue to MD code */ 276 277 int sc_cfflags; /* Copy of config flags */ 278 279 /* register defaults */ 280 u_char sc_cfg1; /* Config 1 */ 281 u_char sc_cfg2; /* Config 2, not ESP100 */ 282 u_char sc_cfg3; /* Config 3, only ESP200 */ 283 u_char sc_cfg3_fscsi; /* Chip-specific FSCSI bit */ 284 u_char sc_cfg4; /* Config 3, only ESP200 */ 285 u_char sc_cfg5; /* Config 3, only ESP200 */ 286 u_char sc_ccf; /* Clock Conversion */ 287 u_char sc_timeout; 288 289 /* register copies, see espreadregs() */ 290 u_char sc_espintr; 291 u_char sc_espstat; 292 u_char sc_espstep; 293 u_char sc_espstat2; 294 u_char sc_espfflags; 295 296 /* Lists of command blocks */ 297 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) 298 ready_list; 299 300 struct ncr53c9x_ecb *sc_nexus; /* Current command */ 301 struct ncr53c9x_tinfo sc_tinfo[NCR_NTARG]; 302 303 /* Data about the current nexus (updated for every cmd switch) */ 304 caddr_t sc_dp; /* Current data pointer */ 305 ssize_t sc_dleft; /* Data left to transfer */ 306 307 /* Adapter state */ 308 int sc_phase; /* Copy of what bus phase we are in */ 309 int sc_prevphase; /* Copy of what bus phase we were in */ 310 u_char sc_state; /* State applicable to the adapter */ 311 u_char sc_flags; /* See below */ 312 u_char sc_selid; 313 u_char sc_lastcmd; 314 315 /* Message stuff */ 316 u_short sc_msgify; /* IDENTIFY message associated with this nexus */ 317 u_short sc_msgout; /* What message is on its way out? */ 318 u_short sc_msgpriq; /* One or more messages to send (encoded) */ 319 u_short sc_msgoutq; /* What messages have been sent so far? */ 320 321 u_char *sc_omess; /* MSGOUT buffer */ 322 caddr_t sc_omp; /* Message pointer (for multibyte messages) */ 323 size_t sc_omlen; 324 u_char *sc_imess; /* MSGIN buffer */ 325 caddr_t sc_imp; /* Message pointer (for multibyte messages) */ 326 size_t sc_imlen; 327 328 caddr_t sc_cmdp; /* Command pointer (for DMAed commands) */ 329 size_t sc_cmdlen; /* Size of command in transit */ 330 331 /* Hardware attributes */ 332 int sc_freq; /* SCSI bus frequency in MHz */ 333 int sc_id; /* Our SCSI id */ 334 int sc_rev; /* Chip revision */ 335 int sc_features; /* Chip features */ 336 int sc_minsync; /* Minimum sync period / 4 */ 337 int sc_maxxfer; /* Maximum transfer size */ 338 }; 339 340 /* values for sc_state */ 341 #define NCR_IDLE 1 /* waiting for something to do */ 342 #define NCR_SELECTING 2 /* SCSI command is arbiting */ 343 #define NCR_RESELECTED 3 /* Has been reselected */ 344 #define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */ 345 #define NCR_CONNECTED 5 /* Actively using the SCSI bus */ 346 #define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */ 347 #define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */ 348 #define NCR_CLEANING 8 349 #define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */ 350 351 /* values for sc_flags */ 352 #define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */ 353 #define NCR_ABORTING 0x02 /* Bailing out */ 354 #define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */ 355 #define NCR_SYNCHNEGO 0x08 /* Synch negotiation in progress. */ 356 #define NCR_ICCS 0x10 /* Expect status phase results */ 357 #define NCR_WAITI 0x20 /* Waiting for non-DMA data to arrive */ 358 #define NCR_ATN 0x40 /* ATN asserted */ 359 #define NCR_EXPECT_ILLCMD 0x80 /* Expect Illegal Command Interrupt */ 360 361 /* values for sc_features */ 362 #define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */ 363 #define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */ 364 #define NCR_F_DMASELECT 0x04 /* can do dmaselect */ 365 #define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */ 366 367 /* values for sc_msgout */ 368 #define SEND_DEV_RESET 0x0001 369 #define SEND_PARITY_ERROR 0x0002 370 #define SEND_INIT_DET_ERR 0x0004 371 #define SEND_REJECT 0x0008 372 #define SEND_IDENTIFY 0x0010 373 #define SEND_ABORT 0x0020 374 #define SEND_WDTR 0x0040 375 #define SEND_SDTR 0x0080 376 #define SEND_TAG 0x0100 377 378 /* SCSI Status codes */ 379 #define ST_MASK 0x3e /* bit 0,6,7 is reserved */ 380 381 /* phase bits */ 382 #define IOI 0x01 383 #define CDI 0x02 384 #define MSGI 0x04 385 386 /* Information transfer phases */ 387 #define DATA_OUT_PHASE (0) 388 #define DATA_IN_PHASE (IOI) 389 #define COMMAND_PHASE (CDI) 390 #define STATUS_PHASE (CDI|IOI) 391 #define MESSAGE_OUT_PHASE (MSGI|CDI) 392 #define MESSAGE_IN_PHASE (MSGI|CDI|IOI) 393 394 #define PHASE_MASK (MSGI|CDI|IOI) 395 396 /* Some pseudo phases for getphase()*/ 397 #define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */ 398 #define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */ 399 #define PSEUDO_PHASE 0x100 /* "pseudo" bit */ 400 401 /* 402 * Macros to read and write the chip's registers. 403 */ 404 #define NCR_READ_REG(sc, reg) \ 405 (*(sc)->sc_glue->gl_read_reg)((sc), (reg)) 406 #define NCR_WRITE_REG(sc, reg, val) \ 407 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val)) 408 409 #ifdef NCR53C9X_DEBUG 410 #define NCRCMD(sc, cmd) do { \ 411 if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \ 412 printf("<CMD:0x%x %d>", (unsigned)cmd, __LINE__); \ 413 sc->sc_lastcmd = cmd; \ 414 NCR_WRITE_REG(sc, NCR_CMD, cmd); \ 415 } while (0) 416 #else 417 #define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd) 418 #endif 419 420 /* 421 * DMA macros for NCR53c9x 422 */ 423 #define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc)) 424 #define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc)) 425 #define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc)) 426 #define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \ 427 (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize)) 428 #define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc)) 429 #define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc)) 430 431 /* 432 * Macro to convert the chip register Clock Per Byte value to 433 * Sunchronous Transfer Period. 434 */ 435 #define ncr53c9x_cpb2stp(sc, cpb) \ 436 ((250 * (cpb)) / (sc)->sc_freq) 437 438 void ncr53c9x_attach __P((struct ncr53c9x_softc *)); 439 int ncr53c9x_detach __P((struct ncr53c9x_softc *, int)); 440 void ncr53c9x_scsipi_request __P((struct scsipi_channel *chan, 441 scsipi_adapter_req_t req, void *)); 442 void ncr53c9x_reset __P((struct ncr53c9x_softc *)); 443 int ncr53c9x_intr __P((void *)); 444 void ncr53c9x_init __P((struct ncr53c9x_softc *, int)); 445
Indexes created Sat Oct 25 16:10:12 GMT 2025