ninjaata32.c revision 1.1.4.2
1 /* $Id: ninjaata32.c,v 1.1.4.2 2006/09/09 02:50:02 rpaulo Exp $ */ 2 3 /* 4 * Copyright (c) 2006 ITOH Yasufumi <itohy (at) NetBSD.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: ninjaata32.c,v 1.1.4.2 2006/09/09 02:50:02 rpaulo Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 36 #include <machine/bus.h> 37 #include <machine/intr.h> 38 39 #include <uvm/uvm_extern.h> 40 41 #include <dev/ata/atavar.h> 42 #include <dev/ic/wdcreg.h> 43 #include <dev/ic/wdcvar.h> 44 45 #include <dev/ic/ninjaata32reg.h> 46 #include <dev/ic/ninjaata32var.h> 47 48 #ifdef NJATA32_DEBUG 49 #define DPRINTF(x) printf x 50 #else 51 #define DPRINTF(x) 52 #endif 53 54 static void njata32_init(struct njata32_softc *, int nosleep); 55 static void njata32_irqack(struct ata_channel *); 56 static void njata32_clearirq(struct ata_channel *, int); 57 static void njata32_setup_channel(struct ata_channel *); 58 static int njata32_dma_init(void *, int channel, int drive, 59 void *databuf, size_t datalen, int flags); 60 static void njata32_piobm_start(void *, int channel, int drive, int skip, 61 int xferlen, int flags); 62 static int njata32_dma_finish(void *, int channel, int drive, int force); 63 static void njata32_piobm_done(void *, int channel, int drive); 64 65 #if 0 /* ATA DMA is currently unused */ 66 static const uint8_t njata32_timing_dma[NJATA32_MODE_MAX_DMA + 1] = { 67 NJATA32_TIMING_DMA0, NJATA32_TIMING_DMA1, NJATA32_TIMING_DMA2 68 }; 69 #endif 70 static const uint8_t njata32_timing_pio[NJATA32_MODE_MAX_PIO + 1] = { 71 NJATA32_TIMING_PIO0, NJATA32_TIMING_PIO1, NJATA32_TIMING_PIO2, 72 NJATA32_TIMING_PIO3, NJATA32_TIMING_PIO4 73 }; 74 75 static void 76 njata32_init(sc, nosleep) 77 struct njata32_softc *sc; 78 int nosleep; /* can't sleep (during cold boot and in interrupt) */ 79 { 80 81 /* disable interrupts */ 82 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 83 NJATA32_REG_IRQ_SELECT, 0); 84 85 /* bus reset */ 86 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS, 87 NJATA32_AS_WAIT0 | NJATA32_AS_BUS_RESET); 88 if (nosleep) 89 delay(50000); 90 else 91 tsleep(sc, PRIBIO, "njaini", mstohz(50)); 92 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS, 93 NJATA32_AS_WAIT0); 94 95 /* initial transfer speed */ 96 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 97 NJATA32_REG_TIMING, NJATA32_TIMING_PIO0); 98 99 /* setup busmaster mode */ 100 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_IOBM, 101 NJATA32_IOBM_DEFAULT); 102 103 /* enable interrupts */ 104 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 105 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER | NJATA32_IRQ_DEV); 106 } 107 108 void 109 njata32_attach(sc) 110 struct njata32_softc *sc; 111 { 112 bus_addr_t dmaaddr; 113 int i, devno, error; 114 struct wdc_regs *wdr; 115 116 /* 117 * allocate DMA resource 118 */ 119 if ((error = bus_dmamem_alloc(sc->sc_dmat, 120 sizeof(struct njata32_dma_page), PAGE_SIZE, 0, 121 &sc->sc_sgt_seg, 1, &sc->sc_sgt_nsegs, BUS_DMA_NOWAIT)) != 0) { 122 printf("%s: unable to allocate sgt page, error = %d\n", 123 NJATA32NAME(sc), error); 124 return; 125 } 126 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_sgt_seg, 127 sc->sc_sgt_nsegs, sizeof(struct njata32_dma_page), 128 (caddr_t *)&sc->sc_sgtpg, 129 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 130 printf("%s: unable to map sgt page, error = %d\n", 131 NJATA32NAME(sc), error); 132 goto fail1; 133 } 134 if ((error = bus_dmamap_create(sc->sc_dmat, 135 sizeof(struct njata32_dma_page), 1, 136 sizeof(struct njata32_dma_page), 0, BUS_DMA_NOWAIT, 137 &sc->sc_dmamap_sgt)) != 0) { 138 printf("%s: unable to create sgt DMA map, error = %d\n", 139 NJATA32NAME(sc), error); 140 goto fail2; 141 } 142 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_sgt, 143 sc->sc_sgtpg, sizeof(struct njata32_dma_page), 144 NULL, BUS_DMA_NOWAIT)) != 0) { 145 printf("%s: unable to load sgt DMA map, error = %d\n", 146 NJATA32NAME(sc), error); 147 goto fail3; 148 } 149 150 dmaaddr = sc->sc_dmamap_sgt->dm_segs[0].ds_addr; 151 152 for (devno = 0; devno < NJATA32_NUM_DEV; devno++) { 153 sc->sc_dev[devno].d_sgt = sc->sc_sgtpg->dp_sg[devno]; 154 sc->sc_dev[devno].d_sgt_dma = dmaaddr + 155 offsetof(struct njata32_dma_page, dp_sg[devno]); 156 157 error = bus_dmamap_create(sc->sc_dmat, 158 NJATA32_MAX_XFER, /* max total map size */ 159 NJATA32_NUM_SG, /* max number of segments */ 160 NJATA32_SGT_MAXSEGLEN, /* max size of a segment */ 161 0, /* boundary */ 162 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 163 &sc->sc_dev[devno].d_dmamap_xfer); 164 if (error) { 165 printf("%s: failed to create DMA map (error = %d)\n", 166 NJATA32NAME(sc), error); 167 goto fail4; 168 } 169 } 170 171 /* device properties */ 172 sc->sc_wdcdev.sc_atac.atac_cap = 173 ATAC_CAP_DATA16 | ATAC_CAP_DATA32 | ATAC_CAP_PIOBM; 174 sc->sc_wdcdev.irqack = njata32_irqack; 175 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_wdc_chanarray; 176 sc->sc_wdcdev.sc_atac.atac_nchannels = NJATA32_NCHAN; /* 1 */ 177 sc->sc_wdcdev.sc_atac.atac_pio_cap = NJATA32_MODE_MAX_PIO; 178 #if 0 /* ATA DMA is currently unused */ 179 sc->sc_wdcdev.sc_atac.atac_dma_cap = NJATA32_MODE_MAX_DMA; 180 #endif 181 sc->sc_wdcdev.sc_atac.atac_set_modes = njata32_setup_channel; 182 183 /* DMA control functions */ 184 sc->sc_wdcdev.dma_arg = sc; 185 sc->sc_wdcdev.dma_init = njata32_dma_init; 186 sc->sc_wdcdev.piobm_start = njata32_piobm_start; 187 sc->sc_wdcdev.dma_finish = njata32_dma_finish; 188 sc->sc_wdcdev.piobm_done = njata32_piobm_done; 189 190 sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_EXTRA_RESETS; 191 192 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs; 193 194 /* only one channel */ 195 sc->sc_wdc_chanarray[0] = &sc->sc_ch[0].ch_ata_channel; 196 sc->sc_ch[0].ch_ata_channel.ch_channel = 0; 197 sc->sc_ch[0].ch_ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 198 sc->sc_ch[0].ch_ata_channel.ch_queue = &sc->sc_wdc_chqueue; 199 sc->sc_ch[0].ch_ata_channel.ch_ndrive = 2; /* max number of drives */ 200 201 /* map ATA registers */ 202 for (i = 0; i < WDC_NREG; i++) { 203 if (bus_space_subregion(NJATA32_REGT(sc), NJATA32_REGH(sc), 204 NJATA32_OFFSET_WDCREGS + i, 205 i == wd_data ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 206 aprint_error("%s: couldn't subregion cmd regs\n", 207 NJATA32NAME(sc)); 208 goto fail4; 209 } 210 } 211 wdc_init_shadow_regs(&sc->sc_ch[0].ch_ata_channel); 212 wdr->data32iot = NJATA32_REGT(sc); 213 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 214 215 /* map ATA ctl reg */ 216 wdr->ctl_iot = NJATA32_REGT(sc); 217 if (bus_space_subregion(NJATA32_REGT(sc), NJATA32_REGH(sc), 218 NJATA32_REG_WD_ALTSTATUS, 1, &wdr->ctl_ioh) != 0) { 219 aprint_error("%s: couldn't subregion ctl regs\n", 220 NJATA32NAME(sc)); 221 goto fail4; 222 } 223 224 sc->sc_flags |= NJATA32_CMDPG_MAPPED; 225 226 /* use flags value as busmaster wait */ 227 if ((sc->sc_bmwait = 228 device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 229 (NJATA32_BM_WAIT_MASK >> NJATA32_BM_WAIT_SHIFT)) > 0) 230 aprint_normal("%s: busmaster wait = %d\n", 231 NJATA32NAME(sc), sc->sc_bmwait); 232 233 njata32_init(sc, cold); 234 235 wdcattach(&sc->sc_ch[0].ch_ata_channel); 236 237 return; 238 239 /* 240 * cleanup 241 */ 242 fail4: while (--devno >= 0) { 243 bus_dmamap_destroy(sc->sc_dmat, 244 sc->sc_dev[devno].d_dmamap_xfer); 245 } 246 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_sgt); 247 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_sgt); 248 fail2: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_sgtpg, 249 sizeof(struct njata32_dma_page)); 250 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_sgt_seg, sc->sc_sgt_nsegs); 251 } 252 253 int 254 njata32_detach(sc, flags) 255 struct njata32_softc *sc; 256 int flags; 257 { 258 int rv, devno; 259 260 if (sc->sc_flags & NJATA32_CMDPG_MAPPED) { 261 if ((rv = wdcdetach(&sc->sc_wdcdev.sc_atac.atac_dev, flags))) 262 return rv; 263 264 /* free DMA resource */ 265 for (devno = 0; devno < NJATA32_NUM_DEV; devno++) { 266 bus_dmamap_destroy(sc->sc_dmat, 267 sc->sc_dev[devno].d_dmamap_xfer); 268 } 269 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_sgt); 270 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_sgt); 271 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_sgtpg, 272 sizeof(struct njata32_dma_page)); 273 bus_dmamem_free(sc->sc_dmat, &sc->sc_sgt_seg, sc->sc_sgt_nsegs); 274 } 275 276 return 0; 277 } 278 279 static void 280 njata32_irqack(chp) 281 struct ata_channel *chp; 282 { 283 struct njata32_softc *sc = (void *)chp->ch_atac; 284 285 /* disable busmaster */ 286 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 287 NJATA32_REG_BM, (sc->sc_bmwait << NJATA32_BM_WAIT_SHIFT)); 288 } 289 290 static void 291 njata32_clearirq(chp, irq) 292 struct ata_channel *chp; 293 int irq; 294 { 295 struct njata32_softc *sc = (void *)chp->ch_atac; 296 297 printf("%s: unhandled intr: irq %#x, bm %#x, ", 298 NJATA32NAME(sc), irq, 299 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 300 NJATA32_REG_BM)); 301 302 /* disable busmaster */ 303 njata32_irqack(chp); 304 305 /* clear device interrupt */ 306 printf("err %#x, seccnt %#x, cyl %#x, sdh %#x, ", 307 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 308 NJATA32_REG_WD_ERROR), 309 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 310 NJATA32_REG_WD_SECCNT), 311 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 312 NJATA32_REG_WD_CYL_LO) | 313 (bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 314 NJATA32_REG_WD_CYL_HI) << 8), 315 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 316 NJATA32_REG_WD_SDH)); 317 printf("status %#x\n", 318 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 319 NJATA32_REG_WD_STATUS)); 320 } 321 322 static void 323 njata32_setup_channel(chp) 324 struct ata_channel *chp; 325 { 326 struct njata32_softc *sc = (void *)chp->ch_atac; 327 struct ata_drive_datas *drvp; 328 int drive; 329 uint8_t mode; 330 331 KASSERT(chp->ch_ndrive != 0); 332 333 sc->sc_timing_pio = 0; 334 #if 0 /* ATA DMA is currently unused */ 335 sc->sc_timing_dma = 0; 336 #endif 337 338 for (drive = 0; drive < chp->ch_ndrive; drive++) { 339 drvp = &chp->ch_drive[drive]; 340 if ((drvp->drive_flags & DRIVE) == 0) 341 continue; /* no drive */ 342 343 #if 0 /* ATA DMA is currently unused */ 344 if ((drvp->drive_flags & DRIVE_DMA) != 0) { 345 /* 346 * Multiword DMA 347 */ 348 if ((mode = drvp->DMA_mode) > NJATA32_MODE_MAX_DMA) 349 mode = NJATA32_MODE_MAX_DMA; 350 if (sc->sc_timing_dma < njata32_timing_dma[mode]) 351 sc->sc_timing_dma = njata32_timing_dma[mode]; 352 } 353 #endif 354 /* 355 * PIO 356 */ 357 if ((mode = drvp->PIO_mode) > NJATA32_MODE_MAX_PIO) 358 mode = NJATA32_MODE_MAX_PIO; 359 if (sc->sc_timing_pio < njata32_timing_pio[mode]) 360 sc->sc_timing_pio = njata32_timing_pio[mode]; 361 } 362 363 /* set timing for PIO */ 364 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 365 NJATA32_REG_TIMING, sc->sc_timing_pio); 366 } 367 368 /* 369 * map DMA buffer 370 */ 371 int 372 njata32_dma_init(v, channel, drive, databuf, datalen, flags) 373 void *v; 374 int channel, drive; 375 void *databuf; 376 size_t datalen; 377 int flags; 378 { 379 struct njata32_softc *sc = v; 380 int error; 381 struct njata32_device *dev = &sc->sc_dev[drive]; 382 383 KASSERT(channel == 0); 384 KASSERT((dev->d_flags & NJATA32_DEV_DMA_MAPPED) == 0); 385 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0); 386 387 KASSERT(flags & (WDC_DMA_PIOBM_ATA | WDC_DMA_PIOBM_ATAPI)); 388 389 /* use PIO for short transfer */ 390 if (datalen < 64 /* needs tune */) { 391 DPRINTF(("%s: njata32_dma_init: short transfer (%u)\n", 392 NJATA32NAME(sc), (unsigned)datalen)); 393 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 394 NJATA32_REG_TIMING, sc->sc_timing_pio); 395 return EINVAL; 396 } 397 398 /* use PIO for unaligned transfer (word alignment seems OK) */ 399 if (((uintptr_t)databuf & 1) || (datalen & 1)) { 400 DPRINTF(("%s: njata32_dma_init: unaligned: buf %p, len %u\n", 401 NJATA32NAME(sc), databuf, (unsigned)datalen)); 402 return EINVAL; 403 } 404 405 DPRINTF(("%s: njata32_dma_init: %s: databuf %p, datalen %u\n", 406 NJATA32NAME(sc), (flags & WDC_DMA_READ) ? "read" : "write", 407 databuf, (unsigned)datalen)); 408 409 error = bus_dmamap_load(sc->sc_dmat, dev->d_dmamap_xfer, 410 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 411 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 412 if (error) { 413 printf("%s: load xfer failed, error %d\n", 414 NJATA32NAME(sc), error); 415 return error; 416 } 417 418 bus_dmamap_sync(sc->sc_dmat, dev->d_dmamap_xfer, 0, 419 dev->d_dmamap_xfer->dm_mapsize, 420 (flags & WDC_DMA_READ) ? 421 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 422 423 dev->d_flags = 424 ((flags & WDC_DMA_READ) ? NJATA32_DEV_DMA_READ : 0) | 425 ((flags & WDC_DMA_PIOBM_ATAPI) ? NJATA32_DEV_DMA_ATAPI : 0) | 426 NJATA32_DEV_DMA_MAPPED; 427 428 return 0; 429 } 430 431 /* 432 * start DMA 433 * 434 * top: databuf + skip 435 * size: xferlen 436 */ 437 void 438 njata32_piobm_start(v, channel, drive, skip, xferlen, flags) 439 void *v; 440 int channel, drive; 441 int skip, xferlen; /* offset/size in mapped DMA buffer */ 442 int flags; 443 { 444 struct njata32_softc *sc = v; 445 struct njata32_device *dev = &sc->sc_dev[drive]; 446 int i, nsegs, seglen; 447 uint8_t bmreg; 448 449 DPRINTF(("%s: njata32_piobm_start: ch%d, dv%d, skip %d, xferlen %d\n", 450 NJATA32NAME(sc), channel, drive, skip, xferlen)); 451 452 KASSERT(channel == 0); 453 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED); 454 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0); 455 456 /* 457 * create scatter/gather table 458 * XXX this code may be slow 459 */ 460 for (i = nsegs = 0; 461 i < dev->d_dmamap_xfer->dm_nsegs && xferlen > 0; i++) { 462 if (dev->d_dmamap_xfer->dm_segs[i].ds_len <= skip) { 463 skip -= dev->d_dmamap_xfer->dm_segs[i].ds_len; 464 continue; 465 } 466 467 seglen = dev->d_dmamap_xfer->dm_segs[i].ds_len - skip; 468 if (seglen > xferlen) 469 seglen = xferlen; 470 471 dev->d_sgt[nsegs].sg_addr = 472 htole32(dev->d_dmamap_xfer->dm_segs[i].ds_addr + skip); 473 dev->d_sgt[nsegs].sg_len = htole32(seglen); 474 475 xferlen -= seglen; 476 nsegs++; 477 skip = 0; 478 } 479 sc->sc_piobm_nsegs = nsegs; 480 /* end mark */ 481 dev->d_sgt[nsegs - 1].sg_len |= htole32(NJATA32_SGT_ENDMARK); 482 483 #ifdef DIAGNOSTIC 484 if (xferlen) 485 panic("%s: njata32_piobm_start: xferlen residue %d\n", 486 NJATA32NAME(sc), xferlen); 487 #endif 488 489 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt, 490 (char *)dev->d_sgt - (char *)sc->sc_sgtpg, 491 sizeof(struct njata32_sgtable) * nsegs, 492 BUS_DMASYNC_PREWRITE); 493 494 /* set timing for PIO */ 495 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 496 NJATA32_REG_TIMING, sc->sc_timing_pio); 497 498 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_IOBM, 499 NJATA32_IOBM_DEFAULT); 500 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS, 501 NJATA32_AS_WAIT0); 502 503 /* 504 * interrupt configuration 505 */ 506 if ((dev->d_flags & (NJATA32_DEV_DMA_READ | NJATA32_DEV_DMA_ATAPI)) == 507 NJATA32_DEV_DMA_READ) { 508 /* 509 * ATA piobm read is executed while device interrupt is active, 510 * so disable device interrupt here 511 */ 512 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 513 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER); 514 } 515 516 /* enable scatter/gather busmaster transfer */ 517 bmreg = NJATA32_BM_EN | NJATA32_BM_SG | 518 (sc->sc_bmwait << NJATA32_BM_WAIT_SHIFT) | 519 ((dev->d_flags & NJATA32_DEV_DMA_READ) ? NJATA32_BM_RD : 0); 520 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM, 521 bmreg); 522 523 /* load scatter/gather table */ 524 bus_space_write_4(NJATA32_REGT(sc), NJATA32_REGH(sc), 525 NJATA32_REG_DMAADDR, dev->d_sgt_dma); 526 bus_space_write_4(NJATA32_REGT(sc), NJATA32_REGH(sc), 527 NJATA32_REG_DMALENGTH, sizeof(struct njata32_sgtable) * nsegs); 528 529 /* start transfer */ 530 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM, 531 (bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 532 NJATA32_REG_BM) 533 & ~(NJATA32_BM_RD|NJATA32_BM_SG|NJATA32_BM_WAIT_MASK)) | 534 bmreg | NJATA32_BM_GO); 535 536 sc->sc_devflags = dev->d_flags; 537 if (flags & WDC_PIOBM_XFER_IRQ) 538 sc->sc_devflags |= NJATA32_DEV_XFER_INTR; 539 #ifdef DIAGNOSTIC 540 dev->d_flags |= NJATA32_DEV_DMA_STARTED; 541 #endif 542 } 543 544 /* 545 * end of DMA 546 */ 547 int 548 njata32_dma_finish(v, channel, drive, force) 549 void *v; 550 int channel, drive; 551 int force; 552 { 553 struct njata32_softc *sc = v; 554 int bm; 555 int error = 0; 556 557 DPRINTF(("%s: njata32_dma_finish: bm = %#x\n", NJATA32NAME(sc), 558 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 559 NJATA32_REG_BM))); 560 561 KASSERT(channel == 0); 562 KASSERT(sc->sc_dev[drive].d_flags & NJATA32_DEV_DMA_MAPPED); 563 KASSERT(sc->sc_dev[drive].d_flags & NJATA32_DEV_DMA_STARTED); 564 565 bm = bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 566 NJATA32_REG_BM); 567 568 #ifdef NJATA32_DEBUG 569 printf("%s: irq %#x, bm %#x, 18 %#x, 1c %#x\n", NJATA32NAME(sc), 570 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 571 NJATA32_REG_IRQ_STAT), 572 bm, 573 bus_space_read_4(NJATA32_REGT(sc), NJATA32_REGH(sc), 0x18), 574 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 0x1c)); 575 #endif 576 577 /* check if DMA is active */ 578 if (bm & NJATA32_BM_GO) { 579 error = WDC_DMAST_NOIRQ; 580 581 switch (force) { 582 case WDC_DMAEND_END: 583 return error; 584 585 case WDC_DMAEND_ABRT: 586 printf("%s: aborting DMA\n", NJATA32NAME(sc)); 587 break; 588 } 589 } 590 591 /* 592 * ??? 593 * For unknown reason, PIOBM transfer sometimes fails in the middle, 594 * in which case the bit #7 of BM register becomes 0. 595 * Increasing the wait value seems to improve the situation. 596 */ 597 if ((bm & NJATA32_BM_DONE) == 0) { 598 error |= WDC_DMAST_ERR; 599 printf("%s: busmaster error", NJATA32NAME(sc)); 600 if (sc->sc_bmwait < 1 /* XXX */) { 601 sc->sc_bmwait++; 602 printf(", new busmaster wait = %d", sc->sc_bmwait); 603 } 604 printf("\n"); 605 } 606 607 /* stop command */ 608 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS, 609 NJATA32_AS_WAIT0); 610 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM, 611 (sc->sc_bmwait << NJATA32_BM_WAIT_SHIFT)); 612 613 /* set timing for PIO */ 614 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 615 NJATA32_REG_TIMING, sc->sc_timing_pio); 616 617 /* 618 * reenable device interrupt in case it was disabled for 619 * this transfer 620 */ 621 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 622 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER | NJATA32_IRQ_DEV); 623 624 #if 1 /* should be? */ 625 if ((sc->sc_devflags & NJATA32_DEV_GOT_XFER_INTR) == 0) 626 error |= WDC_DMAST_ERR; 627 #endif 628 sc->sc_devflags = 0; 629 630 #ifdef DIAGNOSTIC 631 sc->sc_dev[drive].d_flags &= ~NJATA32_DEV_DMA_STARTED; 632 #endif 633 634 return error; 635 } 636 637 /* 638 * unmap DMA buffer 639 */ 640 void 641 njata32_piobm_done(v, channel, drive) 642 void *v; 643 int channel, drive; 644 { 645 struct njata32_softc *sc = v; 646 struct njata32_device *dev = &sc->sc_dev[drive]; 647 648 DPRINTF(("%s: njata32_piobm_done: ch%d dv%d\n", 649 NJATA32NAME(sc), channel, drive)); 650 651 KASSERT(channel == 0); 652 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED); 653 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0); 654 655 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt, 656 (char *)dev->d_sgt - (char *)sc->sc_sgtpg, 657 sizeof(struct njata32_sgtable) * sc->sc_piobm_nsegs, 658 BUS_DMASYNC_POSTWRITE); 659 660 /* unload dma map */ 661 bus_dmamap_sync(sc->sc_dmat, dev->d_dmamap_xfer, 662 0, dev->d_dmamap_xfer->dm_mapsize, 663 (dev->d_flags & NJATA32_DEV_DMA_READ) ? 664 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 665 666 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt, 667 (char *)dev->d_sgt - (char *)sc->sc_sgtpg, 668 sizeof(struct njata32_sgtable) * NJATA32_NUM_SG, 669 BUS_DMASYNC_POSTWRITE); 670 671 bus_dmamap_unload(sc->sc_dmat, dev->d_dmamap_xfer); 672 dev->d_flags &= ~NJATA32_DEV_DMA_MAPPED; 673 } 674 675 int 676 njata32_intr(arg) 677 void *arg; 678 { 679 struct njata32_softc *sc = arg; 680 struct ata_channel *chp; 681 int irq; 682 683 irq = bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 684 NJATA32_REG_IRQ_STAT); 685 if ((irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == 0) 686 return 0; /* not mine */ 687 688 DPRINTF(("%s: njata32_intr: irq = %#x, altstatus = %#x\n", 689 NJATA32NAME(sc), irq, 690 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 691 NJATA32_REG_WD_ALTSTATUS))); 692 693 chp = &sc->sc_ch[0].ch_ata_channel; 694 695 if (irq & NJATA32_IRQ_XFER) 696 sc->sc_devflags |= NJATA32_DEV_GOT_XFER_INTR; 697 698 if ((irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == NJATA32_IRQ_XFER && 699 (sc->sc_devflags & NJATA32_DEV_XFER_INTR) == 0) { 700 /* 701 * transfer done, wait for device interrupt 702 */ 703 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 704 NJATA32_REG_BM, (sc->sc_bmwait << NJATA32_BM_WAIT_SHIFT)); 705 return 1; 706 } 707 708 /* 709 * If both transfer done interrupt and device interrupt are 710 * active for ATAPI transfer, call wdcintr() twice. 711 */ 712 if ((sc->sc_devflags & NJATA32_DEV_DMA_ATAPI) && 713 (irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == 714 (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV) && 715 (sc->sc_devflags & NJATA32_DEV_XFER_INTR)) { 716 if (wdcintr(chp) == 0) { 717 njata32_clearirq(&sc->sc_ch[0].ch_ata_channel, irq); 718 } 719 } 720 721 if (wdcintr(chp) == 0) { 722 njata32_clearirq(&sc->sc_ch[0].ch_ata_channel, irq); 723 } 724 725 return 1; 726 } 727
Indexes created Mon Oct 20 08:09:54 GMT 2025