ninjaata32.c revision 1.9
1 /* $NetBSD: ninjaata32.c,v 1.9 2007/10/19 11:59:57 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2006 ITOH Yasufumi <itohy (at) NetBSD.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: ninjaata32.c,v 1.9 2007/10/19 11:59:57 ad Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/proc.h> 36 37 #include <sys/bus.h> 38 #include <sys/intr.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <dev/ata/atavar.h> 43 #include <dev/ic/wdcreg.h> 44 #include <dev/ic/wdcvar.h> 45 46 #include <dev/ic/ninjaata32reg.h> 47 #include <dev/ic/ninjaata32var.h> 48 49 #ifdef NJATA32_DEBUG 50 #define DPRINTF(x) printf x 51 #else 52 #define DPRINTF(x) 53 #endif 54 55 static void njata32_init(struct njata32_softc *, int nosleep); 56 static void njata32_irqack(struct ata_channel *); 57 static void njata32_clearirq(struct ata_channel *, int); 58 static void njata32_setup_channel(struct ata_channel *); 59 static int njata32_dma_init(void *, int channel, int drive, 60 void *databuf, size_t datalen, int flags); 61 static void njata32_piobm_start(void *, int channel, int drive, int skip, 62 int xferlen, int flags); 63 static int njata32_dma_finish(void *, int channel, int drive, int force); 64 static void njata32_piobm_done(void *, int channel, int drive); 65 66 #if 0 /* ATA DMA is currently unused */ 67 static const uint8_t njata32_timing_dma[NJATA32_MODE_MAX_DMA + 1] = { 68 NJATA32_TIMING_DMA0, NJATA32_TIMING_DMA1, NJATA32_TIMING_DMA2 69 }; 70 #endif 71 static const uint8_t njata32_timing_pio[NJATA32_MODE_MAX_PIO + 1] = { 72 NJATA32_TIMING_PIO0, NJATA32_TIMING_PIO1, NJATA32_TIMING_PIO2, 73 NJATA32_TIMING_PIO3, NJATA32_TIMING_PIO4 74 }; 75 76 static void 77 njata32_init(sc, nosleep) 78 struct njata32_softc *sc; 79 int nosleep; /* can't sleep (during cold boot and in interrupt) */ 80 { 81 82 /* disable interrupts */ 83 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 84 NJATA32_REG_IRQ_SELECT, 0); 85 86 /* bus reset */ 87 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS, 88 NJATA32_AS_WAIT0 | NJATA32_AS_BUS_RESET); 89 if (nosleep) 90 delay(50000); 91 else 92 tsleep(sc, PRIBIO, "njaini", mstohz(50)); 93 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS, 94 NJATA32_AS_WAIT0); 95 96 /* initial transfer speed */ 97 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 98 NJATA32_REG_TIMING, NJATA32_TIMING_PIO0 + sc->sc_atawait); 99 100 /* setup busmaster mode */ 101 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_IOBM, 102 NJATA32_IOBM_DEFAULT); 103 104 /* enable interrupts */ 105 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 106 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER | NJATA32_IRQ_DEV); 107 } 108 109 void 110 njata32_attach(sc) 111 struct njata32_softc *sc; 112 { 113 bus_addr_t dmaaddr; 114 int i, devno, error; 115 struct wdc_regs *wdr; 116 117 /* 118 * allocate DMA resource 119 */ 120 if ((error = bus_dmamem_alloc(sc->sc_dmat, 121 sizeof(struct njata32_dma_page), PAGE_SIZE, 0, 122 &sc->sc_sgt_seg, 1, &sc->sc_sgt_nsegs, BUS_DMA_NOWAIT)) != 0) { 123 printf("%s: unable to allocate sgt page, error = %d\n", 124 NJATA32NAME(sc), error); 125 return; 126 } 127 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_sgt_seg, 128 sc->sc_sgt_nsegs, sizeof(struct njata32_dma_page), 129 (void **)&sc->sc_sgtpg, 130 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 131 printf("%s: unable to map sgt page, error = %d\n", 132 NJATA32NAME(sc), error); 133 goto fail1; 134 } 135 if ((error = bus_dmamap_create(sc->sc_dmat, 136 sizeof(struct njata32_dma_page), 1, 137 sizeof(struct njata32_dma_page), 0, BUS_DMA_NOWAIT, 138 &sc->sc_dmamap_sgt)) != 0) { 139 printf("%s: unable to create sgt DMA map, error = %d\n", 140 NJATA32NAME(sc), error); 141 goto fail2; 142 } 143 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_sgt, 144 sc->sc_sgtpg, sizeof(struct njata32_dma_page), 145 NULL, BUS_DMA_NOWAIT)) != 0) { 146 printf("%s: unable to load sgt DMA map, error = %d\n", 147 NJATA32NAME(sc), error); 148 goto fail3; 149 } 150 151 dmaaddr = sc->sc_dmamap_sgt->dm_segs[0].ds_addr; 152 153 for (devno = 0; devno < NJATA32_NUM_DEV; devno++) { 154 sc->sc_dev[devno].d_sgt = sc->sc_sgtpg->dp_sg[devno]; 155 sc->sc_dev[devno].d_sgt_dma = dmaaddr + 156 offsetof(struct njata32_dma_page, dp_sg[devno]); 157 158 error = bus_dmamap_create(sc->sc_dmat, 159 NJATA32_MAX_XFER, /* max total map size */ 160 NJATA32_NUM_SG, /* max number of segments */ 161 NJATA32_SGT_MAXSEGLEN, /* max size of a segment */ 162 0, /* boundary */ 163 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 164 &sc->sc_dev[devno].d_dmamap_xfer); 165 if (error) { 166 printf("%s: failed to create DMA map (error = %d)\n", 167 NJATA32NAME(sc), error); 168 goto fail4; 169 } 170 } 171 172 /* device properties */ 173 sc->sc_wdcdev.sc_atac.atac_cap = 174 ATAC_CAP_DATA16 | ATAC_CAP_DATA32 | ATAC_CAP_PIOBM; 175 sc->sc_wdcdev.irqack = njata32_irqack; 176 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_wdc_chanarray; 177 sc->sc_wdcdev.sc_atac.atac_nchannels = NJATA32_NCHAN; /* 1 */ 178 sc->sc_wdcdev.sc_atac.atac_pio_cap = NJATA32_MODE_MAX_PIO; 179 #if 0 /* ATA DMA is currently unused */ 180 sc->sc_wdcdev.sc_atac.atac_dma_cap = NJATA32_MODE_MAX_DMA; 181 #endif 182 sc->sc_wdcdev.sc_atac.atac_set_modes = njata32_setup_channel; 183 184 /* DMA control functions */ 185 sc->sc_wdcdev.dma_arg = sc; 186 sc->sc_wdcdev.dma_init = njata32_dma_init; 187 sc->sc_wdcdev.piobm_start = njata32_piobm_start; 188 sc->sc_wdcdev.dma_finish = njata32_dma_finish; 189 sc->sc_wdcdev.piobm_done = njata32_piobm_done; 190 191 sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_EXTRA_RESETS; 192 193 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs; 194 195 /* only one channel */ 196 sc->sc_wdc_chanarray[0] = &sc->sc_ch[0].ch_ata_channel; 197 sc->sc_ch[0].ch_ata_channel.ch_channel = 0; 198 sc->sc_ch[0].ch_ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 199 sc->sc_ch[0].ch_ata_channel.ch_queue = &sc->sc_wdc_chqueue; 200 sc->sc_ch[0].ch_ata_channel.ch_ndrive = 2; /* max number of drives */ 201 202 /* map ATA registers */ 203 for (i = 0; i < WDC_NREG; i++) { 204 if (bus_space_subregion(NJATA32_REGT(sc), NJATA32_REGH(sc), 205 NJATA32_OFFSET_WDCREGS + i, 206 i == wd_data ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 207 aprint_error("%s: couldn't subregion cmd regs\n", 208 NJATA32NAME(sc)); 209 goto fail4; 210 } 211 } 212 wdc_init_shadow_regs(&sc->sc_ch[0].ch_ata_channel); 213 wdr->data32iot = NJATA32_REGT(sc); 214 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 215 216 /* map ATA ctl reg */ 217 wdr->ctl_iot = NJATA32_REGT(sc); 218 if (bus_space_subregion(NJATA32_REGT(sc), NJATA32_REGH(sc), 219 NJATA32_REG_WD_ALTSTATUS, 1, &wdr->ctl_ioh) != 0) { 220 aprint_error("%s: couldn't subregion ctl regs\n", 221 NJATA32NAME(sc)); 222 goto fail4; 223 } 224 225 sc->sc_flags |= NJATA32_CMDPG_MAPPED; 226 227 /* use flags value as busmaster wait */ 228 if ((sc->sc_atawait = 229 (uint8_t)device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags)) 230 aprint_normal("%s: ATA wait = %#x\n", 231 NJATA32NAME(sc), sc->sc_atawait); 232 233 njata32_init(sc, cold); 234 235 wdcattach(&sc->sc_ch[0].ch_ata_channel); 236 237 return; 238 239 /* 240 * cleanup 241 */ 242 fail4: while (--devno >= 0) { 243 bus_dmamap_destroy(sc->sc_dmat, 244 sc->sc_dev[devno].d_dmamap_xfer); 245 } 246 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_sgt); 247 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_sgt); 248 fail2: bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_sgtpg, 249 sizeof(struct njata32_dma_page)); 250 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_sgt_seg, sc->sc_sgt_nsegs); 251 } 252 253 int 254 njata32_detach(sc, flags) 255 struct njata32_softc *sc; 256 int flags; 257 { 258 int rv, devno; 259 260 if (sc->sc_flags & NJATA32_CMDPG_MAPPED) { 261 if ((rv = wdcdetach(&sc->sc_wdcdev.sc_atac.atac_dev, flags))) 262 return rv; 263 264 /* free DMA resource */ 265 for (devno = 0; devno < NJATA32_NUM_DEV; devno++) { 266 bus_dmamap_destroy(sc->sc_dmat, 267 sc->sc_dev[devno].d_dmamap_xfer); 268 } 269 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_sgt); 270 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_sgt); 271 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_sgtpg, 272 sizeof(struct njata32_dma_page)); 273 bus_dmamem_free(sc->sc_dmat, &sc->sc_sgt_seg, sc->sc_sgt_nsegs); 274 } 275 276 return 0; 277 } 278 279 static void 280 njata32_irqack(chp) 281 struct ata_channel *chp; 282 { 283 struct njata32_softc *sc = (void *)chp->ch_atac; 284 285 /* disable busmaster */ 286 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 287 NJATA32_REG_BM, NJATA32_BM_WAIT0); 288 } 289 290 static void 291 njata32_clearirq(chp, irq) 292 struct ata_channel *chp; 293 int irq; 294 { 295 struct njata32_softc *sc = (void *)chp->ch_atac; 296 297 printf("%s: unhandled intr: irq %#x, bm %#x, ", 298 NJATA32NAME(sc), irq, 299 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 300 NJATA32_REG_BM)); 301 302 /* disable busmaster */ 303 njata32_irqack(chp); 304 305 /* clear device interrupt */ 306 printf("err %#x, seccnt %#x, cyl %#x, sdh %#x, ", 307 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 308 NJATA32_REG_WD_ERROR), 309 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 310 NJATA32_REG_WD_SECCNT), 311 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 312 NJATA32_REG_WD_CYL_LO) | 313 (bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 314 NJATA32_REG_WD_CYL_HI) << 8), 315 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 316 NJATA32_REG_WD_SDH)); 317 printf("status %#x\n", 318 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 319 NJATA32_REG_WD_STATUS)); 320 } 321 322 static void 323 njata32_setup_channel(chp) 324 struct ata_channel *chp; 325 { 326 struct njata32_softc *sc = (void *)chp->ch_atac; 327 struct ata_drive_datas *drvp; 328 int drive; 329 uint8_t mode; 330 331 KASSERT(chp->ch_ndrive != 0); 332 333 sc->sc_timing_pio = 0; 334 #if 0 /* ATA DMA is currently unused */ 335 sc->sc_timing_dma = 0; 336 #endif 337 338 for (drive = 0; drive < chp->ch_ndrive; drive++) { 339 drvp = &chp->ch_drive[drive]; 340 if ((drvp->drive_flags & DRIVE) == 0) 341 continue; /* no drive */ 342 343 #if 0 /* ATA DMA is currently unused */ 344 if ((drvp->drive_flags & DRIVE_DMA) != 0) { 345 /* 346 * Multiword DMA 347 */ 348 if ((mode = drvp->DMA_mode) > NJATA32_MODE_MAX_DMA) 349 mode = NJATA32_MODE_MAX_DMA; 350 if (sc->sc_timing_dma < njata32_timing_dma[mode]) 351 sc->sc_timing_dma = njata32_timing_dma[mode]; 352 } 353 #endif 354 /* 355 * PIO 356 */ 357 if ((mode = drvp->PIO_mode) > NJATA32_MODE_MAX_PIO) 358 mode = NJATA32_MODE_MAX_PIO; 359 if (sc->sc_timing_pio < njata32_timing_pio[mode]) 360 sc->sc_timing_pio = njata32_timing_pio[mode]; 361 } 362 363 sc->sc_timing_pio += sc->sc_atawait; 364 365 /* set timing for PIO */ 366 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 367 NJATA32_REG_TIMING, sc->sc_timing_pio); 368 } 369 370 /* 371 * map DMA buffer 372 */ 373 int 374 njata32_dma_init(void *v, int channel, int drive, void *databuf, 375 size_t datalen, int flags) 376 { 377 struct njata32_softc *sc = v; 378 int error; 379 struct njata32_device *dev = &sc->sc_dev[drive]; 380 381 KASSERT(channel == 0); 382 KASSERT((dev->d_flags & NJATA32_DEV_DMA_MAPPED) == 0); 383 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0); 384 385 KASSERT(flags & (WDC_DMA_PIOBM_ATA | WDC_DMA_PIOBM_ATAPI)); 386 387 /* use PIO for short transfer */ 388 if (datalen < 64 /* needs tune */) { 389 DPRINTF(("%s: njata32_dma_init: short transfer (%u)\n", 390 NJATA32NAME(sc), (unsigned)datalen)); 391 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 392 NJATA32_REG_TIMING, sc->sc_timing_pio); 393 return EINVAL; 394 } 395 396 /* use PIO for unaligned transfer (word alignment seems OK) */ 397 if (((uintptr_t)databuf & 1) || (datalen & 1)) { 398 DPRINTF(("%s: njata32_dma_init: unaligned: buf %p, len %u\n", 399 NJATA32NAME(sc), databuf, (unsigned)datalen)); 400 return EINVAL; 401 } 402 403 DPRINTF(("%s: njata32_dma_init: %s: databuf %p, datalen %u\n", 404 NJATA32NAME(sc), (flags & WDC_DMA_READ) ? "read" : "write", 405 databuf, (unsigned)datalen)); 406 407 error = bus_dmamap_load(sc->sc_dmat, dev->d_dmamap_xfer, 408 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 409 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 410 if (error) { 411 printf("%s: load xfer failed, error %d\n", 412 NJATA32NAME(sc), error); 413 return error; 414 } 415 416 bus_dmamap_sync(sc->sc_dmat, dev->d_dmamap_xfer, 0, 417 dev->d_dmamap_xfer->dm_mapsize, 418 (flags & WDC_DMA_READ) ? 419 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 420 421 dev->d_flags = 422 ((flags & WDC_DMA_READ) ? NJATA32_DEV_DMA_READ : 0) | 423 ((flags & WDC_DMA_PIOBM_ATAPI) ? NJATA32_DEV_DMA_ATAPI : 0) | 424 NJATA32_DEV_DMA_MAPPED; 425 426 return 0; 427 } 428 429 /* 430 * start DMA 431 * 432 * top: databuf + skip 433 * size: xferlen 434 */ 435 void 436 njata32_piobm_start(void *v, int channel, int drive, 437 int skip, int xferlen, int flags) 438 { 439 struct njata32_softc *sc = v; 440 struct njata32_device *dev = &sc->sc_dev[drive]; 441 int i, nsegs, seglen; 442 uint8_t bmreg; 443 444 DPRINTF(("%s: njata32_piobm_start: ch%d, dv%d, skip %d, xferlen %d\n", 445 NJATA32NAME(sc), channel, drive, skip, xferlen)); 446 447 KASSERT(channel == 0); 448 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED); 449 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0); 450 451 /* 452 * create scatter/gather table 453 * XXX this code may be slow 454 */ 455 for (i = nsegs = 0; 456 i < dev->d_dmamap_xfer->dm_nsegs && xferlen > 0; i++) { 457 if (dev->d_dmamap_xfer->dm_segs[i].ds_len <= skip) { 458 skip -= dev->d_dmamap_xfer->dm_segs[i].ds_len; 459 continue; 460 } 461 462 seglen = dev->d_dmamap_xfer->dm_segs[i].ds_len - skip; 463 if (seglen > xferlen) 464 seglen = xferlen; 465 466 dev->d_sgt[nsegs].sg_addr = 467 htole32(dev->d_dmamap_xfer->dm_segs[i].ds_addr + skip); 468 dev->d_sgt[nsegs].sg_len = htole32(seglen); 469 470 xferlen -= seglen; 471 nsegs++; 472 skip = 0; 473 } 474 sc->sc_piobm_nsegs = nsegs; 475 /* end mark */ 476 dev->d_sgt[nsegs - 1].sg_len |= htole32(NJATA32_SGT_ENDMARK); 477 478 #ifdef DIAGNOSTIC 479 if (xferlen) 480 panic("%s: njata32_piobm_start: xferlen residue %d\n", 481 NJATA32NAME(sc), xferlen); 482 #endif 483 484 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt, 485 (char *)dev->d_sgt - (char *)sc->sc_sgtpg, 486 sizeof(struct njata32_sgtable) * nsegs, 487 BUS_DMASYNC_PREWRITE); 488 489 /* set timing for PIO */ 490 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 491 NJATA32_REG_TIMING, sc->sc_timing_pio); 492 493 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_IOBM, 494 NJATA32_IOBM_DEFAULT); 495 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS, 496 NJATA32_AS_WAIT0); 497 498 /* 499 * interrupt configuration 500 */ 501 if ((dev->d_flags & (NJATA32_DEV_DMA_READ | NJATA32_DEV_DMA_ATAPI)) == 502 NJATA32_DEV_DMA_READ) { 503 /* 504 * ATA piobm read is executed while device interrupt is active, 505 * so disable device interrupt here 506 */ 507 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 508 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER); 509 } 510 511 /* enable scatter/gather busmaster transfer */ 512 bmreg = NJATA32_BM_EN | NJATA32_BM_SG | NJATA32_BM_WAIT0 | 513 ((dev->d_flags & NJATA32_DEV_DMA_READ) ? NJATA32_BM_RD : 0); 514 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM, 515 bmreg); 516 517 /* load scatter/gather table */ 518 bus_space_write_4(NJATA32_REGT(sc), NJATA32_REGH(sc), 519 NJATA32_REG_DMAADDR, dev->d_sgt_dma); 520 bus_space_write_4(NJATA32_REGT(sc), NJATA32_REGH(sc), 521 NJATA32_REG_DMALENGTH, sizeof(struct njata32_sgtable) * nsegs); 522 523 /* start transfer */ 524 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM, 525 (bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 526 NJATA32_REG_BM) 527 & ~(NJATA32_BM_RD|NJATA32_BM_SG|NJATA32_BM_WAIT_MASK)) | 528 bmreg | NJATA32_BM_GO); 529 530 sc->sc_devflags = dev->d_flags; 531 if (flags & WDC_PIOBM_XFER_IRQ) 532 sc->sc_devflags |= NJATA32_DEV_XFER_INTR; 533 #ifdef DIAGNOSTIC 534 dev->d_flags |= NJATA32_DEV_DMA_STARTED; 535 #endif 536 } 537 538 /* 539 * end of DMA 540 */ 541 int 542 njata32_dma_finish(void *v, int channel, int drive, 543 int force) 544 { 545 struct njata32_softc *sc = v; 546 struct njata32_device *dev = &sc->sc_dev[drive]; 547 int bm; 548 int error = 0; 549 550 DPRINTF(("%s: njata32_dma_finish: bm = %#x\n", NJATA32NAME(sc), 551 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 552 NJATA32_REG_BM))); 553 554 KASSERT(channel == 0); 555 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED); 556 KASSERT(dev->d_flags & NJATA32_DEV_DMA_STARTED); 557 558 bm = bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 559 NJATA32_REG_BM); 560 561 #ifdef NJATA32_DEBUG 562 printf("%s: irq %#x, bm %#x, 18 %#x, 1c %#x\n", NJATA32NAME(sc), 563 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 564 NJATA32_REG_IRQ_STAT), 565 bm, 566 bus_space_read_4(NJATA32_REGT(sc), NJATA32_REGH(sc), 0x18), 567 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 0x1c)); 568 #endif 569 570 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt, 571 (char *)dev->d_sgt - (char *)sc->sc_sgtpg, 572 sizeof(struct njata32_sgtable) * sc->sc_piobm_nsegs, 573 BUS_DMASYNC_POSTWRITE); 574 575 /* check if DMA is active */ 576 if (bm & NJATA32_BM_GO) { 577 error = WDC_DMAST_NOIRQ; 578 579 switch (force) { 580 case WDC_DMAEND_END: 581 return error; 582 583 case WDC_DMAEND_ABRT: 584 printf("%s: aborting DMA\n", NJATA32NAME(sc)); 585 break; 586 } 587 } 588 589 /* 590 * ??? 591 * For unknown reason, PIOBM transfer sometimes fails in the middle, 592 * in which case the bit #7 of BM register becomes 0. 593 * Increasing the wait value seems to improve the situation. 594 * 595 * XXX 596 * PIO transfer may also fail, but it seems it can't be detected. 597 */ 598 if ((bm & NJATA32_BM_DONE) == 0) { 599 error |= WDC_DMAST_ERR; 600 printf("%s: busmaster error", NJATA32NAME(sc)); 601 if (sc->sc_atawait < 0x11) { 602 if ((sc->sc_atawait & 0xf) == 0) 603 sc->sc_atawait++; 604 else 605 sc->sc_atawait += 0x10; 606 printf(", new ATA wait = %#x", sc->sc_atawait); 607 njata32_setup_channel(&sc->sc_ch[0].ch_ata_channel); 608 } 609 printf("\n"); 610 } 611 612 /* stop command */ 613 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS, 614 NJATA32_AS_WAIT0); 615 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM, 616 NJATA32_BM_WAIT0); 617 618 /* set timing for PIO */ 619 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 620 NJATA32_REG_TIMING, sc->sc_timing_pio); 621 622 /* 623 * reenable device interrupt in case it was disabled for 624 * this transfer 625 */ 626 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 627 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER | NJATA32_IRQ_DEV); 628 629 #if 1 /* should be? */ 630 if ((sc->sc_devflags & NJATA32_DEV_GOT_XFER_INTR) == 0) 631 error |= WDC_DMAST_ERR; 632 #endif 633 sc->sc_devflags = 0; 634 635 #ifdef DIAGNOSTIC 636 dev->d_flags &= ~NJATA32_DEV_DMA_STARTED; 637 #endif 638 639 return error; 640 } 641 642 /* 643 * unmap DMA buffer 644 */ 645 void 646 njata32_piobm_done(void *v, int channel, int drive) 647 { 648 struct njata32_softc *sc = v; 649 struct njata32_device *dev = &sc->sc_dev[drive]; 650 651 DPRINTF(("%s: njata32_piobm_done: ch%d dv%d\n", 652 NJATA32NAME(sc), channel, drive)); 653 654 KASSERT(channel == 0); 655 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED); 656 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0); 657 658 /* unload dma map */ 659 bus_dmamap_sync(sc->sc_dmat, dev->d_dmamap_xfer, 660 0, dev->d_dmamap_xfer->dm_mapsize, 661 (dev->d_flags & NJATA32_DEV_DMA_READ) ? 662 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 663 664 bus_dmamap_unload(sc->sc_dmat, dev->d_dmamap_xfer); 665 dev->d_flags &= ~NJATA32_DEV_DMA_MAPPED; 666 } 667 668 int 669 njata32_intr(arg) 670 void *arg; 671 { 672 struct njata32_softc *sc = arg; 673 struct ata_channel *chp; 674 int irq; 675 676 irq = bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 677 NJATA32_REG_IRQ_STAT); 678 if ((irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == 0) 679 return 0; /* not mine */ 680 681 DPRINTF(("%s: njata32_intr: irq = %#x, altstatus = %#x\n", 682 NJATA32NAME(sc), irq, 683 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 684 NJATA32_REG_WD_ALTSTATUS))); 685 686 chp = &sc->sc_ch[0].ch_ata_channel; 687 688 if (irq & NJATA32_IRQ_XFER) 689 sc->sc_devflags |= NJATA32_DEV_GOT_XFER_INTR; 690 691 if ((irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == NJATA32_IRQ_XFER && 692 (sc->sc_devflags & NJATA32_DEV_XFER_INTR) == 0) { 693 /* 694 * transfer done, wait for device interrupt 695 */ 696 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 697 NJATA32_REG_BM, NJATA32_BM_WAIT0); 698 return 1; 699 } 700 701 /* 702 * If both transfer done interrupt and device interrupt are 703 * active for ATAPI transfer, call wdcintr() twice. 704 */ 705 if ((sc->sc_devflags & NJATA32_DEV_DMA_ATAPI) && 706 (irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == 707 (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV) && 708 (sc->sc_devflags & NJATA32_DEV_XFER_INTR)) { 709 if (wdcintr(chp) == 0) { 710 njata32_clearirq(&sc->sc_ch[0].ch_ata_channel, irq); 711 } 712 } 713 714 if (wdcintr(chp) == 0) { 715 njata32_clearirq(&sc->sc_ch[0].ch_ata_channel, irq); 716 } 717 718 return 1; 719 } 720
Indexes created Wed Sep 24 05:09:52 GMT 2025