1 1.4 itohy /* $NetBSD: ninjaata32reg.h,v 1.4 2011/02/21 02:32:00 itohy Exp $ */ 2 1.1 itohy 3 1.1 itohy /* 4 1.4 itohy * Copyright (c) 2006 ITOH Yasufumi. 5 1.1 itohy * All rights reserved. 6 1.1 itohy * 7 1.1 itohy * Redistribution and use in source and binary forms, with or without 8 1.1 itohy * modification, are permitted provided that the following conditions 9 1.1 itohy * are met: 10 1.1 itohy * 1. Redistributions of source code must retain the above copyright 11 1.1 itohy * notice, this list of conditions and the following disclaimer. 12 1.1 itohy * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 itohy * notice, this list of conditions and the following disclaimer in the 14 1.1 itohy * documentation and/or other materials provided with the distribution. 15 1.1 itohy * 16 1.1 itohy * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' 17 1.1 itohy * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 1.1 itohy * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.1 itohy * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS 20 1.1 itohy * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.1 itohy * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.1 itohy * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.1 itohy * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.1 itohy * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.1 itohy * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 1.1 itohy * THE POSSIBILITY OF SUCH DAMAGE. 27 1.1 itohy */ 28 1.1 itohy 29 1.1 itohy #ifndef _NJATA32REG_H_ 30 1.1 itohy #define _NJATA32REG_H_ 31 1.1 itohy 32 1.1 itohy /* 33 1.1 itohy * Workbit NinjaATA (32bit versions), IDE Controller with Busmastering PIO: 34 1.1 itohy * NinjaATA-32Bi PCMCIA/CardBus dual mode device ("DuoATA") 35 1.1 itohy * (CardBus mode only) 36 1.3 itohy * NPATA-32 CardBus device 37 1.1 itohy */ 38 1.1 itohy 39 1.1 itohy /* 40 1.1 itohy * CAVEAT 41 1.1 itohy * The names and the functions of the registers are probably incorrect 42 1.1 itohy * since no programming information is available in the public. 43 1.1 itohy */ 44 1.1 itohy 45 1.1 itohy #define NJATA32_REGSIZE 32 /* size of register set */ 46 1.1 itohy #define NJATA32_MEMOFFSET_REG 0x860 /* offset of memory mapped register */ 47 1.1 itohy 48 1.1 itohy #define NJATA32_REG_IRQ_STAT 0x00 /* len=1 RO */ 49 1.1 itohy #define NJATA32_REG_IRQ_SELECT 0x01 /* len=1 WO */ 50 1.1 itohy # define NJATA32_IRQ_XFER 0x01 51 1.1 itohy # define NJATA32_IRQ_DEV 0x04 52 1.1 itohy 53 1.1 itohy #define NJATA32_REG_IOBM 0x02 /* len=1 WO */ 54 1.1 itohy # define NJATA32_IOBM_01 0x01 55 1.1 itohy # define NJATA32_IOBM_02 0x02 56 1.1 itohy # define NJATA32_IOBM_MMENBL 0x08 57 1.1 itohy # define NJATA32_IOBM_BURST 0x10 58 1.1 itohy # define NJATA32_IOBM_NO_BMSTART0 0x20 59 1.1 itohy # define NJATA32_IOBM_80 0x80 60 1.1 itohy 61 1.1 itohy # define NJATA32_IOBM_DEFAULT (NJATA32_IOBM_01 | NJATA32_IOBM_02 | \ 62 1.1 itohy NJATA32_IOBM_BURST | NJATA32_IOBM_NO_BMSTART0 | NJATA32_IOBM_80) 63 1.1 itohy 64 1.1 itohy #define NJATA32_REG_AS 0x04 /* len=1 WO */ 65 1.1 itohy # define NJATA32_AS_START 0x01 /* 0: PIO BM, 1: DMA BM */ 66 1.1 itohy # define NJATA32_AS_WAIT0 0x00 67 1.1 itohy # define NJATA32_AS_WAIT1 0x04 68 1.1 itohy # define NJATA32_AS_WAIT2 0x08 69 1.1 itohy # define NJATA32_AS_WAIT3 0x0c 70 1.1 itohy # define NJATA32_AS_BUS_RESET 0x80 71 1.1 itohy 72 1.1 itohy #define NJATA32_REG_DMAADDR 0x08 /* len=4 R/W */ 73 1.1 itohy #define NJATA32_REG_DMALENGTH 0x0c /* len=4 R/W */ 74 1.1 itohy 75 1.1 itohy /* 76 1.1 itohy * WDC registers 77 1.1 itohy */ 78 1.1 itohy #define NJATA32_OFFSET_WDCREGS 0x10 79 1.1 itohy 80 1.1 itohy #define NJATA32_REG_WD_DATA 0x10 /* len=1/2/4 R/W */ 81 1.1 itohy #define NJATA32_REG_WD_ERROR 0x11 /* len=1 RO */ 82 1.1 itohy #define NJATA32_REG_WD_FEATURES 0x11 /* len=1 WO */ 83 1.1 itohy #define NJATA32_REG_WD_SECCNT 0x12 /* len=1 R/W */ 84 1.1 itohy #define NJATA32_REG_WD_IREASON 0x12 /* len=1 R/W (ATAPI) */ 85 1.1 itohy #define NJATA32_REG_WD_SECTOR 0x13 /* len=1 R/W */ 86 1.1 itohy #define NJATA32_REG_WD_LBA_LO 0x13 /* len=1 R/W */ 87 1.1 itohy #define NJATA32_REG_WD_CYL_LO 0x14 /* len=1 R/W */ 88 1.1 itohy #define NJATA32_REG_WD_LBA_MI 0x14 /* len=1 R/W */ 89 1.1 itohy #define NJATA32_REG_WD_CYL_HI 0x15 /* len=1 R/W */ 90 1.1 itohy #define NJATA32_REG_WD_LBA_HI 0x15 /* len=1 R/W */ 91 1.1 itohy #define NJATA32_REG_WD_SDH 0x16 /* len=1 R/W */ 92 1.1 itohy #define NJATA32_REG_WD_COMMAND 0x17 /* len=1 WO */ 93 1.1 itohy #define NJATA32_REG_WD_STATUS 0x17 /* len=1 RO */ 94 1.1 itohy 95 1.1 itohy #if 0 /* these registers seem to show the busmaster status */ 96 1.1 itohy /* ? */ 97 1.1 itohy #define NJATA32_REG_18 0x18 /* len=4 RO */ 98 1.1 itohy /* ? */ 99 1.1 itohy #define NJATA32_REG_1c 0x1c /* len=1 RO */ 100 1.1 itohy #endif 101 1.1 itohy 102 1.1 itohy #define NJATA32_REG_BM 0x1d /* len=1 R/W */ 103 1.1 itohy # define NJATA32_BM_EN 0x01 104 1.1 itohy # define NJATA32_BM_RD 0x02 /* 0: write, 1: read */ 105 1.1 itohy # define NJATA32_BM_SG 0x04 /* 1: use scatter/gather tbl */ 106 1.1 itohy # define NJATA32_BM_GO 0x08 107 1.1 itohy # define NJATA32_BM_WAIT0 0x00 108 1.1 itohy # define NJATA32_BM_WAIT1 0x10 109 1.1 itohy # define NJATA32_BM_WAIT2 0x20 110 1.1 itohy # define NJATA32_BM_WAIT3 0x30 111 1.1 itohy # define NJATA32_BM_WAIT_MASK 0x30 112 1.1 itohy # define NJATA32_BM_WAIT_SHIFT 4 113 1.1 itohy # define NJATA32_BM_DONE 0x80 /* ? */ 114 1.1 itohy 115 1.1 itohy #define NJATA32_REG_WD_ALTSTATUS 0x1e /* len=1 R */ 116 1.1 itohy 117 1.1 itohy #define NJATA32_REG_TIMING 0x1f /* len=1 W */ 118 1.1 itohy /* timing values for PIO transfer */ 119 1.1 itohy # define NJATA32_TIMING_PIO0 0xd6 120 1.1 itohy # define NJATA32_TIMING_PIO1 0x85 121 1.1 itohy # define NJATA32_TIMING_PIO2 0x44 122 1.1 itohy # define NJATA32_TIMING_PIO3 0x33 123 1.1 itohy # define NJATA32_TIMING_PIO4 0x13 124 1.1 itohy # define NJATA32_TIMING_PIO4_ 0x14 /* for timing tweak */ 125 1.1 itohy # define NJATA32_TIMING_PIO4__ 0x24 /* for timing tweak */ 126 1.1 itohy /* timing values for multiword DMA transfer */ 127 1.1 itohy # define NJATA32_TIMING_DMA0 0x88 128 1.1 itohy # define NJATA32_TIMING_DMA1 0x23 129 1.1 itohy # define NJATA32_TIMING_DMA2 0x13 130 1.1 itohy /* timing values for obsolete singleword DMA transfer */ 131 1.1 itohy # define NJATA32_TIMING_SMDMA0 0xff 132 1.1 itohy # define NJATA32_TIMING_SMDMA1 0x88 133 1.1 itohy # define NJATA32_TIMING_SMDMA2 0x44 134 1.1 itohy 135 1.1 itohy /* 136 1.1 itohy * DMA data structure 137 1.1 itohy */ 138 1.1 itohy 139 1.1 itohy /* scatter/gather transfer table entry (8 bytes) */ 140 1.1 itohy struct njata32_sgtable { 141 1.1 itohy uint32_t sg_addr; /* transfer address (little endian) */ 142 1.1 itohy uint32_t sg_len; /* transfer length (little endian) */ 143 1.1 itohy #define NJATA32_SGT_ENDMARK 0x80000000 144 1.1 itohy #define NJATA32_SGT_MAXSEGLEN 0x10000 145 1.1 itohy }; 146 1.1 itohy #define NJATA32_SGT_MAXENTRY 18 147 1.1 itohy 148 1.1 itohy /* 149 1.1 itohy * device specific constants 150 1.1 itohy */ 151 1.1 itohy #define NJATA32_MODE_MAX_DMA 2 152 1.1 itohy #define NJATA32_MODE_MAX_PIO 4 153 1.1 itohy 154 1.1 itohy #endif /* _NJATA32REG_H_ */ 155