ninjascsi32.c revision 1.2.2.3.2.2
1 1.2.2.3.2.2 bouyer /* $NetBSD: ninjascsi32.c,v 1.2.2.3.2.2 2007/11/19 20:40:03 bouyer Exp $ */ 2 1.2.2.2 tron 3 1.2.2.2 tron /*- 4 1.2.2.3.2.2 bouyer * Copyright (c) 2004, 2006, 2007 The NetBSD Foundation, Inc. 5 1.2.2.2 tron * All rights reserved. 6 1.2.2.2 tron * 7 1.2.2.2 tron * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 tron * by ITOH Yasufumi. 9 1.2.2.2 tron * 10 1.2.2.2 tron * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 tron * modification, are permitted provided that the following conditions 12 1.2.2.2 tron * are met: 13 1.2.2.2 tron * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 tron * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 tron * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 tron * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 tron * documentation and/or other materials provided with the distribution. 18 1.2.2.2 tron * 3. All advertising materials mentioning features or use of this software 19 1.2.2.2 tron * must display the following acknowledgement: 20 1.2.2.2 tron * This product includes software developed by the NetBSD 21 1.2.2.2 tron * Foundation, Inc. and its contributors. 22 1.2.2.2 tron * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.2.2.2 tron * contributors may be used to endorse or promote products derived 24 1.2.2.2 tron * from this software without specific prior written permission. 25 1.2.2.2 tron * 26 1.2.2.2 tron * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.2.2.2 tron * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.2.2.2 tron * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.2.2.2 tron * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.2.2.2 tron * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.2.2.2 tron * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.2.2.2 tron * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.2.2.2 tron * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.2.2.2 tron * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.2.2.2 tron * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.2.2.2 tron * POSSIBILITY OF SUCH DAMAGE. 37 1.2.2.2 tron */ 38 1.2.2.2 tron 39 1.2.2.2 tron #include <sys/cdefs.h> 40 1.2.2.3.2.2 bouyer __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.2.2.3.2.2 2007/11/19 20:40:03 bouyer Exp $"); 41 1.2.2.2 tron 42 1.2.2.2 tron #include <sys/param.h> 43 1.2.2.2 tron #include <sys/systm.h> 44 1.2.2.2 tron #include <sys/callout.h> 45 1.2.2.2 tron #include <sys/device.h> 46 1.2.2.2 tron #include <sys/kernel.h> 47 1.2.2.2 tron #include <sys/buf.h> 48 1.2.2.2 tron #include <sys/scsiio.h> 49 1.2.2.2 tron 50 1.2.2.2 tron #include <machine/bus.h> 51 1.2.2.2 tron #include <machine/intr.h> 52 1.2.2.2 tron 53 1.2.2.2 tron #include <uvm/uvm_extern.h> 54 1.2.2.2 tron 55 1.2.2.2 tron #include <dev/scsipi/scsi_all.h> 56 1.2.2.2 tron #include <dev/scsipi/scsipi_all.h> 57 1.2.2.2 tron #include <dev/scsipi/scsiconf.h> 58 1.2.2.2 tron #include <dev/scsipi/scsi_message.h> 59 1.2.2.2 tron 60 1.2.2.2 tron /* 61 1.2.2.2 tron * DualEdge transfer support 62 1.2.2.2 tron */ 63 1.2.2.2 tron /* #define NJSC32_DUALEDGE */ /* XXX untested */ 64 1.2.2.2 tron 65 1.2.2.2 tron /* 66 1.2.2.2 tron * Auto param loading does not work properly (it partially works (works on 67 1.2.2.2 tron * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51), 68 1.2.2.2 tron * and it doesn't improve the performance so much, 69 1.2.2.2 tron * forget about it. 70 1.2.2.2 tron */ 71 1.2.2.2 tron #undef NJSC32_AUTOPARAM 72 1.2.2.2 tron 73 1.2.2.2 tron #include <dev/ic/ninjascsi32reg.h> 74 1.2.2.2 tron #include <dev/ic/ninjascsi32var.h> 75 1.2.2.2 tron 76 1.2.2.2 tron /* #define NJSC32_DEBUG */ 77 1.2.2.2 tron /* #define NJSC32_TRACE */ 78 1.2.2.2 tron 79 1.2.2.2 tron #ifdef NJSC32_DEBUG 80 1.2.2.2 tron #define DPRINTF(x) printf x 81 1.2.2.2 tron #define DPRINTC(cmd, x) PRINTC(cmd, x) 82 1.2.2.2 tron #else 83 1.2.2.2 tron #define DPRINTF(x) 84 1.2.2.2 tron #define DPRINTC(cmd, x) 85 1.2.2.2 tron #endif 86 1.2.2.2 tron #ifdef NJSC32_TRACE 87 1.2.2.2 tron #define TPRINTF(x) printf x 88 1.2.2.2 tron #define TPRINTC(cmd, x) PRINTC(cmd, x) 89 1.2.2.2 tron #else 90 1.2.2.2 tron #define TPRINTF(x) 91 1.2.2.2 tron #define TPRINTC(cmd, x) 92 1.2.2.2 tron #endif 93 1.2.2.2 tron 94 1.2.2.2 tron #define PRINTC(cmd, x) do { \ 95 1.2.2.2 tron scsi_print_addr((cmd)->c_xs->xs_periph); \ 96 1.2.2.2 tron printf x; \ 97 1.2.2.2 tron } while (/* CONSTCOND */ 0) 98 1.2.2.2 tron 99 1.2.2.3 tron static void njsc32_scsipi_request(struct scsipi_channel *, 100 1.2.2.3 tron scsipi_adapter_req_t, void *); 101 1.2.2.3 tron static void njsc32_scsipi_minphys(struct buf *buf); 102 1.2.2.3 tron static int njsc32_scsipi_ioctl(struct scsipi_channel *, u_long, caddr_t, 103 1.2.2.3 tron int, struct proc *); 104 1.2.2.3 tron 105 1.2.2.3 tron static void njsc32_init(struct njsc32_softc *, int nosleep); 106 1.2.2.3 tron static int njsc32_init_cmds(struct njsc32_softc *); 107 1.2.2.3 tron static void njsc32_target_async(struct njsc32_softc *, 108 1.2.2.3 tron struct njsc32_target *); 109 1.2.2.3 tron static void njsc32_init_targets(struct njsc32_softc *); 110 1.2.2.3 tron static void njsc32_add_msgout(struct njsc32_softc *, int); 111 1.2.2.3 tron static u_int32_t njsc32_get_auto_msgout(struct njsc32_softc *); 112 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 113 1.2.2.3 tron static void njsc32_msgout_wdtr(struct njsc32_softc *, int); 114 1.2.2.2 tron #endif 115 1.2.2.3 tron static void njsc32_msgout_sdtr(struct njsc32_softc *, int period, 116 1.2.2.3 tron int offset); 117 1.2.2.3 tron static void njsc32_negotiate_xfer(struct njsc32_softc *, 118 1.2.2.3 tron struct njsc32_target *); 119 1.2.2.3 tron static void njsc32_arbitration_failed(struct njsc32_softc *); 120 1.2.2.3 tron static void njsc32_start(struct njsc32_softc *); 121 1.2.2.3 tron static void njsc32_run_xfer(struct njsc32_softc *, struct scsipi_xfer *); 122 1.2.2.3 tron static void njsc32_end_cmd(struct njsc32_softc *, struct njsc32_cmd *, 123 1.2.2.3 tron scsipi_xfer_result_t); 124 1.2.2.3.2.2 bouyer static void njsc32_wait_reset_release(void *); 125 1.2.2.3 tron static void njsc32_reset_bus(struct njsc32_softc *); 126 1.2.2.3 tron static void njsc32_clear_cmds(struct njsc32_softc *, 127 1.2.2.3 tron scsipi_xfer_result_t); 128 1.2.2.3 tron static void njsc32_set_ptr(struct njsc32_softc *, struct njsc32_cmd *, 129 1.2.2.3 tron u_int32_t); 130 1.2.2.3 tron static void njsc32_assert_ack(struct njsc32_softc *); 131 1.2.2.3 tron static void njsc32_negate_ack(struct njsc32_softc *); 132 1.2.2.3 tron static void njsc32_wait_req_negate(struct njsc32_softc *); 133 1.2.2.3 tron static void njsc32_reconnect(struct njsc32_softc *, struct njsc32_cmd *); 134 1.2.2.2 tron enum njsc32_reselstat { 135 1.2.2.2 tron NJSC32_RESEL_ERROR, /* to be rejected */ 136 1.2.2.2 tron NJSC32_RESEL_COMPLETE, /* reselection is just complete */ 137 1.2.2.2 tron NJSC32_RESEL_THROUGH /* this message is OK (no reply) */ 138 1.2.2.2 tron }; 139 1.2.2.3 tron static enum njsc32_reselstat njsc32_resel_identify(struct njsc32_softc *, 140 1.2.2.3 tron int lun, struct njsc32_cmd **); 141 1.2.2.3 tron static enum njsc32_reselstat njsc32_resel_tag(struct njsc32_softc *, 142 1.2.2.3 tron int tag, struct njsc32_cmd **); 143 1.2.2.3 tron static void njsc32_cmd_reload(struct njsc32_softc *, struct njsc32_cmd *, 144 1.2.2.3 tron int); 145 1.2.2.3 tron static void njsc32_update_xfer_mode(struct njsc32_softc *, 146 1.2.2.3 tron struct njsc32_target *); 147 1.2.2.3 tron static void njsc32_msgin(struct njsc32_softc *); 148 1.2.2.3 tron static void njsc32_msgout(struct njsc32_softc *); 149 1.2.2.3 tron static void njsc32_cmdtimeout(void *); 150 1.2.2.3 tron static void njsc32_reseltimeout(void *); 151 1.2.2.2 tron 152 1.2.2.2 tron static __inline unsigned 153 1.2.2.3 tron njsc32_read_1(struct njsc32_softc *sc, int no) 154 1.2.2.2 tron { 155 1.2.2.2 tron 156 1.2.2.2 tron return bus_space_read_1(sc->sc_regt, sc->sc_regh, no); 157 1.2.2.2 tron } 158 1.2.2.2 tron 159 1.2.2.2 tron static __inline unsigned 160 1.2.2.3 tron njsc32_read_2(struct njsc32_softc *sc, int no) 161 1.2.2.2 tron { 162 1.2.2.2 tron 163 1.2.2.2 tron return bus_space_read_2(sc->sc_regt, sc->sc_regh, no); 164 1.2.2.2 tron } 165 1.2.2.2 tron 166 1.2.2.2 tron static __inline u_int32_t 167 1.2.2.3 tron njsc32_read_4(struct njsc32_softc *sc, int no) 168 1.2.2.2 tron { 169 1.2.2.2 tron 170 1.2.2.2 tron return bus_space_read_4(sc->sc_regt, sc->sc_regh, no); 171 1.2.2.2 tron } 172 1.2.2.2 tron 173 1.2.2.2 tron static __inline void 174 1.2.2.3 tron njsc32_write_1(struct njsc32_softc *sc, int no, int val) 175 1.2.2.2 tron { 176 1.2.2.2 tron 177 1.2.2.2 tron bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val); 178 1.2.2.2 tron } 179 1.2.2.2 tron 180 1.2.2.2 tron static __inline void 181 1.2.2.3 tron njsc32_write_2(struct njsc32_softc *sc, int no, int val) 182 1.2.2.2 tron { 183 1.2.2.2 tron 184 1.2.2.2 tron bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val); 185 1.2.2.2 tron } 186 1.2.2.2 tron 187 1.2.2.2 tron static __inline void 188 1.2.2.3 tron njsc32_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 189 1.2.2.2 tron { 190 1.2.2.2 tron 191 1.2.2.2 tron bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val); 192 1.2.2.2 tron } 193 1.2.2.2 tron 194 1.2.2.2 tron static __inline unsigned 195 1.2.2.3 tron njsc32_ireg_read_1(struct njsc32_softc *sc, int no) 196 1.2.2.2 tron { 197 1.2.2.2 tron 198 1.2.2.2 tron bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 199 1.2.2.2 tron return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 200 1.2.2.2 tron } 201 1.2.2.2 tron 202 1.2.2.2 tron static __inline unsigned 203 1.2.2.3 tron njsc32_ireg_read_2(struct njsc32_softc *sc, int no) 204 1.2.2.2 tron { 205 1.2.2.2 tron 206 1.2.2.2 tron bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 207 1.2.2.2 tron return bus_space_read_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 208 1.2.2.2 tron } 209 1.2.2.2 tron 210 1.2.2.2 tron static __inline u_int32_t 211 1.2.2.3 tron njsc32_ireg_read_4(struct njsc32_softc *sc, int no) 212 1.2.2.2 tron { 213 1.2.2.2 tron u_int32_t val; 214 1.2.2.2 tron 215 1.2.2.2 tron bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 216 1.2.2.2 tron val = (u_int16_t)bus_space_read_2(sc->sc_regt, sc->sc_regh, 217 1.2.2.2 tron NJSC32_REG_DATA_LOW); 218 1.2.2.2 tron return val | (bus_space_read_2(sc->sc_regt, sc->sc_regh, 219 1.2.2.2 tron NJSC32_REG_DATA_HIGH) << 16); 220 1.2.2.2 tron } 221 1.2.2.2 tron 222 1.2.2.2 tron static __inline void 223 1.2.2.3 tron njsc32_ireg_write_1(struct njsc32_softc *sc, int no, int val) 224 1.2.2.2 tron { 225 1.2.2.2 tron 226 1.2.2.2 tron bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 227 1.2.2.2 tron bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 228 1.2.2.2 tron } 229 1.2.2.2 tron 230 1.2.2.2 tron static __inline void 231 1.2.2.3 tron njsc32_ireg_write_2(struct njsc32_softc *sc, int no, int val) 232 1.2.2.2 tron { 233 1.2.2.2 tron 234 1.2.2.2 tron bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 235 1.2.2.2 tron bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 236 1.2.2.2 tron } 237 1.2.2.2 tron 238 1.2.2.2 tron static __inline void 239 1.2.2.3 tron njsc32_ireg_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 240 1.2.2.2 tron { 241 1.2.2.2 tron 242 1.2.2.2 tron bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 243 1.2.2.2 tron bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 244 1.2.2.2 tron bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_HIGH, 245 1.2.2.2 tron val >> 16); 246 1.2.2.2 tron } 247 1.2.2.2 tron 248 1.2.2.2 tron #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */ 249 1.2.2.2 tron #ifdef __STDC__ 250 1.2.2.2 tron # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK 251 1.2.2.2 tron # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \ 252 1.2.2.2 tron NJSC32_SREQ_SAMPLING_ENABLE) 253 1.2.2.2 tron #else 254 1.2.2.2 tron # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK 255 1.2.2.2 tron # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \ 256 1.2.2.2 tron NJSC32_SREQ_SAMPLING_ENABLE) 257 1.2.2.2 tron #endif 258 1.2.2.2 tron 259 1.2.2.2 tron #define NJSC32_NSYNCT_MAXSYNC 1 260 1.2.2.2 tron #define NJSC32_NSYNCT 16 261 1.2.2.2 tron 262 1.2.2.2 tron /* 40MHz (25ns) */ 263 1.2.2.2 tron static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = { 264 1.2.2.2 tron { 0, 0, 0 }, /* dummy for async */ 265 1.2.2.2 tron { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */ 266 1.2.2.2 tron { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */ 267 1.2.2.2 tron { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */ 268 1.2.2.2 tron { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */ 269 1.2.2.2 tron { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */ 270 1.2.2.2 tron { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */ 271 1.2.2.2 tron { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 272 1.2.2.2 tron { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */ 273 1.2.2.2 tron { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 274 1.2.2.2 tron { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */ 275 1.2.2.2 tron { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */ 276 1.2.2.2 tron { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */ 277 1.2.2.2 tron { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */ 278 1.2.2.2 tron { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */ 279 1.2.2.2 tron { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */ 280 1.2.2.2 tron }; 281 1.2.2.2 tron 282 1.2.2.2 tron #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 283 1.2.2.2 tron /* 20MHz (50ns) */ 284 1.2.2.2 tron static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = { 285 1.2.2.2 tron { 0, 0, 0 }, /* dummy for async */ 286 1.2.2.2 tron { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */ 287 1.2.2.2 tron { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */ 288 1.2.2.2 tron { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 289 1.2.2.2 tron { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 290 1.2.2.2 tron { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */ 291 1.2.2.2 tron { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */ 292 1.2.2.2 tron { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */ 293 1.2.2.2 tron { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */ 294 1.2.2.2 tron { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */ 295 1.2.2.2 tron { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */ 296 1.2.2.2 tron { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */ 297 1.2.2.2 tron { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */ 298 1.2.2.2 tron { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */ 299 1.2.2.2 tron { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */ 300 1.2.2.2 tron { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */ 301 1.2.2.2 tron }; 302 1.2.2.2 tron 303 1.2.2.2 tron /* 33.3MHz (30ns) */ 304 1.2.2.2 tron static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = { 305 1.2.2.2 tron { 0, 0, 0 }, /* dummy for async */ 306 1.2.2.2 tron { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */ 307 1.2.2.2 tron { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */ 308 1.2.2.2 tron { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */ 309 1.2.2.2 tron { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */ 310 1.2.2.2 tron { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */ 311 1.2.2.2 tron { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */ 312 1.2.2.2 tron { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */ 313 1.2.2.2 tron { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */ 314 1.2.2.2 tron { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */ 315 1.2.2.2 tron { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */ 316 1.2.2.2 tron { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */ 317 1.2.2.2 tron { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */ 318 1.2.2.2 tron { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */ 319 1.2.2.2 tron { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */ 320 1.2.2.2 tron { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */ 321 1.2.2.2 tron }; 322 1.2.2.2 tron #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */ 323 1.2.2.2 tron 324 1.2.2.2 tron #undef NS 325 1.2.2.2 tron #undef ACKW 326 1.2.2.2 tron #undef SMPL 327 1.2.2.2 tron 328 1.2.2.2 tron /* initialize device */ 329 1.2.2.2 tron static void 330 1.2.2.3 tron njsc32_init(struct njsc32_softc *sc, int nosleep) 331 1.2.2.2 tron { 332 1.2.2.2 tron u_int16_t intstat; 333 1.2.2.3.2.2 bouyer int i; 334 1.2.2.2 tron 335 1.2.2.2 tron /* block all interrupts */ 336 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 337 1.2.2.2 tron 338 1.2.2.2 tron /* clear transfer */ 339 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 340 1.2.2.2 tron njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0); 341 1.2.2.2 tron 342 1.2.2.2 tron /* make sure interrupts are cleared */ 343 1.2.2.3.2.2 bouyer for (i = 0; ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ)) 344 1.2.2.3.2.2 bouyer & NJSC32_IRQ_INTR_PENDING) && i < 5 /* just not forever */; i++) { 345 1.2.2.2 tron DPRINTF(("%s: njsc32_init: intr pending: %#x\n", 346 1.2.2.2 tron sc->sc_dev.dv_xname, intstat)); 347 1.2.2.2 tron } 348 1.2.2.2 tron 349 1.2.2.2 tron /* FIFO threshold */ 350 1.2.2.2 tron njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL, 351 1.2.2.2 tron NJSC32_FIFO_FULL_BUSMASTER); 352 1.2.2.2 tron njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY, 353 1.2.2.2 tron NJSC32_FIFO_EMPTY_BUSMASTER); 354 1.2.2.2 tron 355 1.2.2.2 tron /* clock source */ 356 1.2.2.2 tron njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk); 357 1.2.2.2 tron 358 1.2.2.2 tron /* memory read multiple */ 359 1.2.2.2 tron njsc32_ireg_write_1(sc, NJSC32_IREG_BM, 360 1.2.2.2 tron NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD); 361 1.2.2.2 tron 362 1.2.2.2 tron /* clear parity error and enable parity detection */ 363 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 364 1.2.2.2 tron NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 365 1.2.2.2 tron 366 1.2.2.2 tron /* misc configuration */ 367 1.2.2.2 tron njsc32_ireg_write_2(sc, NJSC32_IREG_MISC, 368 1.2.2.2 tron NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT | 369 1.2.2.2 tron NJSC32_MISC_DELAYED_BMSTART | 370 1.2.2.2 tron NJSC32_MISC_MASTER_TERMINATION_SELECT | 371 1.2.2.2 tron NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL | 372 1.2.2.2 tron NJSC32_MISC_AUTOSEL_TIMING_SEL | 373 1.2.2.2 tron NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE); 374 1.2.2.2 tron 375 1.2.2.2 tron /* 376 1.2.2.3.2.2 bouyer * Check for termination power (32Bi and some versions of 32UDE). 377 1.2.2.2 tron */ 378 1.2.2.2 tron if (!nosleep || cold) { 379 1.2.2.2 tron DPRINTF(("%s: njsc32_init: checking TERMPWR\n", 380 1.2.2.2 tron sc->sc_dev.dv_xname)); 381 1.2.2.2 tron 382 1.2.2.2 tron /* First, turn termination power off */ 383 1.2.2.2 tron njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0); 384 1.2.2.2 tron 385 1.2.2.2 tron /* give 0.5s to settle */ 386 1.2.2.2 tron if (nosleep) 387 1.2.2.2 tron delay(500000); 388 1.2.2.2 tron else 389 1.2.2.2 tron tsleep(sc, PWAIT, "njs_t1", hz / 2); 390 1.2.2.2 tron } 391 1.2.2.2 tron 392 1.2.2.2 tron /* supply termination power if not supplied by other devices */ 393 1.2.2.2 tron if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) & 394 1.2.2.2 tron NJSC32_TERMPWR_SENSE) == 0) { 395 1.2.2.2 tron /* termination power is not present on the bus */ 396 1.2.2.2 tron if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) { 397 1.2.2.2 tron /* 398 1.2.2.2 tron * CardBus device must not supply termination power 399 1.2.2.2 tron * to avoid excessive power consumption. 400 1.2.2.2 tron */ 401 1.2.2.2 tron printf("%s: no termination power present\n", 402 1.2.2.2 tron sc->sc_dev.dv_xname); 403 1.2.2.2 tron } else { 404 1.2.2.2 tron /* supply termination power */ 405 1.2.2.2 tron njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 406 1.2.2.2 tron NJSC32_TERMPWR_BPWR); 407 1.2.2.2 tron 408 1.2.2.2 tron DPRINTF(("%s: supplying termination power\n", 409 1.2.2.2 tron sc->sc_dev.dv_xname)); 410 1.2.2.2 tron 411 1.2.2.2 tron /* give 0.5s to settle */ 412 1.2.2.2 tron if (!nosleep) 413 1.2.2.2 tron tsleep(sc, PWAIT, "njs_t2", hz / 2); 414 1.2.2.2 tron } 415 1.2.2.2 tron } 416 1.2.2.2 tron 417 1.2.2.2 tron /* stop timer */ 418 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 419 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 420 1.2.2.2 tron 421 1.2.2.2 tron /* default transfer parameter */ 422 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_SYNC, 0); 423 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK); 424 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT, 425 1.2.2.2 tron NJSC32_SEL_TIMEOUT_TIME); 426 1.2.2.2 tron 427 1.2.2.2 tron /* select interrupt source */ 428 1.2.2.2 tron njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT, 429 1.2.2.2 tron NJSC32_IRQSEL_RESELECT | 430 1.2.2.2 tron NJSC32_IRQSEL_PHASE_CHANGE | 431 1.2.2.2 tron NJSC32_IRQSEL_SCSIRESET | 432 1.2.2.2 tron NJSC32_IRQSEL_TIMER | 433 1.2.2.2 tron NJSC32_IRQSEL_FIFO_THRESHOLD | 434 1.2.2.2 tron NJSC32_IRQSEL_TARGET_ABORT | 435 1.2.2.2 tron NJSC32_IRQSEL_MASTER_ABORT | 436 1.2.2.2 tron /* XXX not yet 437 1.2.2.2 tron NJSC32_IRQSEL_SERR | 438 1.2.2.2 tron NJSC32_IRQSEL_PERR | 439 1.2.2.2 tron NJSC32_IRQSEL_BMCNTERR | 440 1.2.2.2 tron */ 441 1.2.2.2 tron NJSC32_IRQSEL_AUTO_SCSI_SEQ); 442 1.2.2.2 tron 443 1.2.2.3.2.2 bouyer /* interrupts will be unblocked later after bus reset */ 444 1.2.2.2 tron 445 1.2.2.2 tron /* turn LED off */ 446 1.2.2.2 tron njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR, 447 1.2.2.2 tron NJSC32_EXTPORT_LED_OFF); 448 1.2.2.2 tron njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, 449 1.2.2.2 tron NJSC32_EXTPORT_LED_OFF); 450 1.2.2.2 tron 451 1.2.2.2 tron /* reset SCSI bus so the targets become known state */ 452 1.2.2.2 tron njsc32_reset_bus(sc); 453 1.2.2.2 tron } 454 1.2.2.2 tron 455 1.2.2.2 tron static int 456 1.2.2.3 tron njsc32_init_cmds(struct njsc32_softc *sc) 457 1.2.2.2 tron { 458 1.2.2.2 tron struct njsc32_cmd *cmd; 459 1.2.2.2 tron bus_addr_t dmaaddr; 460 1.2.2.2 tron int i, error; 461 1.2.2.2 tron 462 1.2.2.2 tron /* 463 1.2.2.2 tron * allocate DMA area for command 464 1.2.2.2 tron */ 465 1.2.2.2 tron if ((error = bus_dmamem_alloc(sc->sc_dmat, 466 1.2.2.2 tron sizeof(struct njsc32_dma_page), PAGE_SIZE, 0, 467 1.2.2.2 tron &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) { 468 1.2.2.2 tron printf("%s: unable to allocate cmd page, error = %d\n", 469 1.2.2.2 tron sc->sc_dev.dv_xname, error); 470 1.2.2.2 tron return 0; 471 1.2.2.2 tron } 472 1.2.2.2 tron if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg, 473 1.2.2.2 tron sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page), 474 1.2.2.2 tron (caddr_t *)&sc->sc_cmdpg, 475 1.2.2.2 tron BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 476 1.2.2.2 tron printf("%s: unable to map cmd page, error = %d\n", 477 1.2.2.2 tron sc->sc_dev.dv_xname, error); 478 1.2.2.2 tron goto fail1; 479 1.2.2.2 tron } 480 1.2.2.2 tron if ((error = bus_dmamap_create(sc->sc_dmat, 481 1.2.2.2 tron sizeof(struct njsc32_dma_page), 1, 482 1.2.2.2 tron sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT, 483 1.2.2.2 tron &sc->sc_dmamap_cmdpg)) != 0) { 484 1.2.2.2 tron printf("%s: unable to create cmd DMA map, error = %d\n", 485 1.2.2.2 tron sc->sc_dev.dv_xname, error); 486 1.2.2.2 tron goto fail2; 487 1.2.2.2 tron } 488 1.2.2.2 tron if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg, 489 1.2.2.2 tron sc->sc_cmdpg, sizeof(struct njsc32_dma_page), 490 1.2.2.2 tron NULL, BUS_DMA_NOWAIT)) != 0) { 491 1.2.2.2 tron printf("%s: unable to load cmd DMA map, error = %d\n", 492 1.2.2.2 tron sc->sc_dev.dv_xname, error); 493 1.2.2.2 tron goto fail3; 494 1.2.2.2 tron } 495 1.2.2.2 tron 496 1.2.2.2 tron memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page)); 497 1.2.2.2 tron dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr; 498 1.2.2.2 tron 499 1.2.2.2 tron #ifdef NJSC32_AUTOPARAM 500 1.2.2.2 tron sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap); 501 1.2.2.2 tron #endif 502 1.2.2.2 tron 503 1.2.2.2 tron for (i = 0; i < NJSC32_NUM_CMD; i++) { 504 1.2.2.2 tron cmd = &sc->sc_cmds[i]; 505 1.2.2.2 tron cmd->c_sc = sc; 506 1.2.2.2 tron cmd->c_sgt = sc->sc_cmdpg->dp_sg[i]; 507 1.2.2.2 tron cmd->c_sgt_dma = dmaaddr + 508 1.2.2.2 tron offsetof(struct njsc32_dma_page, dp_sg[i]); 509 1.2.2.2 tron cmd->c_flags = 0; 510 1.2.2.2 tron 511 1.2.2.2 tron error = bus_dmamap_create(sc->sc_dmat, 512 1.2.2.2 tron NJSC32_MAX_XFER, /* max total map size */ 513 1.2.2.2 tron NJSC32_NUM_SG, /* max number of segments */ 514 1.2.2.2 tron NJSC32_SGT_MAXSEGLEN, /* max size of a segment */ 515 1.2.2.2 tron 0, /* boundary */ 516 1.2.2.2 tron BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer); 517 1.2.2.2 tron if (error) { 518 1.2.2.2 tron printf("%s: only %d cmd descs available (error = %d)\n", 519 1.2.2.2 tron sc->sc_dev.dv_xname, i, error); 520 1.2.2.2 tron break; 521 1.2.2.2 tron } 522 1.2.2.2 tron TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q); 523 1.2.2.2 tron } 524 1.2.2.2 tron 525 1.2.2.2 tron if (i > 0) 526 1.2.2.2 tron return i; 527 1.2.2.2 tron 528 1.2.2.3.2.1 tron bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 529 1.2.2.2 tron fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 530 1.2.2.2 tron fail2: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg, 531 1.2.2.2 tron sizeof(struct njsc32_dma_page)); 532 1.2.2.2 tron fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs); 533 1.2.2.2 tron 534 1.2.2.2 tron return 0; 535 1.2.2.2 tron } 536 1.2.2.2 tron 537 1.2.2.2 tron static void 538 1.2.2.3 tron njsc32_target_async(struct njsc32_softc *sc, struct njsc32_target *target) 539 1.2.2.2 tron { 540 1.2.2.2 tron 541 1.2.2.2 tron target->t_sync = 542 1.2.2.2 tron NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC); 543 1.2.2.2 tron target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK; 544 1.2.2.2 tron target->t_sample = 0; /* disable */ 545 1.2.2.2 tron target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC; 546 1.2.2.2 tron target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC; 547 1.2.2.2 tron } 548 1.2.2.2 tron 549 1.2.2.2 tron static void 550 1.2.2.3 tron njsc32_init_targets(struct njsc32_softc *sc) 551 1.2.2.2 tron { 552 1.2.2.2 tron int id, lun; 553 1.2.2.2 tron struct njsc32_lu *lu; 554 1.2.2.2 tron 555 1.2.2.2 tron for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 556 1.2.2.2 tron /* cancel negotiation status */ 557 1.2.2.2 tron sc->sc_targets[id].t_state = NJSC32_TARST_INIT; 558 1.2.2.2 tron 559 1.2.2.2 tron /* default to async mode */ 560 1.2.2.2 tron njsc32_target_async(sc, &sc->sc_targets[id]); 561 1.2.2.2 tron 562 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 563 1.2.2.2 tron sc->sc_targets[id].t_xferctl = 0; 564 1.2.2.2 tron #endif 565 1.2.2.2 tron 566 1.2.2.2 tron sc->sc_targets[id].t_targetid = 567 1.2.2.2 tron (1 << id) | (1 << NJSC32_INITIATOR_ID); 568 1.2.2.2 tron 569 1.2.2.2 tron /* init logical units */ 570 1.2.2.2 tron for (lun = 0; lun < NJSC32_NLU; lun++) { 571 1.2.2.2 tron lu = &sc->sc_targets[id].t_lus[lun]; 572 1.2.2.2 tron lu->lu_cmd = NULL; 573 1.2.2.2 tron TAILQ_INIT(&lu->lu_q); 574 1.2.2.2 tron } 575 1.2.2.2 tron } 576 1.2.2.2 tron } 577 1.2.2.2 tron 578 1.2.2.2 tron void 579 1.2.2.3 tron njsc32_attach(struct njsc32_softc *sc) 580 1.2.2.2 tron { 581 1.2.2.2 tron const char *str; 582 1.2.2.2 tron #if 1 /* test */ 583 1.2.2.2 tron int reg; 584 1.2.2.2 tron njsc32_model_t detected_model; 585 1.2.2.2 tron #endif 586 1.2.2.2 tron 587 1.2.2.2 tron /* init */ 588 1.2.2.2 tron TAILQ_INIT(&sc->sc_freecmd); 589 1.2.2.2 tron TAILQ_INIT(&sc->sc_reqcmd); 590 1.2.2.3.2.2 bouyer callout_init(&sc->sc_callout); 591 1.2.2.2 tron 592 1.2.2.2 tron #if 1 /* test */ 593 1.2.2.2 tron /* 594 1.2.2.2 tron * try to distinguish 32Bi and 32UDE 595 1.2.2.2 tron */ 596 1.2.2.2 tron /* try to set DualEdge bit (exists on 32UDE only) and read it back */ 597 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE); 598 1.2.2.2 tron if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) { 599 1.2.2.2 tron /* device was removed? */ 600 1.2.2.2 tron aprint_error("%s: attach failed\n", sc->sc_dev.dv_xname); 601 1.2.2.2 tron return; 602 1.2.2.2 tron } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) { 603 1.2.2.2 tron detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE; 604 1.2.2.2 tron } else { 605 1.2.2.2 tron detected_model = NJSC32_MODEL_32BI; 606 1.2.2.2 tron } 607 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */ 608 1.2.2.2 tron 609 1.2.2.2 tron #if 1/*def DIAGNOSTIC*/ 610 1.2.2.2 tron /* compare what is configured with what is detected */ 611 1.2.2.2 tron if ((sc->sc_model & NJSC32_MODEL_MASK) != 612 1.2.2.2 tron (detected_model & NJSC32_MODEL_MASK)) { 613 1.2.2.2 tron /* 614 1.2.2.2 tron * Please report this error if it happens. 615 1.2.2.2 tron */ 616 1.2.2.2 tron aprint_error("%s: model mismatch: %#x vs %#x\n", 617 1.2.2.2 tron sc->sc_dev.dv_xname, sc->sc_model, detected_model); 618 1.2.2.2 tron return; 619 1.2.2.2 tron } 620 1.2.2.2 tron #endif 621 1.2.2.2 tron #endif 622 1.2.2.2 tron 623 1.2.2.2 tron /* check model */ 624 1.2.2.2 tron switch (sc->sc_model & NJSC32_MODEL_MASK) { 625 1.2.2.2 tron case NJSC32_MODEL_32BI: 626 1.2.2.2 tron str = "Bi"; 627 1.2.2.2 tron /* 32Bi doesn't support DualEdge transfer */ 628 1.2.2.2 tron KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0); 629 1.2.2.2 tron break; 630 1.2.2.2 tron case NJSC32_MODEL_32UDE: 631 1.2.2.2 tron str = "UDE"; 632 1.2.2.2 tron break; 633 1.2.2.2 tron default: 634 1.2.2.2 tron aprint_error("%s: unknown model!\n", sc->sc_dev.dv_xname); 635 1.2.2.2 tron return; 636 1.2.2.2 tron } 637 1.2.2.2 tron aprint_normal("%s: NJSC-32%s", sc->sc_dev.dv_xname, str); 638 1.2.2.2 tron 639 1.2.2.2 tron switch (sc->sc_clk) { 640 1.2.2.2 tron default: 641 1.2.2.2 tron #ifdef DIAGNOSTIC 642 1.2.2.2 tron panic("njsc32_attach: unknown clk %d", sc->sc_clk); 643 1.2.2.2 tron #endif 644 1.2.2.2 tron case NJSC32_CLOCK_DIV_4: 645 1.2.2.2 tron sc->sc_synct = njsc32_synct_40M; 646 1.2.2.2 tron str = "40MHz"; 647 1.2.2.2 tron break; 648 1.2.2.2 tron #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 649 1.2.2.2 tron case NJSC32_CLOCK_DIV_2: 650 1.2.2.2 tron sc->sc_synct = njsc32_synct_20M; 651 1.2.2.2 tron str = "20MHz"; 652 1.2.2.2 tron break; 653 1.2.2.2 tron case NJSC32_CLOCK_PCICLK: 654 1.2.2.2 tron sc->sc_synct = njsc32_synct_pci; 655 1.2.2.2 tron str = "PCI"; 656 1.2.2.2 tron break; 657 1.2.2.2 tron #endif 658 1.2.2.2 tron } 659 1.2.2.2 tron aprint_normal(", G/A rev %#x, clk %s%s\n", 660 1.2.2.2 tron NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str, 661 1.2.2.2 tron (sc->sc_model & NJSC32_FLAG_DUALEDGE) ? 662 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 663 1.2.2.2 tron ", DualEdge" 664 1.2.2.2 tron #else 665 1.2.2.2 tron ", DualEdge (no driver support)" 666 1.2.2.2 tron #endif 667 1.2.2.2 tron : ""); 668 1.2.2.2 tron 669 1.2.2.2 tron /* allocate DMA resource */ 670 1.2.2.2 tron if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) { 671 1.2.2.2 tron printf("%s: no usable DMA map\n", sc->sc_dev.dv_xname); 672 1.2.2.2 tron return; 673 1.2.2.2 tron } 674 1.2.2.2 tron sc->sc_flags |= NJSC32_CMDPG_MAPPED; 675 1.2.2.2 tron 676 1.2.2.2 tron sc->sc_curcmd = NULL; 677 1.2.2.2 tron sc->sc_nusedcmds = 0; 678 1.2.2.2 tron 679 1.2.2.2 tron sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */ 680 1.2.2.2 tron 681 1.2.2.3.2.2 bouyer /* initialize hardware and target structure */ 682 1.2.2.2 tron njsc32_init(sc, cold); 683 1.2.2.2 tron 684 1.2.2.2 tron /* setup adapter */ 685 1.2.2.2 tron sc->sc_adapter.adapt_dev = &sc->sc_dev; 686 1.2.2.2 tron sc->sc_adapter.adapt_nchannels = 1; 687 1.2.2.2 tron sc->sc_adapter.adapt_request = njsc32_scsipi_request; 688 1.2.2.2 tron sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys; 689 1.2.2.2 tron sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl; 690 1.2.2.2 tron 691 1.2.2.2 tron sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings = 692 1.2.2.2 tron sc->sc_ncmd; 693 1.2.2.2 tron 694 1.2.2.2 tron /* setup channel */ 695 1.2.2.2 tron sc->sc_channel.chan_adapter = &sc->sc_adapter; 696 1.2.2.2 tron sc->sc_channel.chan_bustype = &scsi_bustype; 697 1.2.2.2 tron sc->sc_channel.chan_channel = 0; 698 1.2.2.2 tron sc->sc_channel.chan_ntargets = NJSC32_NTARGET; 699 1.2.2.2 tron sc->sc_channel.chan_nluns = NJSC32_NLU; 700 1.2.2.2 tron sc->sc_channel.chan_id = NJSC32_INITIATOR_ID; 701 1.2.2.2 tron 702 1.2.2.2 tron sc->sc_scsi = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 703 1.2.2.2 tron } 704 1.2.2.2 tron 705 1.2.2.2 tron int 706 1.2.2.3 tron njsc32_detach(struct njsc32_softc *sc, int flags) 707 1.2.2.2 tron { 708 1.2.2.2 tron int rv = 0; 709 1.2.2.2 tron int i, s; 710 1.2.2.2 tron struct njsc32_cmd *cmd; 711 1.2.2.2 tron 712 1.2.2.3.2.2 bouyer callout_stop(&sc->sc_callout); 713 1.2.2.3.2.2 bouyer 714 1.2.2.2 tron s = splbio(); 715 1.2.2.2 tron 716 1.2.2.2 tron /* clear running/disconnected commands */ 717 1.2.2.2 tron njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP); 718 1.2.2.2 tron 719 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_DETACH; 720 1.2.2.2 tron 721 1.2.2.2 tron /* clear pending commands */ 722 1.2.2.2 tron while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 723 1.2.2.2 tron TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 724 1.2.2.2 tron njsc32_end_cmd(sc, cmd, XS_RESET); 725 1.2.2.2 tron } 726 1.2.2.2 tron 727 1.2.2.2 tron if (sc->sc_scsi != NULL) 728 1.2.2.2 tron rv = config_detach(sc->sc_scsi, flags); 729 1.2.2.2 tron 730 1.2.2.2 tron splx(s); 731 1.2.2.2 tron 732 1.2.2.2 tron /* free DMA resource */ 733 1.2.2.2 tron if (sc->sc_flags & NJSC32_CMDPG_MAPPED) { 734 1.2.2.2 tron for (i = 0; i < sc->sc_ncmd; i++) { 735 1.2.2.2 tron cmd = &sc->sc_cmds[i]; 736 1.2.2.2 tron if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) 737 1.2.2.2 tron bus_dmamap_unload(sc->sc_dmat, 738 1.2.2.2 tron cmd->c_dmamap_xfer); 739 1.2.2.2 tron bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer); 740 1.2.2.2 tron } 741 1.2.2.2 tron 742 1.2.2.2 tron bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 743 1.2.2.2 tron bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 744 1.2.2.2 tron bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg, 745 1.2.2.2 tron sizeof(struct njsc32_dma_page)); 746 1.2.2.2 tron bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, 747 1.2.2.2 tron sc->sc_cmdpg_nsegs); 748 1.2.2.2 tron } 749 1.2.2.2 tron 750 1.2.2.2 tron return 0; 751 1.2.2.2 tron } 752 1.2.2.2 tron 753 1.2.2.2 tron static __inline void 754 1.2.2.3 tron njsc32_cmd_init(struct njsc32_cmd *cmd) 755 1.2.2.2 tron { 756 1.2.2.2 tron 757 1.2.2.2 tron cmd->c_flags = 0; 758 1.2.2.2 tron 759 1.2.2.2 tron /* scatter/gather table */ 760 1.2.2.2 tron cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0); 761 1.2.2.2 tron cmd->c_sgoffset = 0; 762 1.2.2.2 tron cmd->c_sgfixcnt = 0; 763 1.2.2.2 tron 764 1.2.2.2 tron /* data pointer */ 765 1.2.2.2 tron cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0; 766 1.2.2.2 tron } 767 1.2.2.2 tron 768 1.2.2.2 tron static __inline void 769 1.2.2.3 tron njsc32_init_msgout(struct njsc32_softc *sc) 770 1.2.2.2 tron { 771 1.2.2.2 tron 772 1.2.2.2 tron sc->sc_msgoutlen = 0; 773 1.2.2.2 tron sc->sc_msgoutidx = 0; 774 1.2.2.2 tron } 775 1.2.2.2 tron 776 1.2.2.2 tron static void 777 1.2.2.3 tron njsc32_add_msgout(struct njsc32_softc *sc, int byte) 778 1.2.2.2 tron { 779 1.2.2.2 tron 780 1.2.2.2 tron if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) { 781 1.2.2.2 tron printf("njsc32_add_msgout: too many\n"); 782 1.2.2.2 tron return; 783 1.2.2.2 tron } 784 1.2.2.2 tron sc->sc_msgout[sc->sc_msgoutlen++] = byte; 785 1.2.2.2 tron } 786 1.2.2.2 tron 787 1.2.2.2 tron static u_int32_t 788 1.2.2.3 tron njsc32_get_auto_msgout(struct njsc32_softc *sc) 789 1.2.2.2 tron { 790 1.2.2.2 tron u_int32_t val; 791 1.2.2.2 tron u_int8_t *p; 792 1.2.2.2 tron 793 1.2.2.2 tron val = 0; 794 1.2.2.2 tron p = sc->sc_msgout; 795 1.2.2.2 tron switch (sc->sc_msgoutlen) { 796 1.2.2.2 tron /* 31-24 23-16 15-8 7 ... 1 0 */ 797 1.2.2.2 tron case 3: /* MSG3 MSG2 MSG1 V --- cnt */ 798 1.2.2.2 tron val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT; 799 1.2.2.2 tron /* FALLTHROUGH */ 800 1.2.2.2 tron 801 1.2.2.2 tron case 2: /* MSG2 MSG1 --- V --- cnt */ 802 1.2.2.2 tron val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT; 803 1.2.2.2 tron /* FALLTHROUGH */ 804 1.2.2.2 tron 805 1.2.2.2 tron case 1: /* MSG1 --- --- V --- cnt */ 806 1.2.2.2 tron val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT; 807 1.2.2.2 tron val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen; 808 1.2.2.2 tron break; 809 1.2.2.2 tron 810 1.2.2.2 tron default: 811 1.2.2.2 tron break; 812 1.2.2.2 tron } 813 1.2.2.2 tron return val; 814 1.2.2.2 tron } 815 1.2.2.2 tron 816 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 817 1.2.2.2 tron /* add Wide Data Transfer Request to the next Message Out */ 818 1.2.2.2 tron static void 819 1.2.2.3 tron njsc32_msgout_wdtr(struct njsc32_softc *sc, int width) 820 1.2.2.2 tron { 821 1.2.2.2 tron 822 1.2.2.2 tron njsc32_add_msgout(sc, MSG_EXTENDED); 823 1.2.2.2 tron njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN); 824 1.2.2.2 tron njsc32_add_msgout(sc, MSG_EXT_WDTR); 825 1.2.2.2 tron njsc32_add_msgout(sc, width); 826 1.2.2.2 tron } 827 1.2.2.2 tron #endif 828 1.2.2.2 tron 829 1.2.2.2 tron /* add Synchronous Data Transfer Request to the next Message Out */ 830 1.2.2.2 tron static void 831 1.2.2.3 tron njsc32_msgout_sdtr(struct njsc32_softc *sc, int period, int offset) 832 1.2.2.2 tron { 833 1.2.2.2 tron 834 1.2.2.2 tron njsc32_add_msgout(sc, MSG_EXTENDED); 835 1.2.2.2 tron njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN); 836 1.2.2.2 tron njsc32_add_msgout(sc, MSG_EXT_SDTR); 837 1.2.2.2 tron njsc32_add_msgout(sc, period); 838 1.2.2.2 tron njsc32_add_msgout(sc, offset); 839 1.2.2.2 tron } 840 1.2.2.2 tron 841 1.2.2.2 tron static void 842 1.2.2.3 tron njsc32_negotiate_xfer(struct njsc32_softc *sc, struct njsc32_target *target) 843 1.2.2.2 tron { 844 1.2.2.2 tron 845 1.2.2.2 tron /* initial negotiation state */ 846 1.2.2.2 tron if (target->t_state == NJSC32_TARST_INIT) { 847 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 848 1.2.2.2 tron if (target->t_flags & NJSC32_TARF_DE) 849 1.2.2.2 tron target->t_state = NJSC32_TARST_DE; 850 1.2.2.2 tron else 851 1.2.2.2 tron #endif 852 1.2.2.2 tron if (target->t_flags & NJSC32_TARF_SYNC) 853 1.2.2.2 tron target->t_state = NJSC32_TARST_SDTR; 854 1.2.2.2 tron else 855 1.2.2.2 tron target->t_state = NJSC32_TARST_DONE; 856 1.2.2.2 tron } 857 1.2.2.2 tron 858 1.2.2.2 tron switch (target->t_state) { 859 1.2.2.2 tron default: 860 1.2.2.2 tron case NJSC32_TARST_INIT: 861 1.2.2.2 tron #ifdef DIAGNOSTIC 862 1.2.2.2 tron panic("njsc32_negotiate_xfer"); 863 1.2.2.2 tron /* NOTREACHED */ 864 1.2.2.2 tron #endif 865 1.2.2.2 tron /* FALLTHROUGH */ 866 1.2.2.2 tron case NJSC32_TARST_DONE: 867 1.2.2.2 tron /* no more work */ 868 1.2.2.2 tron break; 869 1.2.2.2 tron 870 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 871 1.2.2.2 tron case NJSC32_TARST_DE: 872 1.2.2.2 tron njsc32_msgout_wdtr(sc, 0xde /* XXX? */); 873 1.2.2.2 tron break; 874 1.2.2.2 tron 875 1.2.2.2 tron case NJSC32_TARST_WDTR: 876 1.2.2.2 tron njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT); 877 1.2.2.2 tron break; 878 1.2.2.2 tron #endif 879 1.2.2.2 tron 880 1.2.2.2 tron case NJSC32_TARST_SDTR: 881 1.2.2.2 tron njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period, 882 1.2.2.2 tron NJSC32_SYNCOFFSET_MAX); 883 1.2.2.2 tron break; 884 1.2.2.2 tron 885 1.2.2.2 tron case NJSC32_TARST_ASYNC: 886 1.2.2.2 tron njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC, 887 1.2.2.2 tron NJSC32_SYNCOFFSET_ASYNC); 888 1.2.2.2 tron break; 889 1.2.2.2 tron } 890 1.2.2.2 tron } 891 1.2.2.2 tron 892 1.2.2.2 tron /* turn LED on */ 893 1.2.2.2 tron static __inline void 894 1.2.2.3 tron njsc32_led_on(struct njsc32_softc *sc) 895 1.2.2.2 tron { 896 1.2.2.2 tron 897 1.2.2.2 tron njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON); 898 1.2.2.2 tron } 899 1.2.2.2 tron 900 1.2.2.2 tron /* turn LED off */ 901 1.2.2.2 tron static __inline void 902 1.2.2.3 tron njsc32_led_off(struct njsc32_softc *sc) 903 1.2.2.2 tron { 904 1.2.2.2 tron 905 1.2.2.2 tron njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF); 906 1.2.2.2 tron } 907 1.2.2.2 tron 908 1.2.2.2 tron static void 909 1.2.2.3 tron njsc32_arbitration_failed(struct njsc32_softc *sc) 910 1.2.2.2 tron { 911 1.2.2.2 tron struct njsc32_cmd *cmd; 912 1.2.2.2 tron 913 1.2.2.2 tron if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT) 914 1.2.2.2 tron return; 915 1.2.2.2 tron 916 1.2.2.2 tron if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) 917 1.2.2.2 tron callout_stop(&cmd->c_xs->xs_callout); 918 1.2.2.2 tron 919 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_IDLE; 920 1.2.2.2 tron sc->sc_curcmd = NULL; 921 1.2.2.2 tron 922 1.2.2.2 tron /* the command is no longer active */ 923 1.2.2.2 tron if (--sc->sc_nusedcmds == 0) 924 1.2.2.2 tron njsc32_led_off(sc); 925 1.2.2.2 tron } 926 1.2.2.2 tron 927 1.2.2.2 tron static __inline void 928 1.2.2.3 tron njsc32_cmd_load(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 929 1.2.2.2 tron { 930 1.2.2.2 tron struct njsc32_target *target; 931 1.2.2.2 tron struct scsipi_xfer *xs; 932 1.2.2.2 tron int i, control, lun; 933 1.2.2.2 tron u_int32_t msgoutreg; 934 1.2.2.2 tron #ifdef NJSC32_AUTOPARAM 935 1.2.2.2 tron struct njsc32_autoparam *ap; 936 1.2.2.2 tron #endif 937 1.2.2.2 tron 938 1.2.2.2 tron xs = cmd->c_xs; 939 1.2.2.2 tron #ifdef NJSC32_AUTOPARAM 940 1.2.2.2 tron ap = &sc->sc_cmdpg->dp_ap; 941 1.2.2.2 tron #else 942 1.2.2.2 tron /* reset CDB pointer */ 943 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR); 944 1.2.2.2 tron #endif 945 1.2.2.2 tron 946 1.2.2.2 tron /* CDB */ 947 1.2.2.2 tron TPRINTC(cmd, ("njsc32_cmd_load: CDB")); 948 1.2.2.2 tron for (i = 0; i < xs->cmdlen; i++) { 949 1.2.2.2 tron #ifdef NJSC32_AUTOPARAM 950 1.2.2.2 tron ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i]; 951 1.2.2.2 tron #else 952 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA, 953 1.2.2.2 tron ((u_int8_t *)xs->cmd)[i]); 954 1.2.2.2 tron #endif 955 1.2.2.2 tron TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i])); 956 1.2.2.2 tron } 957 1.2.2.2 tron #ifdef NJSC32_AUTOPARAM /* XXX needed? */ 958 1.2.2.2 tron for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++) 959 1.2.2.2 tron ap->ap_cdb[i].cdb_data = 0; 960 1.2.2.2 tron #endif 961 1.2.2.2 tron 962 1.2.2.2 tron control = xs->xs_control; 963 1.2.2.2 tron 964 1.2.2.2 tron /* 965 1.2.2.2 tron * Message Out 966 1.2.2.2 tron */ 967 1.2.2.2 tron njsc32_init_msgout(sc); 968 1.2.2.2 tron 969 1.2.2.2 tron /* Identify */ 970 1.2.2.2 tron lun = xs->xs_periph->periph_lun; 971 1.2.2.2 tron njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ? 972 1.2.2.2 tron MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1)); 973 1.2.2.2 tron 974 1.2.2.2 tron /* tagged queueing */ 975 1.2.2.2 tron if (control & XS_CTL_TAGMASK) { 976 1.2.2.2 tron njsc32_add_msgout(sc, xs->xs_tag_type); 977 1.2.2.2 tron njsc32_add_msgout(sc, xs->xs_tag_id); 978 1.2.2.2 tron TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id)); 979 1.2.2.2 tron } 980 1.2.2.2 tron TPRINTF(("\n")); 981 1.2.2.2 tron 982 1.2.2.2 tron target = cmd->c_target; 983 1.2.2.2 tron 984 1.2.2.2 tron /* transfer negotiation */ 985 1.2.2.2 tron if (control & XS_CTL_REQSENSE) 986 1.2.2.2 tron target->t_state = NJSC32_TARST_INIT; 987 1.2.2.2 tron njsc32_negotiate_xfer(sc, target); 988 1.2.2.2 tron 989 1.2.2.2 tron msgoutreg = njsc32_get_auto_msgout(sc); 990 1.2.2.2 tron 991 1.2.2.2 tron #ifdef NJSC32_AUTOPARAM 992 1.2.2.2 tron ap->ap_msgout = htole32(msgoutreg); 993 1.2.2.2 tron 994 1.2.2.2 tron ap->ap_sync = target->t_sync; 995 1.2.2.2 tron ap->ap_ackwidth = target->t_ackwidth; 996 1.2.2.2 tron ap->ap_targetid = target->t_targetid; 997 1.2.2.2 tron ap->ap_sample = target->t_sample; 998 1.2.2.2 tron 999 1.2.2.2 tron ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 1000 1.2.2.2 tron NJSC32_CMD_AUTO_COMMAND_PHASE | 1001 1.2.2.2 tron NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1002 1.2.2.2 tron NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1003 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 1004 1.2.2.2 tron ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl); 1005 1.2.2.2 tron #else 1006 1.2.2.2 tron ap->ap_xferctl = htole16(cmd->c_xferctl); 1007 1.2.2.2 tron #endif 1008 1.2.2.2 tron ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr); 1009 1.2.2.2 tron 1010 1.2.2.2 tron /* sync njsc32_autoparam */ 1011 1.2.2.2 tron bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1012 1.2.2.2 tron offsetof(struct njsc32_dma_page, dp_ap), /* offset */ 1013 1.2.2.2 tron sizeof(struct njsc32_autoparam), 1014 1.2.2.2 tron BUS_DMASYNC_PREWRITE); 1015 1.2.2.2 tron 1016 1.2.2.2 tron /* autoparam DMA address */ 1017 1.2.2.2 tron njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma); 1018 1.2.2.2 tron 1019 1.2.2.2 tron /* start command (autoparam) */ 1020 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1021 1.2.2.2 tron NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER); 1022 1.2.2.2 tron 1023 1.2.2.2 tron #else /* not NJSC32_AUTOPARAM */ 1024 1.2.2.2 tron 1025 1.2.2.2 tron njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg); 1026 1.2.2.2 tron 1027 1.2.2.2 tron /* load parameters */ 1028 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid); 1029 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1030 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1031 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1032 1.2.2.2 tron njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1033 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 1034 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1035 1.2.2.2 tron cmd->c_xferctl | target->t_xferctl); 1036 1.2.2.2 tron #else 1037 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1038 1.2.2.2 tron #endif 1039 1.2.2.2 tron /* start AutoSCSI */ 1040 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1041 1.2.2.2 tron NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE | 1042 1.2.2.2 tron NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1043 1.2.2.2 tron NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1044 1.2.2.2 tron #endif /* not NJSC32_AUTOPARAM */ 1045 1.2.2.2 tron } 1046 1.2.2.2 tron 1047 1.2.2.2 tron /* Note: must be called at splbio() */ 1048 1.2.2.2 tron static void 1049 1.2.2.3 tron njsc32_start(struct njsc32_softc *sc) 1050 1.2.2.2 tron { 1051 1.2.2.2 tron struct njsc32_cmd *cmd; 1052 1.2.2.2 tron 1053 1.2.2.2 tron /* get a command to issue */ 1054 1.2.2.2 tron TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) { 1055 1.2.2.2 tron if (cmd->c_lu->lu_cmd == NULL && 1056 1.2.2.2 tron ((cmd->c_flags & NJSC32_CMD_TAGGED) || 1057 1.2.2.2 tron TAILQ_EMPTY(&cmd->c_lu->lu_q))) 1058 1.2.2.2 tron break; /* OK, the logical unit is free */ 1059 1.2.2.2 tron } 1060 1.2.2.2 tron if (!cmd) 1061 1.2.2.2 tron goto out; /* no work to do */ 1062 1.2.2.2 tron 1063 1.2.2.2 tron /* request will always fail if not in bus free phase */ 1064 1.2.2.2 tron if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) != 1065 1.2.2.2 tron NJSC32_BUSMON_BUSFREE) 1066 1.2.2.2 tron goto busy; 1067 1.2.2.2 tron 1068 1.2.2.2 tron /* clear parity error and enable parity detection */ 1069 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1070 1.2.2.2 tron NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1071 1.2.2.2 tron 1072 1.2.2.2 tron njsc32_cmd_load(sc, cmd); 1073 1.2.2.2 tron 1074 1.2.2.2 tron if (sc->sc_nusedcmds++ == 0) 1075 1.2.2.2 tron njsc32_led_on(sc); 1076 1.2.2.2 tron 1077 1.2.2.2 tron sc->sc_curcmd = cmd; 1078 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_ARBIT; 1079 1.2.2.2 tron 1080 1.2.2.2 tron if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) { 1081 1.2.2.2 tron callout_reset(&cmd->c_xs->xs_callout, 1082 1.2.2.2 tron mstohz(cmd->c_xs->timeout), 1083 1.2.2.2 tron njsc32_cmdtimeout, cmd); 1084 1.2.2.2 tron } 1085 1.2.2.2 tron 1086 1.2.2.2 tron return; 1087 1.2.2.2 tron 1088 1.2.2.2 tron busy: /* XXX retry counter */ 1089 1.2.2.2 tron TPRINTF(("%s: njsc32_start: busy\n", sc->sc_dev.dv_xname)); 1090 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME); 1091 1.2.2.2 tron out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 1092 1.2.2.2 tron } 1093 1.2.2.2 tron 1094 1.2.2.2 tron static void 1095 1.2.2.3 tron njsc32_run_xfer(struct njsc32_softc *sc, struct scsipi_xfer *xs) 1096 1.2.2.2 tron { 1097 1.2.2.2 tron struct scsipi_periph *periph; 1098 1.2.2.2 tron int control; 1099 1.2.2.2 tron int lun; 1100 1.2.2.2 tron struct njsc32_cmd *cmd; 1101 1.2.2.2 tron int s, i, error; 1102 1.2.2.2 tron 1103 1.2.2.2 tron periph = xs->xs_periph; 1104 1.2.2.2 tron KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID); 1105 1.2.2.2 tron 1106 1.2.2.2 tron control = xs->xs_control; 1107 1.2.2.2 tron lun = periph->periph_lun; 1108 1.2.2.2 tron 1109 1.2.2.2 tron /* 1110 1.2.2.2 tron * get a free cmd 1111 1.2.2.2 tron * (scsipi layer knows the number of cmds, so this shall never fail) 1112 1.2.2.2 tron */ 1113 1.2.2.2 tron s = splbio(); 1114 1.2.2.2 tron cmd = TAILQ_FIRST(&sc->sc_freecmd); 1115 1.2.2.2 tron KASSERT(cmd); 1116 1.2.2.2 tron TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q); 1117 1.2.2.2 tron splx(s); 1118 1.2.2.2 tron 1119 1.2.2.2 tron /* 1120 1.2.2.2 tron * build a request 1121 1.2.2.2 tron */ 1122 1.2.2.2 tron njsc32_cmd_init(cmd); 1123 1.2.2.2 tron cmd->c_xs = xs; 1124 1.2.2.2 tron cmd->c_target = &sc->sc_targets[periph->periph_target]; 1125 1.2.2.2 tron cmd->c_lu = &cmd->c_target->t_lus[lun]; 1126 1.2.2.2 tron 1127 1.2.2.2 tron /* tagged queueing */ 1128 1.2.2.2 tron if (control & XS_CTL_TAGMASK) { 1129 1.2.2.2 tron cmd->c_flags |= NJSC32_CMD_TAGGED; 1130 1.2.2.2 tron if (control & XS_CTL_HEAD_TAG) 1131 1.2.2.2 tron cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD; 1132 1.2.2.2 tron } 1133 1.2.2.2 tron 1134 1.2.2.2 tron /* map DMA buffer */ 1135 1.2.2.2 tron cmd->c_datacnt = xs->datalen; 1136 1.2.2.2 tron if (xs->datalen) { 1137 1.2.2.2 tron /* Is XS_CTL_DATA_UIO ever used anywhere? */ 1138 1.2.2.2 tron KASSERT((control & XS_CTL_DATA_UIO) == 0); 1139 1.2.2.2 tron 1140 1.2.2.2 tron error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer, 1141 1.2.2.2 tron xs->data, xs->datalen, NULL, 1142 1.2.2.2 tron ((control & XS_CTL_NOSLEEP) ? 1143 1.2.2.2 tron BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 1144 1.2.2.2 tron BUS_DMA_STREAMING | 1145 1.2.2.2 tron ((control & XS_CTL_DATA_IN) ? 1146 1.2.2.2 tron BUS_DMA_READ : BUS_DMA_WRITE)); 1147 1.2.2.2 tron 1148 1.2.2.2 tron switch (error) { 1149 1.2.2.2 tron case 0: 1150 1.2.2.2 tron break; 1151 1.2.2.2 tron case ENOMEM: 1152 1.2.2.2 tron case EAGAIN: 1153 1.2.2.2 tron xs->error = XS_RESOURCE_SHORTAGE; 1154 1.2.2.2 tron goto map_failed; 1155 1.2.2.2 tron default: 1156 1.2.2.2 tron xs->error = XS_DRIVER_STUFFUP; 1157 1.2.2.2 tron map_failed: 1158 1.2.2.2 tron printf("%s: njsc32_run_xfer: map failed, error %d\n", 1159 1.2.2.2 tron sc->sc_dev.dv_xname, error); 1160 1.2.2.2 tron /* put it back to free command list */ 1161 1.2.2.2 tron s = splbio(); 1162 1.2.2.2 tron TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1163 1.2.2.2 tron splx(s); 1164 1.2.2.2 tron /* abort this transfer */ 1165 1.2.2.2 tron scsipi_done(xs); 1166 1.2.2.2 tron return; 1167 1.2.2.2 tron } 1168 1.2.2.2 tron 1169 1.2.2.2 tron bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1170 1.2.2.2 tron 0, cmd->c_dmamap_xfer->dm_mapsize, 1171 1.2.2.2 tron (control & XS_CTL_DATA_IN) ? 1172 1.2.2.2 tron BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1173 1.2.2.2 tron 1174 1.2.2.2 tron for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) { 1175 1.2.2.2 tron cmd->c_sgt[i].sg_addr = 1176 1.2.2.2 tron htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr); 1177 1.2.2.2 tron cmd->c_sgt[i].sg_len = 1178 1.2.2.2 tron htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len); 1179 1.2.2.2 tron } 1180 1.2.2.2 tron /* end mark */ 1181 1.2.2.2 tron cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK); 1182 1.2.2.2 tron 1183 1.2.2.2 tron bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1184 1.2.2.2 tron (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1185 1.2.2.2 tron NJSC32_SIZE_SGT, 1186 1.2.2.2 tron BUS_DMASYNC_PREWRITE); 1187 1.2.2.2 tron 1188 1.2.2.2 tron cmd->c_flags |= NJSC32_CMD_DMA_MAPPED; 1189 1.2.2.2 tron 1190 1.2.2.2 tron /* enable transfer */ 1191 1.2.2.2 tron cmd->c_xferctl = 1192 1.2.2.2 tron NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START | 1193 1.2.2.2 tron NJSC32_XFR_ALL_COUNT_CLR; 1194 1.2.2.2 tron 1195 1.2.2.2 tron /* XXX How can we specify the DMA direction? */ 1196 1.2.2.2 tron 1197 1.2.2.2 tron #if 0 /* faster write mode? (doesn't work) */ 1198 1.2.2.2 tron if ((control & XS_CTL_DATA_IN) == 0) 1199 1.2.2.2 tron cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE; 1200 1.2.2.2 tron #endif 1201 1.2.2.2 tron } else { 1202 1.2.2.2 tron /* no data transfer */ 1203 1.2.2.2 tron cmd->c_xferctl = 0; 1204 1.2.2.2 tron } 1205 1.2.2.2 tron 1206 1.2.2.2 tron /* queue request */ 1207 1.2.2.2 tron s = splbio(); 1208 1.2.2.2 tron TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q); 1209 1.2.2.2 tron 1210 1.2.2.2 tron /* start the controller if idle */ 1211 1.2.2.2 tron if (sc->sc_stat == NJSC32_STAT_IDLE) 1212 1.2.2.2 tron njsc32_start(sc); 1213 1.2.2.2 tron 1214 1.2.2.2 tron splx(s); 1215 1.2.2.2 tron 1216 1.2.2.2 tron if (control & XS_CTL_POLL) { 1217 1.2.2.2 tron /* wait for completion */ 1218 1.2.2.2 tron /* XXX should handle timeout? */ 1219 1.2.2.2 tron while ((xs->xs_status & XS_STS_DONE) == 0) { 1220 1.2.2.2 tron delay(1000); 1221 1.2.2.2 tron njsc32_intr(sc); 1222 1.2.2.2 tron } 1223 1.2.2.2 tron } 1224 1.2.2.2 tron } 1225 1.2.2.2 tron 1226 1.2.2.2 tron static void 1227 1.2.2.3 tron njsc32_end_cmd(struct njsc32_softc *sc, struct njsc32_cmd *cmd, 1228 1.2.2.3 tron scsipi_xfer_result_t result) 1229 1.2.2.2 tron { 1230 1.2.2.2 tron struct scsipi_xfer *xs; 1231 1.2.2.2 tron int s; 1232 1.2.2.2 tron #ifdef DIAGNOSTIC 1233 1.2.2.2 tron struct njsc32_cmd *c; 1234 1.2.2.2 tron #endif 1235 1.2.2.2 tron 1236 1.2.2.2 tron KASSERT(cmd); 1237 1.2.2.2 tron 1238 1.2.2.2 tron #ifdef DIAGNOSTIC 1239 1.2.2.2 tron s = splbio(); 1240 1.2.2.2 tron TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) { 1241 1.2.2.2 tron if (cmd == c) 1242 1.2.2.2 tron panic("njsc32_end_cmd: already in free list"); 1243 1.2.2.2 tron } 1244 1.2.2.2 tron splx(s); 1245 1.2.2.2 tron #endif 1246 1.2.2.2 tron xs = cmd->c_xs; 1247 1.2.2.2 tron 1248 1.2.2.2 tron if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) { 1249 1.2.2.2 tron if (cmd->c_datacnt) { 1250 1.2.2.2 tron bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1251 1.2.2.2 tron 0, cmd->c_dmamap_xfer->dm_mapsize, 1252 1.2.2.2 tron (xs->xs_control & XS_CTL_DATA_IN) ? 1253 1.2.2.2 tron BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1254 1.2.2.2 tron 1255 1.2.2.2 tron bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1256 1.2.2.2 tron (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, 1257 1.2.2.2 tron NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE); 1258 1.2.2.2 tron } 1259 1.2.2.2 tron 1260 1.2.2.2 tron bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer); 1261 1.2.2.2 tron cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED; 1262 1.2.2.2 tron } 1263 1.2.2.2 tron 1264 1.2.2.2 tron s = splbio(); 1265 1.2.2.2 tron if ((xs->xs_control & XS_CTL_POLL) == 0) 1266 1.2.2.2 tron callout_stop(&xs->xs_callout); 1267 1.2.2.2 tron 1268 1.2.2.2 tron TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1269 1.2.2.2 tron splx(s); 1270 1.2.2.2 tron 1271 1.2.2.2 tron xs->error = result; 1272 1.2.2.2 tron scsipi_done(xs); 1273 1.2.2.2 tron 1274 1.2.2.2 tron if (--sc->sc_nusedcmds == 0) 1275 1.2.2.2 tron njsc32_led_off(sc); 1276 1.2.2.2 tron } 1277 1.2.2.2 tron 1278 1.2.2.2 tron /* 1279 1.2.2.2 tron * request from scsipi layer 1280 1.2.2.2 tron */ 1281 1.2.2.3 tron static void 1282 1.2.2.3 tron njsc32_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1283 1.2.2.3 tron void *arg) 1284 1.2.2.2 tron { 1285 1.2.2.2 tron struct njsc32_softc *sc; 1286 1.2.2.2 tron struct scsipi_xfer_mode *xm; 1287 1.2.2.2 tron struct njsc32_target *target; 1288 1.2.2.2 tron 1289 1.2.2.2 tron sc = (void *)chan->chan_adapter->adapt_dev; 1290 1.2.2.2 tron 1291 1.2.2.2 tron switch (req) { 1292 1.2.2.2 tron case ADAPTER_REQ_RUN_XFER: 1293 1.2.2.2 tron njsc32_run_xfer(sc, arg); 1294 1.2.2.2 tron break; 1295 1.2.2.2 tron 1296 1.2.2.2 tron case ADAPTER_REQ_GROW_RESOURCES: 1297 1.2.2.2 tron /* not supported */ 1298 1.2.2.2 tron break; 1299 1.2.2.2 tron 1300 1.2.2.2 tron case ADAPTER_REQ_SET_XFER_MODE: 1301 1.2.2.2 tron xm = arg; 1302 1.2.2.2 tron target = &sc->sc_targets[xm->xm_target]; 1303 1.2.2.2 tron 1304 1.2.2.2 tron target->t_flags = 0; 1305 1.2.2.2 tron if (xm->xm_mode & PERIPH_CAP_TQING) 1306 1.2.2.2 tron target->t_flags |= NJSC32_TARF_TAG; 1307 1.2.2.2 tron if (xm->xm_mode & PERIPH_CAP_SYNC) { 1308 1.2.2.2 tron target->t_flags |= NJSC32_TARF_SYNC; 1309 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 1310 1.2.2.2 tron if (sc->sc_model & NJSC32_FLAG_DUALEDGE) 1311 1.2.2.2 tron target->t_flags |= NJSC32_TARF_DE; 1312 1.2.2.2 tron #endif 1313 1.2.2.2 tron } 1314 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 1315 1.2.2.2 tron target->t_xferctl = 0; 1316 1.2.2.2 tron #endif 1317 1.2.2.2 tron target->t_state = NJSC32_TARST_INIT; 1318 1.2.2.2 tron njsc32_target_async(sc, target); 1319 1.2.2.2 tron 1320 1.2.2.2 tron break; 1321 1.2.2.2 tron default: 1322 1.2.2.2 tron break; 1323 1.2.2.2 tron } 1324 1.2.2.2 tron } 1325 1.2.2.2 tron 1326 1.2.2.3 tron static void 1327 1.2.2.3 tron njsc32_scsipi_minphys(struct buf *bp) 1328 1.2.2.2 tron { 1329 1.2.2.2 tron 1330 1.2.2.2 tron if (bp->b_bcount > NJSC32_MAX_XFER) 1331 1.2.2.2 tron bp->b_bcount = NJSC32_MAX_XFER; 1332 1.2.2.2 tron minphys(bp); 1333 1.2.2.2 tron } 1334 1.2.2.2 tron 1335 1.2.2.3.2.2 bouyer /* 1336 1.2.2.3.2.2 bouyer * On some versions of 32UDE (probably the earlier ones), the controller 1337 1.2.2.3.2.2 bouyer * detects continuous bus reset when the termination power is absent. 1338 1.2.2.3.2.2 bouyer * Make sure the system won't hang on such situation. 1339 1.2.2.3.2.2 bouyer */ 1340 1.2.2.3.2.2 bouyer static void 1341 1.2.2.3.2.2 bouyer njsc32_wait_reset_release(void *arg) 1342 1.2.2.3.2.2 bouyer { 1343 1.2.2.3.2.2 bouyer struct njsc32_softc *sc = arg; 1344 1.2.2.3.2.2 bouyer struct njsc32_cmd *cmd; 1345 1.2.2.3.2.2 bouyer 1346 1.2.2.3.2.2 bouyer /* clear pending commands */ 1347 1.2.2.3.2.2 bouyer while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 1348 1.2.2.3.2.2 bouyer TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 1349 1.2.2.3.2.2 bouyer njsc32_end_cmd(sc, cmd, XS_RESET); 1350 1.2.2.3.2.2 bouyer } 1351 1.2.2.3.2.2 bouyer 1352 1.2.2.3.2.2 bouyer /* If Bus Reset is not released yet, schedule recheck. */ 1353 1.2.2.3.2.2 bouyer if (njsc32_read_2(sc, NJSC32_REG_IRQ) & NJSC32_IRQ_SCSIRESET) { 1354 1.2.2.3.2.2 bouyer switch (sc->sc_stat) { 1355 1.2.2.3.2.2 bouyer case NJSC32_STAT_RESET: 1356 1.2.2.3.2.2 bouyer sc->sc_stat = NJSC32_STAT_RESET1; 1357 1.2.2.3.2.2 bouyer break; 1358 1.2.2.3.2.2 bouyer case NJSC32_STAT_RESET1: 1359 1.2.2.3.2.2 bouyer /* print message if Bus Reset is detected twice */ 1360 1.2.2.3.2.2 bouyer sc->sc_stat = NJSC32_STAT_RESET2; 1361 1.2.2.3.2.2 bouyer printf("%s: detected excessive bus reset --- missing termination power?\n", 1362 1.2.2.3.2.2 bouyer sc->sc_dev.dv_xname); 1363 1.2.2.3.2.2 bouyer break; 1364 1.2.2.3.2.2 bouyer default: 1365 1.2.2.3.2.2 bouyer break; 1366 1.2.2.3.2.2 bouyer } 1367 1.2.2.3.2.2 bouyer callout_reset(&sc->sc_callout, 1368 1.2.2.3.2.2 bouyer hz * 2 /* poll every 2s */, 1369 1.2.2.3.2.2 bouyer njsc32_wait_reset_release, sc); 1370 1.2.2.3.2.2 bouyer return; 1371 1.2.2.3.2.2 bouyer } 1372 1.2.2.3.2.2 bouyer 1373 1.2.2.3.2.2 bouyer if (sc->sc_stat == NJSC32_STAT_RESET2) 1374 1.2.2.3.2.2 bouyer printf("%s: bus reset is released\n", sc->sc_dev.dv_xname); 1375 1.2.2.3.2.2 bouyer 1376 1.2.2.3.2.2 bouyer /* unblock interrupts */ 1377 1.2.2.3.2.2 bouyer njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 1378 1.2.2.3.2.2 bouyer 1379 1.2.2.3.2.2 bouyer sc->sc_stat = NJSC32_STAT_IDLE; 1380 1.2.2.3.2.2 bouyer } 1381 1.2.2.3.2.2 bouyer 1382 1.2.2.2 tron static void 1383 1.2.2.3 tron njsc32_reset_bus(struct njsc32_softc *sc) 1384 1.2.2.2 tron { 1385 1.2.2.2 tron int s; 1386 1.2.2.2 tron 1387 1.2.2.2 tron DPRINTF(("%s: njsc32_reset_bus:\n", sc->sc_dev.dv_xname)); 1388 1.2.2.2 tron 1389 1.2.2.3.2.2 bouyer /* block interrupts */ 1390 1.2.2.3.2.2 bouyer njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 1391 1.2.2.3.2.2 bouyer 1392 1.2.2.3.2.2 bouyer sc->sc_stat = NJSC32_STAT_RESET; 1393 1.2.2.3.2.2 bouyer 1394 1.2.2.3.2.2 bouyer /* hold SCSI bus reset */ 1395 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST); 1396 1.2.2.2 tron delay(NJSC32_RESET_HOLD_TIME); 1397 1.2.2.2 tron 1398 1.2.2.2 tron /* clear transfer */ 1399 1.2.2.3.2.2 bouyer njsc32_clear_cmds(sc, XS_RESET); 1400 1.2.2.3.2.2 bouyer 1401 1.2.2.3.2.2 bouyer /* initialize target structure */ 1402 1.2.2.3.2.2 bouyer njsc32_init_targets(sc); 1403 1.2.2.3.2.2 bouyer 1404 1.2.2.2 tron s = splbio(); 1405 1.2.2.3.2.2 bouyer scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL); 1406 1.2.2.2 tron splx(s); 1407 1.2.2.3.2.2 bouyer 1408 1.2.2.3.2.2 bouyer /* release SCSI bus reset */ 1409 1.2.2.3.2.2 bouyer njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0); 1410 1.2.2.3.2.2 bouyer 1411 1.2.2.3.2.2 bouyer njsc32_wait_reset_release(sc); 1412 1.2.2.2 tron } 1413 1.2.2.2 tron 1414 1.2.2.2 tron /* 1415 1.2.2.2 tron * clear running/disconnected commands 1416 1.2.2.2 tron */ 1417 1.2.2.2 tron static void 1418 1.2.2.3 tron njsc32_clear_cmds(struct njsc32_softc *sc, scsipi_xfer_result_t cmdresult) 1419 1.2.2.2 tron { 1420 1.2.2.2 tron struct njsc32_cmd *cmd; 1421 1.2.2.2 tron int id, lun; 1422 1.2.2.2 tron struct njsc32_lu *lu; 1423 1.2.2.2 tron 1424 1.2.2.2 tron njsc32_arbitration_failed(sc); 1425 1.2.2.2 tron 1426 1.2.2.2 tron /* clear current transfer */ 1427 1.2.2.2 tron if ((cmd = sc->sc_curcmd) != NULL) { 1428 1.2.2.2 tron sc->sc_curcmd = NULL; 1429 1.2.2.2 tron njsc32_end_cmd(sc, cmd, cmdresult); 1430 1.2.2.2 tron } 1431 1.2.2.2 tron 1432 1.2.2.2 tron /* clear disconnected transfers */ 1433 1.2.2.2 tron for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 1434 1.2.2.2 tron for (lun = 0; lun < NJSC32_NLU; lun++) { 1435 1.2.2.2 tron lu = &sc->sc_targets[id].t_lus[lun]; 1436 1.2.2.2 tron 1437 1.2.2.2 tron if ((cmd = lu->lu_cmd) != NULL) { 1438 1.2.2.2 tron lu->lu_cmd = NULL; 1439 1.2.2.2 tron njsc32_end_cmd(sc, cmd, cmdresult); 1440 1.2.2.2 tron } 1441 1.2.2.2 tron while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) { 1442 1.2.2.2 tron TAILQ_REMOVE(&lu->lu_q, cmd, c_q); 1443 1.2.2.2 tron njsc32_end_cmd(sc, cmd, cmdresult); 1444 1.2.2.2 tron } 1445 1.2.2.2 tron } 1446 1.2.2.2 tron } 1447 1.2.2.2 tron } 1448 1.2.2.2 tron 1449 1.2.2.3 tron static int 1450 1.2.2.3 tron njsc32_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd, caddr_t addr, 1451 1.2.2.3 tron int flag, struct proc *p) 1452 1.2.2.2 tron { 1453 1.2.2.2 tron struct njsc32_softc *sc = (void *)chan->chan_adapter->adapt_dev; 1454 1.2.2.2 tron 1455 1.2.2.2 tron switch (cmd) { 1456 1.2.2.2 tron case SCBUSIORESET: 1457 1.2.2.2 tron njsc32_init(sc, 0); 1458 1.2.2.2 tron return 0; 1459 1.2.2.2 tron default: 1460 1.2.2.2 tron break; 1461 1.2.2.2 tron } 1462 1.2.2.2 tron 1463 1.2.2.2 tron return ENOTTY; 1464 1.2.2.2 tron } 1465 1.2.2.2 tron 1466 1.2.2.2 tron /* 1467 1.2.2.2 tron * set current data pointer 1468 1.2.2.2 tron */ 1469 1.2.2.2 tron static __inline void 1470 1.2.2.3 tron njsc32_set_cur_ptr(struct njsc32_cmd *cmd, u_int32_t pos) 1471 1.2.2.2 tron { 1472 1.2.2.2 tron 1473 1.2.2.2 tron /* new current data pointer */ 1474 1.2.2.2 tron cmd->c_dp_cur = pos; 1475 1.2.2.2 tron 1476 1.2.2.2 tron /* update number of bytes transferred */ 1477 1.2.2.2 tron if (pos > cmd->c_dp_max) 1478 1.2.2.2 tron cmd->c_dp_max = pos; 1479 1.2.2.2 tron } 1480 1.2.2.2 tron 1481 1.2.2.2 tron /* 1482 1.2.2.2 tron * set data pointer for the next transfer 1483 1.2.2.2 tron */ 1484 1.2.2.2 tron static void 1485 1.2.2.3 tron njsc32_set_ptr(struct njsc32_softc *sc, struct njsc32_cmd *cmd, u_int32_t pos) 1486 1.2.2.2 tron { 1487 1.2.2.2 tron struct njsc32_sgtable *sg; 1488 1.2.2.2 tron unsigned sgte; 1489 1.2.2.2 tron u_int32_t len; 1490 1.2.2.2 tron 1491 1.2.2.2 tron /* set current pointer */ 1492 1.2.2.2 tron njsc32_set_cur_ptr(cmd, pos); 1493 1.2.2.2 tron 1494 1.2.2.2 tron /* undo previous fix if any */ 1495 1.2.2.2 tron if (cmd->c_sgfixcnt != 0) { 1496 1.2.2.2 tron sg = &cmd->c_sgt[cmd->c_sgoffset]; 1497 1.2.2.2 tron sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt); 1498 1.2.2.2 tron sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt); 1499 1.2.2.2 tron cmd->c_sgfixcnt = 0; 1500 1.2.2.2 tron } 1501 1.2.2.2 tron 1502 1.2.2.2 tron if (pos >= cmd->c_datacnt) { 1503 1.2.2.2 tron /* transfer done */ 1504 1.2.2.2 tron #if 1 /*def DIAGNOSTIC*/ 1505 1.2.2.2 tron if (pos > cmd->c_datacnt) 1506 1.2.2.2 tron printf("%s: pos %u too large\n", 1507 1.2.2.2 tron sc->sc_dev.dv_xname, pos - cmd->c_datacnt); 1508 1.2.2.2 tron #endif 1509 1.2.2.2 tron cmd->c_xferctl = 0; /* XXX correct? */ 1510 1.2.2.2 tron 1511 1.2.2.2 tron return; 1512 1.2.2.2 tron } 1513 1.2.2.2 tron 1514 1.2.2.2 tron for (sgte = 0, sg = cmd->c_sgt; 1515 1.2.2.2 tron sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) { 1516 1.2.2.2 tron len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK; 1517 1.2.2.2 tron if (pos < len) { 1518 1.2.2.2 tron sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos); 1519 1.2.2.2 tron sg->sg_len = htole32(le32toh(sg->sg_len) - pos); 1520 1.2.2.2 tron cmd->c_sgfixcnt = pos; 1521 1.2.2.2 tron break; 1522 1.2.2.2 tron } 1523 1.2.2.2 tron pos -= len; 1524 1.2.2.2 tron #ifdef DIAGNOSTIC 1525 1.2.2.2 tron if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) { 1526 1.2.2.2 tron panic("njsc32_set_ptr: bad pos"); 1527 1.2.2.2 tron } 1528 1.2.2.2 tron #endif 1529 1.2.2.2 tron } 1530 1.2.2.2 tron #ifdef DIAGNOSTIC 1531 1.2.2.2 tron if (sgte >= NJSC32_NUM_SG) 1532 1.2.2.2 tron panic("njsc32_set_ptr: bad sg"); 1533 1.2.2.2 tron #endif 1534 1.2.2.2 tron if (cmd->c_sgoffset != sgte) { 1535 1.2.2.2 tron cmd->c_sgoffset = sgte; 1536 1.2.2.2 tron cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte); 1537 1.2.2.2 tron } 1538 1.2.2.2 tron 1539 1.2.2.2 tron /* XXX overkill */ 1540 1.2.2.2 tron bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1541 1.2.2.2 tron (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1542 1.2.2.2 tron NJSC32_SIZE_SGT, 1543 1.2.2.2 tron BUS_DMASYNC_PREWRITE); 1544 1.2.2.2 tron } 1545 1.2.2.2 tron 1546 1.2.2.2 tron /* 1547 1.2.2.2 tron * save data pointer 1548 1.2.2.2 tron */ 1549 1.2.2.2 tron static __inline void 1550 1.2.2.3 tron njsc32_save_ptr(struct njsc32_cmd *cmd) 1551 1.2.2.2 tron { 1552 1.2.2.2 tron 1553 1.2.2.2 tron cmd->c_dp_saved = cmd->c_dp_cur; 1554 1.2.2.2 tron } 1555 1.2.2.2 tron 1556 1.2.2.2 tron static void 1557 1.2.2.3 tron njsc32_assert_ack(struct njsc32_softc *sc) 1558 1.2.2.2 tron { 1559 1.2.2.2 tron u_int8_t reg; 1560 1.2.2.2 tron 1561 1.2.2.2 tron reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1562 1.2.2.2 tron reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE; 1563 1.2.2.2 tron #if 0 /* needed? */ 1564 1.2.2.2 tron reg |= NJSC32_SBCTL_AUTODIRECTION; 1565 1.2.2.2 tron #endif 1566 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1567 1.2.2.2 tron } 1568 1.2.2.2 tron 1569 1.2.2.2 tron static void 1570 1.2.2.3 tron njsc32_negate_ack(struct njsc32_softc *sc) 1571 1.2.2.2 tron { 1572 1.2.2.2 tron u_int8_t reg; 1573 1.2.2.2 tron 1574 1.2.2.2 tron reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1575 1.2.2.2 tron #if 0 /* needed? */ 1576 1.2.2.2 tron reg |= NJSC32_SBCTL_ACK_ENABLE; 1577 1.2.2.2 tron reg |= NJSC32_SBCTL_AUTODIRECTION; 1578 1.2.2.2 tron #endif 1579 1.2.2.2 tron reg &= ~NJSC32_SBCTL_ACK; 1580 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1581 1.2.2.2 tron } 1582 1.2.2.2 tron 1583 1.2.2.2 tron static void 1584 1.2.2.3 tron njsc32_wait_req_negate(struct njsc32_softc *sc) 1585 1.2.2.2 tron { 1586 1.2.2.2 tron int cnt; 1587 1.2.2.2 tron 1588 1.2.2.2 tron for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) { 1589 1.2.2.2 tron if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 1590 1.2.2.2 tron NJSC32_BUSMON_REQ) == 0) 1591 1.2.2.2 tron return; 1592 1.2.2.2 tron delay(1); 1593 1.2.2.2 tron } 1594 1.2.2.2 tron printf("%s: njsc32_wait_req_negate: timed out\n", sc->sc_dev.dv_xname); 1595 1.2.2.2 tron } 1596 1.2.2.2 tron 1597 1.2.2.2 tron static void 1598 1.2.2.3 tron njsc32_reconnect(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 1599 1.2.2.2 tron { 1600 1.2.2.2 tron struct scsipi_xfer *xs; 1601 1.2.2.2 tron 1602 1.2.2.2 tron xs = cmd->c_xs; 1603 1.2.2.2 tron if ((xs->xs_control & XS_CTL_POLL) == 0) { 1604 1.2.2.2 tron callout_stop(&xs->xs_callout); 1605 1.2.2.2 tron callout_reset(&xs->xs_callout, 1606 1.2.2.2 tron mstohz(xs->timeout), 1607 1.2.2.2 tron njsc32_cmdtimeout, cmd); 1608 1.2.2.2 tron } 1609 1.2.2.2 tron 1610 1.2.2.2 tron /* Reconnection implies Restore Pointers */ 1611 1.2.2.2 tron njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1612 1.2.2.2 tron } 1613 1.2.2.2 tron 1614 1.2.2.2 tron static enum njsc32_reselstat 1615 1.2.2.3 tron njsc32_resel_identify(struct njsc32_softc *sc, int lun, 1616 1.2.2.3 tron struct njsc32_cmd **pcmd) 1617 1.2.2.2 tron { 1618 1.2.2.2 tron int targetid; 1619 1.2.2.2 tron struct njsc32_lu *plu; 1620 1.2.2.2 tron struct njsc32_cmd *cmd; 1621 1.2.2.2 tron 1622 1.2.2.2 tron switch (sc->sc_stat) { 1623 1.2.2.2 tron case NJSC32_STAT_RESEL: 1624 1.2.2.2 tron break; /* OK */ 1625 1.2.2.2 tron 1626 1.2.2.2 tron case NJSC32_STAT_RESEL_LUN: 1627 1.2.2.2 tron case NJSC32_STAT_RECONNECT: 1628 1.2.2.2 tron /* 1629 1.2.2.2 tron * accept and ignore if the LUN is the same as the current one, 1630 1.2.2.2 tron * reject otherwise. 1631 1.2.2.2 tron */ 1632 1.2.2.2 tron return sc->sc_resellun == lun ? 1633 1.2.2.2 tron NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR; 1634 1.2.2.2 tron 1635 1.2.2.2 tron default: 1636 1.2.2.2 tron printf("%s: njsc32_resel_identify: not in reselection\n", 1637 1.2.2.2 tron sc->sc_dev.dv_xname); 1638 1.2.2.2 tron return NJSC32_RESEL_ERROR; 1639 1.2.2.2 tron } 1640 1.2.2.2 tron 1641 1.2.2.2 tron targetid = sc->sc_reselid; 1642 1.2.2.2 tron TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n", 1643 1.2.2.2 tron sc->sc_dev.dv_xname, lun)); 1644 1.2.2.2 tron 1645 1.2.2.2 tron if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU) 1646 1.2.2.2 tron return NJSC32_RESEL_ERROR; 1647 1.2.2.2 tron 1648 1.2.2.2 tron sc->sc_resellun = lun; 1649 1.2.2.2 tron plu = &sc->sc_targets[targetid].t_lus[lun]; 1650 1.2.2.2 tron 1651 1.2.2.2 tron if ((cmd = plu->lu_cmd) != NULL) { 1652 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_RECONNECT; 1653 1.2.2.2 tron plu->lu_cmd = NULL; 1654 1.2.2.2 tron *pcmd = cmd; 1655 1.2.2.2 tron TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n")); 1656 1.2.2.2 tron njsc32_reconnect(sc, cmd); 1657 1.2.2.2 tron return NJSC32_RESEL_COMPLETE; 1658 1.2.2.2 tron } else if (!TAILQ_EMPTY(&plu->lu_q)) { 1659 1.2.2.2 tron /* wait for tag */ 1660 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_RESEL_LUN; 1661 1.2.2.2 tron return NJSC32_RESEL_THROUGH; 1662 1.2.2.2 tron } 1663 1.2.2.2 tron 1664 1.2.2.2 tron /* no disconnected commands */ 1665 1.2.2.2 tron return NJSC32_RESEL_ERROR; 1666 1.2.2.2 tron } 1667 1.2.2.2 tron 1668 1.2.2.2 tron static enum njsc32_reselstat 1669 1.2.2.3 tron njsc32_resel_tag(struct njsc32_softc *sc, int tag, struct njsc32_cmd **pcmd) 1670 1.2.2.2 tron { 1671 1.2.2.2 tron struct njsc32_cmd_head *head; 1672 1.2.2.2 tron struct njsc32_cmd *cmd; 1673 1.2.2.2 tron 1674 1.2.2.2 tron TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n", 1675 1.2.2.2 tron sc->sc_dev.dv_xname, tag)); 1676 1.2.2.2 tron if (sc->sc_stat != NJSC32_STAT_RESEL_LUN) 1677 1.2.2.2 tron return NJSC32_RESEL_ERROR; 1678 1.2.2.2 tron 1679 1.2.2.2 tron head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q; 1680 1.2.2.2 tron 1681 1.2.2.2 tron /* XXX slow? */ 1682 1.2.2.2 tron /* search for the command of the tag */ 1683 1.2.2.2 tron TAILQ_FOREACH(cmd, head, c_q) { 1684 1.2.2.2 tron if (cmd->c_xs->xs_tag_id == tag) { 1685 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_RECONNECT; 1686 1.2.2.2 tron TAILQ_REMOVE(head, cmd, c_q); 1687 1.2.2.2 tron *pcmd = cmd; 1688 1.2.2.2 tron TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n")); 1689 1.2.2.2 tron njsc32_reconnect(sc, cmd); 1690 1.2.2.2 tron return NJSC32_RESEL_COMPLETE; 1691 1.2.2.2 tron } 1692 1.2.2.2 tron } 1693 1.2.2.2 tron 1694 1.2.2.2 tron /* no disconnected commands */ 1695 1.2.2.2 tron return NJSC32_RESEL_ERROR; 1696 1.2.2.2 tron } 1697 1.2.2.2 tron 1698 1.2.2.2 tron /* 1699 1.2.2.2 tron * Reload parameters and restart AutoSCSI. 1700 1.2.2.2 tron * 1701 1.2.2.2 tron * XXX autoparam doesn't work as expected and we can't use it here. 1702 1.2.2.2 tron */ 1703 1.2.2.2 tron static void 1704 1.2.2.3 tron njsc32_cmd_reload(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int cctl) 1705 1.2.2.2 tron { 1706 1.2.2.2 tron struct njsc32_target *target; 1707 1.2.2.2 tron 1708 1.2.2.2 tron target = cmd->c_target; 1709 1.2.2.2 tron 1710 1.2.2.2 tron /* clear parity error and enable parity detection */ 1711 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1712 1.2.2.2 tron NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1713 1.2.2.2 tron 1714 1.2.2.2 tron /* load parameters */ 1715 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1716 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1717 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1718 1.2.2.2 tron njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1719 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 1720 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1721 1.2.2.2 tron cmd->c_xferctl | target->t_xferctl); 1722 1.2.2.2 tron #else 1723 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1724 1.2.2.2 tron #endif 1725 1.2.2.2 tron /* start AutoSCSI */ 1726 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 1727 1.2.2.2 tron 1728 1.2.2.2 tron sc->sc_curcmd = cmd; 1729 1.2.2.2 tron } 1730 1.2.2.2 tron 1731 1.2.2.2 tron static void 1732 1.2.2.3 tron njsc32_update_xfer_mode(struct njsc32_softc *sc, struct njsc32_target *target) 1733 1.2.2.2 tron { 1734 1.2.2.2 tron struct scsipi_xfer_mode xm; 1735 1.2.2.2 tron 1736 1.2.2.2 tron xm.xm_target = target - sc->sc_targets; /* target ID */ 1737 1.2.2.2 tron xm.xm_mode = 0; 1738 1.2.2.2 tron xm.xm_period = target->t_syncperiod; 1739 1.2.2.2 tron xm.xm_offset = target->t_syncoffset; 1740 1.2.2.2 tron if (xm.xm_offset != 0) 1741 1.2.2.2 tron xm.xm_mode |= PERIPH_CAP_SYNC; 1742 1.2.2.2 tron if (target->t_flags & NJSC32_TARF_TAG) 1743 1.2.2.2 tron xm.xm_mode |= PERIPH_CAP_TQING; 1744 1.2.2.2 tron 1745 1.2.2.2 tron scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 1746 1.2.2.2 tron } 1747 1.2.2.2 tron 1748 1.2.2.2 tron static void 1749 1.2.2.3 tron njsc32_msgin(struct njsc32_softc *sc) 1750 1.2.2.2 tron { 1751 1.2.2.2 tron u_int8_t msg0, msg; 1752 1.2.2.2 tron int msgcnt; 1753 1.2.2.2 tron struct njsc32_cmd *cmd; 1754 1.2.2.2 tron enum njsc32_reselstat rstat; 1755 1.2.2.2 tron int cctl = 0; 1756 1.2.2.2 tron u_int32_t ptr; /* unsigned type ensures 2-complement calculation */ 1757 1.2.2.2 tron u_int32_t msgout = 0; 1758 1.2.2.2 tron boolean_t reload_params = FALSE; 1759 1.2.2.2 tron struct njsc32_target *target; 1760 1.2.2.2 tron int idx, period, offset; 1761 1.2.2.2 tron 1762 1.2.2.2 tron /* 1763 1.2.2.2 tron * we are in Message In, so the previous Message Out should have 1764 1.2.2.2 tron * been done. 1765 1.2.2.2 tron */ 1766 1.2.2.2 tron njsc32_init_msgout(sc); 1767 1.2.2.2 tron 1768 1.2.2.2 tron /* get a byte of Message In */ 1769 1.2.2.2 tron msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN); 1770 1.2.2.2 tron TPRINTF(("%s: njsc32_msgin: got %#x\n", sc->sc_dev.dv_xname, msg)); 1771 1.2.2.2 tron if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN) 1772 1.2.2.2 tron sc->sc_msginbuf[sc->sc_msgincnt] = msg; 1773 1.2.2.2 tron 1774 1.2.2.2 tron njsc32_assert_ack(sc); 1775 1.2.2.2 tron 1776 1.2.2.2 tron msg0 = sc->sc_msginbuf[0]; 1777 1.2.2.2 tron cmd = sc->sc_curcmd; 1778 1.2.2.2 tron 1779 1.2.2.2 tron /* check for parity error */ 1780 1.2.2.2 tron if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 1781 1.2.2.2 tron NJSC32_PARITYSTATUS_ERROR_LSB) { 1782 1.2.2.2 tron 1783 1.2.2.2 tron printf("%s: msgin: parity error\n", sc->sc_dev.dv_xname); 1784 1.2.2.2 tron 1785 1.2.2.2 tron /* clear parity error */ 1786 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1787 1.2.2.2 tron NJSC32_PARITYCTL_CHECK_ENABLE | 1788 1.2.2.2 tron NJSC32_PARITYCTL_CLEAR_ERROR); 1789 1.2.2.2 tron 1790 1.2.2.2 tron /* respond as Message Parity Error */ 1791 1.2.2.2 tron njsc32_add_msgout(sc, MSG_PARITY_ERROR); 1792 1.2.2.2 tron 1793 1.2.2.2 tron /* clear Message In */ 1794 1.2.2.2 tron sc->sc_msgincnt = 0; 1795 1.2.2.2 tron goto reply; 1796 1.2.2.2 tron } 1797 1.2.2.2 tron 1798 1.2.2.2 tron #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0) 1799 1.2.2.2 tron #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0) 1800 1.2.2.2 tron if (MSG_ISIDENTIFY(msg0)) { 1801 1.2.2.2 tron /* 1802 1.2.2.2 tron * Got Identify message from target. 1803 1.2.2.2 tron */ 1804 1.2.2.2 tron if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG || 1805 1.2.2.2 tron (rstat = njsc32_resel_identify(sc, msg0 & 1806 1.2.2.2 tron MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) { 1807 1.2.2.2 tron /* 1808 1.2.2.2 tron * invalid Identify -> Reject 1809 1.2.2.2 tron */ 1810 1.2.2.2 tron goto reject; 1811 1.2.2.2 tron } 1812 1.2.2.2 tron if (rstat == NJSC32_RESEL_COMPLETE) 1813 1.2.2.2 tron reload_params = TRUE; 1814 1.2.2.2 tron MSGCOMPLETE; 1815 1.2.2.2 tron } 1816 1.2.2.2 tron 1817 1.2.2.2 tron if (msg0 == MSG_SIMPLE_Q_TAG) { 1818 1.2.2.2 tron if (msgcnt == 0) 1819 1.2.2.2 tron WAITNEXTMSG; 1820 1.2.2.2 tron 1821 1.2.2.2 tron /* got whole message */ 1822 1.2.2.2 tron sc->sc_msgincnt = 0; 1823 1.2.2.2 tron 1824 1.2.2.2 tron if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd)) 1825 1.2.2.2 tron == NJSC32_RESEL_ERROR) { 1826 1.2.2.2 tron /* 1827 1.2.2.2 tron * invalid Simple Queue Tag -> Abort Tag 1828 1.2.2.2 tron */ 1829 1.2.2.2 tron printf("%s: msgin: invalid tag\n", sc->sc_dev.dv_xname); 1830 1.2.2.2 tron njsc32_add_msgout(sc, MSG_ABORT_TAG); 1831 1.2.2.2 tron goto reply; 1832 1.2.2.2 tron } 1833 1.2.2.2 tron if (rstat == NJSC32_RESEL_COMPLETE) 1834 1.2.2.2 tron reload_params = TRUE; 1835 1.2.2.2 tron MSGCOMPLETE; 1836 1.2.2.2 tron } 1837 1.2.2.2 tron 1838 1.2.2.2 tron /* I_T_L or I_T_L_Q nexus should be established now */ 1839 1.2.2.2 tron if (cmd == NULL) { 1840 1.2.2.2 tron printf("%s: msgin %#x without nexus -- sending abort\n", 1841 1.2.2.2 tron sc->sc_dev.dv_xname, msg0); 1842 1.2.2.2 tron njsc32_add_msgout(sc, MSG_ABORT); 1843 1.2.2.2 tron goto reply; 1844 1.2.2.2 tron } 1845 1.2.2.2 tron 1846 1.2.2.2 tron /* 1847 1.2.2.2 tron * extended message 1848 1.2.2.2 tron * 0x01 <length (0 stands for 256)> <length bytes> 1849 1.2.2.2 tron * (<code> [<parameter> ...]) 1850 1.2.2.2 tron */ 1851 1.2.2.2 tron #define EXTLENOFF 1 1852 1.2.2.2 tron #define EXTCODEOFF 2 1853 1.2.2.2 tron if (msg0 == MSG_EXTENDED) { 1854 1.2.2.2 tron if (msgcnt < EXTLENOFF || 1855 1.2.2.2 tron msgcnt < EXTLENOFF + 1 + 1856 1.2.2.2 tron (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1)) 1857 1.2.2.2 tron WAITNEXTMSG; 1858 1.2.2.2 tron 1859 1.2.2.2 tron /* got whole message */ 1860 1.2.2.2 tron sc->sc_msgincnt = 0; 1861 1.2.2.2 tron 1862 1.2.2.2 tron switch (sc->sc_msginbuf[EXTCODEOFF]) { 1863 1.2.2.2 tron case 0: /* Modify Data Pointer */ 1864 1.2.2.2 tron if (msgcnt != 5 + EXTCODEOFF - 1) 1865 1.2.2.2 tron break; 1866 1.2.2.2 tron /* 1867 1.2.2.2 tron * parameter is 32bit big-endian signed (2-complement) 1868 1.2.2.2 tron * value 1869 1.2.2.2 tron */ 1870 1.2.2.2 tron ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) | 1871 1.2.2.2 tron (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) | 1872 1.2.2.2 tron (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) | 1873 1.2.2.2 tron sc->sc_msginbuf[EXTCODEOFF + 4]; 1874 1.2.2.2 tron 1875 1.2.2.2 tron /* new pointer */ 1876 1.2.2.2 tron ptr += cmd->c_dp_cur; /* ignore overflow */ 1877 1.2.2.2 tron 1878 1.2.2.2 tron /* reject if ptr is not in data buffer */ 1879 1.2.2.2 tron if (ptr > cmd->c_datacnt) 1880 1.2.2.2 tron break; 1881 1.2.2.2 tron 1882 1.2.2.2 tron njsc32_set_ptr(sc, cmd, ptr); 1883 1.2.2.2 tron goto restart; 1884 1.2.2.2 tron 1885 1.2.2.2 tron case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */ 1886 1.2.2.2 tron DPRINTC(cmd, ("SDTR %#x %#x\n", 1887 1.2.2.2 tron sc->sc_msginbuf[EXTCODEOFF + 1], 1888 1.2.2.2 tron sc->sc_msginbuf[EXTCODEOFF + 2])); 1889 1.2.2.2 tron if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1) 1890 1.2.2.2 tron break; /* reject */ 1891 1.2.2.2 tron 1892 1.2.2.2 tron target = cmd->c_target; 1893 1.2.2.2 tron 1894 1.2.2.2 tron /* lookup sync period parameters */ 1895 1.2.2.2 tron period = sc->sc_msginbuf[EXTCODEOFF + 1]; 1896 1.2.2.2 tron for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++) 1897 1.2.2.2 tron if (sc->sc_synct[idx].sp_period >= period) { 1898 1.2.2.2 tron period = sc->sc_synct[idx].sp_period; 1899 1.2.2.2 tron break; 1900 1.2.2.2 tron } 1901 1.2.2.2 tron if (idx >= NJSC32_NSYNCT) { 1902 1.2.2.2 tron /* 1903 1.2.2.2 tron * We can't meet the timing condition that 1904 1.2.2.2 tron * the target requests -- use async. 1905 1.2.2.2 tron */ 1906 1.2.2.2 tron njsc32_target_async(sc, target); 1907 1.2.2.2 tron njsc32_update_xfer_mode(sc, target); 1908 1.2.2.2 tron if (target->t_state == NJSC32_TARST_SDTR) { 1909 1.2.2.2 tron /* 1910 1.2.2.2 tron * We started SDTR exchange -- start 1911 1.2.2.2 tron * negotiation again and request async. 1912 1.2.2.2 tron */ 1913 1.2.2.2 tron target->t_state = NJSC32_TARST_ASYNC; 1914 1.2.2.2 tron njsc32_negotiate_xfer(sc, target); 1915 1.2.2.2 tron goto reply; 1916 1.2.2.2 tron } else { 1917 1.2.2.2 tron /* 1918 1.2.2.2 tron * The target started SDTR exchange 1919 1.2.2.2 tron * -- just reject and fallback 1920 1.2.2.2 tron * to async. 1921 1.2.2.2 tron */ 1922 1.2.2.2 tron goto reject; 1923 1.2.2.2 tron } 1924 1.2.2.2 tron } 1925 1.2.2.2 tron 1926 1.2.2.2 tron /* check sync offset */ 1927 1.2.2.2 tron offset = sc->sc_msginbuf[EXTCODEOFF + 2]; 1928 1.2.2.2 tron if (offset > NJSC32_SYNCOFFSET_MAX) { 1929 1.2.2.2 tron if (target->t_state == NJSC32_TARST_SDTR) { 1930 1.2.2.2 tron printf("%s: wrong sync offset: %d\n", 1931 1.2.2.2 tron cmd->c_xs->xs_periph->periph_dev->dv_xname, 1932 1.2.2.2 tron offset); 1933 1.2.2.2 tron /* XXX what to do? */ 1934 1.2.2.2 tron } 1935 1.2.2.2 tron offset = NJSC32_SYNCOFFSET_MAX; 1936 1.2.2.2 tron } 1937 1.2.2.2 tron 1938 1.2.2.2 tron target->t_ackwidth = sc->sc_synct[idx].sp_ackw; 1939 1.2.2.2 tron target->t_sample = sc->sc_synct[idx].sp_sample; 1940 1.2.2.2 tron target->t_syncperiod = period; 1941 1.2.2.2 tron target->t_syncoffset = offset; 1942 1.2.2.2 tron target->t_sync = NJSC32_SYNC_VAL(idx, offset); 1943 1.2.2.2 tron njsc32_update_xfer_mode(sc, target); 1944 1.2.2.2 tron 1945 1.2.2.2 tron if (target->t_state == NJSC32_TARST_SDTR) { 1946 1.2.2.2 tron target->t_state = NJSC32_TARST_DONE; 1947 1.2.2.2 tron } else { 1948 1.2.2.2 tron njsc32_msgout_sdtr(sc, period, offset); 1949 1.2.2.2 tron goto reply; 1950 1.2.2.2 tron } 1951 1.2.2.2 tron goto restart; 1952 1.2.2.2 tron 1953 1.2.2.2 tron case MSG_EXT_WDTR: /* Wide Data Transfer Request */ 1954 1.2.2.2 tron DPRINTC(cmd, 1955 1.2.2.2 tron ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1])); 1956 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 1957 1.2.2.2 tron if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1) 1958 1.2.2.2 tron break; /* reject */ 1959 1.2.2.2 tron 1960 1.2.2.2 tron /* 1961 1.2.2.2 tron * T->I of this message is not used for 1962 1.2.2.2 tron * DualEdge negotiation, so the device 1963 1.2.2.2 tron * must not be a DualEdge device. 1964 1.2.2.2 tron * 1965 1.2.2.2 tron * XXX correct? 1966 1.2.2.2 tron */ 1967 1.2.2.2 tron target = cmd->c_target; 1968 1.2.2.2 tron target->t_xferctl = 0; 1969 1.2.2.2 tron 1970 1.2.2.2 tron switch (target->t_state) { 1971 1.2.2.2 tron case NJSC32_TARST_DE: 1972 1.2.2.2 tron if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1973 1.2.2.2 tron MSG_EXT_WDTR_BUS_8_BIT) { 1974 1.2.2.2 tron /* 1975 1.2.2.2 tron * Oops, we got unexpected WDTR. 1976 1.2.2.2 tron * Negotiate for 8bit. 1977 1.2.2.2 tron */ 1978 1.2.2.2 tron target->t_state = NJSC32_TARST_WDTR; 1979 1.2.2.2 tron } else { 1980 1.2.2.2 tron target->t_state = NJSC32_TARST_SDTR; 1981 1.2.2.2 tron } 1982 1.2.2.2 tron njsc32_negotiate_xfer(sc, target); 1983 1.2.2.2 tron goto reply; 1984 1.2.2.2 tron 1985 1.2.2.2 tron case NJSC32_TARST_WDTR: 1986 1.2.2.2 tron if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1987 1.2.2.2 tron MSG_EXT_WDTR_BUS_8_BIT) { 1988 1.2.2.2 tron printf("%s: unexpected transfer width: %#x\n", 1989 1.2.2.2 tron cmd->c_xs->xs_periph->periph_dev->dv_xname, 1990 1.2.2.2 tron sc->sc_msginbuf[EXTCODEOFF + 1]); 1991 1.2.2.2 tron /* XXX what to do? */ 1992 1.2.2.2 tron } 1993 1.2.2.2 tron target->t_state = NJSC32_TARST_SDTR; 1994 1.2.2.2 tron njsc32_negotiate_xfer(sc, target); 1995 1.2.2.2 tron goto reply; 1996 1.2.2.2 tron 1997 1.2.2.2 tron default: 1998 1.2.2.2 tron /* the target started WDTR exchange */ 1999 1.2.2.2 tron DPRINTC(cmd, ("WDTR from target\n")); 2000 1.2.2.2 tron 2001 1.2.2.2 tron target->t_state = NJSC32_TARST_SDTR; 2002 1.2.2.2 tron njsc32_target_async(sc, target); 2003 1.2.2.2 tron 2004 1.2.2.2 tron break; /* reject the WDTR (8bit transfer) */ 2005 1.2.2.2 tron } 2006 1.2.2.2 tron #endif /* NJSC32_DUALEDGE */ 2007 1.2.2.2 tron break; /* reject */ 2008 1.2.2.2 tron } 2009 1.2.2.2 tron DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n", 2010 1.2.2.2 tron sc->sc_msginbuf[EXTCODEOFF], msgcnt)); 2011 1.2.2.2 tron goto reject; 2012 1.2.2.2 tron } 2013 1.2.2.2 tron 2014 1.2.2.2 tron /* 2byte messages */ 2015 1.2.2.2 tron if (MSG_IS2BYTE(msg0)) { 2016 1.2.2.2 tron if (msgcnt == 0) 2017 1.2.2.2 tron WAITNEXTMSG; 2018 1.2.2.2 tron 2019 1.2.2.2 tron /* got whole message */ 2020 1.2.2.2 tron sc->sc_msgincnt = 0; 2021 1.2.2.2 tron } 2022 1.2.2.2 tron 2023 1.2.2.2 tron switch (msg0) { 2024 1.2.2.2 tron case MSG_CMDCOMPLETE: /* 0x00 */ 2025 1.2.2.2 tron case MSG_SAVEDATAPOINTER: /* 0x02 */ 2026 1.2.2.2 tron case MSG_DISCONNECT: /* 0x04 */ 2027 1.2.2.2 tron /* handled by AutoSCSI */ 2028 1.2.2.2 tron PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0)); 2029 1.2.2.2 tron break; 2030 1.2.2.2 tron 2031 1.2.2.2 tron case MSG_RESTOREPOINTERS: /* 0x03 */ 2032 1.2.2.2 tron /* restore data pointer to what was saved */ 2033 1.2.2.2 tron DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n")); 2034 1.2.2.2 tron njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 2035 1.2.2.2 tron reload_params = TRUE; 2036 1.2.2.2 tron MSGCOMPLETE; 2037 1.2.2.2 tron /* NOTREACHED */ 2038 1.2.2.2 tron break; 2039 1.2.2.2 tron 2040 1.2.2.2 tron #if 0 /* handled above */ 2041 1.2.2.2 tron case MSG_EXTENDED: /* 0x01 */ 2042 1.2.2.2 tron #endif 2043 1.2.2.2 tron case MSG_MESSAGE_REJECT: /* 0x07 */ 2044 1.2.2.2 tron target = cmd->c_target; 2045 1.2.2.2 tron DPRINTC(cmd, ("Reject tarst %d\n", target->t_state)); 2046 1.2.2.2 tron switch (target->t_state) { 2047 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 2048 1.2.2.2 tron case NJSC32_TARST_WDTR: 2049 1.2.2.2 tron case NJSC32_TARST_DE: 2050 1.2.2.2 tron target->t_xferctl = 0; 2051 1.2.2.2 tron target->t_state = NJSC32_TARST_SDTR; 2052 1.2.2.2 tron njsc32_negotiate_xfer(sc, target); 2053 1.2.2.2 tron goto reply; 2054 1.2.2.2 tron #endif 2055 1.2.2.2 tron case NJSC32_TARST_SDTR: 2056 1.2.2.2 tron case NJSC32_TARST_ASYNC: 2057 1.2.2.2 tron njsc32_target_async(sc, target); 2058 1.2.2.2 tron target->t_state = NJSC32_TARST_DONE; 2059 1.2.2.2 tron njsc32_update_xfer_mode(sc, target); 2060 1.2.2.2 tron break; 2061 1.2.2.2 tron default: 2062 1.2.2.2 tron break; 2063 1.2.2.2 tron } 2064 1.2.2.2 tron goto restart; 2065 1.2.2.2 tron 2066 1.2.2.2 tron case MSG_NOOP: /* 0x08 */ 2067 1.2.2.2 tron #ifdef NJSC32_DUALEDGE 2068 1.2.2.2 tron target = cmd->c_target; 2069 1.2.2.2 tron if (target->t_state == NJSC32_TARST_DE) { 2070 1.2.2.2 tron aprint_normal("%s: DualEdge transfer\n", 2071 1.2.2.2 tron cmd->c_xs->xs_periph->periph_dev->dv_xname); 2072 1.2.2.2 tron target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE; 2073 1.2.2.2 tron /* go to next negotiation */ 2074 1.2.2.2 tron target->t_state = NJSC32_TARST_SDTR; 2075 1.2.2.2 tron njsc32_negotiate_xfer(sc, target); 2076 1.2.2.2 tron goto reply; 2077 1.2.2.2 tron } 2078 1.2.2.2 tron #endif 2079 1.2.2.2 tron goto restart; 2080 1.2.2.2 tron 2081 1.2.2.2 tron case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */ 2082 1.2.2.2 tron case MSG_ABORT: /* 0x06 I->T only */ 2083 1.2.2.2 tron case MSG_PARITY_ERROR: /* 0x09 I->T only */ 2084 1.2.2.2 tron case MSG_LINK_CMD_COMPLETE: /* 0x0a */ 2085 1.2.2.2 tron case MSG_LINK_CMD_COMPLETEF: /* 0x0b */ 2086 1.2.2.2 tron case MSG_BUS_DEV_RESET: /* 0x0c I->T only */ 2087 1.2.2.2 tron case MSG_ABORT_TAG: /* 0x0d I->T only */ 2088 1.2.2.2 tron case MSG_CLEAR_QUEUE: /* 0x0e I->T only */ 2089 1.2.2.2 tron 2090 1.2.2.2 tron #if 0 /* handled above */ 2091 1.2.2.2 tron case MSG_SIMPLE_Q_TAG: /* 0x20 */ 2092 1.2.2.2 tron #endif 2093 1.2.2.2 tron case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */ 2094 1.2.2.2 tron case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */ 2095 1.2.2.2 tron case MSG_IGN_WIDE_RESIDUE: /* 0x23 */ 2096 1.2.2.2 tron 2097 1.2.2.2 tron default: 2098 1.2.2.2 tron #ifdef NJSC32_DEBUG 2099 1.2.2.2 tron PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0)); 2100 1.2.2.2 tron if (MSG_IS2BYTE(msg0)) 2101 1.2.2.2 tron printf(" %#x", msg); 2102 1.2.2.2 tron printf("\n"); 2103 1.2.2.2 tron #endif 2104 1.2.2.2 tron break; 2105 1.2.2.2 tron } 2106 1.2.2.2 tron 2107 1.2.2.2 tron reject: 2108 1.2.2.2 tron njsc32_add_msgout(sc, MSG_MESSAGE_REJECT); 2109 1.2.2.2 tron 2110 1.2.2.2 tron reply: 2111 1.2.2.2 tron msgout = njsc32_get_auto_msgout(sc); 2112 1.2.2.2 tron 2113 1.2.2.2 tron restart: 2114 1.2.2.2 tron cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2115 1.2.2.2 tron NJSC32_CMD_AUTO_COMMAND_PHASE | 2116 1.2.2.2 tron NJSC32_CMD_AUTO_SCSI_RESTART; 2117 1.2.2.2 tron 2118 1.2.2.2 tron /* 2119 1.2.2.2 tron * Be careful the second and latter bytes of Message In 2120 1.2.2.2 tron * shall not be absorbed by AutoSCSI. 2121 1.2.2.2 tron */ 2122 1.2.2.2 tron if (sc->sc_msgincnt == 0) 2123 1.2.2.2 tron cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2124 1.2.2.2 tron 2125 1.2.2.2 tron if (sc->sc_msgoutlen != 0) 2126 1.2.2.2 tron cctl |= NJSC32_CMD_AUTO_ATN; 2127 1.2.2.2 tron 2128 1.2.2.2 tron njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout); 2129 1.2.2.2 tron 2130 1.2.2.2 tron /* (re)start AutoSCSI (may assert ATN) */ 2131 1.2.2.2 tron if (reload_params) { 2132 1.2.2.2 tron njsc32_cmd_reload(sc, cmd, cctl); 2133 1.2.2.2 tron } else { 2134 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2135 1.2.2.2 tron } 2136 1.2.2.2 tron 2137 1.2.2.2 tron /* +ATN -> -REQ: need 90ns delay? */ 2138 1.2.2.2 tron 2139 1.2.2.2 tron njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2140 1.2.2.2 tron 2141 1.2.2.2 tron njsc32_negate_ack(sc); 2142 1.2.2.2 tron 2143 1.2.2.2 tron return; 2144 1.2.2.2 tron } 2145 1.2.2.2 tron 2146 1.2.2.2 tron static void 2147 1.2.2.3 tron njsc32_msgout(struct njsc32_softc *sc) 2148 1.2.2.2 tron { 2149 1.2.2.2 tron int cctl; 2150 1.2.2.2 tron u_int8_t bus; 2151 1.2.2.2 tron unsigned n; 2152 1.2.2.2 tron 2153 1.2.2.2 tron if (sc->sc_msgoutlen == 0) { 2154 1.2.2.2 tron /* target entered to Message Out on unexpected timing */ 2155 1.2.2.2 tron njsc32_add_msgout(sc, MSG_NOOP); 2156 1.2.2.2 tron } 2157 1.2.2.2 tron 2158 1.2.2.2 tron cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2159 1.2.2.2 tron NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART | 2160 1.2.2.2 tron NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2161 1.2.2.2 tron 2162 1.2.2.2 tron /* make sure target is in Message Out phase */ 2163 1.2.2.2 tron bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR); 2164 1.2.2.2 tron if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) { 2165 1.2.2.2 tron /* 2166 1.2.2.2 tron * Message Out is aborted by target. 2167 1.2.2.2 tron */ 2168 1.2.2.2 tron printf("%s: njsc32_msgout: phase change %#x\n", 2169 1.2.2.2 tron sc->sc_dev.dv_xname, bus); 2170 1.2.2.2 tron 2171 1.2.2.2 tron /* XXX what to do? */ 2172 1.2.2.2 tron 2173 1.2.2.2 tron /* restart AutoSCSI (negate ATN) */ 2174 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2175 1.2.2.2 tron 2176 1.2.2.2 tron sc->sc_msgoutidx = 0; 2177 1.2.2.2 tron return; 2178 1.2.2.2 tron } 2179 1.2.2.2 tron 2180 1.2.2.2 tron n = sc->sc_msgoutidx; 2181 1.2.2.2 tron if (n == sc->sc_msgoutlen - 1) { 2182 1.2.2.2 tron /* 2183 1.2.2.2 tron * negate ATN before sending ACK 2184 1.2.2.2 tron */ 2185 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0); 2186 1.2.2.2 tron 2187 1.2.2.2 tron sc->sc_msgoutidx = 0; /* target may retry Message Out */ 2188 1.2.2.2 tron } else { 2189 1.2.2.2 tron cctl |= NJSC32_CMD_AUTO_ATN; 2190 1.2.2.2 tron sc->sc_msgoutidx++; 2191 1.2.2.2 tron } 2192 1.2.2.2 tron 2193 1.2.2.2 tron /* Send Message Out */ 2194 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]); 2195 1.2.2.2 tron 2196 1.2.2.2 tron /* DBn -> +ACK: need 55ns delay? */ 2197 1.2.2.2 tron 2198 1.2.2.2 tron njsc32_assert_ack(sc); 2199 1.2.2.2 tron njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2200 1.2.2.2 tron 2201 1.2.2.2 tron /* restart AutoSCSI */ 2202 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2203 1.2.2.2 tron 2204 1.2.2.2 tron njsc32_negate_ack(sc); 2205 1.2.2.2 tron 2206 1.2.2.2 tron /* 2207 1.2.2.2 tron * do not reset sc->sc_msgoutlen so the target 2208 1.2.2.2 tron * can retry Message Out phase 2209 1.2.2.2 tron */ 2210 1.2.2.2 tron } 2211 1.2.2.2 tron 2212 1.2.2.2 tron static void 2213 1.2.2.3 tron njsc32_cmdtimeout(void *arg) 2214 1.2.2.2 tron { 2215 1.2.2.2 tron struct njsc32_cmd *cmd = arg; 2216 1.2.2.2 tron struct njsc32_softc *sc; 2217 1.2.2.2 tron int s; 2218 1.2.2.2 tron 2219 1.2.2.2 tron PRINTC(cmd, ("command timeout\n")); 2220 1.2.2.2 tron 2221 1.2.2.2 tron sc = cmd->c_sc; 2222 1.2.2.2 tron 2223 1.2.2.2 tron s = splbio(); 2224 1.2.2.2 tron 2225 1.2.2.2 tron if (sc->sc_stat == NJSC32_STAT_ARBIT) 2226 1.2.2.2 tron njsc32_arbitration_failed(sc); 2227 1.2.2.2 tron else { 2228 1.2.2.2 tron sc->sc_curcmd = NULL; 2229 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_IDLE; 2230 1.2.2.2 tron njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2231 1.2.2.2 tron } 2232 1.2.2.2 tron 2233 1.2.2.2 tron /* XXX? */ 2234 1.2.2.2 tron njsc32_init(sc, 1); /* bus reset */ 2235 1.2.2.2 tron 2236 1.2.2.2 tron splx(s); 2237 1.2.2.2 tron } 2238 1.2.2.2 tron 2239 1.2.2.2 tron static void 2240 1.2.2.3 tron njsc32_reseltimeout(void *arg) 2241 1.2.2.2 tron { 2242 1.2.2.2 tron struct njsc32_cmd *cmd = arg; 2243 1.2.2.2 tron struct njsc32_softc *sc; 2244 1.2.2.2 tron int s; 2245 1.2.2.2 tron 2246 1.2.2.2 tron PRINTC(cmd, ("reselection timeout\n")); 2247 1.2.2.2 tron 2248 1.2.2.2 tron sc = cmd->c_sc; 2249 1.2.2.2 tron 2250 1.2.2.2 tron s = splbio(); 2251 1.2.2.2 tron 2252 1.2.2.2 tron /* remove from disconnected list */ 2253 1.2.2.2 tron if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2254 1.2.2.2 tron /* I_T_L_Q */ 2255 1.2.2.2 tron KASSERT(cmd->c_lu->lu_cmd == NULL); 2256 1.2.2.2 tron TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q); 2257 1.2.2.2 tron } else { 2258 1.2.2.2 tron /* I_T_L */ 2259 1.2.2.2 tron KASSERT(cmd->c_lu->lu_cmd == cmd); 2260 1.2.2.2 tron cmd->c_lu->lu_cmd = NULL; 2261 1.2.2.2 tron } 2262 1.2.2.2 tron 2263 1.2.2.2 tron njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2264 1.2.2.2 tron 2265 1.2.2.2 tron /* XXX? */ 2266 1.2.2.2 tron njsc32_init(sc, 1); /* bus reset */ 2267 1.2.2.2 tron 2268 1.2.2.2 tron splx(s); 2269 1.2.2.2 tron } 2270 1.2.2.2 tron 2271 1.2.2.2 tron static __inline void 2272 1.2.2.3 tron njsc32_end_auto(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int auto_phase) 2273 1.2.2.2 tron { 2274 1.2.2.2 tron struct scsipi_xfer *xs; 2275 1.2.2.2 tron 2276 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_MSGIN_02) { 2277 1.2.2.2 tron /* Message In: 0x02 Save Data Pointer */ 2278 1.2.2.2 tron 2279 1.2.2.2 tron /* 2280 1.2.2.2 tron * Adjust saved data pointer 2281 1.2.2.2 tron * if the command is not completed yet. 2282 1.2.2.2 tron */ 2283 1.2.2.2 tron if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 && 2284 1.2.2.2 tron (auto_phase & 2285 1.2.2.2 tron (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) { 2286 1.2.2.2 tron njsc32_save_ptr(cmd); 2287 1.2.2.2 tron } 2288 1.2.2.2 tron TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2289 1.2.2.2 tron njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2290 1.2.2.2 tron njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2291 1.2.2.2 tron njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2292 1.2.2.2 tron njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT))); 2293 1.2.2.2 tron } 2294 1.2.2.2 tron 2295 1.2.2.2 tron xs = cmd->c_xs; 2296 1.2.2.2 tron 2297 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_MSGIN_00) { 2298 1.2.2.2 tron /* Command Complete */ 2299 1.2.2.2 tron TPRINTC(cmd, ("njsc32_intr: Command Complete\n")); 2300 1.2.2.2 tron switch (xs->status) { 2301 1.2.2.2 tron case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY: 2302 1.2.2.2 tron /* 2303 1.2.2.2 tron * scsipi layer will automatically handle the error 2304 1.2.2.2 tron */ 2305 1.2.2.2 tron njsc32_end_cmd(sc, cmd, XS_BUSY); 2306 1.2.2.2 tron break; 2307 1.2.2.2 tron default: 2308 1.2.2.2 tron xs->resid -= cmd->c_dp_max; 2309 1.2.2.2 tron njsc32_end_cmd(sc, cmd, XS_NOERROR); 2310 1.2.2.2 tron break; 2311 1.2.2.2 tron } 2312 1.2.2.2 tron } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) { 2313 1.2.2.2 tron /* Disconnect */ 2314 1.2.2.2 tron TPRINTC(cmd, ("njsc32_intr: Disconnect\n")); 2315 1.2.2.2 tron 2316 1.2.2.2 tron /* for ill-designed devices */ 2317 1.2.2.2 tron if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0) 2318 1.2.2.2 tron njsc32_save_ptr(cmd); 2319 1.2.2.2 tron 2320 1.2.2.2 tron /* 2321 1.2.2.2 tron * move current cmd to disconnected list 2322 1.2.2.2 tron */ 2323 1.2.2.2 tron if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2324 1.2.2.2 tron /* I_T_L_Q */ 2325 1.2.2.2 tron if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD) 2326 1.2.2.2 tron TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q); 2327 1.2.2.2 tron else 2328 1.2.2.2 tron TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q); 2329 1.2.2.2 tron } else { 2330 1.2.2.2 tron /* I_T_L */ 2331 1.2.2.2 tron cmd->c_lu->lu_cmd = cmd; 2332 1.2.2.2 tron } 2333 1.2.2.2 tron 2334 1.2.2.2 tron /* 2335 1.2.2.2 tron * schedule timeout -- avoid being 2336 1.2.2.2 tron * disconnected forever 2337 1.2.2.2 tron */ 2338 1.2.2.2 tron if ((xs->xs_control & XS_CTL_POLL) == 0) { 2339 1.2.2.2 tron callout_stop(&xs->xs_callout); 2340 1.2.2.2 tron callout_reset(&xs->xs_callout, mstohz(xs->timeout), 2341 1.2.2.2 tron njsc32_reseltimeout, cmd); 2342 1.2.2.2 tron } 2343 1.2.2.2 tron 2344 1.2.2.2 tron } else { 2345 1.2.2.2 tron /* 2346 1.2.2.2 tron * target has come to Bus Free phase 2347 1.2.2.2 tron * probably to notify an error 2348 1.2.2.2 tron */ 2349 1.2.2.2 tron PRINTC(cmd, ("njsc32_intr: unexpected bus free\n")); 2350 1.2.2.2 tron /* try Request Sense */ 2351 1.2.2.2 tron xs->status = SCSI_CHECK; 2352 1.2.2.2 tron njsc32_end_cmd(sc, cmd, XS_BUSY); 2353 1.2.2.2 tron } 2354 1.2.2.2 tron } 2355 1.2.2.2 tron 2356 1.2.2.2 tron int 2357 1.2.2.3 tron njsc32_intr(void *arg) 2358 1.2.2.2 tron { 2359 1.2.2.2 tron struct njsc32_softc *sc = arg; 2360 1.2.2.2 tron u_int16_t intr; 2361 1.2.2.2 tron u_int8_t arbstat, bus_phase; 2362 1.2.2.2 tron int auto_phase; 2363 1.2.2.2 tron int idbit; 2364 1.2.2.2 tron struct njsc32_cmd *cmd; 2365 1.2.2.2 tron 2366 1.2.2.2 tron intr = njsc32_read_2(sc, NJSC32_REG_IRQ); 2367 1.2.2.2 tron if ((intr & NJSC32_IRQ_INTR_PENDING) == 0) 2368 1.2.2.2 tron return 0; /* not mine */ 2369 1.2.2.2 tron 2370 1.2.2.2 tron TPRINTF(("%s: njsc32_intr: %#x\n", sc->sc_dev.dv_xname, intr)); 2371 1.2.2.2 tron 2372 1.2.2.2 tron #if 0 /* I don't think this is required */ 2373 1.2.2.2 tron /* mask interrupts */ 2374 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 2375 1.2.2.2 tron #endif 2376 1.2.2.2 tron 2377 1.2.2.2 tron /* we got an interrupt, so stop the timer */ 2378 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 2379 1.2.2.2 tron 2380 1.2.2.2 tron if (intr & NJSC32_IRQ_SCSIRESET) { 2381 1.2.2.2 tron printf("%s: detected bus reset\n", sc->sc_dev.dv_xname); 2382 1.2.2.3.2.2 bouyer /* make sure all devices on the bus are certainly reset */ 2383 1.2.2.3.2.2 bouyer njsc32_reset_bus(sc); 2384 1.2.2.2 tron goto out; 2385 1.2.2.2 tron } 2386 1.2.2.2 tron 2387 1.2.2.2 tron if (sc->sc_stat == NJSC32_STAT_ARBIT) { 2388 1.2.2.2 tron cmd = sc->sc_curcmd; 2389 1.2.2.2 tron KASSERT(cmd); 2390 1.2.2.2 tron arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT); 2391 1.2.2.2 tron if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) { 2392 1.2.2.2 tron /* 2393 1.2.2.2 tron * arbitration done 2394 1.2.2.2 tron */ 2395 1.2.2.2 tron /* clear arbitration status */ 2396 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION, 2397 1.2.2.2 tron NJSC32_SETARB_CLEAR); 2398 1.2.2.2 tron 2399 1.2.2.2 tron if (arbstat & NJSC32_ARBSTAT_WIN) { 2400 1.2.2.2 tron TPRINTC(cmd, 2401 1.2.2.2 tron ("njsc32_intr: arbitration won\n")); 2402 1.2.2.2 tron 2403 1.2.2.2 tron TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 2404 1.2.2.2 tron 2405 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_CONNECT; 2406 1.2.2.2 tron } else { 2407 1.2.2.2 tron TPRINTC(cmd, 2408 1.2.2.2 tron ("njsc32_intr: arbitration failed\n")); 2409 1.2.2.2 tron 2410 1.2.2.2 tron njsc32_arbitration_failed(sc); 2411 1.2.2.2 tron 2412 1.2.2.2 tron /* XXX delay */ 2413 1.2.2.2 tron /* XXX retry counter */ 2414 1.2.2.2 tron } 2415 1.2.2.2 tron } 2416 1.2.2.2 tron } 2417 1.2.2.2 tron 2418 1.2.2.2 tron if (intr & NJSC32_IRQ_TIMER) { 2419 1.2.2.2 tron TPRINTF(("%s: njsc32_intr: timer interrupt\n", 2420 1.2.2.2 tron sc->sc_dev.dv_xname)); 2421 1.2.2.2 tron } 2422 1.2.2.2 tron 2423 1.2.2.2 tron if (intr & NJSC32_IRQ_RESELECT) { 2424 1.2.2.2 tron /* Reselection from a target */ 2425 1.2.2.2 tron njsc32_arbitration_failed(sc); /* just in case */ 2426 1.2.2.2 tron if ((cmd = sc->sc_curcmd) != NULL) { 2427 1.2.2.2 tron /* ? */ 2428 1.2.2.2 tron printf("%s: unexpected reselection\n", 2429 1.2.2.2 tron sc->sc_dev.dv_xname); 2430 1.2.2.2 tron sc->sc_curcmd = NULL; 2431 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_IDLE; 2432 1.2.2.2 tron njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP); 2433 1.2.2.2 tron } 2434 1.2.2.2 tron 2435 1.2.2.2 tron idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID); 2436 1.2.2.2 tron if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 || 2437 1.2.2.3.2.2 bouyer (sc->sc_reselid = 2438 1.2.2.3.2.2 bouyer ffs(idbit & ~(1 << NJSC32_INITIATOR_ID)) - 1) < 0) { 2439 1.2.2.2 tron printf("%s: invalid reselection (id: %#x)\n", 2440 1.2.2.2 tron sc->sc_dev.dv_xname, idbit); 2441 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */ 2442 1.2.2.2 tron } else { 2443 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_RESEL; 2444 1.2.2.2 tron TPRINTF(("%s: njsc32_intr: reselection from %d\n", 2445 1.2.2.2 tron sc->sc_dev.dv_xname, sc->sc_reselid)); 2446 1.2.2.2 tron } 2447 1.2.2.2 tron } 2448 1.2.2.2 tron 2449 1.2.2.2 tron if (intr & NJSC32_IRQ_PHASE_CHANGE) { 2450 1.2.2.2 tron #if 1 /* XXX probably not needed */ 2451 1.2.2.2 tron if (sc->sc_stat == NJSC32_STAT_ARBIT) 2452 1.2.2.2 tron PRINTC(sc->sc_curcmd, 2453 1.2.2.2 tron ("njsc32_intr: cancel arbitration phase\n")); 2454 1.2.2.2 tron njsc32_arbitration_failed(sc); 2455 1.2.2.2 tron #endif 2456 1.2.2.2 tron /* current bus phase */ 2457 1.2.2.2 tron bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 2458 1.2.2.2 tron NJSC32_BUSMON_PHASE_MASK; 2459 1.2.2.2 tron 2460 1.2.2.2 tron switch (bus_phase) { 2461 1.2.2.2 tron case NJSC32_PHASE_MESSAGE_IN: 2462 1.2.2.2 tron njsc32_msgin(sc); 2463 1.2.2.2 tron break; 2464 1.2.2.2 tron 2465 1.2.2.2 tron /* 2466 1.2.2.2 tron * target may suddenly become Status / Bus Free phase 2467 1.2.2.2 tron * to notify an error condition 2468 1.2.2.2 tron */ 2469 1.2.2.2 tron case NJSC32_PHASE_STATUS: 2470 1.2.2.2 tron printf("%s: unexpected bus phase: Status\n", 2471 1.2.2.2 tron sc->sc_dev.dv_xname); 2472 1.2.2.2 tron if ((cmd = sc->sc_curcmd) != NULL) { 2473 1.2.2.2 tron cmd->c_xs->status = 2474 1.2.2.2 tron njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2475 1.2.2.2 tron TPRINTC(cmd, ("njsc32_intr: Status %d\n", 2476 1.2.2.2 tron cmd->c_xs->status)); 2477 1.2.2.2 tron } 2478 1.2.2.2 tron break; 2479 1.2.2.2 tron case NJSC32_PHASE_BUSFREE: 2480 1.2.2.2 tron printf("%s: unexpected bus phase: Bus Free\n", 2481 1.2.2.2 tron sc->sc_dev.dv_xname); 2482 1.2.2.2 tron if ((cmd = sc->sc_curcmd) != NULL) { 2483 1.2.2.2 tron sc->sc_curcmd = NULL; 2484 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_IDLE; 2485 1.2.2.2 tron if (cmd->c_xs->status != SCSI_QUEUE_FULL && 2486 1.2.2.2 tron cmd->c_xs->status != SCSI_BUSY) 2487 1.2.2.2 tron cmd->c_xs->status = SCSI_CHECK;/* XXX */ 2488 1.2.2.2 tron njsc32_end_cmd(sc, cmd, XS_BUSY); 2489 1.2.2.2 tron } 2490 1.2.2.2 tron goto out; 2491 1.2.2.2 tron default: 2492 1.2.2.2 tron #ifdef NJSC32_DEBUG 2493 1.2.2.2 tron printf("%s: unexpected bus phase: ", 2494 1.2.2.2 tron sc->sc_dev.dv_xname); 2495 1.2.2.2 tron switch (bus_phase) { 2496 1.2.2.2 tron case NJSC32_PHASE_COMMAND: 2497 1.2.2.2 tron printf("Command\n"); break; 2498 1.2.2.2 tron case NJSC32_PHASE_MESSAGE_OUT: 2499 1.2.2.2 tron printf("Message Out\n");break; 2500 1.2.2.2 tron case NJSC32_PHASE_DATA_IN: 2501 1.2.2.2 tron printf("Data In\n"); break; 2502 1.2.2.2 tron case NJSC32_PHASE_DATA_OUT: 2503 1.2.2.2 tron printf("Data Out\n"); break; 2504 1.2.2.2 tron case NJSC32_PHASE_RESELECT: 2505 1.2.2.2 tron printf("Reselect\n");break; 2506 1.2.2.2 tron default: printf("%#x\n", bus_phase); break; 2507 1.2.2.2 tron } 2508 1.2.2.2 tron #else 2509 1.2.2.2 tron printf("%s: unexpected bus phase: %#x", 2510 1.2.2.2 tron sc->sc_dev.dv_xname, bus_phase); 2511 1.2.2.2 tron #endif 2512 1.2.2.2 tron break; 2513 1.2.2.2 tron } 2514 1.2.2.2 tron } 2515 1.2.2.2 tron 2516 1.2.2.2 tron if (intr & NJSC32_IRQ_AUTOSCSI) { 2517 1.2.2.2 tron /* 2518 1.2.2.2 tron * AutoSCSI interrupt 2519 1.2.2.2 tron */ 2520 1.2.2.2 tron auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE); 2521 1.2.2.2 tron TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n", 2522 1.2.2.2 tron sc->sc_dev.dv_xname, auto_phase)); 2523 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0); 2524 1.2.2.2 tron 2525 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) { 2526 1.2.2.2 tron cmd = sc->sc_curcmd; 2527 1.2.2.2 tron if (cmd == NULL) { 2528 1.2.2.2 tron printf("%s: sel no cmd\n", 2529 1.2.2.2 tron sc->sc_dev.dv_xname); 2530 1.2.2.2 tron goto out; 2531 1.2.2.2 tron } 2532 1.2.2.2 tron DPRINTC(cmd, ("njsc32_intr: selection timeout\n")); 2533 1.2.2.2 tron 2534 1.2.2.2 tron sc->sc_curcmd = NULL; 2535 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_IDLE; 2536 1.2.2.2 tron njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT); 2537 1.2.2.2 tron 2538 1.2.2.2 tron goto out; 2539 1.2.2.2 tron } 2540 1.2.2.2 tron 2541 1.2.2.2 tron #ifdef NJSC32_TRACE 2542 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_COMMAND) { 2543 1.2.2.2 tron /* Command phase has been automatically processed */ 2544 1.2.2.2 tron TPRINTF(("%s: njsc32_intr: Command\n", 2545 1.2.2.2 tron sc->sc_dev.dv_xname)); 2546 1.2.2.2 tron } 2547 1.2.2.2 tron #endif 2548 1.2.2.2 tron #ifdef NJSC32_DEBUG 2549 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_ILLEGAL) { 2550 1.2.2.2 tron printf("%s: njsc32_intr: Illegal phase\n", 2551 1.2.2.2 tron sc->sc_dev.dv_xname); 2552 1.2.2.2 tron } 2553 1.2.2.2 tron #endif 2554 1.2.2.2 tron 2555 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) { 2556 1.2.2.2 tron TPRINTF(("%s: njsc32_intr: Process Message In\n", 2557 1.2.2.2 tron sc->sc_dev.dv_xname)); 2558 1.2.2.2 tron njsc32_msgin(sc); 2559 1.2.2.2 tron } 2560 1.2.2.2 tron 2561 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) { 2562 1.2.2.2 tron TPRINTF(("%s: njsc32_intr: Process Message Out\n", 2563 1.2.2.2 tron sc->sc_dev.dv_xname)); 2564 1.2.2.2 tron njsc32_msgout(sc); 2565 1.2.2.2 tron } 2566 1.2.2.2 tron 2567 1.2.2.2 tron cmd = sc->sc_curcmd; 2568 1.2.2.2 tron if (cmd == NULL) { 2569 1.2.2.2 tron TPRINTF(("%s: njsc32_intr: no cmd\n", 2570 1.2.2.2 tron sc->sc_dev.dv_xname)); 2571 1.2.2.2 tron goto out; 2572 1.2.2.2 tron } 2573 1.2.2.2 tron 2574 1.2.2.2 tron if (auto_phase & 2575 1.2.2.2 tron (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) { 2576 1.2.2.3.2.1 tron u_int32_t sackcnt, cntoffset; 2577 1.2.2.3.2.1 tron 2578 1.2.2.2 tron #ifdef NJSC32_TRACE 2579 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_DATA_IN) 2580 1.2.2.2 tron PRINTC(cmd, ("njsc32_intr: data in done\n")); 2581 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_DATA_OUT) 2582 1.2.2.2 tron PRINTC(cmd, ("njsc32_intr: data out done\n")); 2583 1.2.2.2 tron printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2584 1.2.2.2 tron njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2585 1.2.2.2 tron njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2586 1.2.2.2 tron njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2587 1.2.2.2 tron njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)); 2588 1.2.2.2 tron #endif 2589 1.2.2.2 tron 2590 1.2.2.2 tron /* 2591 1.2.2.2 tron * detected parity error on data transfer? 2592 1.2.2.2 tron */ 2593 1.2.2.2 tron if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 2594 1.2.2.2 tron (NJSC32_PARITYSTATUS_ERROR_LSB| 2595 1.2.2.2 tron NJSC32_PARITYSTATUS_ERROR_MSB)) { 2596 1.2.2.2 tron 2597 1.2.2.2 tron PRINTC(cmd, ("datain: parity error\n")); 2598 1.2.2.2 tron 2599 1.2.2.2 tron /* clear parity error */ 2600 1.2.2.2 tron njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 2601 1.2.2.2 tron NJSC32_PARITYCTL_CHECK_ENABLE | 2602 1.2.2.2 tron NJSC32_PARITYCTL_CLEAR_ERROR); 2603 1.2.2.2 tron 2604 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2605 1.2.2.2 tron /* 2606 1.2.2.2 tron * XXX command has already finished 2607 1.2.2.2 tron * -- what can we do? 2608 1.2.2.2 tron * 2609 1.2.2.2 tron * It is not clear current command 2610 1.2.2.2 tron * caused the error -- reset everything. 2611 1.2.2.2 tron */ 2612 1.2.2.2 tron njsc32_init(sc, 1); /* XXX */ 2613 1.2.2.2 tron } else { 2614 1.2.2.2 tron /* XXX does this case occur? */ 2615 1.2.2.2 tron #if 1 2616 1.2.2.2 tron printf("%s: datain: parity error\n", 2617 1.2.2.2 tron sc->sc_dev.dv_xname); 2618 1.2.2.2 tron #endif 2619 1.2.2.2 tron /* 2620 1.2.2.2 tron * Make attention condition and try 2621 1.2.2.2 tron * to send Initiator Detected Error 2622 1.2.2.2 tron * message. 2623 1.2.2.2 tron */ 2624 1.2.2.2 tron njsc32_init_msgout(sc); 2625 1.2.2.2 tron njsc32_add_msgout(sc, 2626 1.2.2.2 tron MSG_INITIATOR_DET_ERR); 2627 1.2.2.2 tron njsc32_write_4(sc, 2628 1.2.2.2 tron NJSC32_REG_SCSI_MSG_OUT, 2629 1.2.2.2 tron njsc32_get_auto_msgout(sc)); 2630 1.2.2.2 tron /* restart autoscsi with ATN */ 2631 1.2.2.2 tron njsc32_write_2(sc, 2632 1.2.2.2 tron NJSC32_REG_COMMAND_CONTROL, 2633 1.2.2.2 tron NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2634 1.2.2.2 tron NJSC32_CMD_AUTO_COMMAND_PHASE | 2635 1.2.2.2 tron NJSC32_CMD_AUTO_SCSI_RESTART | 2636 1.2.2.2 tron NJSC32_CMD_AUTO_MSGIN_00_04 | 2637 1.2.2.2 tron NJSC32_CMD_AUTO_MSGIN_02 | 2638 1.2.2.2 tron NJSC32_CMD_AUTO_ATN); 2639 1.2.2.2 tron } 2640 1.2.2.2 tron goto out; 2641 1.2.2.2 tron } 2642 1.2.2.2 tron 2643 1.2.2.2 tron /* 2644 1.2.2.2 tron * data has been transferred, and current pointer 2645 1.2.2.2 tron * is changed 2646 1.2.2.2 tron */ 2647 1.2.2.3.2.1 tron sackcnt = njsc32_read_4(sc, NJSC32_REG_SACK_CNT); 2648 1.2.2.3.2.1 tron 2649 1.2.2.3.2.1 tron /* 2650 1.2.2.3.2.1 tron * The controller returns extra ACK count 2651 1.2.2.3.2.1 tron * if the DMA buffer is not 4byte aligned. 2652 1.2.2.3.2.1 tron */ 2653 1.2.2.3.2.1 tron cntoffset = le32toh(cmd->c_sgt[0].sg_addr) & 3; 2654 1.2.2.3.2.1 tron #ifdef NJSC32_DEBUG 2655 1.2.2.3.2.1 tron if (cntoffset != 0) { 2656 1.2.2.3.2.1 tron printf("sackcnt %u, cntoffset %u\n", 2657 1.2.2.3.2.1 tron sackcnt, cntoffset); 2658 1.2.2.3.2.1 tron } 2659 1.2.2.3.2.1 tron #endif 2660 1.2.2.3.2.1 tron /* advance SCSI pointer */ 2661 1.2.2.3.2.1 tron njsc32_set_cur_ptr(cmd, 2662 1.2.2.3.2.1 tron cmd->c_dp_cur + sackcnt - cntoffset); 2663 1.2.2.2 tron } 2664 1.2.2.2 tron 2665 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_MSGOUT) { 2666 1.2.2.2 tron /* Message Out phase has been automatically processed */ 2667 1.2.2.2 tron TPRINTC(cmd, ("njsc32_intr: Message Out\n")); 2668 1.2.2.2 tron if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 && 2669 1.2.2.2 tron sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) { 2670 1.2.2.2 tron njsc32_init_msgout(sc); 2671 1.2.2.2 tron } 2672 1.2.2.2 tron } 2673 1.2.2.2 tron 2674 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_STATUS) { 2675 1.2.2.2 tron /* Status phase has been automatically processed */ 2676 1.2.2.2 tron cmd->c_xs->status = 2677 1.2.2.2 tron njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2678 1.2.2.2 tron TPRINTC(cmd, ("njsc32_intr: Status %#x\n", 2679 1.2.2.2 tron cmd->c_xs->status)); 2680 1.2.2.2 tron } 2681 1.2.2.2 tron 2682 1.2.2.2 tron if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2683 1.2.2.2 tron /* AutoSCSI is finished */ 2684 1.2.2.2 tron 2685 1.2.2.2 tron TPRINTC(cmd, ("njsc32_intr: Bus Free\n")); 2686 1.2.2.2 tron 2687 1.2.2.2 tron sc->sc_stat = NJSC32_STAT_IDLE; 2688 1.2.2.2 tron sc->sc_curcmd = NULL; 2689 1.2.2.2 tron 2690 1.2.2.2 tron njsc32_end_auto(sc, cmd, auto_phase); 2691 1.2.2.2 tron } 2692 1.2.2.2 tron goto out; 2693 1.2.2.2 tron } 2694 1.2.2.2 tron 2695 1.2.2.2 tron if (intr & NJSC32_IRQ_FIFO_THRESHOLD) { 2696 1.2.2.2 tron /* XXX We use DMA, and this shouldn't happen */ 2697 1.2.2.2 tron printf("%s: njsc32_intr: FIFO\n", sc->sc_dev.dv_xname); 2698 1.2.2.2 tron njsc32_init(sc, 1); 2699 1.2.2.2 tron goto out; 2700 1.2.2.2 tron } 2701 1.2.2.2 tron if (intr & NJSC32_IRQ_PCI) { 2702 1.2.2.2 tron /* XXX? */ 2703 1.2.2.2 tron printf("%s: njsc32_intr: PCI\n", sc->sc_dev.dv_xname); 2704 1.2.2.2 tron } 2705 1.2.2.2 tron if (intr & NJSC32_IRQ_BMCNTERR) { 2706 1.2.2.2 tron /* XXX? */ 2707 1.2.2.2 tron printf("%s: njsc32_intr: BM\n", sc->sc_dev.dv_xname); 2708 1.2.2.2 tron } 2709 1.2.2.2 tron 2710 1.2.2.2 tron out: 2711 1.2.2.2 tron /* go next command if controller is idle */ 2712 1.2.2.2 tron if (sc->sc_stat == NJSC32_STAT_IDLE) 2713 1.2.2.2 tron njsc32_start(sc); 2714 1.2.2.2 tron 2715 1.2.2.2 tron #if 0 2716 1.2.2.2 tron /* enable interrupts */ 2717 1.2.2.2 tron njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 2718 1.2.2.2 tron #endif 2719 1.2.2.2 tron 2720 1.2.2.2 tron return 1; /* processed */ 2721 1.2.2.2 tron } 2722
Indexes created Tue Oct 28 12:10:06 GMT 2025