ninjascsi32.c revision 1.2.4.2
1 1.2.4.2 skrll /* $NetBSD: ninjascsi32.c,v 1.2.4.2 2004/09/03 12:45:18 skrll Exp $ */ 2 1.2.4.2 skrll 3 1.2.4.2 skrll /*- 4 1.2.4.2 skrll * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 1.2.4.2 skrll * All rights reserved. 6 1.2.4.2 skrll * 7 1.2.4.2 skrll * This code is derived from software contributed to The NetBSD Foundation 8 1.2.4.2 skrll * by ITOH Yasufumi. 9 1.2.4.2 skrll * 10 1.2.4.2 skrll * Redistribution and use in source and binary forms, with or without 11 1.2.4.2 skrll * modification, are permitted provided that the following conditions 12 1.2.4.2 skrll * are met: 13 1.2.4.2 skrll * 1. Redistributions of source code must retain the above copyright 14 1.2.4.2 skrll * notice, this list of conditions and the following disclaimer. 15 1.2.4.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.4.2 skrll * notice, this list of conditions and the following disclaimer in the 17 1.2.4.2 skrll * documentation and/or other materials provided with the distribution. 18 1.2.4.2 skrll * 3. All advertising materials mentioning features or use of this software 19 1.2.4.2 skrll * must display the following acknowledgement: 20 1.2.4.2 skrll * This product includes software developed by the NetBSD 21 1.2.4.2 skrll * Foundation, Inc. and its contributors. 22 1.2.4.2 skrll * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.2.4.2 skrll * contributors may be used to endorse or promote products derived 24 1.2.4.2 skrll * from this software without specific prior written permission. 25 1.2.4.2 skrll * 26 1.2.4.2 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.2.4.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.2.4.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.2.4.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.2.4.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.2.4.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.2.4.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.2.4.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.2.4.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.2.4.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.2.4.2 skrll * POSSIBILITY OF SUCH DAMAGE. 37 1.2.4.2 skrll */ 38 1.2.4.2 skrll 39 1.2.4.2 skrll #include <sys/cdefs.h> 40 1.2.4.2 skrll __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.2.4.2 2004/09/03 12:45:18 skrll Exp $"); 41 1.2.4.2 skrll 42 1.2.4.2 skrll #include <sys/param.h> 43 1.2.4.2 skrll #include <sys/systm.h> 44 1.2.4.2 skrll #include <sys/callout.h> 45 1.2.4.2 skrll #include <sys/device.h> 46 1.2.4.2 skrll #include <sys/kernel.h> 47 1.2.4.2 skrll #include <sys/buf.h> 48 1.2.4.2 skrll #include <sys/scsiio.h> 49 1.2.4.2 skrll 50 1.2.4.2 skrll #include <machine/bus.h> 51 1.2.4.2 skrll #include <machine/intr.h> 52 1.2.4.2 skrll 53 1.2.4.2 skrll #include <uvm/uvm_extern.h> 54 1.2.4.2 skrll 55 1.2.4.2 skrll #include <dev/scsipi/scsi_all.h> 56 1.2.4.2 skrll #include <dev/scsipi/scsipi_all.h> 57 1.2.4.2 skrll #include <dev/scsipi/scsiconf.h> 58 1.2.4.2 skrll #include <dev/scsipi/scsi_message.h> 59 1.2.4.2 skrll 60 1.2.4.2 skrll /* 61 1.2.4.2 skrll * DualEdge transfer support 62 1.2.4.2 skrll */ 63 1.2.4.2 skrll /* #define NJSC32_DUALEDGE */ /* XXX untested */ 64 1.2.4.2 skrll 65 1.2.4.2 skrll /* 66 1.2.4.2 skrll * Auto param loading does not work properly (it partially works (works on 67 1.2.4.2 skrll * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51), 68 1.2.4.2 skrll * and it doesn't improve the performance so much, 69 1.2.4.2 skrll * forget about it. 70 1.2.4.2 skrll */ 71 1.2.4.2 skrll #undef NJSC32_AUTOPARAM 72 1.2.4.2 skrll 73 1.2.4.2 skrll #include <dev/ic/ninjascsi32reg.h> 74 1.2.4.2 skrll #include <dev/ic/ninjascsi32var.h> 75 1.2.4.2 skrll 76 1.2.4.2 skrll /* #define NJSC32_DEBUG */ 77 1.2.4.2 skrll /* #define NJSC32_TRACE */ 78 1.2.4.2 skrll 79 1.2.4.2 skrll #ifdef NJSC32_DEBUG 80 1.2.4.2 skrll #define DPRINTF(x) printf x 81 1.2.4.2 skrll #define DPRINTC(cmd, x) PRINTC(cmd, x) 82 1.2.4.2 skrll #else 83 1.2.4.2 skrll #define DPRINTF(x) 84 1.2.4.2 skrll #define DPRINTC(cmd, x) 85 1.2.4.2 skrll #endif 86 1.2.4.2 skrll #ifdef NJSC32_TRACE 87 1.2.4.2 skrll #define TPRINTF(x) printf x 88 1.2.4.2 skrll #define TPRINTC(cmd, x) PRINTC(cmd, x) 89 1.2.4.2 skrll #else 90 1.2.4.2 skrll #define TPRINTF(x) 91 1.2.4.2 skrll #define TPRINTC(cmd, x) 92 1.2.4.2 skrll #endif 93 1.2.4.2 skrll 94 1.2.4.2 skrll #define PRINTC(cmd, x) do { \ 95 1.2.4.2 skrll scsi_print_addr((cmd)->c_xs->xs_periph); \ 96 1.2.4.2 skrll printf x; \ 97 1.2.4.2 skrll } while (/* CONSTCOND */ 0) 98 1.2.4.2 skrll 99 1.2.4.2 skrll static void njsc32_scsipi_request(struct scsipi_channel *, 100 1.2.4.2 skrll scsipi_adapter_req_t, void *); 101 1.2.4.2 skrll static void njsc32_scsipi_minphys(struct buf *buf); 102 1.2.4.2 skrll static int njsc32_scsipi_ioctl(struct scsipi_channel *, u_long, caddr_t, 103 1.2.4.2 skrll int, struct proc *); 104 1.2.4.2 skrll 105 1.2.4.2 skrll static void njsc32_init(struct njsc32_softc *, int nosleep); 106 1.2.4.2 skrll static int njsc32_init_cmds(struct njsc32_softc *); 107 1.2.4.2 skrll static void njsc32_target_async(struct njsc32_softc *, 108 1.2.4.2 skrll struct njsc32_target *); 109 1.2.4.2 skrll static void njsc32_init_targets(struct njsc32_softc *); 110 1.2.4.2 skrll static void njsc32_add_msgout(struct njsc32_softc *, int); 111 1.2.4.2 skrll static u_int32_t njsc32_get_auto_msgout(struct njsc32_softc *); 112 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 113 1.2.4.2 skrll static void njsc32_msgout_wdtr(struct njsc32_softc *, int); 114 1.2.4.2 skrll #endif 115 1.2.4.2 skrll static void njsc32_msgout_sdtr(struct njsc32_softc *, int period, 116 1.2.4.2 skrll int offset); 117 1.2.4.2 skrll static void njsc32_negotiate_xfer(struct njsc32_softc *, 118 1.2.4.2 skrll struct njsc32_target *); 119 1.2.4.2 skrll static void njsc32_arbitration_failed(struct njsc32_softc *); 120 1.2.4.2 skrll static void njsc32_start(struct njsc32_softc *); 121 1.2.4.2 skrll static void njsc32_run_xfer(struct njsc32_softc *, struct scsipi_xfer *); 122 1.2.4.2 skrll static void njsc32_end_cmd(struct njsc32_softc *, struct njsc32_cmd *, 123 1.2.4.2 skrll scsipi_xfer_result_t); 124 1.2.4.2 skrll static void njsc32_reset_bus(struct njsc32_softc *); 125 1.2.4.2 skrll static void njsc32_clear_cmds(struct njsc32_softc *, 126 1.2.4.2 skrll scsipi_xfer_result_t); 127 1.2.4.2 skrll static void njsc32_reset_detected(struct njsc32_softc *); 128 1.2.4.2 skrll static void njsc32_set_ptr(struct njsc32_softc *, struct njsc32_cmd *, 129 1.2.4.2 skrll u_int32_t); 130 1.2.4.2 skrll static void njsc32_assert_ack(struct njsc32_softc *); 131 1.2.4.2 skrll static void njsc32_negate_ack(struct njsc32_softc *); 132 1.2.4.2 skrll static void njsc32_wait_req_negate(struct njsc32_softc *); 133 1.2.4.2 skrll static void njsc32_reconnect(struct njsc32_softc *, struct njsc32_cmd *); 134 1.2.4.2 skrll enum njsc32_reselstat { 135 1.2.4.2 skrll NJSC32_RESEL_ERROR, /* to be rejected */ 136 1.2.4.2 skrll NJSC32_RESEL_COMPLETE, /* reselection is just complete */ 137 1.2.4.2 skrll NJSC32_RESEL_THROUGH /* this message is OK (no reply) */ 138 1.2.4.2 skrll }; 139 1.2.4.2 skrll static enum njsc32_reselstat njsc32_resel_identify(struct njsc32_softc *, 140 1.2.4.2 skrll int lun, struct njsc32_cmd **); 141 1.2.4.2 skrll static enum njsc32_reselstat njsc32_resel_tag(struct njsc32_softc *, 142 1.2.4.2 skrll int tag, struct njsc32_cmd **); 143 1.2.4.2 skrll static void njsc32_cmd_reload(struct njsc32_softc *, struct njsc32_cmd *, 144 1.2.4.2 skrll int); 145 1.2.4.2 skrll static void njsc32_update_xfer_mode(struct njsc32_softc *, 146 1.2.4.2 skrll struct njsc32_target *); 147 1.2.4.2 skrll static void njsc32_msgin(struct njsc32_softc *); 148 1.2.4.2 skrll static void njsc32_msgout(struct njsc32_softc *); 149 1.2.4.2 skrll static void njsc32_cmdtimeout(void *); 150 1.2.4.2 skrll static void njsc32_reseltimeout(void *); 151 1.2.4.2 skrll 152 1.2.4.2 skrll static __inline unsigned 153 1.2.4.2 skrll njsc32_read_1(struct njsc32_softc *sc, int no) 154 1.2.4.2 skrll { 155 1.2.4.2 skrll 156 1.2.4.2 skrll return bus_space_read_1(sc->sc_regt, sc->sc_regh, no); 157 1.2.4.2 skrll } 158 1.2.4.2 skrll 159 1.2.4.2 skrll static __inline unsigned 160 1.2.4.2 skrll njsc32_read_2(struct njsc32_softc *sc, int no) 161 1.2.4.2 skrll { 162 1.2.4.2 skrll 163 1.2.4.2 skrll return bus_space_read_2(sc->sc_regt, sc->sc_regh, no); 164 1.2.4.2 skrll } 165 1.2.4.2 skrll 166 1.2.4.2 skrll static __inline u_int32_t 167 1.2.4.2 skrll njsc32_read_4(struct njsc32_softc *sc, int no) 168 1.2.4.2 skrll { 169 1.2.4.2 skrll 170 1.2.4.2 skrll return bus_space_read_4(sc->sc_regt, sc->sc_regh, no); 171 1.2.4.2 skrll } 172 1.2.4.2 skrll 173 1.2.4.2 skrll static __inline void 174 1.2.4.2 skrll njsc32_write_1(struct njsc32_softc *sc, int no, int val) 175 1.2.4.2 skrll { 176 1.2.4.2 skrll 177 1.2.4.2 skrll bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val); 178 1.2.4.2 skrll } 179 1.2.4.2 skrll 180 1.2.4.2 skrll static __inline void 181 1.2.4.2 skrll njsc32_write_2(struct njsc32_softc *sc, int no, int val) 182 1.2.4.2 skrll { 183 1.2.4.2 skrll 184 1.2.4.2 skrll bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val); 185 1.2.4.2 skrll } 186 1.2.4.2 skrll 187 1.2.4.2 skrll static __inline void 188 1.2.4.2 skrll njsc32_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 189 1.2.4.2 skrll { 190 1.2.4.2 skrll 191 1.2.4.2 skrll bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val); 192 1.2.4.2 skrll } 193 1.2.4.2 skrll 194 1.2.4.2 skrll static __inline unsigned 195 1.2.4.2 skrll njsc32_ireg_read_1(struct njsc32_softc *sc, int no) 196 1.2.4.2 skrll { 197 1.2.4.2 skrll 198 1.2.4.2 skrll bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 199 1.2.4.2 skrll return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 200 1.2.4.2 skrll } 201 1.2.4.2 skrll 202 1.2.4.2 skrll static __inline unsigned 203 1.2.4.2 skrll njsc32_ireg_read_2(struct njsc32_softc *sc, int no) 204 1.2.4.2 skrll { 205 1.2.4.2 skrll 206 1.2.4.2 skrll bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 207 1.2.4.2 skrll return bus_space_read_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 208 1.2.4.2 skrll } 209 1.2.4.2 skrll 210 1.2.4.2 skrll static __inline u_int32_t 211 1.2.4.2 skrll njsc32_ireg_read_4(struct njsc32_softc *sc, int no) 212 1.2.4.2 skrll { 213 1.2.4.2 skrll u_int32_t val; 214 1.2.4.2 skrll 215 1.2.4.2 skrll bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 216 1.2.4.2 skrll val = (u_int16_t)bus_space_read_2(sc->sc_regt, sc->sc_regh, 217 1.2.4.2 skrll NJSC32_REG_DATA_LOW); 218 1.2.4.2 skrll return val | (bus_space_read_2(sc->sc_regt, sc->sc_regh, 219 1.2.4.2 skrll NJSC32_REG_DATA_HIGH) << 16); 220 1.2.4.2 skrll } 221 1.2.4.2 skrll 222 1.2.4.2 skrll static __inline void 223 1.2.4.2 skrll njsc32_ireg_write_1(struct njsc32_softc *sc, int no, int val) 224 1.2.4.2 skrll { 225 1.2.4.2 skrll 226 1.2.4.2 skrll bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 227 1.2.4.2 skrll bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 228 1.2.4.2 skrll } 229 1.2.4.2 skrll 230 1.2.4.2 skrll static __inline void 231 1.2.4.2 skrll njsc32_ireg_write_2(struct njsc32_softc *sc, int no, int val) 232 1.2.4.2 skrll { 233 1.2.4.2 skrll 234 1.2.4.2 skrll bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 235 1.2.4.2 skrll bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 236 1.2.4.2 skrll } 237 1.2.4.2 skrll 238 1.2.4.2 skrll static __inline void 239 1.2.4.2 skrll njsc32_ireg_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 240 1.2.4.2 skrll { 241 1.2.4.2 skrll 242 1.2.4.2 skrll bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 243 1.2.4.2 skrll bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 244 1.2.4.2 skrll bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_HIGH, 245 1.2.4.2 skrll val >> 16); 246 1.2.4.2 skrll } 247 1.2.4.2 skrll 248 1.2.4.2 skrll #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */ 249 1.2.4.2 skrll #ifdef __STDC__ 250 1.2.4.2 skrll # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK 251 1.2.4.2 skrll # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \ 252 1.2.4.2 skrll NJSC32_SREQ_SAMPLING_ENABLE) 253 1.2.4.2 skrll #else 254 1.2.4.2 skrll # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK 255 1.2.4.2 skrll # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \ 256 1.2.4.2 skrll NJSC32_SREQ_SAMPLING_ENABLE) 257 1.2.4.2 skrll #endif 258 1.2.4.2 skrll 259 1.2.4.2 skrll #define NJSC32_NSYNCT_MAXSYNC 1 260 1.2.4.2 skrll #define NJSC32_NSYNCT 16 261 1.2.4.2 skrll 262 1.2.4.2 skrll /* 40MHz (25ns) */ 263 1.2.4.2 skrll static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = { 264 1.2.4.2 skrll { 0, 0, 0 }, /* dummy for async */ 265 1.2.4.2 skrll { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */ 266 1.2.4.2 skrll { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */ 267 1.2.4.2 skrll { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */ 268 1.2.4.2 skrll { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */ 269 1.2.4.2 skrll { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */ 270 1.2.4.2 skrll { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */ 271 1.2.4.2 skrll { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 272 1.2.4.2 skrll { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */ 273 1.2.4.2 skrll { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 274 1.2.4.2 skrll { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */ 275 1.2.4.2 skrll { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */ 276 1.2.4.2 skrll { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */ 277 1.2.4.2 skrll { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */ 278 1.2.4.2 skrll { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */ 279 1.2.4.2 skrll { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */ 280 1.2.4.2 skrll }; 281 1.2.4.2 skrll 282 1.2.4.2 skrll #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 283 1.2.4.2 skrll /* 20MHz (50ns) */ 284 1.2.4.2 skrll static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = { 285 1.2.4.2 skrll { 0, 0, 0 }, /* dummy for async */ 286 1.2.4.2 skrll { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */ 287 1.2.4.2 skrll { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */ 288 1.2.4.2 skrll { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 289 1.2.4.2 skrll { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 290 1.2.4.2 skrll { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */ 291 1.2.4.2 skrll { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */ 292 1.2.4.2 skrll { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */ 293 1.2.4.2 skrll { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */ 294 1.2.4.2 skrll { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */ 295 1.2.4.2 skrll { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */ 296 1.2.4.2 skrll { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */ 297 1.2.4.2 skrll { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */ 298 1.2.4.2 skrll { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */ 299 1.2.4.2 skrll { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */ 300 1.2.4.2 skrll { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */ 301 1.2.4.2 skrll }; 302 1.2.4.2 skrll 303 1.2.4.2 skrll /* 33.3MHz (30ns) */ 304 1.2.4.2 skrll static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = { 305 1.2.4.2 skrll { 0, 0, 0 }, /* dummy for async */ 306 1.2.4.2 skrll { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */ 307 1.2.4.2 skrll { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */ 308 1.2.4.2 skrll { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */ 309 1.2.4.2 skrll { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */ 310 1.2.4.2 skrll { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */ 311 1.2.4.2 skrll { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */ 312 1.2.4.2 skrll { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */ 313 1.2.4.2 skrll { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */ 314 1.2.4.2 skrll { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */ 315 1.2.4.2 skrll { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */ 316 1.2.4.2 skrll { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */ 317 1.2.4.2 skrll { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */ 318 1.2.4.2 skrll { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */ 319 1.2.4.2 skrll { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */ 320 1.2.4.2 skrll { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */ 321 1.2.4.2 skrll }; 322 1.2.4.2 skrll #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */ 323 1.2.4.2 skrll 324 1.2.4.2 skrll #undef NS 325 1.2.4.2 skrll #undef ACKW 326 1.2.4.2 skrll #undef SMPL 327 1.2.4.2 skrll 328 1.2.4.2 skrll /* initialize device */ 329 1.2.4.2 skrll static void 330 1.2.4.2 skrll njsc32_init(struct njsc32_softc *sc, int nosleep) 331 1.2.4.2 skrll { 332 1.2.4.2 skrll u_int16_t intstat; 333 1.2.4.2 skrll 334 1.2.4.2 skrll /* block all interrupts */ 335 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 336 1.2.4.2 skrll 337 1.2.4.2 skrll /* clear transfer */ 338 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 339 1.2.4.2 skrll njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0); 340 1.2.4.2 skrll 341 1.2.4.2 skrll /* make sure interrupts are cleared */ 342 1.2.4.2 skrll /* XXX loop forever? */ 343 1.2.4.2 skrll while ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ)) & 344 1.2.4.2 skrll NJSC32_IRQ_INTR_PENDING) { 345 1.2.4.2 skrll DPRINTF(("%s: njsc32_init: intr pending: %#x\n", 346 1.2.4.2 skrll sc->sc_dev.dv_xname, intstat)); 347 1.2.4.2 skrll } 348 1.2.4.2 skrll 349 1.2.4.2 skrll /* FIFO threshold */ 350 1.2.4.2 skrll njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL, 351 1.2.4.2 skrll NJSC32_FIFO_FULL_BUSMASTER); 352 1.2.4.2 skrll njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY, 353 1.2.4.2 skrll NJSC32_FIFO_EMPTY_BUSMASTER); 354 1.2.4.2 skrll 355 1.2.4.2 skrll /* clock source */ 356 1.2.4.2 skrll njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk); 357 1.2.4.2 skrll 358 1.2.4.2 skrll /* memory read multiple */ 359 1.2.4.2 skrll njsc32_ireg_write_1(sc, NJSC32_IREG_BM, 360 1.2.4.2 skrll NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD); 361 1.2.4.2 skrll 362 1.2.4.2 skrll /* clear parity error and enable parity detection */ 363 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 364 1.2.4.2 skrll NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 365 1.2.4.2 skrll 366 1.2.4.2 skrll /* misc configuration */ 367 1.2.4.2 skrll njsc32_ireg_write_2(sc, NJSC32_IREG_MISC, 368 1.2.4.2 skrll NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT | 369 1.2.4.2 skrll NJSC32_MISC_DELAYED_BMSTART | 370 1.2.4.2 skrll NJSC32_MISC_MASTER_TERMINATION_SELECT | 371 1.2.4.2 skrll NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL | 372 1.2.4.2 skrll NJSC32_MISC_AUTOSEL_TIMING_SEL | 373 1.2.4.2 skrll NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE); 374 1.2.4.2 skrll 375 1.2.4.2 skrll /* 376 1.2.4.2 skrll * Check for termination power (32Bi only?). 377 1.2.4.2 skrll */ 378 1.2.4.2 skrll if (!nosleep || cold) { 379 1.2.4.2 skrll DPRINTF(("%s: njsc32_init: checking TERMPWR\n", 380 1.2.4.2 skrll sc->sc_dev.dv_xname)); 381 1.2.4.2 skrll 382 1.2.4.2 skrll /* First, turn termination power off */ 383 1.2.4.2 skrll njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0); 384 1.2.4.2 skrll 385 1.2.4.2 skrll /* give 0.5s to settle */ 386 1.2.4.2 skrll if (nosleep) 387 1.2.4.2 skrll delay(500000); 388 1.2.4.2 skrll else 389 1.2.4.2 skrll tsleep(sc, PWAIT, "njs_t1", hz / 2); 390 1.2.4.2 skrll } 391 1.2.4.2 skrll 392 1.2.4.2 skrll /* supply termination power if not supplied by other devices */ 393 1.2.4.2 skrll if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) & 394 1.2.4.2 skrll NJSC32_TERMPWR_SENSE) == 0) { 395 1.2.4.2 skrll /* termination power is not present on the bus */ 396 1.2.4.2 skrll if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) { 397 1.2.4.2 skrll /* 398 1.2.4.2 skrll * CardBus device must not supply termination power 399 1.2.4.2 skrll * to avoid excessive power consumption. 400 1.2.4.2 skrll */ 401 1.2.4.2 skrll printf("%s: no termination power present\n", 402 1.2.4.2 skrll sc->sc_dev.dv_xname); 403 1.2.4.2 skrll } else { 404 1.2.4.2 skrll /* supply termination power */ 405 1.2.4.2 skrll njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 406 1.2.4.2 skrll NJSC32_TERMPWR_BPWR); 407 1.2.4.2 skrll 408 1.2.4.2 skrll DPRINTF(("%s: supplying termination power\n", 409 1.2.4.2 skrll sc->sc_dev.dv_xname)); 410 1.2.4.2 skrll 411 1.2.4.2 skrll /* give 0.5s to settle */ 412 1.2.4.2 skrll if (!nosleep) 413 1.2.4.2 skrll tsleep(sc, PWAIT, "njs_t2", hz / 2); 414 1.2.4.2 skrll } 415 1.2.4.2 skrll } 416 1.2.4.2 skrll 417 1.2.4.2 skrll /* stop timer */ 418 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 419 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 420 1.2.4.2 skrll 421 1.2.4.2 skrll /* default transfer parameter */ 422 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SYNC, 0); 423 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK); 424 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT, 425 1.2.4.2 skrll NJSC32_SEL_TIMEOUT_TIME); 426 1.2.4.2 skrll 427 1.2.4.2 skrll /* select interrupt source */ 428 1.2.4.2 skrll njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT, 429 1.2.4.2 skrll NJSC32_IRQSEL_RESELECT | 430 1.2.4.2 skrll NJSC32_IRQSEL_PHASE_CHANGE | 431 1.2.4.2 skrll NJSC32_IRQSEL_SCSIRESET | 432 1.2.4.2 skrll NJSC32_IRQSEL_TIMER | 433 1.2.4.2 skrll NJSC32_IRQSEL_FIFO_THRESHOLD | 434 1.2.4.2 skrll NJSC32_IRQSEL_TARGET_ABORT | 435 1.2.4.2 skrll NJSC32_IRQSEL_MASTER_ABORT | 436 1.2.4.2 skrll /* XXX not yet 437 1.2.4.2 skrll NJSC32_IRQSEL_SERR | 438 1.2.4.2 skrll NJSC32_IRQSEL_PERR | 439 1.2.4.2 skrll NJSC32_IRQSEL_BMCNTERR | 440 1.2.4.2 skrll */ 441 1.2.4.2 skrll NJSC32_IRQSEL_AUTO_SCSI_SEQ); 442 1.2.4.2 skrll 443 1.2.4.2 skrll /* unblock interrupts */ 444 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 445 1.2.4.2 skrll 446 1.2.4.2 skrll /* turn LED off */ 447 1.2.4.2 skrll njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR, 448 1.2.4.2 skrll NJSC32_EXTPORT_LED_OFF); 449 1.2.4.2 skrll njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, 450 1.2.4.2 skrll NJSC32_EXTPORT_LED_OFF); 451 1.2.4.2 skrll 452 1.2.4.2 skrll /* reset SCSI bus so the targets become known state */ 453 1.2.4.2 skrll njsc32_reset_bus(sc); 454 1.2.4.2 skrll } 455 1.2.4.2 skrll 456 1.2.4.2 skrll static int 457 1.2.4.2 skrll njsc32_init_cmds(struct njsc32_softc *sc) 458 1.2.4.2 skrll { 459 1.2.4.2 skrll struct njsc32_cmd *cmd; 460 1.2.4.2 skrll bus_addr_t dmaaddr; 461 1.2.4.2 skrll int i, error; 462 1.2.4.2 skrll 463 1.2.4.2 skrll /* 464 1.2.4.2 skrll * allocate DMA area for command 465 1.2.4.2 skrll */ 466 1.2.4.2 skrll if ((error = bus_dmamem_alloc(sc->sc_dmat, 467 1.2.4.2 skrll sizeof(struct njsc32_dma_page), PAGE_SIZE, 0, 468 1.2.4.2 skrll &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) { 469 1.2.4.2 skrll printf("%s: unable to allocate cmd page, error = %d\n", 470 1.2.4.2 skrll sc->sc_dev.dv_xname, error); 471 1.2.4.2 skrll return 0; 472 1.2.4.2 skrll } 473 1.2.4.2 skrll if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg, 474 1.2.4.2 skrll sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page), 475 1.2.4.2 skrll (caddr_t *)&sc->sc_cmdpg, 476 1.2.4.2 skrll BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 477 1.2.4.2 skrll printf("%s: unable to map cmd page, error = %d\n", 478 1.2.4.2 skrll sc->sc_dev.dv_xname, error); 479 1.2.4.2 skrll goto fail1; 480 1.2.4.2 skrll } 481 1.2.4.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, 482 1.2.4.2 skrll sizeof(struct njsc32_dma_page), 1, 483 1.2.4.2 skrll sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT, 484 1.2.4.2 skrll &sc->sc_dmamap_cmdpg)) != 0) { 485 1.2.4.2 skrll printf("%s: unable to create cmd DMA map, error = %d\n", 486 1.2.4.2 skrll sc->sc_dev.dv_xname, error); 487 1.2.4.2 skrll goto fail2; 488 1.2.4.2 skrll } 489 1.2.4.2 skrll if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg, 490 1.2.4.2 skrll sc->sc_cmdpg, sizeof(struct njsc32_dma_page), 491 1.2.4.2 skrll NULL, BUS_DMA_NOWAIT)) != 0) { 492 1.2.4.2 skrll printf("%s: unable to load cmd DMA map, error = %d\n", 493 1.2.4.2 skrll sc->sc_dev.dv_xname, error); 494 1.2.4.2 skrll goto fail3; 495 1.2.4.2 skrll } 496 1.2.4.2 skrll 497 1.2.4.2 skrll memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page)); 498 1.2.4.2 skrll dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr; 499 1.2.4.2 skrll 500 1.2.4.2 skrll #ifdef NJSC32_AUTOPARAM 501 1.2.4.2 skrll sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap); 502 1.2.4.2 skrll #endif 503 1.2.4.2 skrll 504 1.2.4.2 skrll for (i = 0; i < NJSC32_NUM_CMD; i++) { 505 1.2.4.2 skrll cmd = &sc->sc_cmds[i]; 506 1.2.4.2 skrll cmd->c_sc = sc; 507 1.2.4.2 skrll cmd->c_sgt = sc->sc_cmdpg->dp_sg[i]; 508 1.2.4.2 skrll cmd->c_sgt_dma = dmaaddr + 509 1.2.4.2 skrll offsetof(struct njsc32_dma_page, dp_sg[i]); 510 1.2.4.2 skrll cmd->c_flags = 0; 511 1.2.4.2 skrll 512 1.2.4.2 skrll error = bus_dmamap_create(sc->sc_dmat, 513 1.2.4.2 skrll NJSC32_MAX_XFER, /* max total map size */ 514 1.2.4.2 skrll NJSC32_NUM_SG, /* max number of segments */ 515 1.2.4.2 skrll NJSC32_SGT_MAXSEGLEN, /* max size of a segment */ 516 1.2.4.2 skrll 0, /* boundary */ 517 1.2.4.2 skrll BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer); 518 1.2.4.2 skrll if (error) { 519 1.2.4.2 skrll printf("%s: only %d cmd descs available (error = %d)\n", 520 1.2.4.2 skrll sc->sc_dev.dv_xname, i, error); 521 1.2.4.2 skrll break; 522 1.2.4.2 skrll } 523 1.2.4.2 skrll TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q); 524 1.2.4.2 skrll } 525 1.2.4.2 skrll 526 1.2.4.2 skrll if (i > 0) 527 1.2.4.2 skrll return i; 528 1.2.4.2 skrll 529 1.2.4.2 skrll fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 530 1.2.4.2 skrll fail2: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg, 531 1.2.4.2 skrll sizeof(struct njsc32_dma_page)); 532 1.2.4.2 skrll fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs); 533 1.2.4.2 skrll 534 1.2.4.2 skrll return 0; 535 1.2.4.2 skrll } 536 1.2.4.2 skrll 537 1.2.4.2 skrll static void 538 1.2.4.2 skrll njsc32_target_async(struct njsc32_softc *sc, struct njsc32_target *target) 539 1.2.4.2 skrll { 540 1.2.4.2 skrll 541 1.2.4.2 skrll target->t_sync = 542 1.2.4.2 skrll NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC); 543 1.2.4.2 skrll target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK; 544 1.2.4.2 skrll target->t_sample = 0; /* disable */ 545 1.2.4.2 skrll target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC; 546 1.2.4.2 skrll target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC; 547 1.2.4.2 skrll } 548 1.2.4.2 skrll 549 1.2.4.2 skrll static void 550 1.2.4.2 skrll njsc32_init_targets(struct njsc32_softc *sc) 551 1.2.4.2 skrll { 552 1.2.4.2 skrll int id, lun; 553 1.2.4.2 skrll struct njsc32_lu *lu; 554 1.2.4.2 skrll 555 1.2.4.2 skrll for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 556 1.2.4.2 skrll /* cancel negotiation status */ 557 1.2.4.2 skrll sc->sc_targets[id].t_state = NJSC32_TARST_INIT; 558 1.2.4.2 skrll 559 1.2.4.2 skrll /* default to async mode */ 560 1.2.4.2 skrll njsc32_target_async(sc, &sc->sc_targets[id]); 561 1.2.4.2 skrll 562 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 563 1.2.4.2 skrll sc->sc_targets[id].t_xferctl = 0; 564 1.2.4.2 skrll #endif 565 1.2.4.2 skrll 566 1.2.4.2 skrll sc->sc_targets[id].t_targetid = 567 1.2.4.2 skrll (1 << id) | (1 << NJSC32_INITIATOR_ID); 568 1.2.4.2 skrll 569 1.2.4.2 skrll /* init logical units */ 570 1.2.4.2 skrll for (lun = 0; lun < NJSC32_NLU; lun++) { 571 1.2.4.2 skrll lu = &sc->sc_targets[id].t_lus[lun]; 572 1.2.4.2 skrll lu->lu_cmd = NULL; 573 1.2.4.2 skrll TAILQ_INIT(&lu->lu_q); 574 1.2.4.2 skrll } 575 1.2.4.2 skrll } 576 1.2.4.2 skrll } 577 1.2.4.2 skrll 578 1.2.4.2 skrll void 579 1.2.4.2 skrll njsc32_attach(struct njsc32_softc *sc) 580 1.2.4.2 skrll { 581 1.2.4.2 skrll const char *str; 582 1.2.4.2 skrll #if 1 /* test */ 583 1.2.4.2 skrll int reg; 584 1.2.4.2 skrll njsc32_model_t detected_model; 585 1.2.4.2 skrll #endif 586 1.2.4.2 skrll 587 1.2.4.2 skrll /* init */ 588 1.2.4.2 skrll TAILQ_INIT(&sc->sc_freecmd); 589 1.2.4.2 skrll TAILQ_INIT(&sc->sc_reqcmd); 590 1.2.4.2 skrll 591 1.2.4.2 skrll #if 1 /* test */ 592 1.2.4.2 skrll /* 593 1.2.4.2 skrll * try to distinguish 32Bi and 32UDE 594 1.2.4.2 skrll */ 595 1.2.4.2 skrll /* try to set DualEdge bit (exists on 32UDE only) and read it back */ 596 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE); 597 1.2.4.2 skrll if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) { 598 1.2.4.2 skrll /* device was removed? */ 599 1.2.4.2 skrll aprint_error("%s: attach failed\n", sc->sc_dev.dv_xname); 600 1.2.4.2 skrll return; 601 1.2.4.2 skrll } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) { 602 1.2.4.2 skrll detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE; 603 1.2.4.2 skrll } else { 604 1.2.4.2 skrll detected_model = NJSC32_MODEL_32BI; 605 1.2.4.2 skrll } 606 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */ 607 1.2.4.2 skrll 608 1.2.4.2 skrll #if 1/*def DIAGNOSTIC*/ 609 1.2.4.2 skrll /* compare what is configured with what is detected */ 610 1.2.4.2 skrll if ((sc->sc_model & NJSC32_MODEL_MASK) != 611 1.2.4.2 skrll (detected_model & NJSC32_MODEL_MASK)) { 612 1.2.4.2 skrll /* 613 1.2.4.2 skrll * Please report this error if it happens. 614 1.2.4.2 skrll */ 615 1.2.4.2 skrll aprint_error("%s: model mismatch: %#x vs %#x\n", 616 1.2.4.2 skrll sc->sc_dev.dv_xname, sc->sc_model, detected_model); 617 1.2.4.2 skrll return; 618 1.2.4.2 skrll } 619 1.2.4.2 skrll #endif 620 1.2.4.2 skrll #endif 621 1.2.4.2 skrll 622 1.2.4.2 skrll /* check model */ 623 1.2.4.2 skrll switch (sc->sc_model & NJSC32_MODEL_MASK) { 624 1.2.4.2 skrll case NJSC32_MODEL_32BI: 625 1.2.4.2 skrll str = "Bi"; 626 1.2.4.2 skrll /* 32Bi doesn't support DualEdge transfer */ 627 1.2.4.2 skrll KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0); 628 1.2.4.2 skrll break; 629 1.2.4.2 skrll case NJSC32_MODEL_32UDE: 630 1.2.4.2 skrll str = "UDE"; 631 1.2.4.2 skrll break; 632 1.2.4.2 skrll default: 633 1.2.4.2 skrll aprint_error("%s: unknown model!\n", sc->sc_dev.dv_xname); 634 1.2.4.2 skrll return; 635 1.2.4.2 skrll } 636 1.2.4.2 skrll aprint_normal("%s: NJSC-32%s", sc->sc_dev.dv_xname, str); 637 1.2.4.2 skrll 638 1.2.4.2 skrll switch (sc->sc_clk) { 639 1.2.4.2 skrll default: 640 1.2.4.2 skrll #ifdef DIAGNOSTIC 641 1.2.4.2 skrll panic("njsc32_attach: unknown clk %d", sc->sc_clk); 642 1.2.4.2 skrll #endif 643 1.2.4.2 skrll case NJSC32_CLOCK_DIV_4: 644 1.2.4.2 skrll sc->sc_synct = njsc32_synct_40M; 645 1.2.4.2 skrll str = "40MHz"; 646 1.2.4.2 skrll break; 647 1.2.4.2 skrll #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 648 1.2.4.2 skrll case NJSC32_CLOCK_DIV_2: 649 1.2.4.2 skrll sc->sc_synct = njsc32_synct_20M; 650 1.2.4.2 skrll str = "20MHz"; 651 1.2.4.2 skrll break; 652 1.2.4.2 skrll case NJSC32_CLOCK_PCICLK: 653 1.2.4.2 skrll sc->sc_synct = njsc32_synct_pci; 654 1.2.4.2 skrll str = "PCI"; 655 1.2.4.2 skrll break; 656 1.2.4.2 skrll #endif 657 1.2.4.2 skrll } 658 1.2.4.2 skrll aprint_normal(", G/A rev %#x, clk %s%s\n", 659 1.2.4.2 skrll NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str, 660 1.2.4.2 skrll (sc->sc_model & NJSC32_FLAG_DUALEDGE) ? 661 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 662 1.2.4.2 skrll ", DualEdge" 663 1.2.4.2 skrll #else 664 1.2.4.2 skrll ", DualEdge (no driver support)" 665 1.2.4.2 skrll #endif 666 1.2.4.2 skrll : ""); 667 1.2.4.2 skrll 668 1.2.4.2 skrll /* allocate DMA resource */ 669 1.2.4.2 skrll if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) { 670 1.2.4.2 skrll printf("%s: no usable DMA map\n", sc->sc_dev.dv_xname); 671 1.2.4.2 skrll return; 672 1.2.4.2 skrll } 673 1.2.4.2 skrll sc->sc_flags |= NJSC32_CMDPG_MAPPED; 674 1.2.4.2 skrll 675 1.2.4.2 skrll sc->sc_curcmd = NULL; 676 1.2.4.2 skrll sc->sc_nusedcmds = 0; 677 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_IDLE; 678 1.2.4.2 skrll 679 1.2.4.2 skrll sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */ 680 1.2.4.2 skrll 681 1.2.4.2 skrll /* initialize target structure */ 682 1.2.4.2 skrll njsc32_init_targets(sc); 683 1.2.4.2 skrll 684 1.2.4.2 skrll /* initialize hardware */ 685 1.2.4.2 skrll njsc32_init(sc, cold); 686 1.2.4.2 skrll 687 1.2.4.2 skrll /* setup adapter */ 688 1.2.4.2 skrll sc->sc_adapter.adapt_dev = &sc->sc_dev; 689 1.2.4.2 skrll sc->sc_adapter.adapt_nchannels = 1; 690 1.2.4.2 skrll sc->sc_adapter.adapt_request = njsc32_scsipi_request; 691 1.2.4.2 skrll sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys; 692 1.2.4.2 skrll sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl; 693 1.2.4.2 skrll 694 1.2.4.2 skrll sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings = 695 1.2.4.2 skrll sc->sc_ncmd; 696 1.2.4.2 skrll 697 1.2.4.2 skrll /* setup channel */ 698 1.2.4.2 skrll sc->sc_channel.chan_adapter = &sc->sc_adapter; 699 1.2.4.2 skrll sc->sc_channel.chan_bustype = &scsi_bustype; 700 1.2.4.2 skrll sc->sc_channel.chan_channel = 0; 701 1.2.4.2 skrll sc->sc_channel.chan_ntargets = NJSC32_NTARGET; 702 1.2.4.2 skrll sc->sc_channel.chan_nluns = NJSC32_NLU; 703 1.2.4.2 skrll sc->sc_channel.chan_id = NJSC32_INITIATOR_ID; 704 1.2.4.2 skrll 705 1.2.4.2 skrll sc->sc_scsi = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 706 1.2.4.2 skrll } 707 1.2.4.2 skrll 708 1.2.4.2 skrll int 709 1.2.4.2 skrll njsc32_detach(struct njsc32_softc *sc, int flags) 710 1.2.4.2 skrll { 711 1.2.4.2 skrll int rv = 0; 712 1.2.4.2 skrll int i, s; 713 1.2.4.2 skrll struct njsc32_cmd *cmd; 714 1.2.4.2 skrll 715 1.2.4.2 skrll s = splbio(); 716 1.2.4.2 skrll 717 1.2.4.2 skrll /* clear running/disconnected commands */ 718 1.2.4.2 skrll njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP); 719 1.2.4.2 skrll 720 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_DETACH; 721 1.2.4.2 skrll 722 1.2.4.2 skrll /* clear pending commands */ 723 1.2.4.2 skrll while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 724 1.2.4.2 skrll TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 725 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, XS_RESET); 726 1.2.4.2 skrll } 727 1.2.4.2 skrll 728 1.2.4.2 skrll if (sc->sc_scsi != NULL) 729 1.2.4.2 skrll rv = config_detach(sc->sc_scsi, flags); 730 1.2.4.2 skrll 731 1.2.4.2 skrll splx(s); 732 1.2.4.2 skrll 733 1.2.4.2 skrll /* free DMA resource */ 734 1.2.4.2 skrll if (sc->sc_flags & NJSC32_CMDPG_MAPPED) { 735 1.2.4.2 skrll for (i = 0; i < sc->sc_ncmd; i++) { 736 1.2.4.2 skrll cmd = &sc->sc_cmds[i]; 737 1.2.4.2 skrll if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) 738 1.2.4.2 skrll bus_dmamap_unload(sc->sc_dmat, 739 1.2.4.2 skrll cmd->c_dmamap_xfer); 740 1.2.4.2 skrll bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer); 741 1.2.4.2 skrll } 742 1.2.4.2 skrll 743 1.2.4.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 744 1.2.4.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 745 1.2.4.2 skrll bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg, 746 1.2.4.2 skrll sizeof(struct njsc32_dma_page)); 747 1.2.4.2 skrll bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, 748 1.2.4.2 skrll sc->sc_cmdpg_nsegs); 749 1.2.4.2 skrll } 750 1.2.4.2 skrll 751 1.2.4.2 skrll return 0; 752 1.2.4.2 skrll } 753 1.2.4.2 skrll 754 1.2.4.2 skrll static __inline void 755 1.2.4.2 skrll njsc32_cmd_init(struct njsc32_cmd *cmd) 756 1.2.4.2 skrll { 757 1.2.4.2 skrll 758 1.2.4.2 skrll cmd->c_flags = 0; 759 1.2.4.2 skrll 760 1.2.4.2 skrll /* scatter/gather table */ 761 1.2.4.2 skrll cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0); 762 1.2.4.2 skrll cmd->c_sgoffset = 0; 763 1.2.4.2 skrll cmd->c_sgfixcnt = 0; 764 1.2.4.2 skrll 765 1.2.4.2 skrll /* data pointer */ 766 1.2.4.2 skrll cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0; 767 1.2.4.2 skrll } 768 1.2.4.2 skrll 769 1.2.4.2 skrll static __inline void 770 1.2.4.2 skrll njsc32_init_msgout(struct njsc32_softc *sc) 771 1.2.4.2 skrll { 772 1.2.4.2 skrll 773 1.2.4.2 skrll sc->sc_msgoutlen = 0; 774 1.2.4.2 skrll sc->sc_msgoutidx = 0; 775 1.2.4.2 skrll } 776 1.2.4.2 skrll 777 1.2.4.2 skrll static void 778 1.2.4.2 skrll njsc32_add_msgout(struct njsc32_softc *sc, int byte) 779 1.2.4.2 skrll { 780 1.2.4.2 skrll 781 1.2.4.2 skrll if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) { 782 1.2.4.2 skrll printf("njsc32_add_msgout: too many\n"); 783 1.2.4.2 skrll return; 784 1.2.4.2 skrll } 785 1.2.4.2 skrll sc->sc_msgout[sc->sc_msgoutlen++] = byte; 786 1.2.4.2 skrll } 787 1.2.4.2 skrll 788 1.2.4.2 skrll static u_int32_t 789 1.2.4.2 skrll njsc32_get_auto_msgout(struct njsc32_softc *sc) 790 1.2.4.2 skrll { 791 1.2.4.2 skrll u_int32_t val; 792 1.2.4.2 skrll u_int8_t *p; 793 1.2.4.2 skrll 794 1.2.4.2 skrll val = 0; 795 1.2.4.2 skrll p = sc->sc_msgout; 796 1.2.4.2 skrll switch (sc->sc_msgoutlen) { 797 1.2.4.2 skrll /* 31-24 23-16 15-8 7 ... 1 0 */ 798 1.2.4.2 skrll case 3: /* MSG3 MSG2 MSG1 V --- cnt */ 799 1.2.4.2 skrll val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT; 800 1.2.4.2 skrll /* FALLTHROUGH */ 801 1.2.4.2 skrll 802 1.2.4.2 skrll case 2: /* MSG2 MSG1 --- V --- cnt */ 803 1.2.4.2 skrll val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT; 804 1.2.4.2 skrll /* FALLTHROUGH */ 805 1.2.4.2 skrll 806 1.2.4.2 skrll case 1: /* MSG1 --- --- V --- cnt */ 807 1.2.4.2 skrll val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT; 808 1.2.4.2 skrll val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen; 809 1.2.4.2 skrll break; 810 1.2.4.2 skrll 811 1.2.4.2 skrll default: 812 1.2.4.2 skrll break; 813 1.2.4.2 skrll } 814 1.2.4.2 skrll return val; 815 1.2.4.2 skrll } 816 1.2.4.2 skrll 817 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 818 1.2.4.2 skrll /* add Wide Data Transfer Request to the next Message Out */ 819 1.2.4.2 skrll static void 820 1.2.4.2 skrll njsc32_msgout_wdtr(struct njsc32_softc *sc, int width) 821 1.2.4.2 skrll { 822 1.2.4.2 skrll 823 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_EXTENDED); 824 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN); 825 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_EXT_WDTR); 826 1.2.4.2 skrll njsc32_add_msgout(sc, width); 827 1.2.4.2 skrll } 828 1.2.4.2 skrll #endif 829 1.2.4.2 skrll 830 1.2.4.2 skrll /* add Synchronous Data Transfer Request to the next Message Out */ 831 1.2.4.2 skrll static void 832 1.2.4.2 skrll njsc32_msgout_sdtr(struct njsc32_softc *sc, int period, int offset) 833 1.2.4.2 skrll { 834 1.2.4.2 skrll 835 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_EXTENDED); 836 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN); 837 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_EXT_SDTR); 838 1.2.4.2 skrll njsc32_add_msgout(sc, period); 839 1.2.4.2 skrll njsc32_add_msgout(sc, offset); 840 1.2.4.2 skrll } 841 1.2.4.2 skrll 842 1.2.4.2 skrll static void 843 1.2.4.2 skrll njsc32_negotiate_xfer(struct njsc32_softc *sc, struct njsc32_target *target) 844 1.2.4.2 skrll { 845 1.2.4.2 skrll 846 1.2.4.2 skrll /* initial negotiation state */ 847 1.2.4.2 skrll if (target->t_state == NJSC32_TARST_INIT) { 848 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 849 1.2.4.2 skrll if (target->t_flags & NJSC32_TARF_DE) 850 1.2.4.2 skrll target->t_state = NJSC32_TARST_DE; 851 1.2.4.2 skrll else 852 1.2.4.2 skrll #endif 853 1.2.4.2 skrll if (target->t_flags & NJSC32_TARF_SYNC) 854 1.2.4.2 skrll target->t_state = NJSC32_TARST_SDTR; 855 1.2.4.2 skrll else 856 1.2.4.2 skrll target->t_state = NJSC32_TARST_DONE; 857 1.2.4.2 skrll } 858 1.2.4.2 skrll 859 1.2.4.2 skrll switch (target->t_state) { 860 1.2.4.2 skrll default: 861 1.2.4.2 skrll case NJSC32_TARST_INIT: 862 1.2.4.2 skrll #ifdef DIAGNOSTIC 863 1.2.4.2 skrll panic("njsc32_negotiate_xfer"); 864 1.2.4.2 skrll /* NOTREACHED */ 865 1.2.4.2 skrll #endif 866 1.2.4.2 skrll /* FALLTHROUGH */ 867 1.2.4.2 skrll case NJSC32_TARST_DONE: 868 1.2.4.2 skrll /* no more work */ 869 1.2.4.2 skrll break; 870 1.2.4.2 skrll 871 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 872 1.2.4.2 skrll case NJSC32_TARST_DE: 873 1.2.4.2 skrll njsc32_msgout_wdtr(sc, 0xde /* XXX? */); 874 1.2.4.2 skrll break; 875 1.2.4.2 skrll 876 1.2.4.2 skrll case NJSC32_TARST_WDTR: 877 1.2.4.2 skrll njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT); 878 1.2.4.2 skrll break; 879 1.2.4.2 skrll #endif 880 1.2.4.2 skrll 881 1.2.4.2 skrll case NJSC32_TARST_SDTR: 882 1.2.4.2 skrll njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period, 883 1.2.4.2 skrll NJSC32_SYNCOFFSET_MAX); 884 1.2.4.2 skrll break; 885 1.2.4.2 skrll 886 1.2.4.2 skrll case NJSC32_TARST_ASYNC: 887 1.2.4.2 skrll njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC, 888 1.2.4.2 skrll NJSC32_SYNCOFFSET_ASYNC); 889 1.2.4.2 skrll break; 890 1.2.4.2 skrll } 891 1.2.4.2 skrll } 892 1.2.4.2 skrll 893 1.2.4.2 skrll /* turn LED on */ 894 1.2.4.2 skrll static __inline void 895 1.2.4.2 skrll njsc32_led_on(struct njsc32_softc *sc) 896 1.2.4.2 skrll { 897 1.2.4.2 skrll 898 1.2.4.2 skrll njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON); 899 1.2.4.2 skrll } 900 1.2.4.2 skrll 901 1.2.4.2 skrll /* turn LED off */ 902 1.2.4.2 skrll static __inline void 903 1.2.4.2 skrll njsc32_led_off(struct njsc32_softc *sc) 904 1.2.4.2 skrll { 905 1.2.4.2 skrll 906 1.2.4.2 skrll njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF); 907 1.2.4.2 skrll } 908 1.2.4.2 skrll 909 1.2.4.2 skrll static void 910 1.2.4.2 skrll njsc32_arbitration_failed(struct njsc32_softc *sc) 911 1.2.4.2 skrll { 912 1.2.4.2 skrll struct njsc32_cmd *cmd; 913 1.2.4.2 skrll 914 1.2.4.2 skrll if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT) 915 1.2.4.2 skrll return; 916 1.2.4.2 skrll 917 1.2.4.2 skrll if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) 918 1.2.4.2 skrll callout_stop(&cmd->c_xs->xs_callout); 919 1.2.4.2 skrll 920 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_IDLE; 921 1.2.4.2 skrll sc->sc_curcmd = NULL; 922 1.2.4.2 skrll 923 1.2.4.2 skrll /* the command is no longer active */ 924 1.2.4.2 skrll if (--sc->sc_nusedcmds == 0) 925 1.2.4.2 skrll njsc32_led_off(sc); 926 1.2.4.2 skrll } 927 1.2.4.2 skrll 928 1.2.4.2 skrll static __inline void 929 1.2.4.2 skrll njsc32_cmd_load(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 930 1.2.4.2 skrll { 931 1.2.4.2 skrll struct njsc32_target *target; 932 1.2.4.2 skrll struct scsipi_xfer *xs; 933 1.2.4.2 skrll int i, control, lun; 934 1.2.4.2 skrll u_int32_t msgoutreg; 935 1.2.4.2 skrll #ifdef NJSC32_AUTOPARAM 936 1.2.4.2 skrll struct njsc32_autoparam *ap; 937 1.2.4.2 skrll #endif 938 1.2.4.2 skrll 939 1.2.4.2 skrll xs = cmd->c_xs; 940 1.2.4.2 skrll #ifdef NJSC32_AUTOPARAM 941 1.2.4.2 skrll ap = &sc->sc_cmdpg->dp_ap; 942 1.2.4.2 skrll #else 943 1.2.4.2 skrll /* reset CDB pointer */ 944 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR); 945 1.2.4.2 skrll #endif 946 1.2.4.2 skrll 947 1.2.4.2 skrll /* CDB */ 948 1.2.4.2 skrll TPRINTC(cmd, ("njsc32_cmd_load: CDB")); 949 1.2.4.2 skrll for (i = 0; i < xs->cmdlen; i++) { 950 1.2.4.2 skrll #ifdef NJSC32_AUTOPARAM 951 1.2.4.2 skrll ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i]; 952 1.2.4.2 skrll #else 953 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA, 954 1.2.4.2 skrll ((u_int8_t *)xs->cmd)[i]); 955 1.2.4.2 skrll #endif 956 1.2.4.2 skrll TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i])); 957 1.2.4.2 skrll } 958 1.2.4.2 skrll #ifdef NJSC32_AUTOPARAM /* XXX needed? */ 959 1.2.4.2 skrll for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++) 960 1.2.4.2 skrll ap->ap_cdb[i].cdb_data = 0; 961 1.2.4.2 skrll #endif 962 1.2.4.2 skrll 963 1.2.4.2 skrll control = xs->xs_control; 964 1.2.4.2 skrll 965 1.2.4.2 skrll /* 966 1.2.4.2 skrll * Message Out 967 1.2.4.2 skrll */ 968 1.2.4.2 skrll njsc32_init_msgout(sc); 969 1.2.4.2 skrll 970 1.2.4.2 skrll /* Identify */ 971 1.2.4.2 skrll lun = xs->xs_periph->periph_lun; 972 1.2.4.2 skrll njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ? 973 1.2.4.2 skrll MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1)); 974 1.2.4.2 skrll 975 1.2.4.2 skrll /* tagged queueing */ 976 1.2.4.2 skrll if (control & XS_CTL_TAGMASK) { 977 1.2.4.2 skrll njsc32_add_msgout(sc, xs->xs_tag_type); 978 1.2.4.2 skrll njsc32_add_msgout(sc, xs->xs_tag_id); 979 1.2.4.2 skrll TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id)); 980 1.2.4.2 skrll } 981 1.2.4.2 skrll TPRINTF(("\n")); 982 1.2.4.2 skrll 983 1.2.4.2 skrll target = cmd->c_target; 984 1.2.4.2 skrll 985 1.2.4.2 skrll /* transfer negotiation */ 986 1.2.4.2 skrll if (control & XS_CTL_REQSENSE) 987 1.2.4.2 skrll target->t_state = NJSC32_TARST_INIT; 988 1.2.4.2 skrll njsc32_negotiate_xfer(sc, target); 989 1.2.4.2 skrll 990 1.2.4.2 skrll msgoutreg = njsc32_get_auto_msgout(sc); 991 1.2.4.2 skrll 992 1.2.4.2 skrll #ifdef NJSC32_AUTOPARAM 993 1.2.4.2 skrll ap->ap_msgout = htole32(msgoutreg); 994 1.2.4.2 skrll 995 1.2.4.2 skrll ap->ap_sync = target->t_sync; 996 1.2.4.2 skrll ap->ap_ackwidth = target->t_ackwidth; 997 1.2.4.2 skrll ap->ap_targetid = target->t_targetid; 998 1.2.4.2 skrll ap->ap_sample = target->t_sample; 999 1.2.4.2 skrll 1000 1.2.4.2 skrll ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 1001 1.2.4.2 skrll NJSC32_CMD_AUTO_COMMAND_PHASE | 1002 1.2.4.2 skrll NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1003 1.2.4.2 skrll NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1004 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 1005 1.2.4.2 skrll ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl); 1006 1.2.4.2 skrll #else 1007 1.2.4.2 skrll ap->ap_xferctl = htole16(cmd->c_xferctl); 1008 1.2.4.2 skrll #endif 1009 1.2.4.2 skrll ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr); 1010 1.2.4.2 skrll 1011 1.2.4.2 skrll /* sync njsc32_autoparam */ 1012 1.2.4.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1013 1.2.4.2 skrll offsetof(struct njsc32_dma_page, dp_ap), /* offset */ 1014 1.2.4.2 skrll sizeof(struct njsc32_autoparam), 1015 1.2.4.2 skrll BUS_DMASYNC_PREWRITE); 1016 1.2.4.2 skrll 1017 1.2.4.2 skrll /* autoparam DMA address */ 1018 1.2.4.2 skrll njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma); 1019 1.2.4.2 skrll 1020 1.2.4.2 skrll /* start command (autoparam) */ 1021 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1022 1.2.4.2 skrll NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER); 1023 1.2.4.2 skrll 1024 1.2.4.2 skrll #else /* not NJSC32_AUTOPARAM */ 1025 1.2.4.2 skrll 1026 1.2.4.2 skrll njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg); 1027 1.2.4.2 skrll 1028 1.2.4.2 skrll /* load parameters */ 1029 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid); 1030 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1031 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1032 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1033 1.2.4.2 skrll njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1034 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 1035 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1036 1.2.4.2 skrll cmd->c_xferctl | target->t_xferctl); 1037 1.2.4.2 skrll #else 1038 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1039 1.2.4.2 skrll #endif 1040 1.2.4.2 skrll /* start AutoSCSI */ 1041 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1042 1.2.4.2 skrll NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE | 1043 1.2.4.2 skrll NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1044 1.2.4.2 skrll NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1045 1.2.4.2 skrll #endif /* not NJSC32_AUTOPARAM */ 1046 1.2.4.2 skrll } 1047 1.2.4.2 skrll 1048 1.2.4.2 skrll /* Note: must be called at splbio() */ 1049 1.2.4.2 skrll static void 1050 1.2.4.2 skrll njsc32_start(struct njsc32_softc *sc) 1051 1.2.4.2 skrll { 1052 1.2.4.2 skrll struct njsc32_cmd *cmd; 1053 1.2.4.2 skrll 1054 1.2.4.2 skrll /* get a command to issue */ 1055 1.2.4.2 skrll TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) { 1056 1.2.4.2 skrll if (cmd->c_lu->lu_cmd == NULL && 1057 1.2.4.2 skrll ((cmd->c_flags & NJSC32_CMD_TAGGED) || 1058 1.2.4.2 skrll TAILQ_EMPTY(&cmd->c_lu->lu_q))) 1059 1.2.4.2 skrll break; /* OK, the logical unit is free */ 1060 1.2.4.2 skrll } 1061 1.2.4.2 skrll if (!cmd) 1062 1.2.4.2 skrll goto out; /* no work to do */ 1063 1.2.4.2 skrll 1064 1.2.4.2 skrll /* request will always fail if not in bus free phase */ 1065 1.2.4.2 skrll if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) != 1066 1.2.4.2 skrll NJSC32_BUSMON_BUSFREE) 1067 1.2.4.2 skrll goto busy; 1068 1.2.4.2 skrll 1069 1.2.4.2 skrll /* clear parity error and enable parity detection */ 1070 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1071 1.2.4.2 skrll NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1072 1.2.4.2 skrll 1073 1.2.4.2 skrll njsc32_cmd_load(sc, cmd); 1074 1.2.4.2 skrll 1075 1.2.4.2 skrll if (sc->sc_nusedcmds++ == 0) 1076 1.2.4.2 skrll njsc32_led_on(sc); 1077 1.2.4.2 skrll 1078 1.2.4.2 skrll sc->sc_curcmd = cmd; 1079 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_ARBIT; 1080 1.2.4.2 skrll 1081 1.2.4.2 skrll if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) { 1082 1.2.4.2 skrll callout_reset(&cmd->c_xs->xs_callout, 1083 1.2.4.2 skrll mstohz(cmd->c_xs->timeout), 1084 1.2.4.2 skrll njsc32_cmdtimeout, cmd); 1085 1.2.4.2 skrll } 1086 1.2.4.2 skrll 1087 1.2.4.2 skrll return; 1088 1.2.4.2 skrll 1089 1.2.4.2 skrll busy: /* XXX retry counter */ 1090 1.2.4.2 skrll TPRINTF(("%s: njsc32_start: busy\n", sc->sc_dev.dv_xname)); 1091 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME); 1092 1.2.4.2 skrll out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 1093 1.2.4.2 skrll } 1094 1.2.4.2 skrll 1095 1.2.4.2 skrll static void 1096 1.2.4.2 skrll njsc32_run_xfer(struct njsc32_softc *sc, struct scsipi_xfer *xs) 1097 1.2.4.2 skrll { 1098 1.2.4.2 skrll struct scsipi_periph *periph; 1099 1.2.4.2 skrll int control; 1100 1.2.4.2 skrll int lun; 1101 1.2.4.2 skrll struct njsc32_cmd *cmd; 1102 1.2.4.2 skrll int s, i, error; 1103 1.2.4.2 skrll 1104 1.2.4.2 skrll periph = xs->xs_periph; 1105 1.2.4.2 skrll KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID); 1106 1.2.4.2 skrll 1107 1.2.4.2 skrll control = xs->xs_control; 1108 1.2.4.2 skrll lun = periph->periph_lun; 1109 1.2.4.2 skrll 1110 1.2.4.2 skrll /* 1111 1.2.4.2 skrll * get a free cmd 1112 1.2.4.2 skrll * (scsipi layer knows the number of cmds, so this shall never fail) 1113 1.2.4.2 skrll */ 1114 1.2.4.2 skrll s = splbio(); 1115 1.2.4.2 skrll cmd = TAILQ_FIRST(&sc->sc_freecmd); 1116 1.2.4.2 skrll KASSERT(cmd); 1117 1.2.4.2 skrll TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q); 1118 1.2.4.2 skrll splx(s); 1119 1.2.4.2 skrll 1120 1.2.4.2 skrll /* 1121 1.2.4.2 skrll * build a request 1122 1.2.4.2 skrll */ 1123 1.2.4.2 skrll njsc32_cmd_init(cmd); 1124 1.2.4.2 skrll cmd->c_xs = xs; 1125 1.2.4.2 skrll cmd->c_target = &sc->sc_targets[periph->periph_target]; 1126 1.2.4.2 skrll cmd->c_lu = &cmd->c_target->t_lus[lun]; 1127 1.2.4.2 skrll 1128 1.2.4.2 skrll /* tagged queueing */ 1129 1.2.4.2 skrll if (control & XS_CTL_TAGMASK) { 1130 1.2.4.2 skrll cmd->c_flags |= NJSC32_CMD_TAGGED; 1131 1.2.4.2 skrll if (control & XS_CTL_HEAD_TAG) 1132 1.2.4.2 skrll cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD; 1133 1.2.4.2 skrll } 1134 1.2.4.2 skrll 1135 1.2.4.2 skrll /* map DMA buffer */ 1136 1.2.4.2 skrll cmd->c_datacnt = xs->datalen; 1137 1.2.4.2 skrll if (xs->datalen) { 1138 1.2.4.2 skrll /* Is XS_CTL_DATA_UIO ever used anywhere? */ 1139 1.2.4.2 skrll KASSERT((control & XS_CTL_DATA_UIO) == 0); 1140 1.2.4.2 skrll 1141 1.2.4.2 skrll error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer, 1142 1.2.4.2 skrll xs->data, xs->datalen, NULL, 1143 1.2.4.2 skrll ((control & XS_CTL_NOSLEEP) ? 1144 1.2.4.2 skrll BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 1145 1.2.4.2 skrll BUS_DMA_STREAMING | 1146 1.2.4.2 skrll ((control & XS_CTL_DATA_IN) ? 1147 1.2.4.2 skrll BUS_DMA_READ : BUS_DMA_WRITE)); 1148 1.2.4.2 skrll 1149 1.2.4.2 skrll switch (error) { 1150 1.2.4.2 skrll case 0: 1151 1.2.4.2 skrll break; 1152 1.2.4.2 skrll case ENOMEM: 1153 1.2.4.2 skrll case EAGAIN: 1154 1.2.4.2 skrll xs->error = XS_RESOURCE_SHORTAGE; 1155 1.2.4.2 skrll goto map_failed; 1156 1.2.4.2 skrll default: 1157 1.2.4.2 skrll xs->error = XS_DRIVER_STUFFUP; 1158 1.2.4.2 skrll map_failed: 1159 1.2.4.2 skrll printf("%s: njsc32_run_xfer: map failed, error %d\n", 1160 1.2.4.2 skrll sc->sc_dev.dv_xname, error); 1161 1.2.4.2 skrll /* put it back to free command list */ 1162 1.2.4.2 skrll s = splbio(); 1163 1.2.4.2 skrll TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1164 1.2.4.2 skrll splx(s); 1165 1.2.4.2 skrll /* abort this transfer */ 1166 1.2.4.2 skrll scsipi_done(xs); 1167 1.2.4.2 skrll return; 1168 1.2.4.2 skrll } 1169 1.2.4.2 skrll 1170 1.2.4.2 skrll bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1171 1.2.4.2 skrll 0, cmd->c_dmamap_xfer->dm_mapsize, 1172 1.2.4.2 skrll (control & XS_CTL_DATA_IN) ? 1173 1.2.4.2 skrll BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1174 1.2.4.2 skrll 1175 1.2.4.2 skrll for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) { 1176 1.2.4.2 skrll cmd->c_sgt[i].sg_addr = 1177 1.2.4.2 skrll htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr); 1178 1.2.4.2 skrll cmd->c_sgt[i].sg_len = 1179 1.2.4.2 skrll htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len); 1180 1.2.4.2 skrll } 1181 1.2.4.2 skrll /* end mark */ 1182 1.2.4.2 skrll cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK); 1183 1.2.4.2 skrll 1184 1.2.4.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1185 1.2.4.2 skrll (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1186 1.2.4.2 skrll NJSC32_SIZE_SGT, 1187 1.2.4.2 skrll BUS_DMASYNC_PREWRITE); 1188 1.2.4.2 skrll 1189 1.2.4.2 skrll cmd->c_flags |= NJSC32_CMD_DMA_MAPPED; 1190 1.2.4.2 skrll 1191 1.2.4.2 skrll /* enable transfer */ 1192 1.2.4.2 skrll cmd->c_xferctl = 1193 1.2.4.2 skrll NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START | 1194 1.2.4.2 skrll NJSC32_XFR_ALL_COUNT_CLR; 1195 1.2.4.2 skrll 1196 1.2.4.2 skrll /* XXX How can we specify the DMA direction? */ 1197 1.2.4.2 skrll 1198 1.2.4.2 skrll #if 0 /* faster write mode? (doesn't work) */ 1199 1.2.4.2 skrll if ((control & XS_CTL_DATA_IN) == 0) 1200 1.2.4.2 skrll cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE; 1201 1.2.4.2 skrll #endif 1202 1.2.4.2 skrll } else { 1203 1.2.4.2 skrll /* no data transfer */ 1204 1.2.4.2 skrll cmd->c_xferctl = 0; 1205 1.2.4.2 skrll } 1206 1.2.4.2 skrll 1207 1.2.4.2 skrll /* queue request */ 1208 1.2.4.2 skrll s = splbio(); 1209 1.2.4.2 skrll TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q); 1210 1.2.4.2 skrll 1211 1.2.4.2 skrll /* start the controller if idle */ 1212 1.2.4.2 skrll if (sc->sc_stat == NJSC32_STAT_IDLE) 1213 1.2.4.2 skrll njsc32_start(sc); 1214 1.2.4.2 skrll 1215 1.2.4.2 skrll splx(s); 1216 1.2.4.2 skrll 1217 1.2.4.2 skrll if (control & XS_CTL_POLL) { 1218 1.2.4.2 skrll /* wait for completion */ 1219 1.2.4.2 skrll /* XXX should handle timeout? */ 1220 1.2.4.2 skrll while ((xs->xs_status & XS_STS_DONE) == 0) { 1221 1.2.4.2 skrll delay(1000); 1222 1.2.4.2 skrll njsc32_intr(sc); 1223 1.2.4.2 skrll } 1224 1.2.4.2 skrll } 1225 1.2.4.2 skrll } 1226 1.2.4.2 skrll 1227 1.2.4.2 skrll static void 1228 1.2.4.2 skrll njsc32_end_cmd(struct njsc32_softc *sc, struct njsc32_cmd *cmd, 1229 1.2.4.2 skrll scsipi_xfer_result_t result) 1230 1.2.4.2 skrll { 1231 1.2.4.2 skrll struct scsipi_xfer *xs; 1232 1.2.4.2 skrll int s; 1233 1.2.4.2 skrll #ifdef DIAGNOSTIC 1234 1.2.4.2 skrll struct njsc32_cmd *c; 1235 1.2.4.2 skrll #endif 1236 1.2.4.2 skrll 1237 1.2.4.2 skrll KASSERT(cmd); 1238 1.2.4.2 skrll 1239 1.2.4.2 skrll #ifdef DIAGNOSTIC 1240 1.2.4.2 skrll s = splbio(); 1241 1.2.4.2 skrll TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) { 1242 1.2.4.2 skrll if (cmd == c) 1243 1.2.4.2 skrll panic("njsc32_end_cmd: already in free list"); 1244 1.2.4.2 skrll } 1245 1.2.4.2 skrll splx(s); 1246 1.2.4.2 skrll #endif 1247 1.2.4.2 skrll xs = cmd->c_xs; 1248 1.2.4.2 skrll 1249 1.2.4.2 skrll if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) { 1250 1.2.4.2 skrll if (cmd->c_datacnt) { 1251 1.2.4.2 skrll bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1252 1.2.4.2 skrll 0, cmd->c_dmamap_xfer->dm_mapsize, 1253 1.2.4.2 skrll (xs->xs_control & XS_CTL_DATA_IN) ? 1254 1.2.4.2 skrll BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1255 1.2.4.2 skrll 1256 1.2.4.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1257 1.2.4.2 skrll (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, 1258 1.2.4.2 skrll NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE); 1259 1.2.4.2 skrll } 1260 1.2.4.2 skrll 1261 1.2.4.2 skrll bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer); 1262 1.2.4.2 skrll cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED; 1263 1.2.4.2 skrll } 1264 1.2.4.2 skrll 1265 1.2.4.2 skrll s = splbio(); 1266 1.2.4.2 skrll if ((xs->xs_control & XS_CTL_POLL) == 0) 1267 1.2.4.2 skrll callout_stop(&xs->xs_callout); 1268 1.2.4.2 skrll 1269 1.2.4.2 skrll TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1270 1.2.4.2 skrll splx(s); 1271 1.2.4.2 skrll 1272 1.2.4.2 skrll xs->error = result; 1273 1.2.4.2 skrll scsipi_done(xs); 1274 1.2.4.2 skrll 1275 1.2.4.2 skrll if (--sc->sc_nusedcmds == 0) 1276 1.2.4.2 skrll njsc32_led_off(sc); 1277 1.2.4.2 skrll } 1278 1.2.4.2 skrll 1279 1.2.4.2 skrll /* 1280 1.2.4.2 skrll * request from scsipi layer 1281 1.2.4.2 skrll */ 1282 1.2.4.2 skrll static void 1283 1.2.4.2 skrll njsc32_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1284 1.2.4.2 skrll void *arg) 1285 1.2.4.2 skrll { 1286 1.2.4.2 skrll struct njsc32_softc *sc; 1287 1.2.4.2 skrll struct scsipi_xfer_mode *xm; 1288 1.2.4.2 skrll struct njsc32_target *target; 1289 1.2.4.2 skrll 1290 1.2.4.2 skrll sc = (void *)chan->chan_adapter->adapt_dev; 1291 1.2.4.2 skrll 1292 1.2.4.2 skrll switch (req) { 1293 1.2.4.2 skrll case ADAPTER_REQ_RUN_XFER: 1294 1.2.4.2 skrll njsc32_run_xfer(sc, arg); 1295 1.2.4.2 skrll break; 1296 1.2.4.2 skrll 1297 1.2.4.2 skrll case ADAPTER_REQ_GROW_RESOURCES: 1298 1.2.4.2 skrll /* not supported */ 1299 1.2.4.2 skrll break; 1300 1.2.4.2 skrll 1301 1.2.4.2 skrll case ADAPTER_REQ_SET_XFER_MODE: 1302 1.2.4.2 skrll xm = arg; 1303 1.2.4.2 skrll target = &sc->sc_targets[xm->xm_target]; 1304 1.2.4.2 skrll 1305 1.2.4.2 skrll target->t_flags = 0; 1306 1.2.4.2 skrll if (xm->xm_mode & PERIPH_CAP_TQING) 1307 1.2.4.2 skrll target->t_flags |= NJSC32_TARF_TAG; 1308 1.2.4.2 skrll if (xm->xm_mode & PERIPH_CAP_SYNC) { 1309 1.2.4.2 skrll target->t_flags |= NJSC32_TARF_SYNC; 1310 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 1311 1.2.4.2 skrll if (sc->sc_model & NJSC32_FLAG_DUALEDGE) 1312 1.2.4.2 skrll target->t_flags |= NJSC32_TARF_DE; 1313 1.2.4.2 skrll #endif 1314 1.2.4.2 skrll } 1315 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 1316 1.2.4.2 skrll target->t_xferctl = 0; 1317 1.2.4.2 skrll #endif 1318 1.2.4.2 skrll target->t_state = NJSC32_TARST_INIT; 1319 1.2.4.2 skrll njsc32_target_async(sc, target); 1320 1.2.4.2 skrll 1321 1.2.4.2 skrll break; 1322 1.2.4.2 skrll default: 1323 1.2.4.2 skrll break; 1324 1.2.4.2 skrll } 1325 1.2.4.2 skrll } 1326 1.2.4.2 skrll 1327 1.2.4.2 skrll static void 1328 1.2.4.2 skrll njsc32_scsipi_minphys(struct buf *bp) 1329 1.2.4.2 skrll { 1330 1.2.4.2 skrll 1331 1.2.4.2 skrll if (bp->b_bcount > NJSC32_MAX_XFER) 1332 1.2.4.2 skrll bp->b_bcount = NJSC32_MAX_XFER; 1333 1.2.4.2 skrll minphys(bp); 1334 1.2.4.2 skrll } 1335 1.2.4.2 skrll 1336 1.2.4.2 skrll static void 1337 1.2.4.2 skrll njsc32_reset_bus(struct njsc32_softc *sc) 1338 1.2.4.2 skrll { 1339 1.2.4.2 skrll int s; 1340 1.2.4.2 skrll 1341 1.2.4.2 skrll DPRINTF(("%s: njsc32_reset_bus:\n", sc->sc_dev.dv_xname)); 1342 1.2.4.2 skrll 1343 1.2.4.2 skrll /* SCSI bus reset */ 1344 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST); 1345 1.2.4.2 skrll delay(NJSC32_RESET_HOLD_TIME); 1346 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0); 1347 1.2.4.2 skrll 1348 1.2.4.2 skrll /* clear transfer */ 1349 1.2.4.2 skrll s = splbio(); 1350 1.2.4.2 skrll njsc32_reset_detected(sc); 1351 1.2.4.2 skrll splx(s); 1352 1.2.4.2 skrll } 1353 1.2.4.2 skrll 1354 1.2.4.2 skrll /* 1355 1.2.4.2 skrll * clear running/disconnected commands 1356 1.2.4.2 skrll */ 1357 1.2.4.2 skrll static void 1358 1.2.4.2 skrll njsc32_clear_cmds(struct njsc32_softc *sc, scsipi_xfer_result_t cmdresult) 1359 1.2.4.2 skrll { 1360 1.2.4.2 skrll struct njsc32_cmd *cmd; 1361 1.2.4.2 skrll int id, lun; 1362 1.2.4.2 skrll struct njsc32_lu *lu; 1363 1.2.4.2 skrll 1364 1.2.4.2 skrll njsc32_arbitration_failed(sc); 1365 1.2.4.2 skrll 1366 1.2.4.2 skrll /* clear current transfer */ 1367 1.2.4.2 skrll if ((cmd = sc->sc_curcmd) != NULL) { 1368 1.2.4.2 skrll sc->sc_curcmd = NULL; 1369 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, cmdresult); 1370 1.2.4.2 skrll } 1371 1.2.4.2 skrll 1372 1.2.4.2 skrll /* clear disconnected transfers */ 1373 1.2.4.2 skrll for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 1374 1.2.4.2 skrll for (lun = 0; lun < NJSC32_NLU; lun++) { 1375 1.2.4.2 skrll lu = &sc->sc_targets[id].t_lus[lun]; 1376 1.2.4.2 skrll 1377 1.2.4.2 skrll if ((cmd = lu->lu_cmd) != NULL) { 1378 1.2.4.2 skrll lu->lu_cmd = NULL; 1379 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, cmdresult); 1380 1.2.4.2 skrll } 1381 1.2.4.2 skrll while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) { 1382 1.2.4.2 skrll TAILQ_REMOVE(&lu->lu_q, cmd, c_q); 1383 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, cmdresult); 1384 1.2.4.2 skrll } 1385 1.2.4.2 skrll } 1386 1.2.4.2 skrll } 1387 1.2.4.2 skrll } 1388 1.2.4.2 skrll 1389 1.2.4.2 skrll static void 1390 1.2.4.2 skrll njsc32_reset_detected(struct njsc32_softc *sc) 1391 1.2.4.2 skrll { 1392 1.2.4.2 skrll 1393 1.2.4.2 skrll njsc32_clear_cmds(sc, XS_RESET); 1394 1.2.4.2 skrll njsc32_init_targets(sc); 1395 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_IDLE; 1396 1.2.4.2 skrll KASSERT(sc->sc_nusedcmds == 0); 1397 1.2.4.2 skrll scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL); 1398 1.2.4.2 skrll } 1399 1.2.4.2 skrll 1400 1.2.4.2 skrll static int 1401 1.2.4.2 skrll njsc32_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd, caddr_t addr, 1402 1.2.4.2 skrll int flag, struct proc *p) 1403 1.2.4.2 skrll { 1404 1.2.4.2 skrll struct njsc32_softc *sc = (void *)chan->chan_adapter->adapt_dev; 1405 1.2.4.2 skrll 1406 1.2.4.2 skrll switch (cmd) { 1407 1.2.4.2 skrll case SCBUSIORESET: 1408 1.2.4.2 skrll njsc32_init(sc, 0); 1409 1.2.4.2 skrll return 0; 1410 1.2.4.2 skrll default: 1411 1.2.4.2 skrll break; 1412 1.2.4.2 skrll } 1413 1.2.4.2 skrll 1414 1.2.4.2 skrll return ENOTTY; 1415 1.2.4.2 skrll } 1416 1.2.4.2 skrll 1417 1.2.4.2 skrll /* 1418 1.2.4.2 skrll * set current data pointer 1419 1.2.4.2 skrll */ 1420 1.2.4.2 skrll static __inline void 1421 1.2.4.2 skrll njsc32_set_cur_ptr(struct njsc32_cmd *cmd, u_int32_t pos) 1422 1.2.4.2 skrll { 1423 1.2.4.2 skrll 1424 1.2.4.2 skrll /* new current data pointer */ 1425 1.2.4.2 skrll cmd->c_dp_cur = pos; 1426 1.2.4.2 skrll 1427 1.2.4.2 skrll /* update number of bytes transferred */ 1428 1.2.4.2 skrll if (pos > cmd->c_dp_max) 1429 1.2.4.2 skrll cmd->c_dp_max = pos; 1430 1.2.4.2 skrll } 1431 1.2.4.2 skrll 1432 1.2.4.2 skrll /* 1433 1.2.4.2 skrll * set data pointer for the next transfer 1434 1.2.4.2 skrll */ 1435 1.2.4.2 skrll static void 1436 1.2.4.2 skrll njsc32_set_ptr(struct njsc32_softc *sc, struct njsc32_cmd *cmd, u_int32_t pos) 1437 1.2.4.2 skrll { 1438 1.2.4.2 skrll struct njsc32_sgtable *sg; 1439 1.2.4.2 skrll unsigned sgte; 1440 1.2.4.2 skrll u_int32_t len; 1441 1.2.4.2 skrll 1442 1.2.4.2 skrll /* set current pointer */ 1443 1.2.4.2 skrll njsc32_set_cur_ptr(cmd, pos); 1444 1.2.4.2 skrll 1445 1.2.4.2 skrll /* undo previous fix if any */ 1446 1.2.4.2 skrll if (cmd->c_sgfixcnt != 0) { 1447 1.2.4.2 skrll sg = &cmd->c_sgt[cmd->c_sgoffset]; 1448 1.2.4.2 skrll sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt); 1449 1.2.4.2 skrll sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt); 1450 1.2.4.2 skrll cmd->c_sgfixcnt = 0; 1451 1.2.4.2 skrll } 1452 1.2.4.2 skrll 1453 1.2.4.2 skrll if (pos >= cmd->c_datacnt) { 1454 1.2.4.2 skrll /* transfer done */ 1455 1.2.4.2 skrll #if 1 /*def DIAGNOSTIC*/ 1456 1.2.4.2 skrll if (pos > cmd->c_datacnt) 1457 1.2.4.2 skrll printf("%s: pos %u too large\n", 1458 1.2.4.2 skrll sc->sc_dev.dv_xname, pos - cmd->c_datacnt); 1459 1.2.4.2 skrll #endif 1460 1.2.4.2 skrll cmd->c_xferctl = 0; /* XXX correct? */ 1461 1.2.4.2 skrll 1462 1.2.4.2 skrll return; 1463 1.2.4.2 skrll } 1464 1.2.4.2 skrll 1465 1.2.4.2 skrll for (sgte = 0, sg = cmd->c_sgt; 1466 1.2.4.2 skrll sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) { 1467 1.2.4.2 skrll len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK; 1468 1.2.4.2 skrll if (pos < len) { 1469 1.2.4.2 skrll sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos); 1470 1.2.4.2 skrll sg->sg_len = htole32(le32toh(sg->sg_len) - pos); 1471 1.2.4.2 skrll cmd->c_sgfixcnt = pos; 1472 1.2.4.2 skrll break; 1473 1.2.4.2 skrll } 1474 1.2.4.2 skrll pos -= len; 1475 1.2.4.2 skrll #ifdef DIAGNOSTIC 1476 1.2.4.2 skrll if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) { 1477 1.2.4.2 skrll panic("njsc32_set_ptr: bad pos"); 1478 1.2.4.2 skrll } 1479 1.2.4.2 skrll #endif 1480 1.2.4.2 skrll } 1481 1.2.4.2 skrll #ifdef DIAGNOSTIC 1482 1.2.4.2 skrll if (sgte >= NJSC32_NUM_SG) 1483 1.2.4.2 skrll panic("njsc32_set_ptr: bad sg"); 1484 1.2.4.2 skrll #endif 1485 1.2.4.2 skrll if (cmd->c_sgoffset != sgte) { 1486 1.2.4.2 skrll cmd->c_sgoffset = sgte; 1487 1.2.4.2 skrll cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte); 1488 1.2.4.2 skrll } 1489 1.2.4.2 skrll 1490 1.2.4.2 skrll /* XXX overkill */ 1491 1.2.4.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1492 1.2.4.2 skrll (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1493 1.2.4.2 skrll NJSC32_SIZE_SGT, 1494 1.2.4.2 skrll BUS_DMASYNC_PREWRITE); 1495 1.2.4.2 skrll } 1496 1.2.4.2 skrll 1497 1.2.4.2 skrll /* 1498 1.2.4.2 skrll * save data pointer 1499 1.2.4.2 skrll */ 1500 1.2.4.2 skrll static __inline void 1501 1.2.4.2 skrll njsc32_save_ptr(struct njsc32_cmd *cmd) 1502 1.2.4.2 skrll { 1503 1.2.4.2 skrll 1504 1.2.4.2 skrll cmd->c_dp_saved = cmd->c_dp_cur; 1505 1.2.4.2 skrll } 1506 1.2.4.2 skrll 1507 1.2.4.2 skrll static void 1508 1.2.4.2 skrll njsc32_assert_ack(struct njsc32_softc *sc) 1509 1.2.4.2 skrll { 1510 1.2.4.2 skrll u_int8_t reg; 1511 1.2.4.2 skrll 1512 1.2.4.2 skrll reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1513 1.2.4.2 skrll reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE; 1514 1.2.4.2 skrll #if 0 /* needed? */ 1515 1.2.4.2 skrll reg |= NJSC32_SBCTL_AUTODIRECTION; 1516 1.2.4.2 skrll #endif 1517 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1518 1.2.4.2 skrll } 1519 1.2.4.2 skrll 1520 1.2.4.2 skrll static void 1521 1.2.4.2 skrll njsc32_negate_ack(struct njsc32_softc *sc) 1522 1.2.4.2 skrll { 1523 1.2.4.2 skrll u_int8_t reg; 1524 1.2.4.2 skrll 1525 1.2.4.2 skrll reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1526 1.2.4.2 skrll #if 0 /* needed? */ 1527 1.2.4.2 skrll reg |= NJSC32_SBCTL_ACK_ENABLE; 1528 1.2.4.2 skrll reg |= NJSC32_SBCTL_AUTODIRECTION; 1529 1.2.4.2 skrll #endif 1530 1.2.4.2 skrll reg &= ~NJSC32_SBCTL_ACK; 1531 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1532 1.2.4.2 skrll } 1533 1.2.4.2 skrll 1534 1.2.4.2 skrll static void 1535 1.2.4.2 skrll njsc32_wait_req_negate(struct njsc32_softc *sc) 1536 1.2.4.2 skrll { 1537 1.2.4.2 skrll int cnt; 1538 1.2.4.2 skrll 1539 1.2.4.2 skrll for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) { 1540 1.2.4.2 skrll if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 1541 1.2.4.2 skrll NJSC32_BUSMON_REQ) == 0) 1542 1.2.4.2 skrll return; 1543 1.2.4.2 skrll delay(1); 1544 1.2.4.2 skrll } 1545 1.2.4.2 skrll printf("%s: njsc32_wait_req_negate: timed out\n", sc->sc_dev.dv_xname); 1546 1.2.4.2 skrll } 1547 1.2.4.2 skrll 1548 1.2.4.2 skrll static void 1549 1.2.4.2 skrll njsc32_reconnect(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 1550 1.2.4.2 skrll { 1551 1.2.4.2 skrll struct scsipi_xfer *xs; 1552 1.2.4.2 skrll 1553 1.2.4.2 skrll xs = cmd->c_xs; 1554 1.2.4.2 skrll if ((xs->xs_control & XS_CTL_POLL) == 0) { 1555 1.2.4.2 skrll callout_stop(&xs->xs_callout); 1556 1.2.4.2 skrll callout_reset(&xs->xs_callout, 1557 1.2.4.2 skrll mstohz(xs->timeout), 1558 1.2.4.2 skrll njsc32_cmdtimeout, cmd); 1559 1.2.4.2 skrll } 1560 1.2.4.2 skrll 1561 1.2.4.2 skrll /* Reconnection implies Restore Pointers */ 1562 1.2.4.2 skrll njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1563 1.2.4.2 skrll } 1564 1.2.4.2 skrll 1565 1.2.4.2 skrll static enum njsc32_reselstat 1566 1.2.4.2 skrll njsc32_resel_identify(struct njsc32_softc *sc, int lun, 1567 1.2.4.2 skrll struct njsc32_cmd **pcmd) 1568 1.2.4.2 skrll { 1569 1.2.4.2 skrll int targetid; 1570 1.2.4.2 skrll struct njsc32_lu *plu; 1571 1.2.4.2 skrll struct njsc32_cmd *cmd; 1572 1.2.4.2 skrll 1573 1.2.4.2 skrll switch (sc->sc_stat) { 1574 1.2.4.2 skrll case NJSC32_STAT_RESEL: 1575 1.2.4.2 skrll break; /* OK */ 1576 1.2.4.2 skrll 1577 1.2.4.2 skrll case NJSC32_STAT_RESEL_LUN: 1578 1.2.4.2 skrll case NJSC32_STAT_RECONNECT: 1579 1.2.4.2 skrll /* 1580 1.2.4.2 skrll * accept and ignore if the LUN is the same as the current one, 1581 1.2.4.2 skrll * reject otherwise. 1582 1.2.4.2 skrll */ 1583 1.2.4.2 skrll return sc->sc_resellun == lun ? 1584 1.2.4.2 skrll NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR; 1585 1.2.4.2 skrll 1586 1.2.4.2 skrll default: 1587 1.2.4.2 skrll printf("%s: njsc32_resel_identify: not in reselection\n", 1588 1.2.4.2 skrll sc->sc_dev.dv_xname); 1589 1.2.4.2 skrll return NJSC32_RESEL_ERROR; 1590 1.2.4.2 skrll } 1591 1.2.4.2 skrll 1592 1.2.4.2 skrll targetid = sc->sc_reselid; 1593 1.2.4.2 skrll TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n", 1594 1.2.4.2 skrll sc->sc_dev.dv_xname, lun)); 1595 1.2.4.2 skrll 1596 1.2.4.2 skrll if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU) 1597 1.2.4.2 skrll return NJSC32_RESEL_ERROR; 1598 1.2.4.2 skrll 1599 1.2.4.2 skrll sc->sc_resellun = lun; 1600 1.2.4.2 skrll plu = &sc->sc_targets[targetid].t_lus[lun]; 1601 1.2.4.2 skrll 1602 1.2.4.2 skrll if ((cmd = plu->lu_cmd) != NULL) { 1603 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_RECONNECT; 1604 1.2.4.2 skrll plu->lu_cmd = NULL; 1605 1.2.4.2 skrll *pcmd = cmd; 1606 1.2.4.2 skrll TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n")); 1607 1.2.4.2 skrll njsc32_reconnect(sc, cmd); 1608 1.2.4.2 skrll return NJSC32_RESEL_COMPLETE; 1609 1.2.4.2 skrll } else if (!TAILQ_EMPTY(&plu->lu_q)) { 1610 1.2.4.2 skrll /* wait for tag */ 1611 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_RESEL_LUN; 1612 1.2.4.2 skrll return NJSC32_RESEL_THROUGH; 1613 1.2.4.2 skrll } 1614 1.2.4.2 skrll 1615 1.2.4.2 skrll /* no disconnected commands */ 1616 1.2.4.2 skrll return NJSC32_RESEL_ERROR; 1617 1.2.4.2 skrll } 1618 1.2.4.2 skrll 1619 1.2.4.2 skrll static enum njsc32_reselstat 1620 1.2.4.2 skrll njsc32_resel_tag(struct njsc32_softc *sc, int tag, struct njsc32_cmd **pcmd) 1621 1.2.4.2 skrll { 1622 1.2.4.2 skrll struct njsc32_cmd_head *head; 1623 1.2.4.2 skrll struct njsc32_cmd *cmd; 1624 1.2.4.2 skrll 1625 1.2.4.2 skrll TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n", 1626 1.2.4.2 skrll sc->sc_dev.dv_xname, tag)); 1627 1.2.4.2 skrll if (sc->sc_stat != NJSC32_STAT_RESEL_LUN) 1628 1.2.4.2 skrll return NJSC32_RESEL_ERROR; 1629 1.2.4.2 skrll 1630 1.2.4.2 skrll head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q; 1631 1.2.4.2 skrll 1632 1.2.4.2 skrll /* XXX slow? */ 1633 1.2.4.2 skrll /* search for the command of the tag */ 1634 1.2.4.2 skrll TAILQ_FOREACH(cmd, head, c_q) { 1635 1.2.4.2 skrll if (cmd->c_xs->xs_tag_id == tag) { 1636 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_RECONNECT; 1637 1.2.4.2 skrll TAILQ_REMOVE(head, cmd, c_q); 1638 1.2.4.2 skrll *pcmd = cmd; 1639 1.2.4.2 skrll TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n")); 1640 1.2.4.2 skrll njsc32_reconnect(sc, cmd); 1641 1.2.4.2 skrll return NJSC32_RESEL_COMPLETE; 1642 1.2.4.2 skrll } 1643 1.2.4.2 skrll } 1644 1.2.4.2 skrll 1645 1.2.4.2 skrll /* no disconnected commands */ 1646 1.2.4.2 skrll return NJSC32_RESEL_ERROR; 1647 1.2.4.2 skrll } 1648 1.2.4.2 skrll 1649 1.2.4.2 skrll /* 1650 1.2.4.2 skrll * Reload parameters and restart AutoSCSI. 1651 1.2.4.2 skrll * 1652 1.2.4.2 skrll * XXX autoparam doesn't work as expected and we can't use it here. 1653 1.2.4.2 skrll */ 1654 1.2.4.2 skrll static void 1655 1.2.4.2 skrll njsc32_cmd_reload(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int cctl) 1656 1.2.4.2 skrll { 1657 1.2.4.2 skrll struct njsc32_target *target; 1658 1.2.4.2 skrll 1659 1.2.4.2 skrll target = cmd->c_target; 1660 1.2.4.2 skrll 1661 1.2.4.2 skrll /* clear parity error and enable parity detection */ 1662 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1663 1.2.4.2 skrll NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1664 1.2.4.2 skrll 1665 1.2.4.2 skrll /* load parameters */ 1666 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1667 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1668 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1669 1.2.4.2 skrll njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1670 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 1671 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1672 1.2.4.2 skrll cmd->c_xferctl | target->t_xferctl); 1673 1.2.4.2 skrll #else 1674 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1675 1.2.4.2 skrll #endif 1676 1.2.4.2 skrll /* start AutoSCSI */ 1677 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 1678 1.2.4.2 skrll 1679 1.2.4.2 skrll sc->sc_curcmd = cmd; 1680 1.2.4.2 skrll } 1681 1.2.4.2 skrll 1682 1.2.4.2 skrll static void 1683 1.2.4.2 skrll njsc32_update_xfer_mode(struct njsc32_softc *sc, struct njsc32_target *target) 1684 1.2.4.2 skrll { 1685 1.2.4.2 skrll struct scsipi_xfer_mode xm; 1686 1.2.4.2 skrll 1687 1.2.4.2 skrll xm.xm_target = target - sc->sc_targets; /* target ID */ 1688 1.2.4.2 skrll xm.xm_mode = 0; 1689 1.2.4.2 skrll xm.xm_period = target->t_syncperiod; 1690 1.2.4.2 skrll xm.xm_offset = target->t_syncoffset; 1691 1.2.4.2 skrll if (xm.xm_offset != 0) 1692 1.2.4.2 skrll xm.xm_mode |= PERIPH_CAP_SYNC; 1693 1.2.4.2 skrll if (target->t_flags & NJSC32_TARF_TAG) 1694 1.2.4.2 skrll xm.xm_mode |= PERIPH_CAP_TQING; 1695 1.2.4.2 skrll 1696 1.2.4.2 skrll scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 1697 1.2.4.2 skrll } 1698 1.2.4.2 skrll 1699 1.2.4.2 skrll static void 1700 1.2.4.2 skrll njsc32_msgin(struct njsc32_softc *sc) 1701 1.2.4.2 skrll { 1702 1.2.4.2 skrll u_int8_t msg0, msg; 1703 1.2.4.2 skrll int msgcnt; 1704 1.2.4.2 skrll struct njsc32_cmd *cmd; 1705 1.2.4.2 skrll enum njsc32_reselstat rstat; 1706 1.2.4.2 skrll int cctl = 0; 1707 1.2.4.2 skrll u_int32_t ptr; /* unsigned type ensures 2-complement calculation */ 1708 1.2.4.2 skrll u_int32_t msgout = 0; 1709 1.2.4.2 skrll boolean_t reload_params = FALSE; 1710 1.2.4.2 skrll struct njsc32_target *target; 1711 1.2.4.2 skrll int idx, period, offset; 1712 1.2.4.2 skrll 1713 1.2.4.2 skrll /* 1714 1.2.4.2 skrll * we are in Message In, so the previous Message Out should have 1715 1.2.4.2 skrll * been done. 1716 1.2.4.2 skrll */ 1717 1.2.4.2 skrll njsc32_init_msgout(sc); 1718 1.2.4.2 skrll 1719 1.2.4.2 skrll /* get a byte of Message In */ 1720 1.2.4.2 skrll msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN); 1721 1.2.4.2 skrll TPRINTF(("%s: njsc32_msgin: got %#x\n", sc->sc_dev.dv_xname, msg)); 1722 1.2.4.2 skrll if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN) 1723 1.2.4.2 skrll sc->sc_msginbuf[sc->sc_msgincnt] = msg; 1724 1.2.4.2 skrll 1725 1.2.4.2 skrll njsc32_assert_ack(sc); 1726 1.2.4.2 skrll 1727 1.2.4.2 skrll msg0 = sc->sc_msginbuf[0]; 1728 1.2.4.2 skrll cmd = sc->sc_curcmd; 1729 1.2.4.2 skrll 1730 1.2.4.2 skrll /* check for parity error */ 1731 1.2.4.2 skrll if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 1732 1.2.4.2 skrll NJSC32_PARITYSTATUS_ERROR_LSB) { 1733 1.2.4.2 skrll 1734 1.2.4.2 skrll printf("%s: msgin: parity error\n", sc->sc_dev.dv_xname); 1735 1.2.4.2 skrll 1736 1.2.4.2 skrll /* clear parity error */ 1737 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1738 1.2.4.2 skrll NJSC32_PARITYCTL_CHECK_ENABLE | 1739 1.2.4.2 skrll NJSC32_PARITYCTL_CLEAR_ERROR); 1740 1.2.4.2 skrll 1741 1.2.4.2 skrll /* respond as Message Parity Error */ 1742 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_PARITY_ERROR); 1743 1.2.4.2 skrll 1744 1.2.4.2 skrll /* clear Message In */ 1745 1.2.4.2 skrll sc->sc_msgincnt = 0; 1746 1.2.4.2 skrll goto reply; 1747 1.2.4.2 skrll } 1748 1.2.4.2 skrll 1749 1.2.4.2 skrll #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0) 1750 1.2.4.2 skrll #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0) 1751 1.2.4.2 skrll if (MSG_ISIDENTIFY(msg0)) { 1752 1.2.4.2 skrll /* 1753 1.2.4.2 skrll * Got Identify message from target. 1754 1.2.4.2 skrll */ 1755 1.2.4.2 skrll if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG || 1756 1.2.4.2 skrll (rstat = njsc32_resel_identify(sc, msg0 & 1757 1.2.4.2 skrll MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) { 1758 1.2.4.2 skrll /* 1759 1.2.4.2 skrll * invalid Identify -> Reject 1760 1.2.4.2 skrll */ 1761 1.2.4.2 skrll goto reject; 1762 1.2.4.2 skrll } 1763 1.2.4.2 skrll if (rstat == NJSC32_RESEL_COMPLETE) 1764 1.2.4.2 skrll reload_params = TRUE; 1765 1.2.4.2 skrll MSGCOMPLETE; 1766 1.2.4.2 skrll } 1767 1.2.4.2 skrll 1768 1.2.4.2 skrll if (msg0 == MSG_SIMPLE_Q_TAG) { 1769 1.2.4.2 skrll if (msgcnt == 0) 1770 1.2.4.2 skrll WAITNEXTMSG; 1771 1.2.4.2 skrll 1772 1.2.4.2 skrll /* got whole message */ 1773 1.2.4.2 skrll sc->sc_msgincnt = 0; 1774 1.2.4.2 skrll 1775 1.2.4.2 skrll if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd)) 1776 1.2.4.2 skrll == NJSC32_RESEL_ERROR) { 1777 1.2.4.2 skrll /* 1778 1.2.4.2 skrll * invalid Simple Queue Tag -> Abort Tag 1779 1.2.4.2 skrll */ 1780 1.2.4.2 skrll printf("%s: msgin: invalid tag\n", sc->sc_dev.dv_xname); 1781 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_ABORT_TAG); 1782 1.2.4.2 skrll goto reply; 1783 1.2.4.2 skrll } 1784 1.2.4.2 skrll if (rstat == NJSC32_RESEL_COMPLETE) 1785 1.2.4.2 skrll reload_params = TRUE; 1786 1.2.4.2 skrll MSGCOMPLETE; 1787 1.2.4.2 skrll } 1788 1.2.4.2 skrll 1789 1.2.4.2 skrll /* I_T_L or I_T_L_Q nexus should be established now */ 1790 1.2.4.2 skrll if (cmd == NULL) { 1791 1.2.4.2 skrll printf("%s: msgin %#x without nexus -- sending abort\n", 1792 1.2.4.2 skrll sc->sc_dev.dv_xname, msg0); 1793 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_ABORT); 1794 1.2.4.2 skrll goto reply; 1795 1.2.4.2 skrll } 1796 1.2.4.2 skrll 1797 1.2.4.2 skrll /* 1798 1.2.4.2 skrll * extended message 1799 1.2.4.2 skrll * 0x01 <length (0 stands for 256)> <length bytes> 1800 1.2.4.2 skrll * (<code> [<parameter> ...]) 1801 1.2.4.2 skrll */ 1802 1.2.4.2 skrll #define EXTLENOFF 1 1803 1.2.4.2 skrll #define EXTCODEOFF 2 1804 1.2.4.2 skrll if (msg0 == MSG_EXTENDED) { 1805 1.2.4.2 skrll if (msgcnt < EXTLENOFF || 1806 1.2.4.2 skrll msgcnt < EXTLENOFF + 1 + 1807 1.2.4.2 skrll (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1)) 1808 1.2.4.2 skrll WAITNEXTMSG; 1809 1.2.4.2 skrll 1810 1.2.4.2 skrll /* got whole message */ 1811 1.2.4.2 skrll sc->sc_msgincnt = 0; 1812 1.2.4.2 skrll 1813 1.2.4.2 skrll switch (sc->sc_msginbuf[EXTCODEOFF]) { 1814 1.2.4.2 skrll case 0: /* Modify Data Pointer */ 1815 1.2.4.2 skrll if (msgcnt != 5 + EXTCODEOFF - 1) 1816 1.2.4.2 skrll break; 1817 1.2.4.2 skrll /* 1818 1.2.4.2 skrll * parameter is 32bit big-endian signed (2-complement) 1819 1.2.4.2 skrll * value 1820 1.2.4.2 skrll */ 1821 1.2.4.2 skrll ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) | 1822 1.2.4.2 skrll (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) | 1823 1.2.4.2 skrll (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) | 1824 1.2.4.2 skrll sc->sc_msginbuf[EXTCODEOFF + 4]; 1825 1.2.4.2 skrll 1826 1.2.4.2 skrll /* new pointer */ 1827 1.2.4.2 skrll ptr += cmd->c_dp_cur; /* ignore overflow */ 1828 1.2.4.2 skrll 1829 1.2.4.2 skrll /* reject if ptr is not in data buffer */ 1830 1.2.4.2 skrll if (ptr > cmd->c_datacnt) 1831 1.2.4.2 skrll break; 1832 1.2.4.2 skrll 1833 1.2.4.2 skrll njsc32_set_ptr(sc, cmd, ptr); 1834 1.2.4.2 skrll goto restart; 1835 1.2.4.2 skrll 1836 1.2.4.2 skrll case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */ 1837 1.2.4.2 skrll DPRINTC(cmd, ("SDTR %#x %#x\n", 1838 1.2.4.2 skrll sc->sc_msginbuf[EXTCODEOFF + 1], 1839 1.2.4.2 skrll sc->sc_msginbuf[EXTCODEOFF + 2])); 1840 1.2.4.2 skrll if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1) 1841 1.2.4.2 skrll break; /* reject */ 1842 1.2.4.2 skrll 1843 1.2.4.2 skrll target = cmd->c_target; 1844 1.2.4.2 skrll 1845 1.2.4.2 skrll /* lookup sync period parameters */ 1846 1.2.4.2 skrll period = sc->sc_msginbuf[EXTCODEOFF + 1]; 1847 1.2.4.2 skrll for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++) 1848 1.2.4.2 skrll if (sc->sc_synct[idx].sp_period >= period) { 1849 1.2.4.2 skrll period = sc->sc_synct[idx].sp_period; 1850 1.2.4.2 skrll break; 1851 1.2.4.2 skrll } 1852 1.2.4.2 skrll if (idx >= NJSC32_NSYNCT) { 1853 1.2.4.2 skrll /* 1854 1.2.4.2 skrll * We can't meet the timing condition that 1855 1.2.4.2 skrll * the target requests -- use async. 1856 1.2.4.2 skrll */ 1857 1.2.4.2 skrll njsc32_target_async(sc, target); 1858 1.2.4.2 skrll njsc32_update_xfer_mode(sc, target); 1859 1.2.4.2 skrll if (target->t_state == NJSC32_TARST_SDTR) { 1860 1.2.4.2 skrll /* 1861 1.2.4.2 skrll * We started SDTR exchange -- start 1862 1.2.4.2 skrll * negotiation again and request async. 1863 1.2.4.2 skrll */ 1864 1.2.4.2 skrll target->t_state = NJSC32_TARST_ASYNC; 1865 1.2.4.2 skrll njsc32_negotiate_xfer(sc, target); 1866 1.2.4.2 skrll goto reply; 1867 1.2.4.2 skrll } else { 1868 1.2.4.2 skrll /* 1869 1.2.4.2 skrll * The target started SDTR exchange 1870 1.2.4.2 skrll * -- just reject and fallback 1871 1.2.4.2 skrll * to async. 1872 1.2.4.2 skrll */ 1873 1.2.4.2 skrll goto reject; 1874 1.2.4.2 skrll } 1875 1.2.4.2 skrll } 1876 1.2.4.2 skrll 1877 1.2.4.2 skrll /* check sync offset */ 1878 1.2.4.2 skrll offset = sc->sc_msginbuf[EXTCODEOFF + 2]; 1879 1.2.4.2 skrll if (offset > NJSC32_SYNCOFFSET_MAX) { 1880 1.2.4.2 skrll if (target->t_state == NJSC32_TARST_SDTR) { 1881 1.2.4.2 skrll printf("%s: wrong sync offset: %d\n", 1882 1.2.4.2 skrll cmd->c_xs->xs_periph->periph_dev->dv_xname, 1883 1.2.4.2 skrll offset); 1884 1.2.4.2 skrll /* XXX what to do? */ 1885 1.2.4.2 skrll } 1886 1.2.4.2 skrll offset = NJSC32_SYNCOFFSET_MAX; 1887 1.2.4.2 skrll } 1888 1.2.4.2 skrll 1889 1.2.4.2 skrll target->t_ackwidth = sc->sc_synct[idx].sp_ackw; 1890 1.2.4.2 skrll target->t_sample = sc->sc_synct[idx].sp_sample; 1891 1.2.4.2 skrll target->t_syncperiod = period; 1892 1.2.4.2 skrll target->t_syncoffset = offset; 1893 1.2.4.2 skrll target->t_sync = NJSC32_SYNC_VAL(idx, offset); 1894 1.2.4.2 skrll njsc32_update_xfer_mode(sc, target); 1895 1.2.4.2 skrll 1896 1.2.4.2 skrll if (target->t_state == NJSC32_TARST_SDTR) { 1897 1.2.4.2 skrll target->t_state = NJSC32_TARST_DONE; 1898 1.2.4.2 skrll } else { 1899 1.2.4.2 skrll njsc32_msgout_sdtr(sc, period, offset); 1900 1.2.4.2 skrll goto reply; 1901 1.2.4.2 skrll } 1902 1.2.4.2 skrll goto restart; 1903 1.2.4.2 skrll 1904 1.2.4.2 skrll case MSG_EXT_WDTR: /* Wide Data Transfer Request */ 1905 1.2.4.2 skrll DPRINTC(cmd, 1906 1.2.4.2 skrll ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1])); 1907 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 1908 1.2.4.2 skrll if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1) 1909 1.2.4.2 skrll break; /* reject */ 1910 1.2.4.2 skrll 1911 1.2.4.2 skrll /* 1912 1.2.4.2 skrll * T->I of this message is not used for 1913 1.2.4.2 skrll * DualEdge negotiation, so the device 1914 1.2.4.2 skrll * must not be a DualEdge device. 1915 1.2.4.2 skrll * 1916 1.2.4.2 skrll * XXX correct? 1917 1.2.4.2 skrll */ 1918 1.2.4.2 skrll target = cmd->c_target; 1919 1.2.4.2 skrll target->t_xferctl = 0; 1920 1.2.4.2 skrll 1921 1.2.4.2 skrll switch (target->t_state) { 1922 1.2.4.2 skrll case NJSC32_TARST_DE: 1923 1.2.4.2 skrll if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1924 1.2.4.2 skrll MSG_EXT_WDTR_BUS_8_BIT) { 1925 1.2.4.2 skrll /* 1926 1.2.4.2 skrll * Oops, we got unexpected WDTR. 1927 1.2.4.2 skrll * Negotiate for 8bit. 1928 1.2.4.2 skrll */ 1929 1.2.4.2 skrll target->t_state = NJSC32_TARST_WDTR; 1930 1.2.4.2 skrll } else { 1931 1.2.4.2 skrll target->t_state = NJSC32_TARST_SDTR; 1932 1.2.4.2 skrll } 1933 1.2.4.2 skrll njsc32_negotiate_xfer(sc, target); 1934 1.2.4.2 skrll goto reply; 1935 1.2.4.2 skrll 1936 1.2.4.2 skrll case NJSC32_TARST_WDTR: 1937 1.2.4.2 skrll if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1938 1.2.4.2 skrll MSG_EXT_WDTR_BUS_8_BIT) { 1939 1.2.4.2 skrll printf("%s: unexpected transfer width: %#x\n", 1940 1.2.4.2 skrll cmd->c_xs->xs_periph->periph_dev->dv_xname, 1941 1.2.4.2 skrll sc->sc_msginbuf[EXTCODEOFF + 1]); 1942 1.2.4.2 skrll /* XXX what to do? */ 1943 1.2.4.2 skrll } 1944 1.2.4.2 skrll target->t_state = NJSC32_TARST_SDTR; 1945 1.2.4.2 skrll njsc32_negotiate_xfer(sc, target); 1946 1.2.4.2 skrll goto reply; 1947 1.2.4.2 skrll 1948 1.2.4.2 skrll default: 1949 1.2.4.2 skrll /* the target started WDTR exchange */ 1950 1.2.4.2 skrll DPRINTC(cmd, ("WDTR from target\n")); 1951 1.2.4.2 skrll 1952 1.2.4.2 skrll target->t_state = NJSC32_TARST_SDTR; 1953 1.2.4.2 skrll njsc32_target_async(sc, target); 1954 1.2.4.2 skrll 1955 1.2.4.2 skrll break; /* reject the WDTR (8bit transfer) */ 1956 1.2.4.2 skrll } 1957 1.2.4.2 skrll #endif /* NJSC32_DUALEDGE */ 1958 1.2.4.2 skrll break; /* reject */ 1959 1.2.4.2 skrll } 1960 1.2.4.2 skrll DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n", 1961 1.2.4.2 skrll sc->sc_msginbuf[EXTCODEOFF], msgcnt)); 1962 1.2.4.2 skrll goto reject; 1963 1.2.4.2 skrll } 1964 1.2.4.2 skrll 1965 1.2.4.2 skrll /* 2byte messages */ 1966 1.2.4.2 skrll if (MSG_IS2BYTE(msg0)) { 1967 1.2.4.2 skrll if (msgcnt == 0) 1968 1.2.4.2 skrll WAITNEXTMSG; 1969 1.2.4.2 skrll 1970 1.2.4.2 skrll /* got whole message */ 1971 1.2.4.2 skrll sc->sc_msgincnt = 0; 1972 1.2.4.2 skrll } 1973 1.2.4.2 skrll 1974 1.2.4.2 skrll switch (msg0) { 1975 1.2.4.2 skrll case MSG_CMDCOMPLETE: /* 0x00 */ 1976 1.2.4.2 skrll case MSG_SAVEDATAPOINTER: /* 0x02 */ 1977 1.2.4.2 skrll case MSG_DISCONNECT: /* 0x04 */ 1978 1.2.4.2 skrll /* handled by AutoSCSI */ 1979 1.2.4.2 skrll PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0)); 1980 1.2.4.2 skrll break; 1981 1.2.4.2 skrll 1982 1.2.4.2 skrll case MSG_RESTOREPOINTERS: /* 0x03 */ 1983 1.2.4.2 skrll /* restore data pointer to what was saved */ 1984 1.2.4.2 skrll DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n")); 1985 1.2.4.2 skrll njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1986 1.2.4.2 skrll reload_params = TRUE; 1987 1.2.4.2 skrll MSGCOMPLETE; 1988 1.2.4.2 skrll /* NOTREACHED */ 1989 1.2.4.2 skrll break; 1990 1.2.4.2 skrll 1991 1.2.4.2 skrll #if 0 /* handled above */ 1992 1.2.4.2 skrll case MSG_EXTENDED: /* 0x01 */ 1993 1.2.4.2 skrll #endif 1994 1.2.4.2 skrll case MSG_MESSAGE_REJECT: /* 0x07 */ 1995 1.2.4.2 skrll target = cmd->c_target; 1996 1.2.4.2 skrll DPRINTC(cmd, ("Reject tarst %d\n", target->t_state)); 1997 1.2.4.2 skrll switch (target->t_state) { 1998 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 1999 1.2.4.2 skrll case NJSC32_TARST_WDTR: 2000 1.2.4.2 skrll case NJSC32_TARST_DE: 2001 1.2.4.2 skrll target->t_xferctl = 0; 2002 1.2.4.2 skrll target->t_state = NJSC32_TARST_SDTR; 2003 1.2.4.2 skrll njsc32_negotiate_xfer(sc, target); 2004 1.2.4.2 skrll goto reply; 2005 1.2.4.2 skrll #endif 2006 1.2.4.2 skrll case NJSC32_TARST_SDTR: 2007 1.2.4.2 skrll case NJSC32_TARST_ASYNC: 2008 1.2.4.2 skrll njsc32_target_async(sc, target); 2009 1.2.4.2 skrll target->t_state = NJSC32_TARST_DONE; 2010 1.2.4.2 skrll njsc32_update_xfer_mode(sc, target); 2011 1.2.4.2 skrll break; 2012 1.2.4.2 skrll default: 2013 1.2.4.2 skrll break; 2014 1.2.4.2 skrll } 2015 1.2.4.2 skrll goto restart; 2016 1.2.4.2 skrll 2017 1.2.4.2 skrll case MSG_NOOP: /* 0x08 */ 2018 1.2.4.2 skrll #ifdef NJSC32_DUALEDGE 2019 1.2.4.2 skrll target = cmd->c_target; 2020 1.2.4.2 skrll if (target->t_state == NJSC32_TARST_DE) { 2021 1.2.4.2 skrll aprint_normal("%s: DualEdge transfer\n", 2022 1.2.4.2 skrll cmd->c_xs->xs_periph->periph_dev->dv_xname); 2023 1.2.4.2 skrll target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE; 2024 1.2.4.2 skrll /* go to next negotiation */ 2025 1.2.4.2 skrll target->t_state = NJSC32_TARST_SDTR; 2026 1.2.4.2 skrll njsc32_negotiate_xfer(sc, target); 2027 1.2.4.2 skrll goto reply; 2028 1.2.4.2 skrll } 2029 1.2.4.2 skrll #endif 2030 1.2.4.2 skrll goto restart; 2031 1.2.4.2 skrll 2032 1.2.4.2 skrll case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */ 2033 1.2.4.2 skrll case MSG_ABORT: /* 0x06 I->T only */ 2034 1.2.4.2 skrll case MSG_PARITY_ERROR: /* 0x09 I->T only */ 2035 1.2.4.2 skrll case MSG_LINK_CMD_COMPLETE: /* 0x0a */ 2036 1.2.4.2 skrll case MSG_LINK_CMD_COMPLETEF: /* 0x0b */ 2037 1.2.4.2 skrll case MSG_BUS_DEV_RESET: /* 0x0c I->T only */ 2038 1.2.4.2 skrll case MSG_ABORT_TAG: /* 0x0d I->T only */ 2039 1.2.4.2 skrll case MSG_CLEAR_QUEUE: /* 0x0e I->T only */ 2040 1.2.4.2 skrll 2041 1.2.4.2 skrll #if 0 /* handled above */ 2042 1.2.4.2 skrll case MSG_SIMPLE_Q_TAG: /* 0x20 */ 2043 1.2.4.2 skrll #endif 2044 1.2.4.2 skrll case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */ 2045 1.2.4.2 skrll case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */ 2046 1.2.4.2 skrll case MSG_IGN_WIDE_RESIDUE: /* 0x23 */ 2047 1.2.4.2 skrll 2048 1.2.4.2 skrll default: 2049 1.2.4.2 skrll #ifdef NJSC32_DEBUG 2050 1.2.4.2 skrll PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0)); 2051 1.2.4.2 skrll if (MSG_IS2BYTE(msg0)) 2052 1.2.4.2 skrll printf(" %#x", msg); 2053 1.2.4.2 skrll printf("\n"); 2054 1.2.4.2 skrll #endif 2055 1.2.4.2 skrll break; 2056 1.2.4.2 skrll } 2057 1.2.4.2 skrll 2058 1.2.4.2 skrll reject: 2059 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_MESSAGE_REJECT); 2060 1.2.4.2 skrll 2061 1.2.4.2 skrll reply: 2062 1.2.4.2 skrll msgout = njsc32_get_auto_msgout(sc); 2063 1.2.4.2 skrll 2064 1.2.4.2 skrll restart: 2065 1.2.4.2 skrll cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2066 1.2.4.2 skrll NJSC32_CMD_AUTO_COMMAND_PHASE | 2067 1.2.4.2 skrll NJSC32_CMD_AUTO_SCSI_RESTART; 2068 1.2.4.2 skrll 2069 1.2.4.2 skrll /* 2070 1.2.4.2 skrll * Be careful the second and latter bytes of Message In 2071 1.2.4.2 skrll * shall not be absorbed by AutoSCSI. 2072 1.2.4.2 skrll */ 2073 1.2.4.2 skrll if (sc->sc_msgincnt == 0) 2074 1.2.4.2 skrll cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2075 1.2.4.2 skrll 2076 1.2.4.2 skrll if (sc->sc_msgoutlen != 0) 2077 1.2.4.2 skrll cctl |= NJSC32_CMD_AUTO_ATN; 2078 1.2.4.2 skrll 2079 1.2.4.2 skrll njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout); 2080 1.2.4.2 skrll 2081 1.2.4.2 skrll /* (re)start AutoSCSI (may assert ATN) */ 2082 1.2.4.2 skrll if (reload_params) { 2083 1.2.4.2 skrll njsc32_cmd_reload(sc, cmd, cctl); 2084 1.2.4.2 skrll } else { 2085 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2086 1.2.4.2 skrll } 2087 1.2.4.2 skrll 2088 1.2.4.2 skrll /* +ATN -> -REQ: need 90ns delay? */ 2089 1.2.4.2 skrll 2090 1.2.4.2 skrll njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2091 1.2.4.2 skrll 2092 1.2.4.2 skrll njsc32_negate_ack(sc); 2093 1.2.4.2 skrll 2094 1.2.4.2 skrll return; 2095 1.2.4.2 skrll } 2096 1.2.4.2 skrll 2097 1.2.4.2 skrll static void 2098 1.2.4.2 skrll njsc32_msgout(struct njsc32_softc *sc) 2099 1.2.4.2 skrll { 2100 1.2.4.2 skrll int cctl; 2101 1.2.4.2 skrll u_int8_t bus; 2102 1.2.4.2 skrll unsigned n; 2103 1.2.4.2 skrll 2104 1.2.4.2 skrll if (sc->sc_msgoutlen == 0) { 2105 1.2.4.2 skrll /* target entered to Message Out on unexpected timing */ 2106 1.2.4.2 skrll njsc32_add_msgout(sc, MSG_NOOP); 2107 1.2.4.2 skrll } 2108 1.2.4.2 skrll 2109 1.2.4.2 skrll cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2110 1.2.4.2 skrll NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART | 2111 1.2.4.2 skrll NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2112 1.2.4.2 skrll 2113 1.2.4.2 skrll /* make sure target is in Message Out phase */ 2114 1.2.4.2 skrll bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR); 2115 1.2.4.2 skrll if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) { 2116 1.2.4.2 skrll /* 2117 1.2.4.2 skrll * Message Out is aborted by target. 2118 1.2.4.2 skrll */ 2119 1.2.4.2 skrll printf("%s: njsc32_msgout: phase change %#x\n", 2120 1.2.4.2 skrll sc->sc_dev.dv_xname, bus); 2121 1.2.4.2 skrll 2122 1.2.4.2 skrll /* XXX what to do? */ 2123 1.2.4.2 skrll 2124 1.2.4.2 skrll /* restart AutoSCSI (negate ATN) */ 2125 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2126 1.2.4.2 skrll 2127 1.2.4.2 skrll sc->sc_msgoutidx = 0; 2128 1.2.4.2 skrll return; 2129 1.2.4.2 skrll } 2130 1.2.4.2 skrll 2131 1.2.4.2 skrll n = sc->sc_msgoutidx; 2132 1.2.4.2 skrll if (n == sc->sc_msgoutlen - 1) { 2133 1.2.4.2 skrll /* 2134 1.2.4.2 skrll * negate ATN before sending ACK 2135 1.2.4.2 skrll */ 2136 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0); 2137 1.2.4.2 skrll 2138 1.2.4.2 skrll sc->sc_msgoutidx = 0; /* target may retry Message Out */ 2139 1.2.4.2 skrll } else { 2140 1.2.4.2 skrll cctl |= NJSC32_CMD_AUTO_ATN; 2141 1.2.4.2 skrll sc->sc_msgoutidx++; 2142 1.2.4.2 skrll } 2143 1.2.4.2 skrll 2144 1.2.4.2 skrll /* Send Message Out */ 2145 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]); 2146 1.2.4.2 skrll 2147 1.2.4.2 skrll /* DBn -> +ACK: need 55ns delay? */ 2148 1.2.4.2 skrll 2149 1.2.4.2 skrll njsc32_assert_ack(sc); 2150 1.2.4.2 skrll njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2151 1.2.4.2 skrll 2152 1.2.4.2 skrll /* restart AutoSCSI */ 2153 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2154 1.2.4.2 skrll 2155 1.2.4.2 skrll njsc32_negate_ack(sc); 2156 1.2.4.2 skrll 2157 1.2.4.2 skrll /* 2158 1.2.4.2 skrll * do not reset sc->sc_msgoutlen so the target 2159 1.2.4.2 skrll * can retry Message Out phase 2160 1.2.4.2 skrll */ 2161 1.2.4.2 skrll } 2162 1.2.4.2 skrll 2163 1.2.4.2 skrll static void 2164 1.2.4.2 skrll njsc32_cmdtimeout(void *arg) 2165 1.2.4.2 skrll { 2166 1.2.4.2 skrll struct njsc32_cmd *cmd = arg; 2167 1.2.4.2 skrll struct njsc32_softc *sc; 2168 1.2.4.2 skrll int s; 2169 1.2.4.2 skrll 2170 1.2.4.2 skrll PRINTC(cmd, ("command timeout\n")); 2171 1.2.4.2 skrll 2172 1.2.4.2 skrll sc = cmd->c_sc; 2173 1.2.4.2 skrll 2174 1.2.4.2 skrll s = splbio(); 2175 1.2.4.2 skrll 2176 1.2.4.2 skrll if (sc->sc_stat == NJSC32_STAT_ARBIT) 2177 1.2.4.2 skrll njsc32_arbitration_failed(sc); 2178 1.2.4.2 skrll else { 2179 1.2.4.2 skrll sc->sc_curcmd = NULL; 2180 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_IDLE; 2181 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2182 1.2.4.2 skrll } 2183 1.2.4.2 skrll 2184 1.2.4.2 skrll /* XXX? */ 2185 1.2.4.2 skrll njsc32_init(sc, 1); /* bus reset */ 2186 1.2.4.2 skrll 2187 1.2.4.2 skrll splx(s); 2188 1.2.4.2 skrll } 2189 1.2.4.2 skrll 2190 1.2.4.2 skrll static void 2191 1.2.4.2 skrll njsc32_reseltimeout(void *arg) 2192 1.2.4.2 skrll { 2193 1.2.4.2 skrll struct njsc32_cmd *cmd = arg; 2194 1.2.4.2 skrll struct njsc32_softc *sc; 2195 1.2.4.2 skrll int s; 2196 1.2.4.2 skrll 2197 1.2.4.2 skrll PRINTC(cmd, ("reselection timeout\n")); 2198 1.2.4.2 skrll 2199 1.2.4.2 skrll sc = cmd->c_sc; 2200 1.2.4.2 skrll 2201 1.2.4.2 skrll s = splbio(); 2202 1.2.4.2 skrll 2203 1.2.4.2 skrll /* remove from disconnected list */ 2204 1.2.4.2 skrll if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2205 1.2.4.2 skrll /* I_T_L_Q */ 2206 1.2.4.2 skrll KASSERT(cmd->c_lu->lu_cmd == NULL); 2207 1.2.4.2 skrll TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q); 2208 1.2.4.2 skrll } else { 2209 1.2.4.2 skrll /* I_T_L */ 2210 1.2.4.2 skrll KASSERT(cmd->c_lu->lu_cmd == cmd); 2211 1.2.4.2 skrll cmd->c_lu->lu_cmd = NULL; 2212 1.2.4.2 skrll } 2213 1.2.4.2 skrll 2214 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2215 1.2.4.2 skrll 2216 1.2.4.2 skrll /* XXX? */ 2217 1.2.4.2 skrll njsc32_init(sc, 1); /* bus reset */ 2218 1.2.4.2 skrll 2219 1.2.4.2 skrll splx(s); 2220 1.2.4.2 skrll } 2221 1.2.4.2 skrll 2222 1.2.4.2 skrll static __inline void 2223 1.2.4.2 skrll njsc32_end_auto(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int auto_phase) 2224 1.2.4.2 skrll { 2225 1.2.4.2 skrll struct scsipi_xfer *xs; 2226 1.2.4.2 skrll 2227 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_MSGIN_02) { 2228 1.2.4.2 skrll /* Message In: 0x02 Save Data Pointer */ 2229 1.2.4.2 skrll 2230 1.2.4.2 skrll /* 2231 1.2.4.2 skrll * Adjust saved data pointer 2232 1.2.4.2 skrll * if the command is not completed yet. 2233 1.2.4.2 skrll */ 2234 1.2.4.2 skrll if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 && 2235 1.2.4.2 skrll (auto_phase & 2236 1.2.4.2 skrll (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) { 2237 1.2.4.2 skrll njsc32_save_ptr(cmd); 2238 1.2.4.2 skrll } 2239 1.2.4.2 skrll TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2240 1.2.4.2 skrll njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2241 1.2.4.2 skrll njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2242 1.2.4.2 skrll njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2243 1.2.4.2 skrll njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT))); 2244 1.2.4.2 skrll } 2245 1.2.4.2 skrll 2246 1.2.4.2 skrll xs = cmd->c_xs; 2247 1.2.4.2 skrll 2248 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_MSGIN_00) { 2249 1.2.4.2 skrll /* Command Complete */ 2250 1.2.4.2 skrll TPRINTC(cmd, ("njsc32_intr: Command Complete\n")); 2251 1.2.4.2 skrll switch (xs->status) { 2252 1.2.4.2 skrll case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY: 2253 1.2.4.2 skrll /* 2254 1.2.4.2 skrll * scsipi layer will automatically handle the error 2255 1.2.4.2 skrll */ 2256 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, XS_BUSY); 2257 1.2.4.2 skrll break; 2258 1.2.4.2 skrll default: 2259 1.2.4.2 skrll xs->resid -= cmd->c_dp_max; 2260 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, XS_NOERROR); 2261 1.2.4.2 skrll break; 2262 1.2.4.2 skrll } 2263 1.2.4.2 skrll } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) { 2264 1.2.4.2 skrll /* Disconnect */ 2265 1.2.4.2 skrll TPRINTC(cmd, ("njsc32_intr: Disconnect\n")); 2266 1.2.4.2 skrll 2267 1.2.4.2 skrll /* for ill-designed devices */ 2268 1.2.4.2 skrll if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0) 2269 1.2.4.2 skrll njsc32_save_ptr(cmd); 2270 1.2.4.2 skrll 2271 1.2.4.2 skrll /* 2272 1.2.4.2 skrll * move current cmd to disconnected list 2273 1.2.4.2 skrll */ 2274 1.2.4.2 skrll if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2275 1.2.4.2 skrll /* I_T_L_Q */ 2276 1.2.4.2 skrll if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD) 2277 1.2.4.2 skrll TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q); 2278 1.2.4.2 skrll else 2279 1.2.4.2 skrll TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q); 2280 1.2.4.2 skrll } else { 2281 1.2.4.2 skrll /* I_T_L */ 2282 1.2.4.2 skrll cmd->c_lu->lu_cmd = cmd; 2283 1.2.4.2 skrll } 2284 1.2.4.2 skrll 2285 1.2.4.2 skrll /* 2286 1.2.4.2 skrll * schedule timeout -- avoid being 2287 1.2.4.2 skrll * disconnected forever 2288 1.2.4.2 skrll */ 2289 1.2.4.2 skrll if ((xs->xs_control & XS_CTL_POLL) == 0) { 2290 1.2.4.2 skrll callout_stop(&xs->xs_callout); 2291 1.2.4.2 skrll callout_reset(&xs->xs_callout, mstohz(xs->timeout), 2292 1.2.4.2 skrll njsc32_reseltimeout, cmd); 2293 1.2.4.2 skrll } 2294 1.2.4.2 skrll 2295 1.2.4.2 skrll } else { 2296 1.2.4.2 skrll /* 2297 1.2.4.2 skrll * target has come to Bus Free phase 2298 1.2.4.2 skrll * probably to notify an error 2299 1.2.4.2 skrll */ 2300 1.2.4.2 skrll PRINTC(cmd, ("njsc32_intr: unexpected bus free\n")); 2301 1.2.4.2 skrll /* try Request Sense */ 2302 1.2.4.2 skrll xs->status = SCSI_CHECK; 2303 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, XS_BUSY); 2304 1.2.4.2 skrll } 2305 1.2.4.2 skrll } 2306 1.2.4.2 skrll 2307 1.2.4.2 skrll int 2308 1.2.4.2 skrll njsc32_intr(void *arg) 2309 1.2.4.2 skrll { 2310 1.2.4.2 skrll struct njsc32_softc *sc = arg; 2311 1.2.4.2 skrll u_int16_t intr; 2312 1.2.4.2 skrll u_int8_t arbstat, bus_phase; 2313 1.2.4.2 skrll int auto_phase; 2314 1.2.4.2 skrll int idbit; 2315 1.2.4.2 skrll struct njsc32_cmd *cmd; 2316 1.2.4.2 skrll 2317 1.2.4.2 skrll intr = njsc32_read_2(sc, NJSC32_REG_IRQ); 2318 1.2.4.2 skrll if ((intr & NJSC32_IRQ_INTR_PENDING) == 0) 2319 1.2.4.2 skrll return 0; /* not mine */ 2320 1.2.4.2 skrll 2321 1.2.4.2 skrll TPRINTF(("%s: njsc32_intr: %#x\n", sc->sc_dev.dv_xname, intr)); 2322 1.2.4.2 skrll 2323 1.2.4.2 skrll #if 0 /* I don't think this is required */ 2324 1.2.4.2 skrll /* mask interrupts */ 2325 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 2326 1.2.4.2 skrll #endif 2327 1.2.4.2 skrll 2328 1.2.4.2 skrll /* we got an interrupt, so stop the timer */ 2329 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 2330 1.2.4.2 skrll 2331 1.2.4.2 skrll if (intr & NJSC32_IRQ_SCSIRESET) { 2332 1.2.4.2 skrll printf("%s: detected bus reset\n", sc->sc_dev.dv_xname); 2333 1.2.4.2 skrll /* clear current request */ 2334 1.2.4.2 skrll njsc32_reset_detected(sc); 2335 1.2.4.2 skrll goto out; 2336 1.2.4.2 skrll } 2337 1.2.4.2 skrll 2338 1.2.4.2 skrll if (sc->sc_stat == NJSC32_STAT_ARBIT) { 2339 1.2.4.2 skrll cmd = sc->sc_curcmd; 2340 1.2.4.2 skrll KASSERT(cmd); 2341 1.2.4.2 skrll arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT); 2342 1.2.4.2 skrll if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) { 2343 1.2.4.2 skrll /* 2344 1.2.4.2 skrll * arbitration done 2345 1.2.4.2 skrll */ 2346 1.2.4.2 skrll /* clear arbitration status */ 2347 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION, 2348 1.2.4.2 skrll NJSC32_SETARB_CLEAR); 2349 1.2.4.2 skrll 2350 1.2.4.2 skrll if (arbstat & NJSC32_ARBSTAT_WIN) { 2351 1.2.4.2 skrll TPRINTC(cmd, 2352 1.2.4.2 skrll ("njsc32_intr: arbitration won\n")); 2353 1.2.4.2 skrll 2354 1.2.4.2 skrll TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 2355 1.2.4.2 skrll 2356 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_CONNECT; 2357 1.2.4.2 skrll } else { 2358 1.2.4.2 skrll TPRINTC(cmd, 2359 1.2.4.2 skrll ("njsc32_intr: arbitration failed\n")); 2360 1.2.4.2 skrll 2361 1.2.4.2 skrll njsc32_arbitration_failed(sc); 2362 1.2.4.2 skrll 2363 1.2.4.2 skrll /* XXX delay */ 2364 1.2.4.2 skrll /* XXX retry counter */ 2365 1.2.4.2 skrll } 2366 1.2.4.2 skrll } 2367 1.2.4.2 skrll } 2368 1.2.4.2 skrll 2369 1.2.4.2 skrll if (intr & NJSC32_IRQ_TIMER) { 2370 1.2.4.2 skrll TPRINTF(("%s: njsc32_intr: timer interrupt\n", 2371 1.2.4.2 skrll sc->sc_dev.dv_xname)); 2372 1.2.4.2 skrll } 2373 1.2.4.2 skrll 2374 1.2.4.2 skrll if (intr & NJSC32_IRQ_RESELECT) { 2375 1.2.4.2 skrll /* Reselection from a target */ 2376 1.2.4.2 skrll njsc32_arbitration_failed(sc); /* just in case */ 2377 1.2.4.2 skrll if ((cmd = sc->sc_curcmd) != NULL) { 2378 1.2.4.2 skrll /* ? */ 2379 1.2.4.2 skrll printf("%s: unexpected reselection\n", 2380 1.2.4.2 skrll sc->sc_dev.dv_xname); 2381 1.2.4.2 skrll sc->sc_curcmd = NULL; 2382 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_IDLE; 2383 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP); 2384 1.2.4.2 skrll } 2385 1.2.4.2 skrll 2386 1.2.4.2 skrll idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID); 2387 1.2.4.2 skrll if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 || 2388 1.2.4.2 skrll (sc->sc_reselid = ffs(idbit & ~NJSC32_INITIATOR_ID) -1) 2389 1.2.4.2 skrll < 0) { 2390 1.2.4.2 skrll printf("%s: invalid reselection (id: %#x)\n", 2391 1.2.4.2 skrll sc->sc_dev.dv_xname, idbit); 2392 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */ 2393 1.2.4.2 skrll } else { 2394 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_RESEL; 2395 1.2.4.2 skrll TPRINTF(("%s: njsc32_intr: reselection from %d\n", 2396 1.2.4.2 skrll sc->sc_dev.dv_xname, sc->sc_reselid)); 2397 1.2.4.2 skrll } 2398 1.2.4.2 skrll } 2399 1.2.4.2 skrll 2400 1.2.4.2 skrll if (intr & NJSC32_IRQ_PHASE_CHANGE) { 2401 1.2.4.2 skrll #if 1 /* XXX probably not needed */ 2402 1.2.4.2 skrll if (sc->sc_stat == NJSC32_STAT_ARBIT) 2403 1.2.4.2 skrll PRINTC(sc->sc_curcmd, 2404 1.2.4.2 skrll ("njsc32_intr: cancel arbitration phase\n")); 2405 1.2.4.2 skrll njsc32_arbitration_failed(sc); 2406 1.2.4.2 skrll #endif 2407 1.2.4.2 skrll /* current bus phase */ 2408 1.2.4.2 skrll bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 2409 1.2.4.2 skrll NJSC32_BUSMON_PHASE_MASK; 2410 1.2.4.2 skrll 2411 1.2.4.2 skrll switch (bus_phase) { 2412 1.2.4.2 skrll case NJSC32_PHASE_MESSAGE_IN: 2413 1.2.4.2 skrll njsc32_msgin(sc); 2414 1.2.4.2 skrll break; 2415 1.2.4.2 skrll 2416 1.2.4.2 skrll /* 2417 1.2.4.2 skrll * target may suddenly become Status / Bus Free phase 2418 1.2.4.2 skrll * to notify an error condition 2419 1.2.4.2 skrll */ 2420 1.2.4.2 skrll case NJSC32_PHASE_STATUS: 2421 1.2.4.2 skrll printf("%s: unexpected bus phase: Status\n", 2422 1.2.4.2 skrll sc->sc_dev.dv_xname); 2423 1.2.4.2 skrll if ((cmd = sc->sc_curcmd) != NULL) { 2424 1.2.4.2 skrll cmd->c_xs->status = 2425 1.2.4.2 skrll njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2426 1.2.4.2 skrll TPRINTC(cmd, ("njsc32_intr: Status %d\n", 2427 1.2.4.2 skrll cmd->c_xs->status)); 2428 1.2.4.2 skrll } 2429 1.2.4.2 skrll break; 2430 1.2.4.2 skrll case NJSC32_PHASE_BUSFREE: 2431 1.2.4.2 skrll printf("%s: unexpected bus phase: Bus Free\n", 2432 1.2.4.2 skrll sc->sc_dev.dv_xname); 2433 1.2.4.2 skrll if ((cmd = sc->sc_curcmd) != NULL) { 2434 1.2.4.2 skrll sc->sc_curcmd = NULL; 2435 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_IDLE; 2436 1.2.4.2 skrll if (cmd->c_xs->status != SCSI_QUEUE_FULL && 2437 1.2.4.2 skrll cmd->c_xs->status != SCSI_BUSY) 2438 1.2.4.2 skrll cmd->c_xs->status = SCSI_CHECK;/* XXX */ 2439 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, XS_BUSY); 2440 1.2.4.2 skrll } 2441 1.2.4.2 skrll goto out; 2442 1.2.4.2 skrll default: 2443 1.2.4.2 skrll #ifdef NJSC32_DEBUG 2444 1.2.4.2 skrll printf("%s: unexpected bus phase: ", 2445 1.2.4.2 skrll sc->sc_dev.dv_xname); 2446 1.2.4.2 skrll switch (bus_phase) { 2447 1.2.4.2 skrll case NJSC32_PHASE_COMMAND: 2448 1.2.4.2 skrll printf("Command\n"); break; 2449 1.2.4.2 skrll case NJSC32_PHASE_MESSAGE_OUT: 2450 1.2.4.2 skrll printf("Message Out\n");break; 2451 1.2.4.2 skrll case NJSC32_PHASE_DATA_IN: 2452 1.2.4.2 skrll printf("Data In\n"); break; 2453 1.2.4.2 skrll case NJSC32_PHASE_DATA_OUT: 2454 1.2.4.2 skrll printf("Data Out\n"); break; 2455 1.2.4.2 skrll case NJSC32_PHASE_RESELECT: 2456 1.2.4.2 skrll printf("Reselect\n");break; 2457 1.2.4.2 skrll default: printf("%#x\n", bus_phase); break; 2458 1.2.4.2 skrll } 2459 1.2.4.2 skrll #else 2460 1.2.4.2 skrll printf("%s: unexpected bus phase: %#x", 2461 1.2.4.2 skrll sc->sc_dev.dv_xname, bus_phase); 2462 1.2.4.2 skrll #endif 2463 1.2.4.2 skrll break; 2464 1.2.4.2 skrll } 2465 1.2.4.2 skrll } 2466 1.2.4.2 skrll 2467 1.2.4.2 skrll if (intr & NJSC32_IRQ_AUTOSCSI) { 2468 1.2.4.2 skrll /* 2469 1.2.4.2 skrll * AutoSCSI interrupt 2470 1.2.4.2 skrll */ 2471 1.2.4.2 skrll auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE); 2472 1.2.4.2 skrll TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n", 2473 1.2.4.2 skrll sc->sc_dev.dv_xname, auto_phase)); 2474 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0); 2475 1.2.4.2 skrll 2476 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) { 2477 1.2.4.2 skrll cmd = sc->sc_curcmd; 2478 1.2.4.2 skrll if (cmd == NULL) { 2479 1.2.4.2 skrll printf("%s: sel no cmd\n", 2480 1.2.4.2 skrll sc->sc_dev.dv_xname); 2481 1.2.4.2 skrll goto out; 2482 1.2.4.2 skrll } 2483 1.2.4.2 skrll DPRINTC(cmd, ("njsc32_intr: selection timeout\n")); 2484 1.2.4.2 skrll 2485 1.2.4.2 skrll sc->sc_curcmd = NULL; 2486 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_IDLE; 2487 1.2.4.2 skrll njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT); 2488 1.2.4.2 skrll 2489 1.2.4.2 skrll goto out; 2490 1.2.4.2 skrll } 2491 1.2.4.2 skrll 2492 1.2.4.2 skrll #ifdef NJSC32_TRACE 2493 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_COMMAND) { 2494 1.2.4.2 skrll /* Command phase has been automatically processed */ 2495 1.2.4.2 skrll TPRINTF(("%s: njsc32_intr: Command\n", 2496 1.2.4.2 skrll sc->sc_dev.dv_xname)); 2497 1.2.4.2 skrll } 2498 1.2.4.2 skrll #endif 2499 1.2.4.2 skrll #ifdef NJSC32_DEBUG 2500 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_ILLEGAL) { 2501 1.2.4.2 skrll printf("%s: njsc32_intr: Illegal phase\n", 2502 1.2.4.2 skrll sc->sc_dev.dv_xname); 2503 1.2.4.2 skrll } 2504 1.2.4.2 skrll #endif 2505 1.2.4.2 skrll 2506 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) { 2507 1.2.4.2 skrll TPRINTF(("%s: njsc32_intr: Process Message In\n", 2508 1.2.4.2 skrll sc->sc_dev.dv_xname)); 2509 1.2.4.2 skrll njsc32_msgin(sc); 2510 1.2.4.2 skrll } 2511 1.2.4.2 skrll 2512 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) { 2513 1.2.4.2 skrll TPRINTF(("%s: njsc32_intr: Process Message Out\n", 2514 1.2.4.2 skrll sc->sc_dev.dv_xname)); 2515 1.2.4.2 skrll njsc32_msgout(sc); 2516 1.2.4.2 skrll } 2517 1.2.4.2 skrll 2518 1.2.4.2 skrll cmd = sc->sc_curcmd; 2519 1.2.4.2 skrll if (cmd == NULL) { 2520 1.2.4.2 skrll TPRINTF(("%s: njsc32_intr: no cmd\n", 2521 1.2.4.2 skrll sc->sc_dev.dv_xname)); 2522 1.2.4.2 skrll goto out; 2523 1.2.4.2 skrll } 2524 1.2.4.2 skrll 2525 1.2.4.2 skrll if (auto_phase & 2526 1.2.4.2 skrll (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) { 2527 1.2.4.2 skrll #ifdef NJSC32_TRACE 2528 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_DATA_IN) 2529 1.2.4.2 skrll PRINTC(cmd, ("njsc32_intr: data in done\n")); 2530 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_DATA_OUT) 2531 1.2.4.2 skrll PRINTC(cmd, ("njsc32_intr: data out done\n")); 2532 1.2.4.2 skrll printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2533 1.2.4.2 skrll njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2534 1.2.4.2 skrll njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2535 1.2.4.2 skrll njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2536 1.2.4.2 skrll njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)); 2537 1.2.4.2 skrll #endif 2538 1.2.4.2 skrll 2539 1.2.4.2 skrll /* 2540 1.2.4.2 skrll * detected parity error on data transfer? 2541 1.2.4.2 skrll */ 2542 1.2.4.2 skrll if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 2543 1.2.4.2 skrll (NJSC32_PARITYSTATUS_ERROR_LSB| 2544 1.2.4.2 skrll NJSC32_PARITYSTATUS_ERROR_MSB)) { 2545 1.2.4.2 skrll 2546 1.2.4.2 skrll PRINTC(cmd, ("datain: parity error\n")); 2547 1.2.4.2 skrll 2548 1.2.4.2 skrll /* clear parity error */ 2549 1.2.4.2 skrll njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 2550 1.2.4.2 skrll NJSC32_PARITYCTL_CHECK_ENABLE | 2551 1.2.4.2 skrll NJSC32_PARITYCTL_CLEAR_ERROR); 2552 1.2.4.2 skrll 2553 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2554 1.2.4.2 skrll /* 2555 1.2.4.2 skrll * XXX command has already finished 2556 1.2.4.2 skrll * -- what can we do? 2557 1.2.4.2 skrll * 2558 1.2.4.2 skrll * It is not clear current command 2559 1.2.4.2 skrll * caused the error -- reset everything. 2560 1.2.4.2 skrll */ 2561 1.2.4.2 skrll njsc32_init(sc, 1); /* XXX */ 2562 1.2.4.2 skrll } else { 2563 1.2.4.2 skrll /* XXX does this case occur? */ 2564 1.2.4.2 skrll #if 1 2565 1.2.4.2 skrll printf("%s: datain: parity error\n", 2566 1.2.4.2 skrll sc->sc_dev.dv_xname); 2567 1.2.4.2 skrll #endif 2568 1.2.4.2 skrll /* 2569 1.2.4.2 skrll * Make attention condition and try 2570 1.2.4.2 skrll * to send Initiator Detected Error 2571 1.2.4.2 skrll * message. 2572 1.2.4.2 skrll */ 2573 1.2.4.2 skrll njsc32_init_msgout(sc); 2574 1.2.4.2 skrll njsc32_add_msgout(sc, 2575 1.2.4.2 skrll MSG_INITIATOR_DET_ERR); 2576 1.2.4.2 skrll njsc32_write_4(sc, 2577 1.2.4.2 skrll NJSC32_REG_SCSI_MSG_OUT, 2578 1.2.4.2 skrll njsc32_get_auto_msgout(sc)); 2579 1.2.4.2 skrll /* restart autoscsi with ATN */ 2580 1.2.4.2 skrll njsc32_write_2(sc, 2581 1.2.4.2 skrll NJSC32_REG_COMMAND_CONTROL, 2582 1.2.4.2 skrll NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2583 1.2.4.2 skrll NJSC32_CMD_AUTO_COMMAND_PHASE | 2584 1.2.4.2 skrll NJSC32_CMD_AUTO_SCSI_RESTART | 2585 1.2.4.2 skrll NJSC32_CMD_AUTO_MSGIN_00_04 | 2586 1.2.4.2 skrll NJSC32_CMD_AUTO_MSGIN_02 | 2587 1.2.4.2 skrll NJSC32_CMD_AUTO_ATN); 2588 1.2.4.2 skrll } 2589 1.2.4.2 skrll goto out; 2590 1.2.4.2 skrll } 2591 1.2.4.2 skrll 2592 1.2.4.2 skrll /* 2593 1.2.4.2 skrll * data has been transferred, and current pointer 2594 1.2.4.2 skrll * is changed 2595 1.2.4.2 skrll */ 2596 1.2.4.2 skrll njsc32_set_cur_ptr(cmd, cmd->c_dp_cur + 2597 1.2.4.2 skrll njsc32_read_4(sc, NJSC32_REG_SACK_CNT)); 2598 1.2.4.2 skrll } 2599 1.2.4.2 skrll 2600 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_MSGOUT) { 2601 1.2.4.2 skrll /* Message Out phase has been automatically processed */ 2602 1.2.4.2 skrll TPRINTC(cmd, ("njsc32_intr: Message Out\n")); 2603 1.2.4.2 skrll if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 && 2604 1.2.4.2 skrll sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) { 2605 1.2.4.2 skrll njsc32_init_msgout(sc); 2606 1.2.4.2 skrll } 2607 1.2.4.2 skrll } 2608 1.2.4.2 skrll 2609 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_STATUS) { 2610 1.2.4.2 skrll /* Status phase has been automatically processed */ 2611 1.2.4.2 skrll cmd->c_xs->status = 2612 1.2.4.2 skrll njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2613 1.2.4.2 skrll TPRINTC(cmd, ("njsc32_intr: Status %#x\n", 2614 1.2.4.2 skrll cmd->c_xs->status)); 2615 1.2.4.2 skrll } 2616 1.2.4.2 skrll 2617 1.2.4.2 skrll if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2618 1.2.4.2 skrll /* AutoSCSI is finished */ 2619 1.2.4.2 skrll 2620 1.2.4.2 skrll TPRINTC(cmd, ("njsc32_intr: Bus Free\n")); 2621 1.2.4.2 skrll 2622 1.2.4.2 skrll sc->sc_stat = NJSC32_STAT_IDLE; 2623 1.2.4.2 skrll sc->sc_curcmd = NULL; 2624 1.2.4.2 skrll 2625 1.2.4.2 skrll njsc32_end_auto(sc, cmd, auto_phase); 2626 1.2.4.2 skrll } 2627 1.2.4.2 skrll goto out; 2628 1.2.4.2 skrll } 2629 1.2.4.2 skrll 2630 1.2.4.2 skrll if (intr & NJSC32_IRQ_FIFO_THRESHOLD) { 2631 1.2.4.2 skrll /* XXX We use DMA, and this shouldn't happen */ 2632 1.2.4.2 skrll printf("%s: njsc32_intr: FIFO\n", sc->sc_dev.dv_xname); 2633 1.2.4.2 skrll njsc32_init(sc, 1); 2634 1.2.4.2 skrll goto out; 2635 1.2.4.2 skrll } 2636 1.2.4.2 skrll if (intr & NJSC32_IRQ_PCI) { 2637 1.2.4.2 skrll /* XXX? */ 2638 1.2.4.2 skrll printf("%s: njsc32_intr: PCI\n", sc->sc_dev.dv_xname); 2639 1.2.4.2 skrll } 2640 1.2.4.2 skrll if (intr & NJSC32_IRQ_BMCNTERR) { 2641 1.2.4.2 skrll /* XXX? */ 2642 1.2.4.2 skrll printf("%s: njsc32_intr: BM\n", sc->sc_dev.dv_xname); 2643 1.2.4.2 skrll } 2644 1.2.4.2 skrll 2645 1.2.4.2 skrll out: 2646 1.2.4.2 skrll /* go next command if controller is idle */ 2647 1.2.4.2 skrll if (sc->sc_stat == NJSC32_STAT_IDLE) 2648 1.2.4.2 skrll njsc32_start(sc); 2649 1.2.4.2 skrll 2650 1.2.4.2 skrll #if 0 2651 1.2.4.2 skrll /* enable interrupts */ 2652 1.2.4.2 skrll njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 2653 1.2.4.2 skrll #endif 2654 1.2.4.2 skrll 2655 1.2.4.2 skrll return 1; /* processed */ 2656 1.2.4.2 skrll } 2657
Indexes created Wed Oct 29 09:09:48 GMT 2025