ninjascsi32.c revision 1.2.6.3
1 1.2.6.3 tron /* $NetBSD: ninjascsi32.c,v 1.2.6.3 2006/01/20 22:20:50 tron Exp $ */ 2 1.2.6.2 he 3 1.2.6.2 he /*- 4 1.2.6.3 tron * Copyright (c) 2004, 2006 The NetBSD Foundation, Inc. 5 1.2.6.2 he * All rights reserved. 6 1.2.6.2 he * 7 1.2.6.2 he * This code is derived from software contributed to The NetBSD Foundation 8 1.2.6.2 he * by ITOH Yasufumi. 9 1.2.6.2 he * 10 1.2.6.2 he * Redistribution and use in source and binary forms, with or without 11 1.2.6.2 he * modification, are permitted provided that the following conditions 12 1.2.6.2 he * are met: 13 1.2.6.2 he * 1. Redistributions of source code must retain the above copyright 14 1.2.6.2 he * notice, this list of conditions and the following disclaimer. 15 1.2.6.2 he * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.6.2 he * notice, this list of conditions and the following disclaimer in the 17 1.2.6.2 he * documentation and/or other materials provided with the distribution. 18 1.2.6.2 he * 3. All advertising materials mentioning features or use of this software 19 1.2.6.2 he * must display the following acknowledgement: 20 1.2.6.2 he * This product includes software developed by the NetBSD 21 1.2.6.2 he * Foundation, Inc. and its contributors. 22 1.2.6.2 he * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.2.6.2 he * contributors may be used to endorse or promote products derived 24 1.2.6.2 he * from this software without specific prior written permission. 25 1.2.6.2 he * 26 1.2.6.2 he * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.2.6.2 he * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.2.6.2 he * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.2.6.2 he * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.2.6.2 he * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.2.6.2 he * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.2.6.2 he * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.2.6.2 he * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.2.6.2 he * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.2.6.2 he * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.2.6.2 he * POSSIBILITY OF SUCH DAMAGE. 37 1.2.6.2 he */ 38 1.2.6.2 he 39 1.2.6.2 he #include <sys/cdefs.h> 40 1.2.6.3 tron __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.2.6.3 2006/01/20 22:20:50 tron Exp $"); 41 1.2.6.2 he 42 1.2.6.2 he #include <sys/param.h> 43 1.2.6.2 he #include <sys/systm.h> 44 1.2.6.2 he #include <sys/callout.h> 45 1.2.6.2 he #include <sys/device.h> 46 1.2.6.2 he #include <sys/kernel.h> 47 1.2.6.2 he #include <sys/buf.h> 48 1.2.6.2 he #include <sys/scsiio.h> 49 1.2.6.2 he 50 1.2.6.2 he #include <machine/bus.h> 51 1.2.6.2 he #include <machine/intr.h> 52 1.2.6.2 he 53 1.2.6.2 he #include <uvm/uvm_extern.h> 54 1.2.6.2 he 55 1.2.6.2 he #include <dev/scsipi/scsi_all.h> 56 1.2.6.2 he #include <dev/scsipi/scsipi_all.h> 57 1.2.6.2 he #include <dev/scsipi/scsiconf.h> 58 1.2.6.2 he #include <dev/scsipi/scsi_message.h> 59 1.2.6.2 he 60 1.2.6.2 he /* 61 1.2.6.2 he * DualEdge transfer support 62 1.2.6.2 he */ 63 1.2.6.2 he /* #define NJSC32_DUALEDGE */ /* XXX untested */ 64 1.2.6.2 he 65 1.2.6.2 he /* 66 1.2.6.2 he * Auto param loading does not work properly (it partially works (works on 67 1.2.6.2 he * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51), 68 1.2.6.2 he * and it doesn't improve the performance so much, 69 1.2.6.2 he * forget about it. 70 1.2.6.2 he */ 71 1.2.6.2 he #undef NJSC32_AUTOPARAM 72 1.2.6.2 he 73 1.2.6.2 he #include <dev/ic/ninjascsi32reg.h> 74 1.2.6.2 he #include <dev/ic/ninjascsi32var.h> 75 1.2.6.2 he 76 1.2.6.2 he /* #define NJSC32_DEBUG */ 77 1.2.6.2 he /* #define NJSC32_TRACE */ 78 1.2.6.2 he 79 1.2.6.2 he #ifdef NJSC32_DEBUG 80 1.2.6.2 he #define DPRINTF(x) printf x 81 1.2.6.2 he #define DPRINTC(cmd, x) PRINTC(cmd, x) 82 1.2.6.2 he #else 83 1.2.6.2 he #define DPRINTF(x) 84 1.2.6.2 he #define DPRINTC(cmd, x) 85 1.2.6.2 he #endif 86 1.2.6.2 he #ifdef NJSC32_TRACE 87 1.2.6.2 he #define TPRINTF(x) printf x 88 1.2.6.2 he #define TPRINTC(cmd, x) PRINTC(cmd, x) 89 1.2.6.2 he #else 90 1.2.6.2 he #define TPRINTF(x) 91 1.2.6.2 he #define TPRINTC(cmd, x) 92 1.2.6.2 he #endif 93 1.2.6.2 he 94 1.2.6.2 he #define PRINTC(cmd, x) do { \ 95 1.2.6.2 he scsi_print_addr((cmd)->c_xs->xs_periph); \ 96 1.2.6.2 he printf x; \ 97 1.2.6.2 he } while (/* CONSTCOND */ 0) 98 1.2.6.2 he 99 1.2.6.2 he static void njsc32_scsipi_request(struct scsipi_channel *, 100 1.2.6.2 he scsipi_adapter_req_t, void *); 101 1.2.6.2 he static void njsc32_scsipi_minphys(struct buf *buf); 102 1.2.6.2 he static int njsc32_scsipi_ioctl(struct scsipi_channel *, u_long, caddr_t, 103 1.2.6.2 he int, struct proc *); 104 1.2.6.2 he 105 1.2.6.2 he static void njsc32_init(struct njsc32_softc *, int nosleep); 106 1.2.6.2 he static int njsc32_init_cmds(struct njsc32_softc *); 107 1.2.6.2 he static void njsc32_target_async(struct njsc32_softc *, 108 1.2.6.2 he struct njsc32_target *); 109 1.2.6.2 he static void njsc32_init_targets(struct njsc32_softc *); 110 1.2.6.2 he static void njsc32_add_msgout(struct njsc32_softc *, int); 111 1.2.6.2 he static u_int32_t njsc32_get_auto_msgout(struct njsc32_softc *); 112 1.2.6.2 he #ifdef NJSC32_DUALEDGE 113 1.2.6.2 he static void njsc32_msgout_wdtr(struct njsc32_softc *, int); 114 1.2.6.2 he #endif 115 1.2.6.2 he static void njsc32_msgout_sdtr(struct njsc32_softc *, int period, 116 1.2.6.2 he int offset); 117 1.2.6.2 he static void njsc32_negotiate_xfer(struct njsc32_softc *, 118 1.2.6.2 he struct njsc32_target *); 119 1.2.6.2 he static void njsc32_arbitration_failed(struct njsc32_softc *); 120 1.2.6.2 he static void njsc32_start(struct njsc32_softc *); 121 1.2.6.2 he static void njsc32_run_xfer(struct njsc32_softc *, struct scsipi_xfer *); 122 1.2.6.2 he static void njsc32_end_cmd(struct njsc32_softc *, struct njsc32_cmd *, 123 1.2.6.2 he scsipi_xfer_result_t); 124 1.2.6.2 he static void njsc32_reset_bus(struct njsc32_softc *); 125 1.2.6.2 he static void njsc32_clear_cmds(struct njsc32_softc *, 126 1.2.6.2 he scsipi_xfer_result_t); 127 1.2.6.2 he static void njsc32_reset_detected(struct njsc32_softc *); 128 1.2.6.2 he static void njsc32_set_ptr(struct njsc32_softc *, struct njsc32_cmd *, 129 1.2.6.2 he u_int32_t); 130 1.2.6.2 he static void njsc32_assert_ack(struct njsc32_softc *); 131 1.2.6.2 he static void njsc32_negate_ack(struct njsc32_softc *); 132 1.2.6.2 he static void njsc32_wait_req_negate(struct njsc32_softc *); 133 1.2.6.2 he static void njsc32_reconnect(struct njsc32_softc *, struct njsc32_cmd *); 134 1.2.6.2 he enum njsc32_reselstat { 135 1.2.6.2 he NJSC32_RESEL_ERROR, /* to be rejected */ 136 1.2.6.2 he NJSC32_RESEL_COMPLETE, /* reselection is just complete */ 137 1.2.6.2 he NJSC32_RESEL_THROUGH /* this message is OK (no reply) */ 138 1.2.6.2 he }; 139 1.2.6.2 he static enum njsc32_reselstat njsc32_resel_identify(struct njsc32_softc *, 140 1.2.6.2 he int lun, struct njsc32_cmd **); 141 1.2.6.2 he static enum njsc32_reselstat njsc32_resel_tag(struct njsc32_softc *, 142 1.2.6.2 he int tag, struct njsc32_cmd **); 143 1.2.6.2 he static void njsc32_cmd_reload(struct njsc32_softc *, struct njsc32_cmd *, 144 1.2.6.2 he int); 145 1.2.6.2 he static void njsc32_update_xfer_mode(struct njsc32_softc *, 146 1.2.6.2 he struct njsc32_target *); 147 1.2.6.2 he static void njsc32_msgin(struct njsc32_softc *); 148 1.2.6.2 he static void njsc32_msgout(struct njsc32_softc *); 149 1.2.6.2 he static void njsc32_cmdtimeout(void *); 150 1.2.6.2 he static void njsc32_reseltimeout(void *); 151 1.2.6.2 he 152 1.2.6.2 he static __inline unsigned 153 1.2.6.2 he njsc32_read_1(struct njsc32_softc *sc, int no) 154 1.2.6.2 he { 155 1.2.6.2 he 156 1.2.6.2 he return bus_space_read_1(sc->sc_regt, sc->sc_regh, no); 157 1.2.6.2 he } 158 1.2.6.2 he 159 1.2.6.2 he static __inline unsigned 160 1.2.6.2 he njsc32_read_2(struct njsc32_softc *sc, int no) 161 1.2.6.2 he { 162 1.2.6.2 he 163 1.2.6.2 he return bus_space_read_2(sc->sc_regt, sc->sc_regh, no); 164 1.2.6.2 he } 165 1.2.6.2 he 166 1.2.6.2 he static __inline u_int32_t 167 1.2.6.2 he njsc32_read_4(struct njsc32_softc *sc, int no) 168 1.2.6.2 he { 169 1.2.6.2 he 170 1.2.6.2 he return bus_space_read_4(sc->sc_regt, sc->sc_regh, no); 171 1.2.6.2 he } 172 1.2.6.2 he 173 1.2.6.2 he static __inline void 174 1.2.6.2 he njsc32_write_1(struct njsc32_softc *sc, int no, int val) 175 1.2.6.2 he { 176 1.2.6.2 he 177 1.2.6.2 he bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val); 178 1.2.6.2 he } 179 1.2.6.2 he 180 1.2.6.2 he static __inline void 181 1.2.6.2 he njsc32_write_2(struct njsc32_softc *sc, int no, int val) 182 1.2.6.2 he { 183 1.2.6.2 he 184 1.2.6.2 he bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val); 185 1.2.6.2 he } 186 1.2.6.2 he 187 1.2.6.2 he static __inline void 188 1.2.6.2 he njsc32_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 189 1.2.6.2 he { 190 1.2.6.2 he 191 1.2.6.2 he bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val); 192 1.2.6.2 he } 193 1.2.6.2 he 194 1.2.6.2 he static __inline unsigned 195 1.2.6.2 he njsc32_ireg_read_1(struct njsc32_softc *sc, int no) 196 1.2.6.2 he { 197 1.2.6.2 he 198 1.2.6.2 he bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 199 1.2.6.2 he return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 200 1.2.6.2 he } 201 1.2.6.2 he 202 1.2.6.2 he static __inline unsigned 203 1.2.6.2 he njsc32_ireg_read_2(struct njsc32_softc *sc, int no) 204 1.2.6.2 he { 205 1.2.6.2 he 206 1.2.6.2 he bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 207 1.2.6.2 he return bus_space_read_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 208 1.2.6.2 he } 209 1.2.6.2 he 210 1.2.6.2 he static __inline u_int32_t 211 1.2.6.2 he njsc32_ireg_read_4(struct njsc32_softc *sc, int no) 212 1.2.6.2 he { 213 1.2.6.2 he u_int32_t val; 214 1.2.6.2 he 215 1.2.6.2 he bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 216 1.2.6.2 he val = (u_int16_t)bus_space_read_2(sc->sc_regt, sc->sc_regh, 217 1.2.6.2 he NJSC32_REG_DATA_LOW); 218 1.2.6.2 he return val | (bus_space_read_2(sc->sc_regt, sc->sc_regh, 219 1.2.6.2 he NJSC32_REG_DATA_HIGH) << 16); 220 1.2.6.2 he } 221 1.2.6.2 he 222 1.2.6.2 he static __inline void 223 1.2.6.2 he njsc32_ireg_write_1(struct njsc32_softc *sc, int no, int val) 224 1.2.6.2 he { 225 1.2.6.2 he 226 1.2.6.2 he bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 227 1.2.6.2 he bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 228 1.2.6.2 he } 229 1.2.6.2 he 230 1.2.6.2 he static __inline void 231 1.2.6.2 he njsc32_ireg_write_2(struct njsc32_softc *sc, int no, int val) 232 1.2.6.2 he { 233 1.2.6.2 he 234 1.2.6.2 he bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 235 1.2.6.2 he bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 236 1.2.6.2 he } 237 1.2.6.2 he 238 1.2.6.2 he static __inline void 239 1.2.6.2 he njsc32_ireg_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 240 1.2.6.2 he { 241 1.2.6.2 he 242 1.2.6.2 he bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 243 1.2.6.2 he bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 244 1.2.6.2 he bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_HIGH, 245 1.2.6.2 he val >> 16); 246 1.2.6.2 he } 247 1.2.6.2 he 248 1.2.6.2 he #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */ 249 1.2.6.2 he #ifdef __STDC__ 250 1.2.6.2 he # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK 251 1.2.6.2 he # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \ 252 1.2.6.2 he NJSC32_SREQ_SAMPLING_ENABLE) 253 1.2.6.2 he #else 254 1.2.6.2 he # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK 255 1.2.6.2 he # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \ 256 1.2.6.2 he NJSC32_SREQ_SAMPLING_ENABLE) 257 1.2.6.2 he #endif 258 1.2.6.2 he 259 1.2.6.2 he #define NJSC32_NSYNCT_MAXSYNC 1 260 1.2.6.2 he #define NJSC32_NSYNCT 16 261 1.2.6.2 he 262 1.2.6.2 he /* 40MHz (25ns) */ 263 1.2.6.2 he static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = { 264 1.2.6.2 he { 0, 0, 0 }, /* dummy for async */ 265 1.2.6.2 he { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */ 266 1.2.6.2 he { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */ 267 1.2.6.2 he { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */ 268 1.2.6.2 he { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */ 269 1.2.6.2 he { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */ 270 1.2.6.2 he { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */ 271 1.2.6.2 he { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 272 1.2.6.2 he { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */ 273 1.2.6.2 he { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 274 1.2.6.2 he { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */ 275 1.2.6.2 he { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */ 276 1.2.6.2 he { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */ 277 1.2.6.2 he { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */ 278 1.2.6.2 he { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */ 279 1.2.6.2 he { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */ 280 1.2.6.2 he }; 281 1.2.6.2 he 282 1.2.6.2 he #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 283 1.2.6.2 he /* 20MHz (50ns) */ 284 1.2.6.2 he static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = { 285 1.2.6.2 he { 0, 0, 0 }, /* dummy for async */ 286 1.2.6.2 he { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */ 287 1.2.6.2 he { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */ 288 1.2.6.2 he { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 289 1.2.6.2 he { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 290 1.2.6.2 he { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */ 291 1.2.6.2 he { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */ 292 1.2.6.2 he { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */ 293 1.2.6.2 he { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */ 294 1.2.6.2 he { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */ 295 1.2.6.2 he { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */ 296 1.2.6.2 he { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */ 297 1.2.6.2 he { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */ 298 1.2.6.2 he { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */ 299 1.2.6.2 he { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */ 300 1.2.6.2 he { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */ 301 1.2.6.2 he }; 302 1.2.6.2 he 303 1.2.6.2 he /* 33.3MHz (30ns) */ 304 1.2.6.2 he static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = { 305 1.2.6.2 he { 0, 0, 0 }, /* dummy for async */ 306 1.2.6.2 he { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */ 307 1.2.6.2 he { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */ 308 1.2.6.2 he { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */ 309 1.2.6.2 he { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */ 310 1.2.6.2 he { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */ 311 1.2.6.2 he { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */ 312 1.2.6.2 he { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */ 313 1.2.6.2 he { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */ 314 1.2.6.2 he { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */ 315 1.2.6.2 he { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */ 316 1.2.6.2 he { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */ 317 1.2.6.2 he { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */ 318 1.2.6.2 he { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */ 319 1.2.6.2 he { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */ 320 1.2.6.2 he { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */ 321 1.2.6.2 he }; 322 1.2.6.2 he #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */ 323 1.2.6.2 he 324 1.2.6.2 he #undef NS 325 1.2.6.2 he #undef ACKW 326 1.2.6.2 he #undef SMPL 327 1.2.6.2 he 328 1.2.6.2 he /* initialize device */ 329 1.2.6.2 he static void 330 1.2.6.2 he njsc32_init(struct njsc32_softc *sc, int nosleep) 331 1.2.6.2 he { 332 1.2.6.2 he u_int16_t intstat; 333 1.2.6.2 he 334 1.2.6.2 he /* block all interrupts */ 335 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 336 1.2.6.2 he 337 1.2.6.2 he /* clear transfer */ 338 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 339 1.2.6.2 he njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0); 340 1.2.6.2 he 341 1.2.6.2 he /* make sure interrupts are cleared */ 342 1.2.6.2 he /* XXX loop forever? */ 343 1.2.6.2 he while ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ)) & 344 1.2.6.2 he NJSC32_IRQ_INTR_PENDING) { 345 1.2.6.2 he DPRINTF(("%s: njsc32_init: intr pending: %#x\n", 346 1.2.6.2 he sc->sc_dev.dv_xname, intstat)); 347 1.2.6.2 he } 348 1.2.6.2 he 349 1.2.6.2 he /* FIFO threshold */ 350 1.2.6.2 he njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL, 351 1.2.6.2 he NJSC32_FIFO_FULL_BUSMASTER); 352 1.2.6.2 he njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY, 353 1.2.6.2 he NJSC32_FIFO_EMPTY_BUSMASTER); 354 1.2.6.2 he 355 1.2.6.2 he /* clock source */ 356 1.2.6.2 he njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk); 357 1.2.6.2 he 358 1.2.6.2 he /* memory read multiple */ 359 1.2.6.2 he njsc32_ireg_write_1(sc, NJSC32_IREG_BM, 360 1.2.6.2 he NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD); 361 1.2.6.2 he 362 1.2.6.2 he /* clear parity error and enable parity detection */ 363 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 364 1.2.6.2 he NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 365 1.2.6.2 he 366 1.2.6.2 he /* misc configuration */ 367 1.2.6.2 he njsc32_ireg_write_2(sc, NJSC32_IREG_MISC, 368 1.2.6.2 he NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT | 369 1.2.6.2 he NJSC32_MISC_DELAYED_BMSTART | 370 1.2.6.2 he NJSC32_MISC_MASTER_TERMINATION_SELECT | 371 1.2.6.2 he NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL | 372 1.2.6.2 he NJSC32_MISC_AUTOSEL_TIMING_SEL | 373 1.2.6.2 he NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE); 374 1.2.6.2 he 375 1.2.6.2 he /* 376 1.2.6.2 he * Check for termination power (32Bi only?). 377 1.2.6.2 he */ 378 1.2.6.2 he if (!nosleep || cold) { 379 1.2.6.2 he DPRINTF(("%s: njsc32_init: checking TERMPWR\n", 380 1.2.6.2 he sc->sc_dev.dv_xname)); 381 1.2.6.2 he 382 1.2.6.2 he /* First, turn termination power off */ 383 1.2.6.2 he njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0); 384 1.2.6.2 he 385 1.2.6.2 he /* give 0.5s to settle */ 386 1.2.6.2 he if (nosleep) 387 1.2.6.2 he delay(500000); 388 1.2.6.2 he else 389 1.2.6.2 he tsleep(sc, PWAIT, "njs_t1", hz / 2); 390 1.2.6.2 he } 391 1.2.6.2 he 392 1.2.6.2 he /* supply termination power if not supplied by other devices */ 393 1.2.6.2 he if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) & 394 1.2.6.2 he NJSC32_TERMPWR_SENSE) == 0) { 395 1.2.6.2 he /* termination power is not present on the bus */ 396 1.2.6.2 he if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) { 397 1.2.6.2 he /* 398 1.2.6.2 he * CardBus device must not supply termination power 399 1.2.6.2 he * to avoid excessive power consumption. 400 1.2.6.2 he */ 401 1.2.6.2 he printf("%s: no termination power present\n", 402 1.2.6.2 he sc->sc_dev.dv_xname); 403 1.2.6.2 he } else { 404 1.2.6.2 he /* supply termination power */ 405 1.2.6.2 he njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 406 1.2.6.2 he NJSC32_TERMPWR_BPWR); 407 1.2.6.2 he 408 1.2.6.2 he DPRINTF(("%s: supplying termination power\n", 409 1.2.6.2 he sc->sc_dev.dv_xname)); 410 1.2.6.2 he 411 1.2.6.2 he /* give 0.5s to settle */ 412 1.2.6.2 he if (!nosleep) 413 1.2.6.2 he tsleep(sc, PWAIT, "njs_t2", hz / 2); 414 1.2.6.2 he } 415 1.2.6.2 he } 416 1.2.6.2 he 417 1.2.6.2 he /* stop timer */ 418 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 419 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 420 1.2.6.2 he 421 1.2.6.2 he /* default transfer parameter */ 422 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SYNC, 0); 423 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK); 424 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT, 425 1.2.6.2 he NJSC32_SEL_TIMEOUT_TIME); 426 1.2.6.2 he 427 1.2.6.2 he /* select interrupt source */ 428 1.2.6.2 he njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT, 429 1.2.6.2 he NJSC32_IRQSEL_RESELECT | 430 1.2.6.2 he NJSC32_IRQSEL_PHASE_CHANGE | 431 1.2.6.2 he NJSC32_IRQSEL_SCSIRESET | 432 1.2.6.2 he NJSC32_IRQSEL_TIMER | 433 1.2.6.2 he NJSC32_IRQSEL_FIFO_THRESHOLD | 434 1.2.6.2 he NJSC32_IRQSEL_TARGET_ABORT | 435 1.2.6.2 he NJSC32_IRQSEL_MASTER_ABORT | 436 1.2.6.2 he /* XXX not yet 437 1.2.6.2 he NJSC32_IRQSEL_SERR | 438 1.2.6.2 he NJSC32_IRQSEL_PERR | 439 1.2.6.2 he NJSC32_IRQSEL_BMCNTERR | 440 1.2.6.2 he */ 441 1.2.6.2 he NJSC32_IRQSEL_AUTO_SCSI_SEQ); 442 1.2.6.2 he 443 1.2.6.2 he /* unblock interrupts */ 444 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 445 1.2.6.2 he 446 1.2.6.2 he /* turn LED off */ 447 1.2.6.2 he njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR, 448 1.2.6.2 he NJSC32_EXTPORT_LED_OFF); 449 1.2.6.2 he njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, 450 1.2.6.2 he NJSC32_EXTPORT_LED_OFF); 451 1.2.6.2 he 452 1.2.6.2 he /* reset SCSI bus so the targets become known state */ 453 1.2.6.2 he njsc32_reset_bus(sc); 454 1.2.6.2 he } 455 1.2.6.2 he 456 1.2.6.2 he static int 457 1.2.6.2 he njsc32_init_cmds(struct njsc32_softc *sc) 458 1.2.6.2 he { 459 1.2.6.2 he struct njsc32_cmd *cmd; 460 1.2.6.2 he bus_addr_t dmaaddr; 461 1.2.6.2 he int i, error; 462 1.2.6.2 he 463 1.2.6.2 he /* 464 1.2.6.2 he * allocate DMA area for command 465 1.2.6.2 he */ 466 1.2.6.2 he if ((error = bus_dmamem_alloc(sc->sc_dmat, 467 1.2.6.2 he sizeof(struct njsc32_dma_page), PAGE_SIZE, 0, 468 1.2.6.2 he &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) { 469 1.2.6.2 he printf("%s: unable to allocate cmd page, error = %d\n", 470 1.2.6.2 he sc->sc_dev.dv_xname, error); 471 1.2.6.2 he return 0; 472 1.2.6.2 he } 473 1.2.6.2 he if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg, 474 1.2.6.2 he sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page), 475 1.2.6.2 he (caddr_t *)&sc->sc_cmdpg, 476 1.2.6.2 he BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 477 1.2.6.2 he printf("%s: unable to map cmd page, error = %d\n", 478 1.2.6.2 he sc->sc_dev.dv_xname, error); 479 1.2.6.2 he goto fail1; 480 1.2.6.2 he } 481 1.2.6.2 he if ((error = bus_dmamap_create(sc->sc_dmat, 482 1.2.6.2 he sizeof(struct njsc32_dma_page), 1, 483 1.2.6.2 he sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT, 484 1.2.6.2 he &sc->sc_dmamap_cmdpg)) != 0) { 485 1.2.6.2 he printf("%s: unable to create cmd DMA map, error = %d\n", 486 1.2.6.2 he sc->sc_dev.dv_xname, error); 487 1.2.6.2 he goto fail2; 488 1.2.6.2 he } 489 1.2.6.2 he if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg, 490 1.2.6.2 he sc->sc_cmdpg, sizeof(struct njsc32_dma_page), 491 1.2.6.2 he NULL, BUS_DMA_NOWAIT)) != 0) { 492 1.2.6.2 he printf("%s: unable to load cmd DMA map, error = %d\n", 493 1.2.6.2 he sc->sc_dev.dv_xname, error); 494 1.2.6.2 he goto fail3; 495 1.2.6.2 he } 496 1.2.6.2 he 497 1.2.6.2 he memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page)); 498 1.2.6.2 he dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr; 499 1.2.6.2 he 500 1.2.6.2 he #ifdef NJSC32_AUTOPARAM 501 1.2.6.2 he sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap); 502 1.2.6.2 he #endif 503 1.2.6.2 he 504 1.2.6.2 he for (i = 0; i < NJSC32_NUM_CMD; i++) { 505 1.2.6.2 he cmd = &sc->sc_cmds[i]; 506 1.2.6.2 he cmd->c_sc = sc; 507 1.2.6.2 he cmd->c_sgt = sc->sc_cmdpg->dp_sg[i]; 508 1.2.6.2 he cmd->c_sgt_dma = dmaaddr + 509 1.2.6.2 he offsetof(struct njsc32_dma_page, dp_sg[i]); 510 1.2.6.2 he cmd->c_flags = 0; 511 1.2.6.2 he 512 1.2.6.2 he error = bus_dmamap_create(sc->sc_dmat, 513 1.2.6.2 he NJSC32_MAX_XFER, /* max total map size */ 514 1.2.6.2 he NJSC32_NUM_SG, /* max number of segments */ 515 1.2.6.2 he NJSC32_SGT_MAXSEGLEN, /* max size of a segment */ 516 1.2.6.2 he 0, /* boundary */ 517 1.2.6.2 he BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer); 518 1.2.6.2 he if (error) { 519 1.2.6.2 he printf("%s: only %d cmd descs available (error = %d)\n", 520 1.2.6.2 he sc->sc_dev.dv_xname, i, error); 521 1.2.6.2 he break; 522 1.2.6.2 he } 523 1.2.6.2 he TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q); 524 1.2.6.2 he } 525 1.2.6.2 he 526 1.2.6.2 he if (i > 0) 527 1.2.6.2 he return i; 528 1.2.6.2 he 529 1.2.6.3 tron bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 530 1.2.6.2 he fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 531 1.2.6.2 he fail2: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg, 532 1.2.6.2 he sizeof(struct njsc32_dma_page)); 533 1.2.6.2 he fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs); 534 1.2.6.2 he 535 1.2.6.2 he return 0; 536 1.2.6.2 he } 537 1.2.6.2 he 538 1.2.6.2 he static void 539 1.2.6.2 he njsc32_target_async(struct njsc32_softc *sc, struct njsc32_target *target) 540 1.2.6.2 he { 541 1.2.6.2 he 542 1.2.6.2 he target->t_sync = 543 1.2.6.2 he NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC); 544 1.2.6.2 he target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK; 545 1.2.6.2 he target->t_sample = 0; /* disable */ 546 1.2.6.2 he target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC; 547 1.2.6.2 he target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC; 548 1.2.6.2 he } 549 1.2.6.2 he 550 1.2.6.2 he static void 551 1.2.6.2 he njsc32_init_targets(struct njsc32_softc *sc) 552 1.2.6.2 he { 553 1.2.6.2 he int id, lun; 554 1.2.6.2 he struct njsc32_lu *lu; 555 1.2.6.2 he 556 1.2.6.2 he for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 557 1.2.6.2 he /* cancel negotiation status */ 558 1.2.6.2 he sc->sc_targets[id].t_state = NJSC32_TARST_INIT; 559 1.2.6.2 he 560 1.2.6.2 he /* default to async mode */ 561 1.2.6.2 he njsc32_target_async(sc, &sc->sc_targets[id]); 562 1.2.6.2 he 563 1.2.6.2 he #ifdef NJSC32_DUALEDGE 564 1.2.6.2 he sc->sc_targets[id].t_xferctl = 0; 565 1.2.6.2 he #endif 566 1.2.6.2 he 567 1.2.6.2 he sc->sc_targets[id].t_targetid = 568 1.2.6.2 he (1 << id) | (1 << NJSC32_INITIATOR_ID); 569 1.2.6.2 he 570 1.2.6.2 he /* init logical units */ 571 1.2.6.2 he for (lun = 0; lun < NJSC32_NLU; lun++) { 572 1.2.6.2 he lu = &sc->sc_targets[id].t_lus[lun]; 573 1.2.6.2 he lu->lu_cmd = NULL; 574 1.2.6.2 he TAILQ_INIT(&lu->lu_q); 575 1.2.6.2 he } 576 1.2.6.2 he } 577 1.2.6.2 he } 578 1.2.6.2 he 579 1.2.6.2 he void 580 1.2.6.2 he njsc32_attach(struct njsc32_softc *sc) 581 1.2.6.2 he { 582 1.2.6.2 he const char *str; 583 1.2.6.2 he #if 1 /* test */ 584 1.2.6.2 he int reg; 585 1.2.6.2 he njsc32_model_t detected_model; 586 1.2.6.2 he #endif 587 1.2.6.2 he 588 1.2.6.2 he /* init */ 589 1.2.6.2 he TAILQ_INIT(&sc->sc_freecmd); 590 1.2.6.2 he TAILQ_INIT(&sc->sc_reqcmd); 591 1.2.6.2 he 592 1.2.6.2 he #if 1 /* test */ 593 1.2.6.2 he /* 594 1.2.6.2 he * try to distinguish 32Bi and 32UDE 595 1.2.6.2 he */ 596 1.2.6.2 he /* try to set DualEdge bit (exists on 32UDE only) and read it back */ 597 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE); 598 1.2.6.2 he if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) { 599 1.2.6.2 he /* device was removed? */ 600 1.2.6.2 he printf("%s: attach failed\n", sc->sc_dev.dv_xname); 601 1.2.6.2 he return; 602 1.2.6.2 he } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) { 603 1.2.6.2 he detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE; 604 1.2.6.2 he } else { 605 1.2.6.2 he detected_model = NJSC32_MODEL_32BI; 606 1.2.6.2 he } 607 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */ 608 1.2.6.2 he 609 1.2.6.2 he #if 1/*def DIAGNOSTIC*/ 610 1.2.6.2 he /* compare what is configured with what is detected */ 611 1.2.6.2 he if ((sc->sc_model & NJSC32_MODEL_MASK) != 612 1.2.6.2 he (detected_model & NJSC32_MODEL_MASK)) { 613 1.2.6.2 he /* 614 1.2.6.2 he * Please report this error if it happens. 615 1.2.6.2 he */ 616 1.2.6.2 he printf("%s: model mismatch: %#x vs %#x\n", 617 1.2.6.2 he sc->sc_dev.dv_xname, sc->sc_model, detected_model); 618 1.2.6.2 he return; 619 1.2.6.2 he } 620 1.2.6.2 he #endif 621 1.2.6.2 he #endif 622 1.2.6.2 he 623 1.2.6.2 he /* check model */ 624 1.2.6.2 he switch (sc->sc_model & NJSC32_MODEL_MASK) { 625 1.2.6.2 he case NJSC32_MODEL_32BI: 626 1.2.6.2 he str = "Bi"; 627 1.2.6.2 he /* 32Bi doesn't support DualEdge transfer */ 628 1.2.6.2 he KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0); 629 1.2.6.2 he break; 630 1.2.6.2 he case NJSC32_MODEL_32UDE: 631 1.2.6.2 he str = "UDE"; 632 1.2.6.2 he break; 633 1.2.6.2 he default: 634 1.2.6.2 he printf("%s: unknown model!\n", sc->sc_dev.dv_xname); 635 1.2.6.2 he return; 636 1.2.6.2 he } 637 1.2.6.2 he printf("%s: NJSC-32%s", sc->sc_dev.dv_xname, str); 638 1.2.6.2 he 639 1.2.6.2 he switch (sc->sc_clk) { 640 1.2.6.2 he default: 641 1.2.6.2 he #ifdef DIAGNOSTIC 642 1.2.6.2 he panic("njsc32_attach: unknown clk %d", sc->sc_clk); 643 1.2.6.2 he #endif 644 1.2.6.2 he case NJSC32_CLOCK_DIV_4: 645 1.2.6.2 he sc->sc_synct = njsc32_synct_40M; 646 1.2.6.2 he str = "40MHz"; 647 1.2.6.2 he break; 648 1.2.6.2 he #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 649 1.2.6.2 he case NJSC32_CLOCK_DIV_2: 650 1.2.6.2 he sc->sc_synct = njsc32_synct_20M; 651 1.2.6.2 he str = "20MHz"; 652 1.2.6.2 he break; 653 1.2.6.2 he case NJSC32_CLOCK_PCICLK: 654 1.2.6.2 he sc->sc_synct = njsc32_synct_pci; 655 1.2.6.2 he str = "PCI"; 656 1.2.6.2 he break; 657 1.2.6.2 he #endif 658 1.2.6.2 he } 659 1.2.6.2 he printf(", G/A rev %#x, clk %s%s\n", 660 1.2.6.2 he NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str, 661 1.2.6.2 he (sc->sc_model & NJSC32_FLAG_DUALEDGE) ? 662 1.2.6.2 he #ifdef NJSC32_DUALEDGE 663 1.2.6.2 he ", DualEdge" 664 1.2.6.2 he #else 665 1.2.6.2 he ", DualEdge (no driver support)" 666 1.2.6.2 he #endif 667 1.2.6.2 he : ""); 668 1.2.6.2 he 669 1.2.6.2 he /* allocate DMA resource */ 670 1.2.6.2 he if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) { 671 1.2.6.2 he printf("%s: no usable DMA map\n", sc->sc_dev.dv_xname); 672 1.2.6.2 he return; 673 1.2.6.2 he } 674 1.2.6.2 he sc->sc_flags |= NJSC32_CMDPG_MAPPED; 675 1.2.6.2 he 676 1.2.6.2 he sc->sc_curcmd = NULL; 677 1.2.6.2 he sc->sc_nusedcmds = 0; 678 1.2.6.2 he sc->sc_stat = NJSC32_STAT_IDLE; 679 1.2.6.2 he 680 1.2.6.2 he sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */ 681 1.2.6.2 he 682 1.2.6.2 he /* initialize target structure */ 683 1.2.6.2 he njsc32_init_targets(sc); 684 1.2.6.2 he 685 1.2.6.2 he /* initialize hardware */ 686 1.2.6.2 he njsc32_init(sc, cold); 687 1.2.6.2 he 688 1.2.6.2 he /* setup adapter */ 689 1.2.6.2 he sc->sc_adapter.adapt_dev = &sc->sc_dev; 690 1.2.6.2 he sc->sc_adapter.adapt_nchannels = 1; 691 1.2.6.2 he sc->sc_adapter.adapt_request = njsc32_scsipi_request; 692 1.2.6.2 he sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys; 693 1.2.6.2 he sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl; 694 1.2.6.2 he 695 1.2.6.2 he sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings = 696 1.2.6.2 he sc->sc_ncmd; 697 1.2.6.2 he 698 1.2.6.2 he /* setup channel */ 699 1.2.6.2 he sc->sc_channel.chan_adapter = &sc->sc_adapter; 700 1.2.6.2 he sc->sc_channel.chan_bustype = &scsi_bustype; 701 1.2.6.2 he sc->sc_channel.chan_channel = 0; 702 1.2.6.2 he sc->sc_channel.chan_ntargets = NJSC32_NTARGET; 703 1.2.6.2 he sc->sc_channel.chan_nluns = NJSC32_NLU; 704 1.2.6.2 he sc->sc_channel.chan_id = NJSC32_INITIATOR_ID; 705 1.2.6.2 he 706 1.2.6.2 he sc->sc_scsi = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 707 1.2.6.2 he } 708 1.2.6.2 he 709 1.2.6.2 he int 710 1.2.6.2 he njsc32_detach(struct njsc32_softc *sc, int flags) 711 1.2.6.2 he { 712 1.2.6.2 he int rv = 0; 713 1.2.6.2 he int i, s; 714 1.2.6.2 he struct njsc32_cmd *cmd; 715 1.2.6.2 he 716 1.2.6.2 he s = splbio(); 717 1.2.6.2 he 718 1.2.6.2 he /* clear running/disconnected commands */ 719 1.2.6.2 he njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP); 720 1.2.6.2 he 721 1.2.6.2 he sc->sc_stat = NJSC32_STAT_DETACH; 722 1.2.6.2 he 723 1.2.6.2 he /* clear pending commands */ 724 1.2.6.2 he while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 725 1.2.6.2 he TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 726 1.2.6.2 he njsc32_end_cmd(sc, cmd, XS_RESET); 727 1.2.6.2 he } 728 1.2.6.2 he 729 1.2.6.2 he if (sc->sc_scsi != NULL) 730 1.2.6.2 he rv = config_detach(sc->sc_scsi, flags); 731 1.2.6.2 he 732 1.2.6.2 he splx(s); 733 1.2.6.2 he 734 1.2.6.2 he /* free DMA resource */ 735 1.2.6.2 he if (sc->sc_flags & NJSC32_CMDPG_MAPPED) { 736 1.2.6.2 he for (i = 0; i < sc->sc_ncmd; i++) { 737 1.2.6.2 he cmd = &sc->sc_cmds[i]; 738 1.2.6.2 he if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) 739 1.2.6.2 he bus_dmamap_unload(sc->sc_dmat, 740 1.2.6.2 he cmd->c_dmamap_xfer); 741 1.2.6.2 he bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer); 742 1.2.6.2 he } 743 1.2.6.2 he 744 1.2.6.2 he bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 745 1.2.6.2 he bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 746 1.2.6.2 he bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg, 747 1.2.6.2 he sizeof(struct njsc32_dma_page)); 748 1.2.6.2 he bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, 749 1.2.6.2 he sc->sc_cmdpg_nsegs); 750 1.2.6.2 he } 751 1.2.6.2 he 752 1.2.6.2 he return 0; 753 1.2.6.2 he } 754 1.2.6.2 he 755 1.2.6.2 he static __inline void 756 1.2.6.2 he njsc32_cmd_init(struct njsc32_cmd *cmd) 757 1.2.6.2 he { 758 1.2.6.2 he 759 1.2.6.2 he cmd->c_flags = 0; 760 1.2.6.2 he 761 1.2.6.2 he /* scatter/gather table */ 762 1.2.6.2 he cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0); 763 1.2.6.2 he cmd->c_sgoffset = 0; 764 1.2.6.2 he cmd->c_sgfixcnt = 0; 765 1.2.6.2 he 766 1.2.6.2 he /* data pointer */ 767 1.2.6.2 he cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0; 768 1.2.6.2 he } 769 1.2.6.2 he 770 1.2.6.2 he static __inline void 771 1.2.6.2 he njsc32_init_msgout(struct njsc32_softc *sc) 772 1.2.6.2 he { 773 1.2.6.2 he 774 1.2.6.2 he sc->sc_msgoutlen = 0; 775 1.2.6.2 he sc->sc_msgoutidx = 0; 776 1.2.6.2 he } 777 1.2.6.2 he 778 1.2.6.2 he static void 779 1.2.6.2 he njsc32_add_msgout(struct njsc32_softc *sc, int byte) 780 1.2.6.2 he { 781 1.2.6.2 he 782 1.2.6.2 he if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) { 783 1.2.6.2 he printf("njsc32_add_msgout: too many\n"); 784 1.2.6.2 he return; 785 1.2.6.2 he } 786 1.2.6.2 he sc->sc_msgout[sc->sc_msgoutlen++] = byte; 787 1.2.6.2 he } 788 1.2.6.2 he 789 1.2.6.2 he static u_int32_t 790 1.2.6.2 he njsc32_get_auto_msgout(struct njsc32_softc *sc) 791 1.2.6.2 he { 792 1.2.6.2 he u_int32_t val; 793 1.2.6.2 he u_int8_t *p; 794 1.2.6.2 he 795 1.2.6.2 he val = 0; 796 1.2.6.2 he p = sc->sc_msgout; 797 1.2.6.2 he switch (sc->sc_msgoutlen) { 798 1.2.6.2 he /* 31-24 23-16 15-8 7 ... 1 0 */ 799 1.2.6.2 he case 3: /* MSG3 MSG2 MSG1 V --- cnt */ 800 1.2.6.2 he val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT; 801 1.2.6.2 he /* FALLTHROUGH */ 802 1.2.6.2 he 803 1.2.6.2 he case 2: /* MSG2 MSG1 --- V --- cnt */ 804 1.2.6.2 he val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT; 805 1.2.6.2 he /* FALLTHROUGH */ 806 1.2.6.2 he 807 1.2.6.2 he case 1: /* MSG1 --- --- V --- cnt */ 808 1.2.6.2 he val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT; 809 1.2.6.2 he val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen; 810 1.2.6.2 he break; 811 1.2.6.2 he 812 1.2.6.2 he default: 813 1.2.6.2 he break; 814 1.2.6.2 he } 815 1.2.6.2 he return val; 816 1.2.6.2 he } 817 1.2.6.2 he 818 1.2.6.2 he #ifdef NJSC32_DUALEDGE 819 1.2.6.2 he /* add Wide Data Transfer Request to the next Message Out */ 820 1.2.6.2 he static void 821 1.2.6.2 he njsc32_msgout_wdtr(struct njsc32_softc *sc, int width) 822 1.2.6.2 he { 823 1.2.6.2 he 824 1.2.6.2 he njsc32_add_msgout(sc, MSG_EXTENDED); 825 1.2.6.2 he njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN); 826 1.2.6.2 he njsc32_add_msgout(sc, MSG_EXT_WDTR); 827 1.2.6.2 he njsc32_add_msgout(sc, width); 828 1.2.6.2 he } 829 1.2.6.2 he #endif 830 1.2.6.2 he 831 1.2.6.2 he /* add Synchronous Data Transfer Request to the next Message Out */ 832 1.2.6.2 he static void 833 1.2.6.2 he njsc32_msgout_sdtr(struct njsc32_softc *sc, int period, int offset) 834 1.2.6.2 he { 835 1.2.6.2 he 836 1.2.6.2 he njsc32_add_msgout(sc, MSG_EXTENDED); 837 1.2.6.2 he njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN); 838 1.2.6.2 he njsc32_add_msgout(sc, MSG_EXT_SDTR); 839 1.2.6.2 he njsc32_add_msgout(sc, period); 840 1.2.6.2 he njsc32_add_msgout(sc, offset); 841 1.2.6.2 he } 842 1.2.6.2 he 843 1.2.6.2 he static void 844 1.2.6.2 he njsc32_negotiate_xfer(struct njsc32_softc *sc, struct njsc32_target *target) 845 1.2.6.2 he { 846 1.2.6.2 he 847 1.2.6.2 he /* initial negotiation state */ 848 1.2.6.2 he if (target->t_state == NJSC32_TARST_INIT) { 849 1.2.6.2 he #ifdef NJSC32_DUALEDGE 850 1.2.6.2 he if (target->t_flags & NJSC32_TARF_DE) 851 1.2.6.2 he target->t_state = NJSC32_TARST_DE; 852 1.2.6.2 he else 853 1.2.6.2 he #endif 854 1.2.6.2 he if (target->t_flags & NJSC32_TARF_SYNC) 855 1.2.6.2 he target->t_state = NJSC32_TARST_SDTR; 856 1.2.6.2 he else 857 1.2.6.2 he target->t_state = NJSC32_TARST_DONE; 858 1.2.6.2 he } 859 1.2.6.2 he 860 1.2.6.2 he switch (target->t_state) { 861 1.2.6.2 he default: 862 1.2.6.2 he case NJSC32_TARST_INIT: 863 1.2.6.2 he #ifdef DIAGNOSTIC 864 1.2.6.2 he panic("njsc32_negotiate_xfer"); 865 1.2.6.2 he /* NOTREACHED */ 866 1.2.6.2 he #endif 867 1.2.6.2 he /* FALLTHROUGH */ 868 1.2.6.2 he case NJSC32_TARST_DONE: 869 1.2.6.2 he /* no more work */ 870 1.2.6.2 he break; 871 1.2.6.2 he 872 1.2.6.2 he #ifdef NJSC32_DUALEDGE 873 1.2.6.2 he case NJSC32_TARST_DE: 874 1.2.6.2 he njsc32_msgout_wdtr(sc, 0xde /* XXX? */); 875 1.2.6.2 he break; 876 1.2.6.2 he 877 1.2.6.2 he case NJSC32_TARST_WDTR: 878 1.2.6.2 he njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT); 879 1.2.6.2 he break; 880 1.2.6.2 he #endif 881 1.2.6.2 he 882 1.2.6.2 he case NJSC32_TARST_SDTR: 883 1.2.6.2 he njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period, 884 1.2.6.2 he NJSC32_SYNCOFFSET_MAX); 885 1.2.6.2 he break; 886 1.2.6.2 he 887 1.2.6.2 he case NJSC32_TARST_ASYNC: 888 1.2.6.2 he njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC, 889 1.2.6.2 he NJSC32_SYNCOFFSET_ASYNC); 890 1.2.6.2 he break; 891 1.2.6.2 he } 892 1.2.6.2 he } 893 1.2.6.2 he 894 1.2.6.2 he /* turn LED on */ 895 1.2.6.2 he static __inline void 896 1.2.6.2 he njsc32_led_on(struct njsc32_softc *sc) 897 1.2.6.2 he { 898 1.2.6.2 he 899 1.2.6.2 he njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON); 900 1.2.6.2 he } 901 1.2.6.2 he 902 1.2.6.2 he /* turn LED off */ 903 1.2.6.2 he static __inline void 904 1.2.6.2 he njsc32_led_off(struct njsc32_softc *sc) 905 1.2.6.2 he { 906 1.2.6.2 he 907 1.2.6.2 he njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF); 908 1.2.6.2 he } 909 1.2.6.2 he 910 1.2.6.2 he static void 911 1.2.6.2 he njsc32_arbitration_failed(struct njsc32_softc *sc) 912 1.2.6.2 he { 913 1.2.6.2 he struct njsc32_cmd *cmd; 914 1.2.6.2 he 915 1.2.6.2 he if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT) 916 1.2.6.2 he return; 917 1.2.6.2 he 918 1.2.6.2 he if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) 919 1.2.6.2 he callout_stop(&cmd->c_xs->xs_callout); 920 1.2.6.2 he 921 1.2.6.2 he sc->sc_stat = NJSC32_STAT_IDLE; 922 1.2.6.2 he sc->sc_curcmd = NULL; 923 1.2.6.2 he 924 1.2.6.2 he /* the command is no longer active */ 925 1.2.6.2 he if (--sc->sc_nusedcmds == 0) 926 1.2.6.2 he njsc32_led_off(sc); 927 1.2.6.2 he } 928 1.2.6.2 he 929 1.2.6.2 he static __inline void 930 1.2.6.2 he njsc32_cmd_load(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 931 1.2.6.2 he { 932 1.2.6.2 he struct njsc32_target *target; 933 1.2.6.2 he struct scsipi_xfer *xs; 934 1.2.6.2 he int i, control, lun; 935 1.2.6.2 he u_int32_t msgoutreg; 936 1.2.6.2 he #ifdef NJSC32_AUTOPARAM 937 1.2.6.2 he struct njsc32_autoparam *ap; 938 1.2.6.2 he #endif 939 1.2.6.2 he 940 1.2.6.2 he xs = cmd->c_xs; 941 1.2.6.2 he #ifdef NJSC32_AUTOPARAM 942 1.2.6.2 he ap = &sc->sc_cmdpg->dp_ap; 943 1.2.6.2 he #else 944 1.2.6.2 he /* reset CDB pointer */ 945 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR); 946 1.2.6.2 he #endif 947 1.2.6.2 he 948 1.2.6.2 he /* CDB */ 949 1.2.6.2 he TPRINTC(cmd, ("njsc32_cmd_load: CDB")); 950 1.2.6.2 he for (i = 0; i < xs->cmdlen; i++) { 951 1.2.6.2 he #ifdef NJSC32_AUTOPARAM 952 1.2.6.2 he ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i]; 953 1.2.6.2 he #else 954 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA, 955 1.2.6.2 he ((u_int8_t *)xs->cmd)[i]); 956 1.2.6.2 he #endif 957 1.2.6.2 he TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i])); 958 1.2.6.2 he } 959 1.2.6.2 he #ifdef NJSC32_AUTOPARAM /* XXX needed? */ 960 1.2.6.2 he for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++) 961 1.2.6.2 he ap->ap_cdb[i].cdb_data = 0; 962 1.2.6.2 he #endif 963 1.2.6.2 he 964 1.2.6.2 he control = xs->xs_control; 965 1.2.6.2 he 966 1.2.6.2 he /* 967 1.2.6.2 he * Message Out 968 1.2.6.2 he */ 969 1.2.6.2 he njsc32_init_msgout(sc); 970 1.2.6.2 he 971 1.2.6.2 he /* Identify */ 972 1.2.6.2 he lun = xs->xs_periph->periph_lun; 973 1.2.6.2 he njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ? 974 1.2.6.2 he MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1)); 975 1.2.6.2 he 976 1.2.6.2 he /* tagged queueing */ 977 1.2.6.2 he if (control & XS_CTL_TAGMASK) { 978 1.2.6.2 he njsc32_add_msgout(sc, xs->xs_tag_type); 979 1.2.6.2 he njsc32_add_msgout(sc, xs->xs_tag_id); 980 1.2.6.2 he TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id)); 981 1.2.6.2 he } 982 1.2.6.2 he TPRINTF(("\n")); 983 1.2.6.2 he 984 1.2.6.2 he target = cmd->c_target; 985 1.2.6.2 he 986 1.2.6.2 he /* transfer negotiation */ 987 1.2.6.2 he if (control & XS_CTL_REQSENSE) 988 1.2.6.2 he target->t_state = NJSC32_TARST_INIT; 989 1.2.6.2 he njsc32_negotiate_xfer(sc, target); 990 1.2.6.2 he 991 1.2.6.2 he msgoutreg = njsc32_get_auto_msgout(sc); 992 1.2.6.2 he 993 1.2.6.2 he #ifdef NJSC32_AUTOPARAM 994 1.2.6.2 he ap->ap_msgout = htole32(msgoutreg); 995 1.2.6.2 he 996 1.2.6.2 he ap->ap_sync = target->t_sync; 997 1.2.6.2 he ap->ap_ackwidth = target->t_ackwidth; 998 1.2.6.2 he ap->ap_targetid = target->t_targetid; 999 1.2.6.2 he ap->ap_sample = target->t_sample; 1000 1.2.6.2 he 1001 1.2.6.2 he ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 1002 1.2.6.2 he NJSC32_CMD_AUTO_COMMAND_PHASE | 1003 1.2.6.2 he NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1004 1.2.6.2 he NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1005 1.2.6.2 he #ifdef NJSC32_DUALEDGE 1006 1.2.6.2 he ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl); 1007 1.2.6.2 he #else 1008 1.2.6.2 he ap->ap_xferctl = htole16(cmd->c_xferctl); 1009 1.2.6.2 he #endif 1010 1.2.6.2 he ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr); 1011 1.2.6.2 he 1012 1.2.6.2 he /* sync njsc32_autoparam */ 1013 1.2.6.2 he bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1014 1.2.6.2 he offsetof(struct njsc32_dma_page, dp_ap), /* offset */ 1015 1.2.6.2 he sizeof(struct njsc32_autoparam), 1016 1.2.6.2 he BUS_DMASYNC_PREWRITE); 1017 1.2.6.2 he 1018 1.2.6.2 he /* autoparam DMA address */ 1019 1.2.6.2 he njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma); 1020 1.2.6.2 he 1021 1.2.6.2 he /* start command (autoparam) */ 1022 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1023 1.2.6.2 he NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER); 1024 1.2.6.2 he 1025 1.2.6.2 he #else /* not NJSC32_AUTOPARAM */ 1026 1.2.6.2 he 1027 1.2.6.2 he njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg); 1028 1.2.6.2 he 1029 1.2.6.2 he /* load parameters */ 1030 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid); 1031 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1032 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1033 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1034 1.2.6.2 he njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1035 1.2.6.2 he #ifdef NJSC32_DUALEDGE 1036 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1037 1.2.6.2 he cmd->c_xferctl | target->t_xferctl); 1038 1.2.6.2 he #else 1039 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1040 1.2.6.2 he #endif 1041 1.2.6.2 he /* start AutoSCSI */ 1042 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1043 1.2.6.2 he NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE | 1044 1.2.6.2 he NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1045 1.2.6.2 he NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1046 1.2.6.2 he #endif /* not NJSC32_AUTOPARAM */ 1047 1.2.6.2 he } 1048 1.2.6.2 he 1049 1.2.6.2 he /* Note: must be called at splbio() */ 1050 1.2.6.2 he static void 1051 1.2.6.2 he njsc32_start(struct njsc32_softc *sc) 1052 1.2.6.2 he { 1053 1.2.6.2 he struct njsc32_cmd *cmd; 1054 1.2.6.2 he 1055 1.2.6.2 he /* get a command to issue */ 1056 1.2.6.2 he TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) { 1057 1.2.6.2 he if (cmd->c_lu->lu_cmd == NULL && 1058 1.2.6.2 he ((cmd->c_flags & NJSC32_CMD_TAGGED) || 1059 1.2.6.2 he TAILQ_EMPTY(&cmd->c_lu->lu_q))) 1060 1.2.6.2 he break; /* OK, the logical unit is free */ 1061 1.2.6.2 he } 1062 1.2.6.2 he if (!cmd) 1063 1.2.6.2 he goto out; /* no work to do */ 1064 1.2.6.2 he 1065 1.2.6.2 he /* request will always fail if not in bus free phase */ 1066 1.2.6.2 he if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) != 1067 1.2.6.2 he NJSC32_BUSMON_BUSFREE) 1068 1.2.6.2 he goto busy; 1069 1.2.6.2 he 1070 1.2.6.2 he /* clear parity error and enable parity detection */ 1071 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1072 1.2.6.2 he NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1073 1.2.6.2 he 1074 1.2.6.2 he njsc32_cmd_load(sc, cmd); 1075 1.2.6.2 he 1076 1.2.6.2 he if (sc->sc_nusedcmds++ == 0) 1077 1.2.6.2 he njsc32_led_on(sc); 1078 1.2.6.2 he 1079 1.2.6.2 he sc->sc_curcmd = cmd; 1080 1.2.6.2 he sc->sc_stat = NJSC32_STAT_ARBIT; 1081 1.2.6.2 he 1082 1.2.6.2 he if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) { 1083 1.2.6.2 he callout_reset(&cmd->c_xs->xs_callout, 1084 1.2.6.2 he mstohz(cmd->c_xs->timeout), 1085 1.2.6.2 he njsc32_cmdtimeout, cmd); 1086 1.2.6.2 he } 1087 1.2.6.2 he 1088 1.2.6.2 he return; 1089 1.2.6.2 he 1090 1.2.6.2 he busy: /* XXX retry counter */ 1091 1.2.6.2 he TPRINTF(("%s: njsc32_start: busy\n", sc->sc_dev.dv_xname)); 1092 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME); 1093 1.2.6.2 he out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 1094 1.2.6.2 he } 1095 1.2.6.2 he 1096 1.2.6.2 he static void 1097 1.2.6.2 he njsc32_run_xfer(struct njsc32_softc *sc, struct scsipi_xfer *xs) 1098 1.2.6.2 he { 1099 1.2.6.2 he struct scsipi_periph *periph; 1100 1.2.6.2 he int control; 1101 1.2.6.2 he int lun; 1102 1.2.6.2 he struct njsc32_cmd *cmd; 1103 1.2.6.2 he int s, i, error; 1104 1.2.6.2 he 1105 1.2.6.2 he periph = xs->xs_periph; 1106 1.2.6.2 he KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID); 1107 1.2.6.2 he 1108 1.2.6.2 he control = xs->xs_control; 1109 1.2.6.2 he lun = periph->periph_lun; 1110 1.2.6.2 he 1111 1.2.6.2 he /* 1112 1.2.6.2 he * get a free cmd 1113 1.2.6.2 he * (scsipi layer knows the number of cmds, so this shall never fail) 1114 1.2.6.2 he */ 1115 1.2.6.2 he s = splbio(); 1116 1.2.6.2 he cmd = TAILQ_FIRST(&sc->sc_freecmd); 1117 1.2.6.2 he KASSERT(cmd); 1118 1.2.6.2 he TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q); 1119 1.2.6.2 he splx(s); 1120 1.2.6.2 he 1121 1.2.6.2 he /* 1122 1.2.6.2 he * build a request 1123 1.2.6.2 he */ 1124 1.2.6.2 he njsc32_cmd_init(cmd); 1125 1.2.6.2 he cmd->c_xs = xs; 1126 1.2.6.2 he cmd->c_target = &sc->sc_targets[periph->periph_target]; 1127 1.2.6.2 he cmd->c_lu = &cmd->c_target->t_lus[lun]; 1128 1.2.6.2 he 1129 1.2.6.2 he /* tagged queueing */ 1130 1.2.6.2 he if (control & XS_CTL_TAGMASK) { 1131 1.2.6.2 he cmd->c_flags |= NJSC32_CMD_TAGGED; 1132 1.2.6.2 he if (control & XS_CTL_HEAD_TAG) 1133 1.2.6.2 he cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD; 1134 1.2.6.2 he } 1135 1.2.6.2 he 1136 1.2.6.2 he /* map DMA buffer */ 1137 1.2.6.2 he cmd->c_datacnt = xs->datalen; 1138 1.2.6.2 he if (xs->datalen) { 1139 1.2.6.2 he /* Is XS_CTL_DATA_UIO ever used anywhere? */ 1140 1.2.6.2 he KASSERT((control & XS_CTL_DATA_UIO) == 0); 1141 1.2.6.2 he 1142 1.2.6.2 he error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer, 1143 1.2.6.2 he xs->data, xs->datalen, NULL, 1144 1.2.6.2 he ((control & XS_CTL_NOSLEEP) ? 1145 1.2.6.2 he BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 1146 1.2.6.2 he BUS_DMA_STREAMING | 1147 1.2.6.2 he ((control & XS_CTL_DATA_IN) ? 1148 1.2.6.2 he BUS_DMA_READ : BUS_DMA_WRITE)); 1149 1.2.6.2 he 1150 1.2.6.2 he switch (error) { 1151 1.2.6.2 he case 0: 1152 1.2.6.2 he break; 1153 1.2.6.2 he case ENOMEM: 1154 1.2.6.2 he case EAGAIN: 1155 1.2.6.2 he xs->error = XS_RESOURCE_SHORTAGE; 1156 1.2.6.2 he goto map_failed; 1157 1.2.6.2 he default: 1158 1.2.6.2 he xs->error = XS_DRIVER_STUFFUP; 1159 1.2.6.2 he map_failed: 1160 1.2.6.2 he printf("%s: njsc32_run_xfer: map failed, error %d\n", 1161 1.2.6.2 he sc->sc_dev.dv_xname, error); 1162 1.2.6.2 he /* put it back to free command list */ 1163 1.2.6.2 he s = splbio(); 1164 1.2.6.2 he TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1165 1.2.6.2 he splx(s); 1166 1.2.6.2 he /* abort this transfer */ 1167 1.2.6.2 he scsipi_done(xs); 1168 1.2.6.2 he return; 1169 1.2.6.2 he } 1170 1.2.6.2 he 1171 1.2.6.2 he bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1172 1.2.6.2 he 0, cmd->c_dmamap_xfer->dm_mapsize, 1173 1.2.6.2 he (control & XS_CTL_DATA_IN) ? 1174 1.2.6.2 he BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1175 1.2.6.2 he 1176 1.2.6.2 he for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) { 1177 1.2.6.2 he cmd->c_sgt[i].sg_addr = 1178 1.2.6.2 he htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr); 1179 1.2.6.2 he cmd->c_sgt[i].sg_len = 1180 1.2.6.2 he htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len); 1181 1.2.6.2 he } 1182 1.2.6.2 he /* end mark */ 1183 1.2.6.2 he cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK); 1184 1.2.6.2 he 1185 1.2.6.2 he bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1186 1.2.6.2 he (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1187 1.2.6.2 he NJSC32_SIZE_SGT, 1188 1.2.6.2 he BUS_DMASYNC_PREWRITE); 1189 1.2.6.2 he 1190 1.2.6.2 he cmd->c_flags |= NJSC32_CMD_DMA_MAPPED; 1191 1.2.6.2 he 1192 1.2.6.2 he /* enable transfer */ 1193 1.2.6.2 he cmd->c_xferctl = 1194 1.2.6.2 he NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START | 1195 1.2.6.2 he NJSC32_XFR_ALL_COUNT_CLR; 1196 1.2.6.2 he 1197 1.2.6.2 he /* XXX How can we specify the DMA direction? */ 1198 1.2.6.2 he 1199 1.2.6.2 he #if 0 /* faster write mode? (doesn't work) */ 1200 1.2.6.2 he if ((control & XS_CTL_DATA_IN) == 0) 1201 1.2.6.2 he cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE; 1202 1.2.6.2 he #endif 1203 1.2.6.2 he } else { 1204 1.2.6.2 he /* no data transfer */ 1205 1.2.6.2 he cmd->c_xferctl = 0; 1206 1.2.6.2 he } 1207 1.2.6.2 he 1208 1.2.6.2 he /* queue request */ 1209 1.2.6.2 he s = splbio(); 1210 1.2.6.2 he TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q); 1211 1.2.6.2 he 1212 1.2.6.2 he /* start the controller if idle */ 1213 1.2.6.2 he if (sc->sc_stat == NJSC32_STAT_IDLE) 1214 1.2.6.2 he njsc32_start(sc); 1215 1.2.6.2 he 1216 1.2.6.2 he splx(s); 1217 1.2.6.2 he 1218 1.2.6.2 he if (control & XS_CTL_POLL) { 1219 1.2.6.2 he /* wait for completion */ 1220 1.2.6.2 he /* XXX should handle timeout? */ 1221 1.2.6.2 he while ((xs->xs_status & XS_STS_DONE) == 0) { 1222 1.2.6.2 he delay(1000); 1223 1.2.6.2 he njsc32_intr(sc); 1224 1.2.6.2 he } 1225 1.2.6.2 he } 1226 1.2.6.2 he } 1227 1.2.6.2 he 1228 1.2.6.2 he static void 1229 1.2.6.2 he njsc32_end_cmd(struct njsc32_softc *sc, struct njsc32_cmd *cmd, 1230 1.2.6.2 he scsipi_xfer_result_t result) 1231 1.2.6.2 he { 1232 1.2.6.2 he struct scsipi_xfer *xs; 1233 1.2.6.2 he int s; 1234 1.2.6.2 he #ifdef DIAGNOSTIC 1235 1.2.6.2 he struct njsc32_cmd *c; 1236 1.2.6.2 he #endif 1237 1.2.6.2 he 1238 1.2.6.2 he KASSERT(cmd); 1239 1.2.6.2 he 1240 1.2.6.2 he #ifdef DIAGNOSTIC 1241 1.2.6.2 he s = splbio(); 1242 1.2.6.2 he TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) { 1243 1.2.6.2 he if (cmd == c) 1244 1.2.6.2 he panic("njsc32_end_cmd: already in free list"); 1245 1.2.6.2 he } 1246 1.2.6.2 he splx(s); 1247 1.2.6.2 he #endif 1248 1.2.6.2 he xs = cmd->c_xs; 1249 1.2.6.2 he 1250 1.2.6.2 he if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) { 1251 1.2.6.2 he if (cmd->c_datacnt) { 1252 1.2.6.2 he bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1253 1.2.6.2 he 0, cmd->c_dmamap_xfer->dm_mapsize, 1254 1.2.6.2 he (xs->xs_control & XS_CTL_DATA_IN) ? 1255 1.2.6.2 he BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1256 1.2.6.2 he 1257 1.2.6.2 he bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1258 1.2.6.2 he (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, 1259 1.2.6.2 he NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE); 1260 1.2.6.2 he } 1261 1.2.6.2 he 1262 1.2.6.2 he bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer); 1263 1.2.6.2 he cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED; 1264 1.2.6.2 he } 1265 1.2.6.2 he 1266 1.2.6.2 he s = splbio(); 1267 1.2.6.2 he if ((xs->xs_control & XS_CTL_POLL) == 0) 1268 1.2.6.2 he callout_stop(&xs->xs_callout); 1269 1.2.6.2 he 1270 1.2.6.2 he TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1271 1.2.6.2 he splx(s); 1272 1.2.6.2 he 1273 1.2.6.2 he xs->error = result; 1274 1.2.6.2 he scsipi_done(xs); 1275 1.2.6.2 he 1276 1.2.6.2 he if (--sc->sc_nusedcmds == 0) 1277 1.2.6.2 he njsc32_led_off(sc); 1278 1.2.6.2 he } 1279 1.2.6.2 he 1280 1.2.6.2 he /* 1281 1.2.6.2 he * request from scsipi layer 1282 1.2.6.2 he */ 1283 1.2.6.2 he static void 1284 1.2.6.2 he njsc32_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1285 1.2.6.2 he void *arg) 1286 1.2.6.2 he { 1287 1.2.6.2 he struct njsc32_softc *sc; 1288 1.2.6.2 he struct scsipi_xfer_mode *xm; 1289 1.2.6.2 he struct njsc32_target *target; 1290 1.2.6.2 he 1291 1.2.6.2 he sc = (void *)chan->chan_adapter->adapt_dev; 1292 1.2.6.2 he 1293 1.2.6.2 he switch (req) { 1294 1.2.6.2 he case ADAPTER_REQ_RUN_XFER: 1295 1.2.6.2 he njsc32_run_xfer(sc, arg); 1296 1.2.6.2 he break; 1297 1.2.6.2 he 1298 1.2.6.2 he case ADAPTER_REQ_GROW_RESOURCES: 1299 1.2.6.2 he /* not supported */ 1300 1.2.6.2 he break; 1301 1.2.6.2 he 1302 1.2.6.2 he case ADAPTER_REQ_SET_XFER_MODE: 1303 1.2.6.2 he xm = arg; 1304 1.2.6.2 he target = &sc->sc_targets[xm->xm_target]; 1305 1.2.6.2 he 1306 1.2.6.2 he target->t_flags = 0; 1307 1.2.6.2 he if (xm->xm_mode & PERIPH_CAP_TQING) 1308 1.2.6.2 he target->t_flags |= NJSC32_TARF_TAG; 1309 1.2.6.2 he if (xm->xm_mode & PERIPH_CAP_SYNC) { 1310 1.2.6.2 he target->t_flags |= NJSC32_TARF_SYNC; 1311 1.2.6.2 he #ifdef NJSC32_DUALEDGE 1312 1.2.6.2 he if (sc->sc_model & NJSC32_FLAG_DUALEDGE) 1313 1.2.6.2 he target->t_flags |= NJSC32_TARF_DE; 1314 1.2.6.2 he #endif 1315 1.2.6.2 he } 1316 1.2.6.2 he #ifdef NJSC32_DUALEDGE 1317 1.2.6.2 he target->t_xferctl = 0; 1318 1.2.6.2 he #endif 1319 1.2.6.2 he target->t_state = NJSC32_TARST_INIT; 1320 1.2.6.2 he njsc32_target_async(sc, target); 1321 1.2.6.2 he 1322 1.2.6.2 he break; 1323 1.2.6.2 he default: 1324 1.2.6.2 he break; 1325 1.2.6.2 he } 1326 1.2.6.2 he } 1327 1.2.6.2 he 1328 1.2.6.2 he static void 1329 1.2.6.2 he njsc32_scsipi_minphys(struct buf *bp) 1330 1.2.6.2 he { 1331 1.2.6.2 he 1332 1.2.6.2 he if (bp->b_bcount > NJSC32_MAX_XFER) 1333 1.2.6.2 he bp->b_bcount = NJSC32_MAX_XFER; 1334 1.2.6.2 he minphys(bp); 1335 1.2.6.2 he } 1336 1.2.6.2 he 1337 1.2.6.2 he static void 1338 1.2.6.2 he njsc32_reset_bus(struct njsc32_softc *sc) 1339 1.2.6.2 he { 1340 1.2.6.2 he int s; 1341 1.2.6.2 he 1342 1.2.6.2 he DPRINTF(("%s: njsc32_reset_bus:\n", sc->sc_dev.dv_xname)); 1343 1.2.6.2 he 1344 1.2.6.2 he /* SCSI bus reset */ 1345 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST); 1346 1.2.6.2 he delay(NJSC32_RESET_HOLD_TIME); 1347 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0); 1348 1.2.6.2 he 1349 1.2.6.2 he /* clear transfer */ 1350 1.2.6.2 he s = splbio(); 1351 1.2.6.2 he njsc32_reset_detected(sc); 1352 1.2.6.2 he splx(s); 1353 1.2.6.2 he } 1354 1.2.6.2 he 1355 1.2.6.2 he /* 1356 1.2.6.2 he * clear running/disconnected commands 1357 1.2.6.2 he */ 1358 1.2.6.2 he static void 1359 1.2.6.2 he njsc32_clear_cmds(struct njsc32_softc *sc, scsipi_xfer_result_t cmdresult) 1360 1.2.6.2 he { 1361 1.2.6.2 he struct njsc32_cmd *cmd; 1362 1.2.6.2 he int id, lun; 1363 1.2.6.2 he struct njsc32_lu *lu; 1364 1.2.6.2 he 1365 1.2.6.2 he njsc32_arbitration_failed(sc); 1366 1.2.6.2 he 1367 1.2.6.2 he /* clear current transfer */ 1368 1.2.6.2 he if ((cmd = sc->sc_curcmd) != NULL) { 1369 1.2.6.2 he sc->sc_curcmd = NULL; 1370 1.2.6.2 he njsc32_end_cmd(sc, cmd, cmdresult); 1371 1.2.6.2 he } 1372 1.2.6.2 he 1373 1.2.6.2 he /* clear disconnected transfers */ 1374 1.2.6.2 he for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 1375 1.2.6.2 he for (lun = 0; lun < NJSC32_NLU; lun++) { 1376 1.2.6.2 he lu = &sc->sc_targets[id].t_lus[lun]; 1377 1.2.6.2 he 1378 1.2.6.2 he if ((cmd = lu->lu_cmd) != NULL) { 1379 1.2.6.2 he lu->lu_cmd = NULL; 1380 1.2.6.2 he njsc32_end_cmd(sc, cmd, cmdresult); 1381 1.2.6.2 he } 1382 1.2.6.2 he while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) { 1383 1.2.6.2 he TAILQ_REMOVE(&lu->lu_q, cmd, c_q); 1384 1.2.6.2 he njsc32_end_cmd(sc, cmd, cmdresult); 1385 1.2.6.2 he } 1386 1.2.6.2 he } 1387 1.2.6.2 he } 1388 1.2.6.2 he } 1389 1.2.6.2 he 1390 1.2.6.2 he static void 1391 1.2.6.2 he njsc32_reset_detected(struct njsc32_softc *sc) 1392 1.2.6.2 he { 1393 1.2.6.2 he 1394 1.2.6.2 he njsc32_clear_cmds(sc, XS_RESET); 1395 1.2.6.2 he njsc32_init_targets(sc); 1396 1.2.6.2 he sc->sc_stat = NJSC32_STAT_IDLE; 1397 1.2.6.2 he KASSERT(sc->sc_nusedcmds == 0); 1398 1.2.6.2 he scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL); 1399 1.2.6.2 he } 1400 1.2.6.2 he 1401 1.2.6.2 he static int 1402 1.2.6.2 he njsc32_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd, caddr_t addr, 1403 1.2.6.2 he int flag, struct proc *p) 1404 1.2.6.2 he { 1405 1.2.6.2 he struct njsc32_softc *sc = (void *)chan->chan_adapter->adapt_dev; 1406 1.2.6.2 he 1407 1.2.6.2 he switch (cmd) { 1408 1.2.6.2 he case SCBUSIORESET: 1409 1.2.6.2 he njsc32_init(sc, 0); 1410 1.2.6.2 he return 0; 1411 1.2.6.2 he default: 1412 1.2.6.2 he break; 1413 1.2.6.2 he } 1414 1.2.6.2 he 1415 1.2.6.2 he return ENOTTY; 1416 1.2.6.2 he } 1417 1.2.6.2 he 1418 1.2.6.2 he /* 1419 1.2.6.2 he * set current data pointer 1420 1.2.6.2 he */ 1421 1.2.6.2 he static __inline void 1422 1.2.6.2 he njsc32_set_cur_ptr(struct njsc32_cmd *cmd, u_int32_t pos) 1423 1.2.6.2 he { 1424 1.2.6.2 he 1425 1.2.6.2 he /* new current data pointer */ 1426 1.2.6.2 he cmd->c_dp_cur = pos; 1427 1.2.6.2 he 1428 1.2.6.2 he /* update number of bytes transferred */ 1429 1.2.6.2 he if (pos > cmd->c_dp_max) 1430 1.2.6.2 he cmd->c_dp_max = pos; 1431 1.2.6.2 he } 1432 1.2.6.2 he 1433 1.2.6.2 he /* 1434 1.2.6.2 he * set data pointer for the next transfer 1435 1.2.6.2 he */ 1436 1.2.6.2 he static void 1437 1.2.6.2 he njsc32_set_ptr(struct njsc32_softc *sc, struct njsc32_cmd *cmd, u_int32_t pos) 1438 1.2.6.2 he { 1439 1.2.6.2 he struct njsc32_sgtable *sg; 1440 1.2.6.2 he unsigned sgte; 1441 1.2.6.2 he u_int32_t len; 1442 1.2.6.2 he 1443 1.2.6.2 he /* set current pointer */ 1444 1.2.6.2 he njsc32_set_cur_ptr(cmd, pos); 1445 1.2.6.2 he 1446 1.2.6.2 he /* undo previous fix if any */ 1447 1.2.6.2 he if (cmd->c_sgfixcnt != 0) { 1448 1.2.6.2 he sg = &cmd->c_sgt[cmd->c_sgoffset]; 1449 1.2.6.2 he sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt); 1450 1.2.6.2 he sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt); 1451 1.2.6.2 he cmd->c_sgfixcnt = 0; 1452 1.2.6.2 he } 1453 1.2.6.2 he 1454 1.2.6.2 he if (pos >= cmd->c_datacnt) { 1455 1.2.6.2 he /* transfer done */ 1456 1.2.6.2 he #if 1 /*def DIAGNOSTIC*/ 1457 1.2.6.2 he if (pos > cmd->c_datacnt) 1458 1.2.6.2 he printf("%s: pos %u too large\n", 1459 1.2.6.2 he sc->sc_dev.dv_xname, pos - cmd->c_datacnt); 1460 1.2.6.2 he #endif 1461 1.2.6.2 he cmd->c_xferctl = 0; /* XXX correct? */ 1462 1.2.6.2 he 1463 1.2.6.2 he return; 1464 1.2.6.2 he } 1465 1.2.6.2 he 1466 1.2.6.2 he for (sgte = 0, sg = cmd->c_sgt; 1467 1.2.6.2 he sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) { 1468 1.2.6.2 he len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK; 1469 1.2.6.2 he if (pos < len) { 1470 1.2.6.2 he sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos); 1471 1.2.6.2 he sg->sg_len = htole32(le32toh(sg->sg_len) - pos); 1472 1.2.6.2 he cmd->c_sgfixcnt = pos; 1473 1.2.6.2 he break; 1474 1.2.6.2 he } 1475 1.2.6.2 he pos -= len; 1476 1.2.6.2 he #ifdef DIAGNOSTIC 1477 1.2.6.2 he if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) { 1478 1.2.6.2 he panic("njsc32_set_ptr: bad pos"); 1479 1.2.6.2 he } 1480 1.2.6.2 he #endif 1481 1.2.6.2 he } 1482 1.2.6.2 he #ifdef DIAGNOSTIC 1483 1.2.6.2 he if (sgte >= NJSC32_NUM_SG) 1484 1.2.6.2 he panic("njsc32_set_ptr: bad sg"); 1485 1.2.6.2 he #endif 1486 1.2.6.2 he if (cmd->c_sgoffset != sgte) { 1487 1.2.6.2 he cmd->c_sgoffset = sgte; 1488 1.2.6.2 he cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte); 1489 1.2.6.2 he } 1490 1.2.6.2 he 1491 1.2.6.2 he /* XXX overkill */ 1492 1.2.6.2 he bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1493 1.2.6.2 he (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1494 1.2.6.2 he NJSC32_SIZE_SGT, 1495 1.2.6.2 he BUS_DMASYNC_PREWRITE); 1496 1.2.6.2 he } 1497 1.2.6.2 he 1498 1.2.6.2 he /* 1499 1.2.6.2 he * save data pointer 1500 1.2.6.2 he */ 1501 1.2.6.2 he static __inline void 1502 1.2.6.2 he njsc32_save_ptr(struct njsc32_cmd *cmd) 1503 1.2.6.2 he { 1504 1.2.6.2 he 1505 1.2.6.2 he cmd->c_dp_saved = cmd->c_dp_cur; 1506 1.2.6.2 he } 1507 1.2.6.2 he 1508 1.2.6.2 he static void 1509 1.2.6.2 he njsc32_assert_ack(struct njsc32_softc *sc) 1510 1.2.6.2 he { 1511 1.2.6.2 he u_int8_t reg; 1512 1.2.6.2 he 1513 1.2.6.2 he reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1514 1.2.6.2 he reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE; 1515 1.2.6.2 he #if 0 /* needed? */ 1516 1.2.6.2 he reg |= NJSC32_SBCTL_AUTODIRECTION; 1517 1.2.6.2 he #endif 1518 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1519 1.2.6.2 he } 1520 1.2.6.2 he 1521 1.2.6.2 he static void 1522 1.2.6.2 he njsc32_negate_ack(struct njsc32_softc *sc) 1523 1.2.6.2 he { 1524 1.2.6.2 he u_int8_t reg; 1525 1.2.6.2 he 1526 1.2.6.2 he reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1527 1.2.6.2 he #if 0 /* needed? */ 1528 1.2.6.2 he reg |= NJSC32_SBCTL_ACK_ENABLE; 1529 1.2.6.2 he reg |= NJSC32_SBCTL_AUTODIRECTION; 1530 1.2.6.2 he #endif 1531 1.2.6.2 he reg &= ~NJSC32_SBCTL_ACK; 1532 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1533 1.2.6.2 he } 1534 1.2.6.2 he 1535 1.2.6.2 he static void 1536 1.2.6.2 he njsc32_wait_req_negate(struct njsc32_softc *sc) 1537 1.2.6.2 he { 1538 1.2.6.2 he int cnt; 1539 1.2.6.2 he 1540 1.2.6.2 he for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) { 1541 1.2.6.2 he if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 1542 1.2.6.2 he NJSC32_BUSMON_REQ) == 0) 1543 1.2.6.2 he return; 1544 1.2.6.2 he delay(1); 1545 1.2.6.2 he } 1546 1.2.6.2 he printf("%s: njsc32_wait_req_negate: timed out\n", sc->sc_dev.dv_xname); 1547 1.2.6.2 he } 1548 1.2.6.2 he 1549 1.2.6.2 he static void 1550 1.2.6.2 he njsc32_reconnect(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 1551 1.2.6.2 he { 1552 1.2.6.2 he struct scsipi_xfer *xs; 1553 1.2.6.2 he 1554 1.2.6.2 he xs = cmd->c_xs; 1555 1.2.6.2 he if ((xs->xs_control & XS_CTL_POLL) == 0) { 1556 1.2.6.2 he callout_stop(&xs->xs_callout); 1557 1.2.6.2 he callout_reset(&xs->xs_callout, 1558 1.2.6.2 he mstohz(xs->timeout), 1559 1.2.6.2 he njsc32_cmdtimeout, cmd); 1560 1.2.6.2 he } 1561 1.2.6.2 he 1562 1.2.6.2 he /* Reconnection implies Restore Pointers */ 1563 1.2.6.2 he njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1564 1.2.6.2 he } 1565 1.2.6.2 he 1566 1.2.6.2 he static enum njsc32_reselstat 1567 1.2.6.2 he njsc32_resel_identify(struct njsc32_softc *sc, int lun, 1568 1.2.6.2 he struct njsc32_cmd **pcmd) 1569 1.2.6.2 he { 1570 1.2.6.2 he int targetid; 1571 1.2.6.2 he struct njsc32_lu *plu; 1572 1.2.6.2 he struct njsc32_cmd *cmd; 1573 1.2.6.2 he 1574 1.2.6.2 he switch (sc->sc_stat) { 1575 1.2.6.2 he case NJSC32_STAT_RESEL: 1576 1.2.6.2 he break; /* OK */ 1577 1.2.6.2 he 1578 1.2.6.2 he case NJSC32_STAT_RESEL_LUN: 1579 1.2.6.2 he case NJSC32_STAT_RECONNECT: 1580 1.2.6.2 he /* 1581 1.2.6.2 he * accept and ignore if the LUN is the same as the current one, 1582 1.2.6.2 he * reject otherwise. 1583 1.2.6.2 he */ 1584 1.2.6.2 he return sc->sc_resellun == lun ? 1585 1.2.6.2 he NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR; 1586 1.2.6.2 he 1587 1.2.6.2 he default: 1588 1.2.6.2 he printf("%s: njsc32_resel_identify: not in reselection\n", 1589 1.2.6.2 he sc->sc_dev.dv_xname); 1590 1.2.6.2 he return NJSC32_RESEL_ERROR; 1591 1.2.6.2 he } 1592 1.2.6.2 he 1593 1.2.6.2 he targetid = sc->sc_reselid; 1594 1.2.6.2 he TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n", 1595 1.2.6.2 he sc->sc_dev.dv_xname, lun)); 1596 1.2.6.2 he 1597 1.2.6.2 he if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU) 1598 1.2.6.2 he return NJSC32_RESEL_ERROR; 1599 1.2.6.2 he 1600 1.2.6.2 he sc->sc_resellun = lun; 1601 1.2.6.2 he plu = &sc->sc_targets[targetid].t_lus[lun]; 1602 1.2.6.2 he 1603 1.2.6.2 he if ((cmd = plu->lu_cmd) != NULL) { 1604 1.2.6.2 he sc->sc_stat = NJSC32_STAT_RECONNECT; 1605 1.2.6.2 he plu->lu_cmd = NULL; 1606 1.2.6.2 he *pcmd = cmd; 1607 1.2.6.2 he TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n")); 1608 1.2.6.2 he njsc32_reconnect(sc, cmd); 1609 1.2.6.2 he return NJSC32_RESEL_COMPLETE; 1610 1.2.6.2 he } else if (!TAILQ_EMPTY(&plu->lu_q)) { 1611 1.2.6.2 he /* wait for tag */ 1612 1.2.6.2 he sc->sc_stat = NJSC32_STAT_RESEL_LUN; 1613 1.2.6.2 he return NJSC32_RESEL_THROUGH; 1614 1.2.6.2 he } 1615 1.2.6.2 he 1616 1.2.6.2 he /* no disconnected commands */ 1617 1.2.6.2 he return NJSC32_RESEL_ERROR; 1618 1.2.6.2 he } 1619 1.2.6.2 he 1620 1.2.6.2 he static enum njsc32_reselstat 1621 1.2.6.2 he njsc32_resel_tag(struct njsc32_softc *sc, int tag, struct njsc32_cmd **pcmd) 1622 1.2.6.2 he { 1623 1.2.6.2 he struct njsc32_cmd_head *head; 1624 1.2.6.2 he struct njsc32_cmd *cmd; 1625 1.2.6.2 he 1626 1.2.6.2 he TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n", 1627 1.2.6.2 he sc->sc_dev.dv_xname, tag)); 1628 1.2.6.2 he if (sc->sc_stat != NJSC32_STAT_RESEL_LUN) 1629 1.2.6.2 he return NJSC32_RESEL_ERROR; 1630 1.2.6.2 he 1631 1.2.6.2 he head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q; 1632 1.2.6.2 he 1633 1.2.6.2 he /* XXX slow? */ 1634 1.2.6.2 he /* search for the command of the tag */ 1635 1.2.6.2 he TAILQ_FOREACH(cmd, head, c_q) { 1636 1.2.6.2 he if (cmd->c_xs->xs_tag_id == tag) { 1637 1.2.6.2 he sc->sc_stat = NJSC32_STAT_RECONNECT; 1638 1.2.6.2 he TAILQ_REMOVE(head, cmd, c_q); 1639 1.2.6.2 he *pcmd = cmd; 1640 1.2.6.2 he TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n")); 1641 1.2.6.2 he njsc32_reconnect(sc, cmd); 1642 1.2.6.2 he return NJSC32_RESEL_COMPLETE; 1643 1.2.6.2 he } 1644 1.2.6.2 he } 1645 1.2.6.2 he 1646 1.2.6.2 he /* no disconnected commands */ 1647 1.2.6.2 he return NJSC32_RESEL_ERROR; 1648 1.2.6.2 he } 1649 1.2.6.2 he 1650 1.2.6.2 he /* 1651 1.2.6.2 he * Reload parameters and restart AutoSCSI. 1652 1.2.6.2 he * 1653 1.2.6.2 he * XXX autoparam doesn't work as expected and we can't use it here. 1654 1.2.6.2 he */ 1655 1.2.6.2 he static void 1656 1.2.6.2 he njsc32_cmd_reload(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int cctl) 1657 1.2.6.2 he { 1658 1.2.6.2 he struct njsc32_target *target; 1659 1.2.6.2 he 1660 1.2.6.2 he target = cmd->c_target; 1661 1.2.6.2 he 1662 1.2.6.2 he /* clear parity error and enable parity detection */ 1663 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1664 1.2.6.2 he NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1665 1.2.6.2 he 1666 1.2.6.2 he /* load parameters */ 1667 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1668 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1669 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1670 1.2.6.2 he njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1671 1.2.6.2 he #ifdef NJSC32_DUALEDGE 1672 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1673 1.2.6.2 he cmd->c_xferctl | target->t_xferctl); 1674 1.2.6.2 he #else 1675 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1676 1.2.6.2 he #endif 1677 1.2.6.2 he /* start AutoSCSI */ 1678 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 1679 1.2.6.2 he 1680 1.2.6.2 he sc->sc_curcmd = cmd; 1681 1.2.6.2 he } 1682 1.2.6.2 he 1683 1.2.6.2 he static void 1684 1.2.6.2 he njsc32_update_xfer_mode(struct njsc32_softc *sc, struct njsc32_target *target) 1685 1.2.6.2 he { 1686 1.2.6.2 he struct scsipi_xfer_mode xm; 1687 1.2.6.2 he 1688 1.2.6.2 he xm.xm_target = target - sc->sc_targets; /* target ID */ 1689 1.2.6.2 he xm.xm_mode = 0; 1690 1.2.6.2 he xm.xm_period = target->t_syncperiod; 1691 1.2.6.2 he xm.xm_offset = target->t_syncoffset; 1692 1.2.6.2 he if (xm.xm_offset != 0) 1693 1.2.6.2 he xm.xm_mode |= PERIPH_CAP_SYNC; 1694 1.2.6.2 he if (target->t_flags & NJSC32_TARF_TAG) 1695 1.2.6.2 he xm.xm_mode |= PERIPH_CAP_TQING; 1696 1.2.6.2 he 1697 1.2.6.2 he scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 1698 1.2.6.2 he } 1699 1.2.6.2 he 1700 1.2.6.2 he static void 1701 1.2.6.2 he njsc32_msgin(struct njsc32_softc *sc) 1702 1.2.6.2 he { 1703 1.2.6.2 he u_int8_t msg0, msg; 1704 1.2.6.2 he int msgcnt; 1705 1.2.6.2 he struct njsc32_cmd *cmd; 1706 1.2.6.2 he enum njsc32_reselstat rstat; 1707 1.2.6.2 he int cctl = 0; 1708 1.2.6.2 he u_int32_t ptr; /* unsigned type ensures 2-complement calculation */ 1709 1.2.6.2 he u_int32_t msgout = 0; 1710 1.2.6.2 he boolean_t reload_params = FALSE; 1711 1.2.6.2 he struct njsc32_target *target; 1712 1.2.6.2 he int idx, period, offset; 1713 1.2.6.2 he 1714 1.2.6.2 he /* 1715 1.2.6.2 he * we are in Message In, so the previous Message Out should have 1716 1.2.6.2 he * been done. 1717 1.2.6.2 he */ 1718 1.2.6.2 he njsc32_init_msgout(sc); 1719 1.2.6.2 he 1720 1.2.6.2 he /* get a byte of Message In */ 1721 1.2.6.2 he msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN); 1722 1.2.6.2 he TPRINTF(("%s: njsc32_msgin: got %#x\n", sc->sc_dev.dv_xname, msg)); 1723 1.2.6.2 he if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN) 1724 1.2.6.2 he sc->sc_msginbuf[sc->sc_msgincnt] = msg; 1725 1.2.6.2 he 1726 1.2.6.2 he njsc32_assert_ack(sc); 1727 1.2.6.2 he 1728 1.2.6.2 he msg0 = sc->sc_msginbuf[0]; 1729 1.2.6.2 he cmd = sc->sc_curcmd; 1730 1.2.6.2 he 1731 1.2.6.2 he /* check for parity error */ 1732 1.2.6.2 he if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 1733 1.2.6.2 he NJSC32_PARITYSTATUS_ERROR_LSB) { 1734 1.2.6.2 he 1735 1.2.6.2 he printf("%s: msgin: parity error\n", sc->sc_dev.dv_xname); 1736 1.2.6.2 he 1737 1.2.6.2 he /* clear parity error */ 1738 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1739 1.2.6.2 he NJSC32_PARITYCTL_CHECK_ENABLE | 1740 1.2.6.2 he NJSC32_PARITYCTL_CLEAR_ERROR); 1741 1.2.6.2 he 1742 1.2.6.2 he /* respond as Message Parity Error */ 1743 1.2.6.2 he njsc32_add_msgout(sc, MSG_PARITY_ERROR); 1744 1.2.6.2 he 1745 1.2.6.2 he /* clear Message In */ 1746 1.2.6.2 he sc->sc_msgincnt = 0; 1747 1.2.6.2 he goto reply; 1748 1.2.6.2 he } 1749 1.2.6.2 he 1750 1.2.6.2 he #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0) 1751 1.2.6.2 he #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0) 1752 1.2.6.2 he if (MSG_ISIDENTIFY(msg0)) { 1753 1.2.6.2 he /* 1754 1.2.6.2 he * Got Identify message from target. 1755 1.2.6.2 he */ 1756 1.2.6.2 he #define MSG_IDENTIFY_LUNMASK 0x3f 1757 1.2.6.2 he if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG || 1758 1.2.6.2 he (rstat = njsc32_resel_identify(sc, msg0 & 1759 1.2.6.2 he MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) { 1760 1.2.6.2 he /* 1761 1.2.6.2 he * invalid Identify -> Reject 1762 1.2.6.2 he */ 1763 1.2.6.2 he goto reject; 1764 1.2.6.2 he } 1765 1.2.6.2 he if (rstat == NJSC32_RESEL_COMPLETE) 1766 1.2.6.2 he reload_params = TRUE; 1767 1.2.6.2 he MSGCOMPLETE; 1768 1.2.6.2 he } 1769 1.2.6.2 he 1770 1.2.6.2 he if (msg0 == MSG_SIMPLE_Q_TAG) { 1771 1.2.6.2 he if (msgcnt == 0) 1772 1.2.6.2 he WAITNEXTMSG; 1773 1.2.6.2 he 1774 1.2.6.2 he /* got whole message */ 1775 1.2.6.2 he sc->sc_msgincnt = 0; 1776 1.2.6.2 he 1777 1.2.6.2 he if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd)) 1778 1.2.6.2 he == NJSC32_RESEL_ERROR) { 1779 1.2.6.2 he /* 1780 1.2.6.2 he * invalid Simple Queue Tag -> Abort Tag 1781 1.2.6.2 he */ 1782 1.2.6.2 he printf("%s: msgin: invalid tag\n", sc->sc_dev.dv_xname); 1783 1.2.6.2 he njsc32_add_msgout(sc, MSG_ABORT_TAG); 1784 1.2.6.2 he goto reply; 1785 1.2.6.2 he } 1786 1.2.6.2 he if (rstat == NJSC32_RESEL_COMPLETE) 1787 1.2.6.2 he reload_params = TRUE; 1788 1.2.6.2 he MSGCOMPLETE; 1789 1.2.6.2 he } 1790 1.2.6.2 he 1791 1.2.6.2 he /* I_T_L or I_T_L_Q nexus should be established now */ 1792 1.2.6.2 he if (cmd == NULL) { 1793 1.2.6.2 he printf("%s: msgin %#x without nexus -- sending abort\n", 1794 1.2.6.2 he sc->sc_dev.dv_xname, msg0); 1795 1.2.6.2 he njsc32_add_msgout(sc, MSG_ABORT); 1796 1.2.6.2 he goto reply; 1797 1.2.6.2 he } 1798 1.2.6.2 he 1799 1.2.6.2 he /* 1800 1.2.6.2 he * extended message 1801 1.2.6.2 he * 0x01 <length (0 stands for 256)> <length bytes> 1802 1.2.6.2 he * (<code> [<parameter> ...]) 1803 1.2.6.2 he */ 1804 1.2.6.2 he #define EXTLENOFF 1 1805 1.2.6.2 he #define EXTCODEOFF 2 1806 1.2.6.2 he if (msg0 == MSG_EXTENDED) { 1807 1.2.6.2 he if (msgcnt < EXTLENOFF || 1808 1.2.6.2 he msgcnt < EXTLENOFF + 1 + 1809 1.2.6.2 he (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1)) 1810 1.2.6.2 he WAITNEXTMSG; 1811 1.2.6.2 he 1812 1.2.6.2 he /* got whole message */ 1813 1.2.6.2 he sc->sc_msgincnt = 0; 1814 1.2.6.2 he 1815 1.2.6.2 he switch (sc->sc_msginbuf[EXTCODEOFF]) { 1816 1.2.6.2 he case 0: /* Modify Data Pointer */ 1817 1.2.6.2 he if (msgcnt != 5 + EXTCODEOFF - 1) 1818 1.2.6.2 he break; 1819 1.2.6.2 he /* 1820 1.2.6.2 he * parameter is 32bit big-endian signed (2-complement) 1821 1.2.6.2 he * value 1822 1.2.6.2 he */ 1823 1.2.6.2 he ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) | 1824 1.2.6.2 he (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) | 1825 1.2.6.2 he (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) | 1826 1.2.6.2 he sc->sc_msginbuf[EXTCODEOFF + 4]; 1827 1.2.6.2 he 1828 1.2.6.2 he /* new pointer */ 1829 1.2.6.2 he ptr += cmd->c_dp_cur; /* ignore overflow */ 1830 1.2.6.2 he 1831 1.2.6.2 he /* reject if ptr is not in data buffer */ 1832 1.2.6.2 he if (ptr > cmd->c_datacnt) 1833 1.2.6.2 he break; 1834 1.2.6.2 he 1835 1.2.6.2 he njsc32_set_ptr(sc, cmd, ptr); 1836 1.2.6.2 he goto restart; 1837 1.2.6.2 he 1838 1.2.6.2 he case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */ 1839 1.2.6.2 he DPRINTC(cmd, ("SDTR %#x %#x\n", 1840 1.2.6.2 he sc->sc_msginbuf[EXTCODEOFF + 1], 1841 1.2.6.2 he sc->sc_msginbuf[EXTCODEOFF + 2])); 1842 1.2.6.2 he if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1) 1843 1.2.6.2 he break; /* reject */ 1844 1.2.6.2 he 1845 1.2.6.2 he target = cmd->c_target; 1846 1.2.6.2 he 1847 1.2.6.2 he /* lookup sync period parameters */ 1848 1.2.6.2 he period = sc->sc_msginbuf[EXTCODEOFF + 1]; 1849 1.2.6.2 he for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++) 1850 1.2.6.2 he if (sc->sc_synct[idx].sp_period >= period) { 1851 1.2.6.2 he period = sc->sc_synct[idx].sp_period; 1852 1.2.6.2 he break; 1853 1.2.6.2 he } 1854 1.2.6.2 he if (idx >= NJSC32_NSYNCT) { 1855 1.2.6.2 he /* 1856 1.2.6.2 he * We can't meet the timing condition that 1857 1.2.6.2 he * the target requests -- use async. 1858 1.2.6.2 he */ 1859 1.2.6.2 he njsc32_target_async(sc, target); 1860 1.2.6.2 he njsc32_update_xfer_mode(sc, target); 1861 1.2.6.2 he if (target->t_state == NJSC32_TARST_SDTR) { 1862 1.2.6.2 he /* 1863 1.2.6.2 he * We started SDTR exchange -- start 1864 1.2.6.2 he * negotiation again and request async. 1865 1.2.6.2 he */ 1866 1.2.6.2 he target->t_state = NJSC32_TARST_ASYNC; 1867 1.2.6.2 he njsc32_negotiate_xfer(sc, target); 1868 1.2.6.2 he goto reply; 1869 1.2.6.2 he } else { 1870 1.2.6.2 he /* 1871 1.2.6.2 he * The target started SDTR exchange 1872 1.2.6.2 he * -- just reject and fallback 1873 1.2.6.2 he * to async. 1874 1.2.6.2 he */ 1875 1.2.6.2 he goto reject; 1876 1.2.6.2 he } 1877 1.2.6.2 he } 1878 1.2.6.2 he 1879 1.2.6.2 he /* check sync offset */ 1880 1.2.6.2 he offset = sc->sc_msginbuf[EXTCODEOFF + 2]; 1881 1.2.6.2 he if (offset > NJSC32_SYNCOFFSET_MAX) { 1882 1.2.6.2 he if (target->t_state == NJSC32_TARST_SDTR) { 1883 1.2.6.2 he printf("%s: wrong sync offset: %d\n", 1884 1.2.6.2 he cmd->c_xs->xs_periph->periph_dev->dv_xname, 1885 1.2.6.2 he offset); 1886 1.2.6.2 he /* XXX what to do? */ 1887 1.2.6.2 he } 1888 1.2.6.2 he offset = NJSC32_SYNCOFFSET_MAX; 1889 1.2.6.2 he } 1890 1.2.6.2 he 1891 1.2.6.2 he target->t_ackwidth = sc->sc_synct[idx].sp_ackw; 1892 1.2.6.2 he target->t_sample = sc->sc_synct[idx].sp_sample; 1893 1.2.6.2 he target->t_syncperiod = period; 1894 1.2.6.2 he target->t_syncoffset = offset; 1895 1.2.6.2 he target->t_sync = NJSC32_SYNC_VAL(idx, offset); 1896 1.2.6.2 he njsc32_update_xfer_mode(sc, target); 1897 1.2.6.2 he 1898 1.2.6.2 he if (target->t_state == NJSC32_TARST_SDTR) { 1899 1.2.6.2 he target->t_state = NJSC32_TARST_DONE; 1900 1.2.6.2 he } else { 1901 1.2.6.2 he njsc32_msgout_sdtr(sc, period, offset); 1902 1.2.6.2 he goto reply; 1903 1.2.6.2 he } 1904 1.2.6.2 he goto restart; 1905 1.2.6.2 he 1906 1.2.6.2 he case MSG_EXT_WDTR: /* Wide Data Transfer Request */ 1907 1.2.6.2 he DPRINTC(cmd, 1908 1.2.6.2 he ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1])); 1909 1.2.6.2 he #ifdef NJSC32_DUALEDGE 1910 1.2.6.2 he if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1) 1911 1.2.6.2 he break; /* reject */ 1912 1.2.6.2 he 1913 1.2.6.2 he /* 1914 1.2.6.2 he * T->I of this message is not used for 1915 1.2.6.2 he * DualEdge negotiation, so the device 1916 1.2.6.2 he * must not be a DualEdge device. 1917 1.2.6.2 he * 1918 1.2.6.2 he * XXX correct? 1919 1.2.6.2 he */ 1920 1.2.6.2 he target = cmd->c_target; 1921 1.2.6.2 he target->t_xferctl = 0; 1922 1.2.6.2 he 1923 1.2.6.2 he switch (target->t_state) { 1924 1.2.6.2 he case NJSC32_TARST_DE: 1925 1.2.6.2 he if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1926 1.2.6.2 he MSG_EXT_WDTR_BUS_8_BIT) { 1927 1.2.6.2 he /* 1928 1.2.6.2 he * Oops, we got unexpected WDTR. 1929 1.2.6.2 he * Negotiate for 8bit. 1930 1.2.6.2 he */ 1931 1.2.6.2 he target->t_state = NJSC32_TARST_WDTR; 1932 1.2.6.2 he } else { 1933 1.2.6.2 he target->t_state = NJSC32_TARST_SDTR; 1934 1.2.6.2 he } 1935 1.2.6.2 he njsc32_negotiate_xfer(sc, target); 1936 1.2.6.2 he goto reply; 1937 1.2.6.2 he 1938 1.2.6.2 he case NJSC32_TARST_WDTR: 1939 1.2.6.2 he if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1940 1.2.6.2 he MSG_EXT_WDTR_BUS_8_BIT) { 1941 1.2.6.2 he printf("%s: unexpected transfer width: %#x\n", 1942 1.2.6.2 he cmd->c_xs->xs_periph->periph_dev->dv_xname, 1943 1.2.6.2 he sc->sc_msginbuf[EXTCODEOFF + 1]); 1944 1.2.6.2 he /* XXX what to do? */ 1945 1.2.6.2 he } 1946 1.2.6.2 he target->t_state = NJSC32_TARST_SDTR; 1947 1.2.6.2 he njsc32_negotiate_xfer(sc, target); 1948 1.2.6.2 he goto reply; 1949 1.2.6.2 he 1950 1.2.6.2 he default: 1951 1.2.6.2 he /* the target started WDTR exchange */ 1952 1.2.6.2 he DPRINTC(cmd, ("WDTR from target\n")); 1953 1.2.6.2 he 1954 1.2.6.2 he target->t_state = NJSC32_TARST_SDTR; 1955 1.2.6.2 he njsc32_target_async(sc, target); 1956 1.2.6.2 he 1957 1.2.6.2 he break; /* reject the WDTR (8bit transfer) */ 1958 1.2.6.2 he } 1959 1.2.6.2 he #endif /* NJSC32_DUALEDGE */ 1960 1.2.6.2 he break; /* reject */ 1961 1.2.6.2 he } 1962 1.2.6.2 he DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n", 1963 1.2.6.2 he sc->sc_msginbuf[EXTCODEOFF], msgcnt)); 1964 1.2.6.2 he goto reject; 1965 1.2.6.2 he } 1966 1.2.6.2 he 1967 1.2.6.2 he /* 2byte messages */ 1968 1.2.6.2 he if (MSG_IS2BYTE(msg0)) { 1969 1.2.6.2 he if (msgcnt == 0) 1970 1.2.6.2 he WAITNEXTMSG; 1971 1.2.6.2 he 1972 1.2.6.2 he /* got whole message */ 1973 1.2.6.2 he sc->sc_msgincnt = 0; 1974 1.2.6.2 he } 1975 1.2.6.2 he 1976 1.2.6.2 he switch (msg0) { 1977 1.2.6.2 he case MSG_CMDCOMPLETE: /* 0x00 */ 1978 1.2.6.2 he case MSG_SAVEDATAPOINTER: /* 0x02 */ 1979 1.2.6.2 he case MSG_DISCONNECT: /* 0x04 */ 1980 1.2.6.2 he /* handled by AutoSCSI */ 1981 1.2.6.2 he PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0)); 1982 1.2.6.2 he break; 1983 1.2.6.2 he 1984 1.2.6.2 he case MSG_RESTOREPOINTERS: /* 0x03 */ 1985 1.2.6.2 he /* restore data pointer to what was saved */ 1986 1.2.6.2 he DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n")); 1987 1.2.6.2 he njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1988 1.2.6.2 he reload_params = TRUE; 1989 1.2.6.2 he MSGCOMPLETE; 1990 1.2.6.2 he /* NOTREACHED */ 1991 1.2.6.2 he break; 1992 1.2.6.2 he 1993 1.2.6.2 he #if 0 /* handled above */ 1994 1.2.6.2 he case MSG_EXTENDED: /* 0x01 */ 1995 1.2.6.2 he #endif 1996 1.2.6.2 he case MSG_MESSAGE_REJECT: /* 0x07 */ 1997 1.2.6.2 he target = cmd->c_target; 1998 1.2.6.2 he DPRINTC(cmd, ("Reject tarst %d\n", target->t_state)); 1999 1.2.6.2 he switch (target->t_state) { 2000 1.2.6.2 he #ifdef NJSC32_DUALEDGE 2001 1.2.6.2 he case NJSC32_TARST_WDTR: 2002 1.2.6.2 he case NJSC32_TARST_DE: 2003 1.2.6.2 he target->t_xferctl = 0; 2004 1.2.6.2 he target->t_state = NJSC32_TARST_SDTR; 2005 1.2.6.2 he njsc32_negotiate_xfer(sc, target); 2006 1.2.6.2 he goto reply; 2007 1.2.6.2 he #endif 2008 1.2.6.2 he case NJSC32_TARST_SDTR: 2009 1.2.6.2 he case NJSC32_TARST_ASYNC: 2010 1.2.6.2 he njsc32_target_async(sc, target); 2011 1.2.6.2 he target->t_state = NJSC32_TARST_DONE; 2012 1.2.6.2 he njsc32_update_xfer_mode(sc, target); 2013 1.2.6.2 he break; 2014 1.2.6.2 he default: 2015 1.2.6.2 he break; 2016 1.2.6.2 he } 2017 1.2.6.2 he goto restart; 2018 1.2.6.2 he 2019 1.2.6.2 he case MSG_NOOP: /* 0x08 */ 2020 1.2.6.2 he #ifdef NJSC32_DUALEDGE 2021 1.2.6.2 he target = cmd->c_target; 2022 1.2.6.2 he if (target->t_state == NJSC32_TARST_DE) { 2023 1.2.6.2 he printf("%s: DualEdge transfer\n", 2024 1.2.6.2 he cmd->c_xs->xs_periph->periph_dev->dv_xname); 2025 1.2.6.2 he target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE; 2026 1.2.6.2 he /* go to next negotiation */ 2027 1.2.6.2 he target->t_state = NJSC32_TARST_SDTR; 2028 1.2.6.2 he njsc32_negotiate_xfer(sc, target); 2029 1.2.6.2 he goto reply; 2030 1.2.6.2 he } 2031 1.2.6.2 he #endif 2032 1.2.6.2 he goto restart; 2033 1.2.6.2 he 2034 1.2.6.2 he case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */ 2035 1.2.6.2 he case MSG_ABORT: /* 0x06 I->T only */ 2036 1.2.6.2 he case MSG_PARITY_ERROR: /* 0x09 I->T only */ 2037 1.2.6.2 he case MSG_LINK_CMD_COMPLETE: /* 0x0a */ 2038 1.2.6.2 he case MSG_LINK_CMD_COMPLETEF: /* 0x0b */ 2039 1.2.6.2 he case MSG_BUS_DEV_RESET: /* 0x0c I->T only */ 2040 1.2.6.2 he case MSG_ABORT_TAG: /* 0x0d I->T only */ 2041 1.2.6.2 he case MSG_CLEAR_QUEUE: /* 0x0e I->T only */ 2042 1.2.6.2 he 2043 1.2.6.2 he #if 0 /* handled above */ 2044 1.2.6.2 he case MSG_SIMPLE_Q_TAG: /* 0x20 */ 2045 1.2.6.2 he #endif 2046 1.2.6.2 he case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */ 2047 1.2.6.2 he case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */ 2048 1.2.6.2 he case MSG_IGN_WIDE_RESIDUE: /* 0x23 */ 2049 1.2.6.2 he 2050 1.2.6.2 he default: 2051 1.2.6.2 he #ifdef NJSC32_DEBUG 2052 1.2.6.2 he PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0)); 2053 1.2.6.2 he if (MSG_IS2BYTE(msg0)) 2054 1.2.6.2 he printf(" %#x", msg); 2055 1.2.6.2 he printf("\n"); 2056 1.2.6.2 he #endif 2057 1.2.6.2 he break; 2058 1.2.6.2 he } 2059 1.2.6.2 he 2060 1.2.6.2 he reject: 2061 1.2.6.2 he njsc32_add_msgout(sc, MSG_MESSAGE_REJECT); 2062 1.2.6.2 he 2063 1.2.6.2 he reply: 2064 1.2.6.2 he msgout = njsc32_get_auto_msgout(sc); 2065 1.2.6.2 he 2066 1.2.6.2 he restart: 2067 1.2.6.2 he cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2068 1.2.6.2 he NJSC32_CMD_AUTO_COMMAND_PHASE | 2069 1.2.6.2 he NJSC32_CMD_AUTO_SCSI_RESTART; 2070 1.2.6.2 he 2071 1.2.6.2 he /* 2072 1.2.6.2 he * Be careful the second and latter bytes of Message In 2073 1.2.6.2 he * shall not be absorbed by AutoSCSI. 2074 1.2.6.2 he */ 2075 1.2.6.2 he if (sc->sc_msgincnt == 0) 2076 1.2.6.2 he cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2077 1.2.6.2 he 2078 1.2.6.2 he if (sc->sc_msgoutlen != 0) 2079 1.2.6.2 he cctl |= NJSC32_CMD_AUTO_ATN; 2080 1.2.6.2 he 2081 1.2.6.2 he njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout); 2082 1.2.6.2 he 2083 1.2.6.2 he /* (re)start AutoSCSI (may assert ATN) */ 2084 1.2.6.2 he if (reload_params) { 2085 1.2.6.2 he njsc32_cmd_reload(sc, cmd, cctl); 2086 1.2.6.2 he } else { 2087 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2088 1.2.6.2 he } 2089 1.2.6.2 he 2090 1.2.6.2 he /* +ATN -> -REQ: need 90ns delay? */ 2091 1.2.6.2 he 2092 1.2.6.2 he njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2093 1.2.6.2 he 2094 1.2.6.2 he njsc32_negate_ack(sc); 2095 1.2.6.2 he 2096 1.2.6.2 he return; 2097 1.2.6.2 he } 2098 1.2.6.2 he 2099 1.2.6.2 he static void 2100 1.2.6.2 he njsc32_msgout(struct njsc32_softc *sc) 2101 1.2.6.2 he { 2102 1.2.6.2 he int cctl; 2103 1.2.6.2 he u_int8_t bus; 2104 1.2.6.2 he unsigned n; 2105 1.2.6.2 he 2106 1.2.6.2 he if (sc->sc_msgoutlen == 0) { 2107 1.2.6.2 he /* target entered to Message Out on unexpected timing */ 2108 1.2.6.2 he njsc32_add_msgout(sc, MSG_NOOP); 2109 1.2.6.2 he } 2110 1.2.6.2 he 2111 1.2.6.2 he cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2112 1.2.6.2 he NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART | 2113 1.2.6.2 he NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2114 1.2.6.2 he 2115 1.2.6.2 he /* make sure target is in Message Out phase */ 2116 1.2.6.2 he bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR); 2117 1.2.6.2 he if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) { 2118 1.2.6.2 he /* 2119 1.2.6.2 he * Message Out is aborted by target. 2120 1.2.6.2 he */ 2121 1.2.6.2 he printf("%s: njsc32_msgout: phase change %#x\n", 2122 1.2.6.2 he sc->sc_dev.dv_xname, bus); 2123 1.2.6.2 he 2124 1.2.6.2 he /* XXX what to do? */ 2125 1.2.6.2 he 2126 1.2.6.2 he /* restart AutoSCSI (negate ATN) */ 2127 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2128 1.2.6.2 he 2129 1.2.6.2 he sc->sc_msgoutidx = 0; 2130 1.2.6.2 he return; 2131 1.2.6.2 he } 2132 1.2.6.2 he 2133 1.2.6.2 he n = sc->sc_msgoutidx; 2134 1.2.6.2 he if (n == sc->sc_msgoutlen - 1) { 2135 1.2.6.2 he /* 2136 1.2.6.2 he * negate ATN before sending ACK 2137 1.2.6.2 he */ 2138 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0); 2139 1.2.6.2 he 2140 1.2.6.2 he sc->sc_msgoutidx = 0; /* target may retry Message Out */ 2141 1.2.6.2 he } else { 2142 1.2.6.2 he cctl |= NJSC32_CMD_AUTO_ATN; 2143 1.2.6.2 he sc->sc_msgoutidx++; 2144 1.2.6.2 he } 2145 1.2.6.2 he 2146 1.2.6.2 he /* Send Message Out */ 2147 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]); 2148 1.2.6.2 he 2149 1.2.6.2 he /* DBn -> +ACK: need 55ns delay? */ 2150 1.2.6.2 he 2151 1.2.6.2 he njsc32_assert_ack(sc); 2152 1.2.6.2 he njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2153 1.2.6.2 he 2154 1.2.6.2 he /* restart AutoSCSI */ 2155 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2156 1.2.6.2 he 2157 1.2.6.2 he njsc32_negate_ack(sc); 2158 1.2.6.2 he 2159 1.2.6.2 he /* 2160 1.2.6.2 he * do not reset sc->sc_msgoutlen so the target 2161 1.2.6.2 he * can retry Message Out phase 2162 1.2.6.2 he */ 2163 1.2.6.2 he } 2164 1.2.6.2 he 2165 1.2.6.2 he static void 2166 1.2.6.2 he njsc32_cmdtimeout(void *arg) 2167 1.2.6.2 he { 2168 1.2.6.2 he struct njsc32_cmd *cmd = arg; 2169 1.2.6.2 he struct njsc32_softc *sc; 2170 1.2.6.2 he int s; 2171 1.2.6.2 he 2172 1.2.6.2 he PRINTC(cmd, ("command timeout\n")); 2173 1.2.6.2 he 2174 1.2.6.2 he sc = cmd->c_sc; 2175 1.2.6.2 he 2176 1.2.6.2 he s = splbio(); 2177 1.2.6.2 he 2178 1.2.6.2 he if (sc->sc_stat == NJSC32_STAT_ARBIT) 2179 1.2.6.2 he njsc32_arbitration_failed(sc); 2180 1.2.6.2 he else { 2181 1.2.6.2 he sc->sc_curcmd = NULL; 2182 1.2.6.2 he sc->sc_stat = NJSC32_STAT_IDLE; 2183 1.2.6.2 he njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2184 1.2.6.2 he } 2185 1.2.6.2 he 2186 1.2.6.2 he /* XXX? */ 2187 1.2.6.2 he njsc32_init(sc, 1); /* bus reset */ 2188 1.2.6.2 he 2189 1.2.6.2 he splx(s); 2190 1.2.6.2 he } 2191 1.2.6.2 he 2192 1.2.6.2 he static void 2193 1.2.6.2 he njsc32_reseltimeout(void *arg) 2194 1.2.6.2 he { 2195 1.2.6.2 he struct njsc32_cmd *cmd = arg; 2196 1.2.6.2 he struct njsc32_softc *sc; 2197 1.2.6.2 he int s; 2198 1.2.6.2 he 2199 1.2.6.2 he PRINTC(cmd, ("reselection timeout\n")); 2200 1.2.6.2 he 2201 1.2.6.2 he sc = cmd->c_sc; 2202 1.2.6.2 he 2203 1.2.6.2 he s = splbio(); 2204 1.2.6.2 he 2205 1.2.6.2 he /* remove from disconnected list */ 2206 1.2.6.2 he if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2207 1.2.6.2 he /* I_T_L_Q */ 2208 1.2.6.2 he KASSERT(cmd->c_lu->lu_cmd == NULL); 2209 1.2.6.2 he TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q); 2210 1.2.6.2 he } else { 2211 1.2.6.2 he /* I_T_L */ 2212 1.2.6.2 he KASSERT(cmd->c_lu->lu_cmd == cmd); 2213 1.2.6.2 he cmd->c_lu->lu_cmd = NULL; 2214 1.2.6.2 he } 2215 1.2.6.2 he 2216 1.2.6.2 he njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2217 1.2.6.2 he 2218 1.2.6.2 he /* XXX? */ 2219 1.2.6.2 he njsc32_init(sc, 1); /* bus reset */ 2220 1.2.6.2 he 2221 1.2.6.2 he splx(s); 2222 1.2.6.2 he } 2223 1.2.6.2 he 2224 1.2.6.2 he static __inline void 2225 1.2.6.2 he njsc32_end_auto(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int auto_phase) 2226 1.2.6.2 he { 2227 1.2.6.2 he struct scsipi_xfer *xs; 2228 1.2.6.2 he 2229 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_MSGIN_02) { 2230 1.2.6.2 he /* Message In: 0x02 Save Data Pointer */ 2231 1.2.6.2 he 2232 1.2.6.2 he /* 2233 1.2.6.2 he * Adjust saved data pointer 2234 1.2.6.2 he * if the command is not completed yet. 2235 1.2.6.2 he */ 2236 1.2.6.2 he if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 && 2237 1.2.6.2 he (auto_phase & 2238 1.2.6.2 he (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) { 2239 1.2.6.2 he njsc32_save_ptr(cmd); 2240 1.2.6.2 he } 2241 1.2.6.2 he TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2242 1.2.6.2 he njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2243 1.2.6.2 he njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2244 1.2.6.2 he njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2245 1.2.6.2 he njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT))); 2246 1.2.6.2 he } 2247 1.2.6.2 he 2248 1.2.6.2 he xs = cmd->c_xs; 2249 1.2.6.2 he 2250 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_MSGIN_00) { 2251 1.2.6.2 he /* Command Complete */ 2252 1.2.6.2 he TPRINTC(cmd, ("njsc32_intr: Command Complete\n")); 2253 1.2.6.2 he switch (xs->status) { 2254 1.2.6.2 he case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY: 2255 1.2.6.2 he /* 2256 1.2.6.2 he * scsipi layer will automatically handle the error 2257 1.2.6.2 he */ 2258 1.2.6.2 he njsc32_end_cmd(sc, cmd, XS_BUSY); 2259 1.2.6.2 he break; 2260 1.2.6.2 he default: 2261 1.2.6.2 he xs->resid -= cmd->c_dp_max; 2262 1.2.6.2 he njsc32_end_cmd(sc, cmd, XS_NOERROR); 2263 1.2.6.2 he break; 2264 1.2.6.2 he } 2265 1.2.6.2 he } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) { 2266 1.2.6.2 he /* Disconnect */ 2267 1.2.6.2 he TPRINTC(cmd, ("njsc32_intr: Disconnect\n")); 2268 1.2.6.2 he 2269 1.2.6.2 he /* for ill-designed devices */ 2270 1.2.6.2 he if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0) 2271 1.2.6.2 he njsc32_save_ptr(cmd); 2272 1.2.6.2 he 2273 1.2.6.2 he /* 2274 1.2.6.2 he * move current cmd to disconnected list 2275 1.2.6.2 he */ 2276 1.2.6.2 he if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2277 1.2.6.2 he /* I_T_L_Q */ 2278 1.2.6.2 he if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD) 2279 1.2.6.2 he TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q); 2280 1.2.6.2 he else 2281 1.2.6.2 he TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q); 2282 1.2.6.2 he } else { 2283 1.2.6.2 he /* I_T_L */ 2284 1.2.6.2 he cmd->c_lu->lu_cmd = cmd; 2285 1.2.6.2 he } 2286 1.2.6.2 he 2287 1.2.6.2 he /* 2288 1.2.6.2 he * schedule timeout -- avoid being 2289 1.2.6.2 he * disconnected forever 2290 1.2.6.2 he */ 2291 1.2.6.2 he if ((xs->xs_control & XS_CTL_POLL) == 0) { 2292 1.2.6.2 he callout_stop(&xs->xs_callout); 2293 1.2.6.2 he callout_reset(&xs->xs_callout, mstohz(xs->timeout), 2294 1.2.6.2 he njsc32_reseltimeout, cmd); 2295 1.2.6.2 he } 2296 1.2.6.2 he 2297 1.2.6.2 he } else { 2298 1.2.6.2 he /* 2299 1.2.6.2 he * target has come to Bus Free phase 2300 1.2.6.2 he * probably to notify an error 2301 1.2.6.2 he */ 2302 1.2.6.2 he PRINTC(cmd, ("njsc32_intr: unexpected bus free\n")); 2303 1.2.6.2 he /* try Request Sense */ 2304 1.2.6.2 he xs->status = SCSI_CHECK; 2305 1.2.6.2 he njsc32_end_cmd(sc, cmd, XS_BUSY); 2306 1.2.6.2 he } 2307 1.2.6.2 he } 2308 1.2.6.2 he 2309 1.2.6.2 he int 2310 1.2.6.2 he njsc32_intr(void *arg) 2311 1.2.6.2 he { 2312 1.2.6.2 he struct njsc32_softc *sc = arg; 2313 1.2.6.2 he u_int16_t intr; 2314 1.2.6.2 he u_int8_t arbstat, bus_phase; 2315 1.2.6.2 he int auto_phase; 2316 1.2.6.2 he int idbit; 2317 1.2.6.2 he struct njsc32_cmd *cmd; 2318 1.2.6.2 he 2319 1.2.6.2 he intr = njsc32_read_2(sc, NJSC32_REG_IRQ); 2320 1.2.6.2 he if ((intr & NJSC32_IRQ_INTR_PENDING) == 0) 2321 1.2.6.2 he return 0; /* not mine */ 2322 1.2.6.2 he 2323 1.2.6.2 he TPRINTF(("%s: njsc32_intr: %#x\n", sc->sc_dev.dv_xname, intr)); 2324 1.2.6.2 he 2325 1.2.6.2 he #if 0 /* I don't think this is required */ 2326 1.2.6.2 he /* mask interrupts */ 2327 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 2328 1.2.6.2 he #endif 2329 1.2.6.2 he 2330 1.2.6.2 he /* we got an interrupt, so stop the timer */ 2331 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 2332 1.2.6.2 he 2333 1.2.6.2 he if (intr & NJSC32_IRQ_SCSIRESET) { 2334 1.2.6.2 he printf("%s: detected bus reset\n", sc->sc_dev.dv_xname); 2335 1.2.6.2 he /* clear current request */ 2336 1.2.6.2 he njsc32_reset_detected(sc); 2337 1.2.6.2 he goto out; 2338 1.2.6.2 he } 2339 1.2.6.2 he 2340 1.2.6.2 he if (sc->sc_stat == NJSC32_STAT_ARBIT) { 2341 1.2.6.2 he cmd = sc->sc_curcmd; 2342 1.2.6.2 he KASSERT(cmd); 2343 1.2.6.2 he arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT); 2344 1.2.6.2 he if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) { 2345 1.2.6.2 he /* 2346 1.2.6.2 he * arbitration done 2347 1.2.6.2 he */ 2348 1.2.6.2 he /* clear arbitration status */ 2349 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION, 2350 1.2.6.2 he NJSC32_SETARB_CLEAR); 2351 1.2.6.2 he 2352 1.2.6.2 he if (arbstat & NJSC32_ARBSTAT_WIN) { 2353 1.2.6.2 he TPRINTC(cmd, 2354 1.2.6.2 he ("njsc32_intr: arbitration won\n")); 2355 1.2.6.2 he 2356 1.2.6.2 he TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 2357 1.2.6.2 he 2358 1.2.6.2 he sc->sc_stat = NJSC32_STAT_CONNECT; 2359 1.2.6.2 he } else { 2360 1.2.6.2 he TPRINTC(cmd, 2361 1.2.6.2 he ("njsc32_intr: arbitration failed\n")); 2362 1.2.6.2 he 2363 1.2.6.2 he njsc32_arbitration_failed(sc); 2364 1.2.6.2 he 2365 1.2.6.2 he /* XXX delay */ 2366 1.2.6.2 he /* XXX retry counter */ 2367 1.2.6.2 he } 2368 1.2.6.2 he } 2369 1.2.6.2 he } 2370 1.2.6.2 he 2371 1.2.6.2 he if (intr & NJSC32_IRQ_TIMER) { 2372 1.2.6.2 he TPRINTF(("%s: njsc32_intr: timer interrupt\n", 2373 1.2.6.2 he sc->sc_dev.dv_xname)); 2374 1.2.6.2 he } 2375 1.2.6.2 he 2376 1.2.6.2 he if (intr & NJSC32_IRQ_RESELECT) { 2377 1.2.6.2 he /* Reselection from a target */ 2378 1.2.6.2 he njsc32_arbitration_failed(sc); /* just in case */ 2379 1.2.6.2 he if ((cmd = sc->sc_curcmd) != NULL) { 2380 1.2.6.2 he /* ? */ 2381 1.2.6.2 he printf("%s: unexpected reselection\n", 2382 1.2.6.2 he sc->sc_dev.dv_xname); 2383 1.2.6.2 he sc->sc_curcmd = NULL; 2384 1.2.6.2 he sc->sc_stat = NJSC32_STAT_IDLE; 2385 1.2.6.2 he njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP); 2386 1.2.6.2 he } 2387 1.2.6.2 he 2388 1.2.6.2 he idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID); 2389 1.2.6.2 he if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 || 2390 1.2.6.2 he (sc->sc_reselid = ffs(idbit & ~NJSC32_INITIATOR_ID) -1) 2391 1.2.6.2 he < 0) { 2392 1.2.6.2 he printf("%s: invalid reselection (id: %#x)\n", 2393 1.2.6.2 he sc->sc_dev.dv_xname, idbit); 2394 1.2.6.2 he sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */ 2395 1.2.6.2 he } else { 2396 1.2.6.2 he sc->sc_stat = NJSC32_STAT_RESEL; 2397 1.2.6.2 he TPRINTF(("%s: njsc32_intr: reselection from %d\n", 2398 1.2.6.2 he sc->sc_dev.dv_xname, sc->sc_reselid)); 2399 1.2.6.2 he } 2400 1.2.6.2 he } 2401 1.2.6.2 he 2402 1.2.6.2 he if (intr & NJSC32_IRQ_PHASE_CHANGE) { 2403 1.2.6.2 he #if 1 /* XXX probably not needed */ 2404 1.2.6.2 he if (sc->sc_stat == NJSC32_STAT_ARBIT) 2405 1.2.6.2 he PRINTC(sc->sc_curcmd, 2406 1.2.6.2 he ("njsc32_intr: cancel arbitration phase\n")); 2407 1.2.6.2 he njsc32_arbitration_failed(sc); 2408 1.2.6.2 he #endif 2409 1.2.6.2 he /* current bus phase */ 2410 1.2.6.2 he bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 2411 1.2.6.2 he NJSC32_BUSMON_PHASE_MASK; 2412 1.2.6.2 he 2413 1.2.6.2 he switch (bus_phase) { 2414 1.2.6.2 he case NJSC32_PHASE_MESSAGE_IN: 2415 1.2.6.2 he njsc32_msgin(sc); 2416 1.2.6.2 he break; 2417 1.2.6.2 he 2418 1.2.6.2 he /* 2419 1.2.6.2 he * target may suddenly become Status / Bus Free phase 2420 1.2.6.2 he * to notify an error condition 2421 1.2.6.2 he */ 2422 1.2.6.2 he case NJSC32_PHASE_STATUS: 2423 1.2.6.2 he printf("%s: unexpected bus phase: Status\n", 2424 1.2.6.2 he sc->sc_dev.dv_xname); 2425 1.2.6.2 he if ((cmd = sc->sc_curcmd) != NULL) { 2426 1.2.6.2 he cmd->c_xs->status = 2427 1.2.6.2 he njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2428 1.2.6.2 he TPRINTC(cmd, ("njsc32_intr: Status %d\n", 2429 1.2.6.2 he cmd->c_xs->status)); 2430 1.2.6.2 he } 2431 1.2.6.2 he break; 2432 1.2.6.2 he case NJSC32_PHASE_BUSFREE: 2433 1.2.6.2 he printf("%s: unexpected bus phase: Bus Free\n", 2434 1.2.6.2 he sc->sc_dev.dv_xname); 2435 1.2.6.2 he if ((cmd = sc->sc_curcmd) != NULL) { 2436 1.2.6.2 he sc->sc_curcmd = NULL; 2437 1.2.6.2 he sc->sc_stat = NJSC32_STAT_IDLE; 2438 1.2.6.2 he if (cmd->c_xs->status != SCSI_QUEUE_FULL && 2439 1.2.6.2 he cmd->c_xs->status != SCSI_BUSY) 2440 1.2.6.2 he cmd->c_xs->status = SCSI_CHECK;/* XXX */ 2441 1.2.6.2 he njsc32_end_cmd(sc, cmd, XS_BUSY); 2442 1.2.6.2 he } 2443 1.2.6.2 he goto out; 2444 1.2.6.2 he default: 2445 1.2.6.2 he #ifdef NJSC32_DEBUG 2446 1.2.6.2 he printf("%s: unexpected bus phase: ", 2447 1.2.6.2 he sc->sc_dev.dv_xname); 2448 1.2.6.2 he switch (bus_phase) { 2449 1.2.6.2 he case NJSC32_PHASE_COMMAND: 2450 1.2.6.2 he printf("Command\n"); break; 2451 1.2.6.2 he case NJSC32_PHASE_MESSAGE_OUT: 2452 1.2.6.2 he printf("Message Out\n");break; 2453 1.2.6.2 he case NJSC32_PHASE_DATA_IN: 2454 1.2.6.2 he printf("Data In\n"); break; 2455 1.2.6.2 he case NJSC32_PHASE_DATA_OUT: 2456 1.2.6.2 he printf("Data Out\n"); break; 2457 1.2.6.2 he case NJSC32_PHASE_RESELECT: 2458 1.2.6.2 he printf("Reselect\n");break; 2459 1.2.6.2 he default: printf("%#x\n", bus_phase); break; 2460 1.2.6.2 he } 2461 1.2.6.2 he #else 2462 1.2.6.2 he printf("%s: unexpected bus phase: %#x", 2463 1.2.6.2 he sc->sc_dev.dv_xname, bus_phase); 2464 1.2.6.2 he #endif 2465 1.2.6.2 he break; 2466 1.2.6.2 he } 2467 1.2.6.2 he } 2468 1.2.6.2 he 2469 1.2.6.2 he if (intr & NJSC32_IRQ_AUTOSCSI) { 2470 1.2.6.2 he /* 2471 1.2.6.2 he * AutoSCSI interrupt 2472 1.2.6.2 he */ 2473 1.2.6.2 he auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE); 2474 1.2.6.2 he TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n", 2475 1.2.6.2 he sc->sc_dev.dv_xname, auto_phase)); 2476 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0); 2477 1.2.6.2 he 2478 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) { 2479 1.2.6.2 he cmd = sc->sc_curcmd; 2480 1.2.6.2 he if (cmd == NULL) { 2481 1.2.6.2 he printf("%s: sel no cmd\n", 2482 1.2.6.2 he sc->sc_dev.dv_xname); 2483 1.2.6.2 he goto out; 2484 1.2.6.2 he } 2485 1.2.6.2 he DPRINTC(cmd, ("njsc32_intr: selection timeout\n")); 2486 1.2.6.2 he 2487 1.2.6.2 he sc->sc_curcmd = NULL; 2488 1.2.6.2 he sc->sc_stat = NJSC32_STAT_IDLE; 2489 1.2.6.2 he njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT); 2490 1.2.6.2 he 2491 1.2.6.2 he goto out; 2492 1.2.6.2 he } 2493 1.2.6.2 he 2494 1.2.6.2 he #ifdef NJSC32_TRACE 2495 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_COMMAND) { 2496 1.2.6.2 he /* Command phase has been automatically processed */ 2497 1.2.6.2 he TPRINTF(("%s: njsc32_intr: Command\n", 2498 1.2.6.2 he sc->sc_dev.dv_xname)); 2499 1.2.6.2 he } 2500 1.2.6.2 he #endif 2501 1.2.6.2 he #ifdef NJSC32_DEBUG 2502 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_ILLEGAL) { 2503 1.2.6.2 he printf("%s: njsc32_intr: Illegal phase\n", 2504 1.2.6.2 he sc->sc_dev.dv_xname); 2505 1.2.6.2 he } 2506 1.2.6.2 he #endif 2507 1.2.6.2 he 2508 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) { 2509 1.2.6.2 he TPRINTF(("%s: njsc32_intr: Process Message In\n", 2510 1.2.6.2 he sc->sc_dev.dv_xname)); 2511 1.2.6.2 he njsc32_msgin(sc); 2512 1.2.6.2 he } 2513 1.2.6.2 he 2514 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) { 2515 1.2.6.2 he TPRINTF(("%s: njsc32_intr: Process Message Out\n", 2516 1.2.6.2 he sc->sc_dev.dv_xname)); 2517 1.2.6.2 he njsc32_msgout(sc); 2518 1.2.6.2 he } 2519 1.2.6.2 he 2520 1.2.6.2 he cmd = sc->sc_curcmd; 2521 1.2.6.2 he if (cmd == NULL) { 2522 1.2.6.2 he TPRINTF(("%s: njsc32_intr: no cmd\n", 2523 1.2.6.2 he sc->sc_dev.dv_xname)); 2524 1.2.6.2 he goto out; 2525 1.2.6.2 he } 2526 1.2.6.2 he 2527 1.2.6.2 he if (auto_phase & 2528 1.2.6.2 he (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) { 2529 1.2.6.3 tron u_int32_t sackcnt, cntoffset; 2530 1.2.6.3 tron 2531 1.2.6.2 he #ifdef NJSC32_TRACE 2532 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_DATA_IN) 2533 1.2.6.2 he PRINTC(cmd, ("njsc32_intr: data in done\n")); 2534 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_DATA_OUT) 2535 1.2.6.2 he PRINTC(cmd, ("njsc32_intr: data out done\n")); 2536 1.2.6.2 he printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2537 1.2.6.2 he njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2538 1.2.6.2 he njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2539 1.2.6.2 he njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2540 1.2.6.2 he njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)); 2541 1.2.6.2 he #endif 2542 1.2.6.2 he 2543 1.2.6.2 he /* 2544 1.2.6.2 he * detected parity error on data transfer? 2545 1.2.6.2 he */ 2546 1.2.6.2 he if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 2547 1.2.6.2 he (NJSC32_PARITYSTATUS_ERROR_LSB| 2548 1.2.6.2 he NJSC32_PARITYSTATUS_ERROR_MSB)) { 2549 1.2.6.2 he 2550 1.2.6.2 he PRINTC(cmd, ("datain: parity error\n")); 2551 1.2.6.2 he 2552 1.2.6.2 he /* clear parity error */ 2553 1.2.6.2 he njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 2554 1.2.6.2 he NJSC32_PARITYCTL_CHECK_ENABLE | 2555 1.2.6.2 he NJSC32_PARITYCTL_CLEAR_ERROR); 2556 1.2.6.2 he 2557 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2558 1.2.6.2 he /* 2559 1.2.6.2 he * XXX command has already finished 2560 1.2.6.2 he * -- what can we do? 2561 1.2.6.2 he * 2562 1.2.6.2 he * It is not clear current command 2563 1.2.6.2 he * caused the error -- reset everything. 2564 1.2.6.2 he */ 2565 1.2.6.2 he njsc32_init(sc, 1); /* XXX */ 2566 1.2.6.2 he } else { 2567 1.2.6.2 he /* XXX does this case occur? */ 2568 1.2.6.2 he #if 1 2569 1.2.6.2 he printf("%s: datain: parity error\n", 2570 1.2.6.2 he sc->sc_dev.dv_xname); 2571 1.2.6.2 he #endif 2572 1.2.6.2 he /* 2573 1.2.6.2 he * Make attention condition and try 2574 1.2.6.2 he * to send Initiator Detected Error 2575 1.2.6.2 he * message. 2576 1.2.6.2 he */ 2577 1.2.6.2 he njsc32_init_msgout(sc); 2578 1.2.6.2 he njsc32_add_msgout(sc, 2579 1.2.6.2 he MSG_INITIATOR_DET_ERR); 2580 1.2.6.2 he njsc32_write_4(sc, 2581 1.2.6.2 he NJSC32_REG_SCSI_MSG_OUT, 2582 1.2.6.2 he njsc32_get_auto_msgout(sc)); 2583 1.2.6.2 he /* restart autoscsi with ATN */ 2584 1.2.6.2 he njsc32_write_2(sc, 2585 1.2.6.2 he NJSC32_REG_COMMAND_CONTROL, 2586 1.2.6.2 he NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2587 1.2.6.2 he NJSC32_CMD_AUTO_COMMAND_PHASE | 2588 1.2.6.2 he NJSC32_CMD_AUTO_SCSI_RESTART | 2589 1.2.6.2 he NJSC32_CMD_AUTO_MSGIN_00_04 | 2590 1.2.6.2 he NJSC32_CMD_AUTO_MSGIN_02 | 2591 1.2.6.2 he NJSC32_CMD_AUTO_ATN); 2592 1.2.6.2 he } 2593 1.2.6.2 he goto out; 2594 1.2.6.2 he } 2595 1.2.6.2 he 2596 1.2.6.2 he /* 2597 1.2.6.2 he * data has been transferred, and current pointer 2598 1.2.6.2 he * is changed 2599 1.2.6.2 he */ 2600 1.2.6.3 tron sackcnt = njsc32_read_4(sc, NJSC32_REG_SACK_CNT); 2601 1.2.6.3 tron 2602 1.2.6.3 tron /* 2603 1.2.6.3 tron * The controller returns extra ACK count 2604 1.2.6.3 tron * if the DMA buffer is not 4byte aligned. 2605 1.2.6.3 tron */ 2606 1.2.6.3 tron cntoffset = le32toh(cmd->c_sgt[0].sg_addr) & 3; 2607 1.2.6.3 tron #ifdef NJSC32_DEBUG 2608 1.2.6.3 tron if (cntoffset != 0) { 2609 1.2.6.3 tron printf("sackcnt %u, cntoffset %u\n", 2610 1.2.6.3 tron sackcnt, cntoffset); 2611 1.2.6.3 tron } 2612 1.2.6.3 tron #endif 2613 1.2.6.3 tron /* advance SCSI pointer */ 2614 1.2.6.3 tron njsc32_set_cur_ptr(cmd, 2615 1.2.6.3 tron cmd->c_dp_cur + sackcnt - cntoffset); 2616 1.2.6.2 he } 2617 1.2.6.2 he 2618 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_MSGOUT) { 2619 1.2.6.2 he /* Message Out phase has been automatically processed */ 2620 1.2.6.2 he TPRINTC(cmd, ("njsc32_intr: Message Out\n")); 2621 1.2.6.2 he if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 && 2622 1.2.6.2 he sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) { 2623 1.2.6.2 he njsc32_init_msgout(sc); 2624 1.2.6.2 he } 2625 1.2.6.2 he } 2626 1.2.6.2 he 2627 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_STATUS) { 2628 1.2.6.2 he /* Status phase has been automatically processed */ 2629 1.2.6.2 he cmd->c_xs->status = 2630 1.2.6.2 he njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2631 1.2.6.2 he TPRINTC(cmd, ("njsc32_intr: Status %#x\n", 2632 1.2.6.2 he cmd->c_xs->status)); 2633 1.2.6.2 he } 2634 1.2.6.2 he 2635 1.2.6.2 he if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2636 1.2.6.2 he /* AutoSCSI is finished */ 2637 1.2.6.2 he 2638 1.2.6.2 he TPRINTC(cmd, ("njsc32_intr: Bus Free\n")); 2639 1.2.6.2 he 2640 1.2.6.2 he sc->sc_stat = NJSC32_STAT_IDLE; 2641 1.2.6.2 he sc->sc_curcmd = NULL; 2642 1.2.6.2 he 2643 1.2.6.2 he njsc32_end_auto(sc, cmd, auto_phase); 2644 1.2.6.2 he } 2645 1.2.6.2 he goto out; 2646 1.2.6.2 he } 2647 1.2.6.2 he 2648 1.2.6.2 he if (intr & NJSC32_IRQ_FIFO_THRESHOLD) { 2649 1.2.6.2 he /* XXX We use DMA, and this shouldn't happen */ 2650 1.2.6.2 he printf("%s: njsc32_intr: FIFO\n", sc->sc_dev.dv_xname); 2651 1.2.6.2 he njsc32_init(sc, 1); 2652 1.2.6.2 he goto out; 2653 1.2.6.2 he } 2654 1.2.6.2 he if (intr & NJSC32_IRQ_PCI) { 2655 1.2.6.2 he /* XXX? */ 2656 1.2.6.2 he printf("%s: njsc32_intr: PCI\n", sc->sc_dev.dv_xname); 2657 1.2.6.2 he } 2658 1.2.6.2 he if (intr & NJSC32_IRQ_BMCNTERR) { 2659 1.2.6.2 he /* XXX? */ 2660 1.2.6.2 he printf("%s: njsc32_intr: BM\n", sc->sc_dev.dv_xname); 2661 1.2.6.2 he } 2662 1.2.6.2 he 2663 1.2.6.2 he out: 2664 1.2.6.2 he /* go next command if controller is idle */ 2665 1.2.6.2 he if (sc->sc_stat == NJSC32_STAT_IDLE) 2666 1.2.6.2 he njsc32_start(sc); 2667 1.2.6.2 he 2668 1.2.6.2 he #if 0 2669 1.2.6.2 he /* enable interrupts */ 2670 1.2.6.2 he njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 2671 1.2.6.2 he #endif 2672 1.2.6.2 he 2673 1.2.6.2 he return 1; /* processed */ 2674 1.2.6.2 he } 2675
Indexes created Sun Oct 26 21:10:03 GMT 2025