ninjascsi32.c revision 1.13
1 /* $NetBSD: ninjascsi32.c,v 1.13 2007/10/29 03:17:24 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by ITOH Yasufumi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.13 2007/10/29 03:17:24 itohy Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/device.h> 46 #include <sys/kernel.h> 47 #include <sys/buf.h> 48 #include <sys/scsiio.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <sys/intr.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 /* 62 * DualEdge transfer support 63 */ 64 /* #define NJSC32_DUALEDGE */ /* XXX untested */ 65 66 /* 67 * Auto param loading does not work properly (it partially works (works on 68 * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51), 69 * and it doesn't improve the performance so much, 70 * forget about it. 71 */ 72 #undef NJSC32_AUTOPARAM 73 74 #include <dev/ic/ninjascsi32reg.h> 75 #include <dev/ic/ninjascsi32var.h> 76 77 /* #define NJSC32_DEBUG */ 78 /* #define NJSC32_TRACE */ 79 80 #ifdef NJSC32_DEBUG 81 #define DPRINTF(x) printf x 82 #define DPRINTC(cmd, x) PRINTC(cmd, x) 83 #else 84 #define DPRINTF(x) 85 #define DPRINTC(cmd, x) 86 #endif 87 #ifdef NJSC32_TRACE 88 #define TPRINTF(x) printf x 89 #define TPRINTC(cmd, x) PRINTC(cmd, x) 90 #else 91 #define TPRINTF(x) 92 #define TPRINTC(cmd, x) 93 #endif 94 95 #define PRINTC(cmd, x) do { \ 96 scsi_print_addr((cmd)->c_xs->xs_periph); \ 97 printf x; \ 98 } while (/* CONSTCOND */ 0) 99 100 static void njsc32_scsipi_request(struct scsipi_channel *, 101 scsipi_adapter_req_t, void *); 102 static void njsc32_scsipi_minphys(struct buf *); 103 static int njsc32_scsipi_ioctl(struct scsipi_channel *, u_long, void *, 104 int, struct proc *); 105 106 static void njsc32_init(struct njsc32_softc *, int nosleep); 107 static int njsc32_init_cmds(struct njsc32_softc *); 108 static void njsc32_target_async(struct njsc32_softc *, 109 struct njsc32_target *); 110 static void njsc32_init_targets(struct njsc32_softc *); 111 static void njsc32_add_msgout(struct njsc32_softc *, int); 112 static u_int32_t njsc32_get_auto_msgout(struct njsc32_softc *); 113 #ifdef NJSC32_DUALEDGE 114 static void njsc32_msgout_wdtr(struct njsc32_softc *, int); 115 #endif 116 static void njsc32_msgout_sdtr(struct njsc32_softc *, int period, 117 int offset); 118 static void njsc32_negotiate_xfer(struct njsc32_softc *, 119 struct njsc32_target *); 120 static void njsc32_arbitration_failed(struct njsc32_softc *); 121 static void njsc32_start(struct njsc32_softc *); 122 static void njsc32_run_xfer(struct njsc32_softc *, struct scsipi_xfer *); 123 static void njsc32_end_cmd(struct njsc32_softc *, struct njsc32_cmd *, 124 scsipi_xfer_result_t); 125 static void njsc32_reset_bus(struct njsc32_softc *); 126 static void njsc32_clear_cmds(struct njsc32_softc *, 127 scsipi_xfer_result_t); 128 static void njsc32_reset_detected(struct njsc32_softc *); 129 static void njsc32_set_ptr(struct njsc32_softc *, struct njsc32_cmd *, 130 u_int32_t); 131 static void njsc32_assert_ack(struct njsc32_softc *); 132 static void njsc32_negate_ack(struct njsc32_softc *); 133 static void njsc32_wait_req_negate(struct njsc32_softc *); 134 static void njsc32_reconnect(struct njsc32_softc *, struct njsc32_cmd *); 135 enum njsc32_reselstat { 136 NJSC32_RESEL_ERROR, /* to be rejected */ 137 NJSC32_RESEL_COMPLETE, /* reselection is just complete */ 138 NJSC32_RESEL_THROUGH /* this message is OK (no reply) */ 139 }; 140 static enum njsc32_reselstat njsc32_resel_identify(struct njsc32_softc *, 141 int lun, struct njsc32_cmd **); 142 static enum njsc32_reselstat njsc32_resel_tag(struct njsc32_softc *, 143 int tag, struct njsc32_cmd **); 144 static void njsc32_cmd_reload(struct njsc32_softc *, struct njsc32_cmd *, 145 int); 146 static void njsc32_update_xfer_mode(struct njsc32_softc *, 147 struct njsc32_target *); 148 static void njsc32_msgin(struct njsc32_softc *); 149 static void njsc32_msgout(struct njsc32_softc *); 150 static void njsc32_cmdtimeout(void *); 151 static void njsc32_reseltimeout(void *); 152 153 static inline unsigned 154 njsc32_read_1(struct njsc32_softc *sc, int no) 155 { 156 157 return bus_space_read_1(sc->sc_regt, sc->sc_regh, no); 158 } 159 160 static inline unsigned 161 njsc32_read_2(struct njsc32_softc *sc, int no) 162 { 163 164 return bus_space_read_2(sc->sc_regt, sc->sc_regh, no); 165 } 166 167 static inline u_int32_t 168 njsc32_read_4(struct njsc32_softc *sc, int no) 169 { 170 171 return bus_space_read_4(sc->sc_regt, sc->sc_regh, no); 172 } 173 174 static inline void 175 njsc32_write_1(struct njsc32_softc *sc, int no, int val) 176 { 177 178 bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val); 179 } 180 181 static inline void 182 njsc32_write_2(struct njsc32_softc *sc, int no, int val) 183 { 184 185 bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val); 186 } 187 188 static inline void 189 njsc32_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 190 { 191 192 bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val); 193 } 194 195 static inline unsigned 196 njsc32_ireg_read_1(struct njsc32_softc *sc, int no) 197 { 198 199 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 200 return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 201 } 202 203 static inline unsigned 204 njsc32_ireg_read_2(struct njsc32_softc *sc, int no) 205 { 206 207 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 208 return bus_space_read_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 209 } 210 211 static inline u_int32_t 212 njsc32_ireg_read_4(struct njsc32_softc *sc, int no) 213 { 214 u_int32_t val; 215 216 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 217 val = (u_int16_t)bus_space_read_2(sc->sc_regt, sc->sc_regh, 218 NJSC32_REG_DATA_LOW); 219 return val | (bus_space_read_2(sc->sc_regt, sc->sc_regh, 220 NJSC32_REG_DATA_HIGH) << 16); 221 } 222 223 static inline void 224 njsc32_ireg_write_1(struct njsc32_softc *sc, int no, int val) 225 { 226 227 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 228 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 229 } 230 231 static inline void 232 njsc32_ireg_write_2(struct njsc32_softc *sc, int no, int val) 233 { 234 235 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 236 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 237 } 238 239 static inline void 240 njsc32_ireg_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 241 { 242 243 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 244 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 245 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_HIGH, 246 val >> 16); 247 } 248 249 #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */ 250 #ifdef __STDC__ 251 # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK 252 # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \ 253 NJSC32_SREQ_SAMPLING_ENABLE) 254 #else 255 # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK 256 # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \ 257 NJSC32_SREQ_SAMPLING_ENABLE) 258 #endif 259 260 #define NJSC32_NSYNCT_MAXSYNC 1 261 #define NJSC32_NSYNCT 16 262 263 /* 40MHz (25ns) */ 264 static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = { 265 { 0, 0, 0 }, /* dummy for async */ 266 { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */ 267 { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */ 268 { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */ 269 { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */ 270 { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */ 271 { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */ 272 { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 273 { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */ 274 { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 275 { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */ 276 { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */ 277 { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */ 278 { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */ 279 { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */ 280 { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */ 281 }; 282 283 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 284 /* 20MHz (50ns) */ 285 static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = { 286 { 0, 0, 0 }, /* dummy for async */ 287 { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */ 288 { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */ 289 { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 290 { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 291 { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */ 292 { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */ 293 { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */ 294 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */ 295 { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */ 296 { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */ 297 { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */ 298 { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */ 299 { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */ 300 { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */ 301 { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */ 302 }; 303 304 /* 33.3MHz (30ns) */ 305 static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = { 306 { 0, 0, 0 }, /* dummy for async */ 307 { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */ 308 { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */ 309 { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */ 310 { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */ 311 { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */ 312 { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */ 313 { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */ 314 { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */ 315 { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */ 316 { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */ 317 { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */ 318 { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */ 319 { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */ 320 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */ 321 { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */ 322 }; 323 #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */ 324 325 #undef NS 326 #undef ACKW 327 #undef SMPL 328 329 /* initialize device */ 330 static void 331 njsc32_init(struct njsc32_softc *sc, int nosleep) 332 { 333 u_int16_t intstat; 334 335 /* block all interrupts */ 336 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 337 338 /* clear transfer */ 339 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 340 njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0); 341 342 /* make sure interrupts are cleared */ 343 /* XXX loop forever? */ 344 while ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ)) & 345 NJSC32_IRQ_INTR_PENDING) { 346 DPRINTF(("%s: njsc32_init: intr pending: %#x\n", 347 sc->sc_dev.dv_xname, intstat)); 348 } 349 350 /* FIFO threshold */ 351 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL, 352 NJSC32_FIFO_FULL_BUSMASTER); 353 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY, 354 NJSC32_FIFO_EMPTY_BUSMASTER); 355 356 /* clock source */ 357 njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk); 358 359 /* memory read multiple */ 360 njsc32_ireg_write_1(sc, NJSC32_IREG_BM, 361 NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD); 362 363 /* clear parity error and enable parity detection */ 364 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 365 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 366 367 /* misc configuration */ 368 njsc32_ireg_write_2(sc, NJSC32_IREG_MISC, 369 NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT | 370 NJSC32_MISC_DELAYED_BMSTART | 371 NJSC32_MISC_MASTER_TERMINATION_SELECT | 372 NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL | 373 NJSC32_MISC_AUTOSEL_TIMING_SEL | 374 NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE); 375 376 /* 377 * Check for termination power (32Bi only?). 378 */ 379 if (!nosleep || cold) { 380 DPRINTF(("%s: njsc32_init: checking TERMPWR\n", 381 sc->sc_dev.dv_xname)); 382 383 /* First, turn termination power off */ 384 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0); 385 386 /* give 0.5s to settle */ 387 if (nosleep) 388 delay(500000); 389 else 390 tsleep(sc, PWAIT, "njs_t1", hz / 2); 391 } 392 393 /* supply termination power if not supplied by other devices */ 394 if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) & 395 NJSC32_TERMPWR_SENSE) == 0) { 396 /* termination power is not present on the bus */ 397 if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) { 398 /* 399 * CardBus device must not supply termination power 400 * to avoid excessive power consumption. 401 */ 402 printf("%s: no termination power present\n", 403 sc->sc_dev.dv_xname); 404 } else { 405 /* supply termination power */ 406 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 407 NJSC32_TERMPWR_BPWR); 408 409 DPRINTF(("%s: supplying termination power\n", 410 sc->sc_dev.dv_xname)); 411 412 /* give 0.5s to settle */ 413 if (!nosleep) 414 tsleep(sc, PWAIT, "njs_t2", hz / 2); 415 } 416 } 417 418 /* stop timer */ 419 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 420 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 421 422 /* default transfer parameter */ 423 njsc32_write_1(sc, NJSC32_REG_SYNC, 0); 424 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK); 425 njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT, 426 NJSC32_SEL_TIMEOUT_TIME); 427 428 /* select interrupt source */ 429 njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT, 430 NJSC32_IRQSEL_RESELECT | 431 NJSC32_IRQSEL_PHASE_CHANGE | 432 NJSC32_IRQSEL_SCSIRESET | 433 NJSC32_IRQSEL_TIMER | 434 NJSC32_IRQSEL_FIFO_THRESHOLD | 435 NJSC32_IRQSEL_TARGET_ABORT | 436 NJSC32_IRQSEL_MASTER_ABORT | 437 /* XXX not yet 438 NJSC32_IRQSEL_SERR | 439 NJSC32_IRQSEL_PERR | 440 NJSC32_IRQSEL_BMCNTERR | 441 */ 442 NJSC32_IRQSEL_AUTO_SCSI_SEQ); 443 444 /* unblock interrupts */ 445 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 446 447 /* turn LED off */ 448 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR, 449 NJSC32_EXTPORT_LED_OFF); 450 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, 451 NJSC32_EXTPORT_LED_OFF); 452 453 /* reset SCSI bus so the targets become known state */ 454 njsc32_reset_bus(sc); 455 } 456 457 static int 458 njsc32_init_cmds(struct njsc32_softc *sc) 459 { 460 struct njsc32_cmd *cmd; 461 bus_addr_t dmaaddr; 462 int i, error; 463 464 /* 465 * allocate DMA area for command 466 */ 467 if ((error = bus_dmamem_alloc(sc->sc_dmat, 468 sizeof(struct njsc32_dma_page), PAGE_SIZE, 0, 469 &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) { 470 printf("%s: unable to allocate cmd page, error = %d\n", 471 sc->sc_dev.dv_xname, error); 472 return 0; 473 } 474 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg, 475 sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page), 476 (void **)&sc->sc_cmdpg, 477 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 478 printf("%s: unable to map cmd page, error = %d\n", 479 sc->sc_dev.dv_xname, error); 480 goto fail1; 481 } 482 if ((error = bus_dmamap_create(sc->sc_dmat, 483 sizeof(struct njsc32_dma_page), 1, 484 sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT, 485 &sc->sc_dmamap_cmdpg)) != 0) { 486 printf("%s: unable to create cmd DMA map, error = %d\n", 487 sc->sc_dev.dv_xname, error); 488 goto fail2; 489 } 490 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg, 491 sc->sc_cmdpg, sizeof(struct njsc32_dma_page), 492 NULL, BUS_DMA_NOWAIT)) != 0) { 493 printf("%s: unable to load cmd DMA map, error = %d\n", 494 sc->sc_dev.dv_xname, error); 495 goto fail3; 496 } 497 498 memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page)); 499 dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr; 500 501 #ifdef NJSC32_AUTOPARAM 502 sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap); 503 #endif 504 505 for (i = 0; i < NJSC32_NUM_CMD; i++) { 506 cmd = &sc->sc_cmds[i]; 507 cmd->c_sc = sc; 508 cmd->c_sgt = sc->sc_cmdpg->dp_sg[i]; 509 cmd->c_sgt_dma = dmaaddr + 510 offsetof(struct njsc32_dma_page, dp_sg[i]); 511 cmd->c_flags = 0; 512 513 error = bus_dmamap_create(sc->sc_dmat, 514 NJSC32_MAX_XFER, /* max total map size */ 515 NJSC32_NUM_SG, /* max number of segments */ 516 NJSC32_SGT_MAXSEGLEN, /* max size of a segment */ 517 0, /* boundary */ 518 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer); 519 if (error) { 520 printf("%s: only %d cmd descs available (error = %d)\n", 521 sc->sc_dev.dv_xname, i, error); 522 break; 523 } 524 TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q); 525 } 526 527 if (i > 0) 528 return i; 529 530 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 531 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 532 fail2: bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cmdpg, 533 sizeof(struct njsc32_dma_page)); 534 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs); 535 536 return 0; 537 } 538 539 static void 540 njsc32_target_async(struct njsc32_softc *sc, struct njsc32_target *target) 541 { 542 543 target->t_sync = 544 NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC); 545 target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK; 546 target->t_sample = 0; /* disable */ 547 target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC; 548 target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC; 549 } 550 551 static void 552 njsc32_init_targets(struct njsc32_softc *sc) 553 { 554 int id, lun; 555 struct njsc32_lu *lu; 556 557 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 558 /* cancel negotiation status */ 559 sc->sc_targets[id].t_state = NJSC32_TARST_INIT; 560 561 /* default to async mode */ 562 njsc32_target_async(sc, &sc->sc_targets[id]); 563 564 #ifdef NJSC32_DUALEDGE 565 sc->sc_targets[id].t_xferctl = 0; 566 #endif 567 568 sc->sc_targets[id].t_targetid = 569 (1 << id) | (1 << NJSC32_INITIATOR_ID); 570 571 /* init logical units */ 572 for (lun = 0; lun < NJSC32_NLU; lun++) { 573 lu = &sc->sc_targets[id].t_lus[lun]; 574 lu->lu_cmd = NULL; 575 TAILQ_INIT(&lu->lu_q); 576 } 577 } 578 } 579 580 void 581 njsc32_attach(struct njsc32_softc *sc) 582 { 583 const char *str; 584 #if 1 /* test */ 585 int reg; 586 njsc32_model_t detected_model; 587 #endif 588 589 /* init */ 590 TAILQ_INIT(&sc->sc_freecmd); 591 TAILQ_INIT(&sc->sc_reqcmd); 592 593 #if 1 /* test */ 594 /* 595 * try to distinguish 32Bi and 32UDE 596 */ 597 /* try to set DualEdge bit (exists on 32UDE only) and read it back */ 598 njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE); 599 if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) { 600 /* device was removed? */ 601 aprint_error("%s: attach failed\n", sc->sc_dev.dv_xname); 602 return; 603 } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) { 604 detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE; 605 } else { 606 detected_model = NJSC32_MODEL_32BI; 607 } 608 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */ 609 610 #if 1/*def DIAGNOSTIC*/ 611 /* compare what is configured with what is detected */ 612 if ((sc->sc_model & NJSC32_MODEL_MASK) != 613 (detected_model & NJSC32_MODEL_MASK)) { 614 /* 615 * Please report this error if it happens. 616 */ 617 aprint_error("%s: model mismatch: %#x vs %#x\n", 618 sc->sc_dev.dv_xname, sc->sc_model, detected_model); 619 return; 620 } 621 #endif 622 #endif 623 624 /* check model */ 625 switch (sc->sc_model & NJSC32_MODEL_MASK) { 626 case NJSC32_MODEL_32BI: 627 str = "Bi"; 628 /* 32Bi doesn't support DualEdge transfer */ 629 KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0); 630 break; 631 case NJSC32_MODEL_32UDE: 632 str = "UDE"; 633 break; 634 default: 635 aprint_error("%s: unknown model!\n", sc->sc_dev.dv_xname); 636 return; 637 } 638 aprint_normal("%s: NJSC-32%s", sc->sc_dev.dv_xname, str); 639 640 switch (sc->sc_clk) { 641 default: 642 #ifdef DIAGNOSTIC 643 panic("njsc32_attach: unknown clk %d", sc->sc_clk); 644 #endif 645 case NJSC32_CLOCK_DIV_4: 646 sc->sc_synct = njsc32_synct_40M; 647 str = "40MHz"; 648 break; 649 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 650 case NJSC32_CLOCK_DIV_2: 651 sc->sc_synct = njsc32_synct_20M; 652 str = "20MHz"; 653 break; 654 case NJSC32_CLOCK_PCICLK: 655 sc->sc_synct = njsc32_synct_pci; 656 str = "PCI"; 657 break; 658 #endif 659 } 660 aprint_normal(", G/A rev %#x, clk %s%s\n", 661 NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str, 662 (sc->sc_model & NJSC32_FLAG_DUALEDGE) ? 663 #ifdef NJSC32_DUALEDGE 664 ", DualEdge" 665 #else 666 ", DualEdge (no driver support)" 667 #endif 668 : ""); 669 670 /* allocate DMA resource */ 671 if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) { 672 printf("%s: no usable DMA map\n", sc->sc_dev.dv_xname); 673 return; 674 } 675 sc->sc_flags |= NJSC32_CMDPG_MAPPED; 676 677 sc->sc_curcmd = NULL; 678 sc->sc_nusedcmds = 0; 679 sc->sc_stat = NJSC32_STAT_IDLE; 680 681 sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */ 682 683 /* initialize target structure */ 684 njsc32_init_targets(sc); 685 686 /* initialize hardware */ 687 njsc32_init(sc, cold); 688 689 /* setup adapter */ 690 sc->sc_adapter.adapt_dev = &sc->sc_dev; 691 sc->sc_adapter.adapt_nchannels = 1; 692 sc->sc_adapter.adapt_request = njsc32_scsipi_request; 693 sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys; 694 sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl; 695 696 sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings = 697 sc->sc_ncmd; 698 699 /* setup channel */ 700 sc->sc_channel.chan_adapter = &sc->sc_adapter; 701 sc->sc_channel.chan_bustype = &scsi_bustype; 702 sc->sc_channel.chan_channel = 0; 703 sc->sc_channel.chan_ntargets = NJSC32_NTARGET; 704 sc->sc_channel.chan_nluns = NJSC32_NLU; 705 sc->sc_channel.chan_id = NJSC32_INITIATOR_ID; 706 707 sc->sc_scsi = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 708 } 709 710 int 711 njsc32_detach(struct njsc32_softc *sc, int flags) 712 { 713 int rv = 0; 714 int i, s; 715 struct njsc32_cmd *cmd; 716 717 s = splbio(); 718 719 /* clear running/disconnected commands */ 720 njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP); 721 722 sc->sc_stat = NJSC32_STAT_DETACH; 723 724 /* clear pending commands */ 725 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 726 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 727 njsc32_end_cmd(sc, cmd, XS_RESET); 728 } 729 730 if (sc->sc_scsi != NULL) 731 rv = config_detach(sc->sc_scsi, flags); 732 733 splx(s); 734 735 /* free DMA resource */ 736 if (sc->sc_flags & NJSC32_CMDPG_MAPPED) { 737 for (i = 0; i < sc->sc_ncmd; i++) { 738 cmd = &sc->sc_cmds[i]; 739 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) 740 bus_dmamap_unload(sc->sc_dmat, 741 cmd->c_dmamap_xfer); 742 bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer); 743 } 744 745 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 746 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 747 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cmdpg, 748 sizeof(struct njsc32_dma_page)); 749 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, 750 sc->sc_cmdpg_nsegs); 751 } 752 753 return 0; 754 } 755 756 static inline void 757 njsc32_cmd_init(struct njsc32_cmd *cmd) 758 { 759 760 cmd->c_flags = 0; 761 762 /* scatter/gather table */ 763 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0); 764 cmd->c_sgoffset = 0; 765 cmd->c_sgfixcnt = 0; 766 767 /* data pointer */ 768 cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0; 769 } 770 771 static inline void 772 njsc32_init_msgout(struct njsc32_softc *sc) 773 { 774 775 sc->sc_msgoutlen = 0; 776 sc->sc_msgoutidx = 0; 777 } 778 779 static void 780 njsc32_add_msgout(struct njsc32_softc *sc, int byte) 781 { 782 783 if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) { 784 printf("njsc32_add_msgout: too many\n"); 785 return; 786 } 787 sc->sc_msgout[sc->sc_msgoutlen++] = byte; 788 } 789 790 static u_int32_t 791 njsc32_get_auto_msgout(struct njsc32_softc *sc) 792 { 793 u_int32_t val; 794 u_int8_t *p; 795 796 val = 0; 797 p = sc->sc_msgout; 798 switch (sc->sc_msgoutlen) { 799 /* 31-24 23-16 15-8 7 ... 1 0 */ 800 case 3: /* MSG3 MSG2 MSG1 V --- cnt */ 801 val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT; 802 /* FALLTHROUGH */ 803 804 case 2: /* MSG2 MSG1 --- V --- cnt */ 805 val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT; 806 /* FALLTHROUGH */ 807 808 case 1: /* MSG1 --- --- V --- cnt */ 809 val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT; 810 val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen; 811 break; 812 813 default: 814 break; 815 } 816 return val; 817 } 818 819 #ifdef NJSC32_DUALEDGE 820 /* add Wide Data Transfer Request to the next Message Out */ 821 static void 822 njsc32_msgout_wdtr(struct njsc32_softc *sc, int width) 823 { 824 825 njsc32_add_msgout(sc, MSG_EXTENDED); 826 njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN); 827 njsc32_add_msgout(sc, MSG_EXT_WDTR); 828 njsc32_add_msgout(sc, width); 829 } 830 #endif 831 832 /* add Synchronous Data Transfer Request to the next Message Out */ 833 static void 834 njsc32_msgout_sdtr(struct njsc32_softc *sc, int period, int offset) 835 { 836 837 njsc32_add_msgout(sc, MSG_EXTENDED); 838 njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN); 839 njsc32_add_msgout(sc, MSG_EXT_SDTR); 840 njsc32_add_msgout(sc, period); 841 njsc32_add_msgout(sc, offset); 842 } 843 844 static void 845 njsc32_negotiate_xfer(struct njsc32_softc *sc, struct njsc32_target *target) 846 { 847 848 /* initial negotiation state */ 849 if (target->t_state == NJSC32_TARST_INIT) { 850 #ifdef NJSC32_DUALEDGE 851 if (target->t_flags & NJSC32_TARF_DE) 852 target->t_state = NJSC32_TARST_DE; 853 else 854 #endif 855 if (target->t_flags & NJSC32_TARF_SYNC) 856 target->t_state = NJSC32_TARST_SDTR; 857 else 858 target->t_state = NJSC32_TARST_DONE; 859 } 860 861 switch (target->t_state) { 862 default: 863 case NJSC32_TARST_INIT: 864 #ifdef DIAGNOSTIC 865 panic("njsc32_negotiate_xfer"); 866 /* NOTREACHED */ 867 #endif 868 /* FALLTHROUGH */ 869 case NJSC32_TARST_DONE: 870 /* no more work */ 871 break; 872 873 #ifdef NJSC32_DUALEDGE 874 case NJSC32_TARST_DE: 875 njsc32_msgout_wdtr(sc, 0xde /* XXX? */); 876 break; 877 878 case NJSC32_TARST_WDTR: 879 njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT); 880 break; 881 #endif 882 883 case NJSC32_TARST_SDTR: 884 njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period, 885 NJSC32_SYNCOFFSET_MAX); 886 break; 887 888 case NJSC32_TARST_ASYNC: 889 njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC, 890 NJSC32_SYNCOFFSET_ASYNC); 891 break; 892 } 893 } 894 895 /* turn LED on */ 896 static inline void 897 njsc32_led_on(struct njsc32_softc *sc) 898 { 899 900 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON); 901 } 902 903 /* turn LED off */ 904 static inline void 905 njsc32_led_off(struct njsc32_softc *sc) 906 { 907 908 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF); 909 } 910 911 static void 912 njsc32_arbitration_failed(struct njsc32_softc *sc) 913 { 914 struct njsc32_cmd *cmd; 915 916 if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT) 917 return; 918 919 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) 920 callout_stop(&cmd->c_xs->xs_callout); 921 922 sc->sc_stat = NJSC32_STAT_IDLE; 923 sc->sc_curcmd = NULL; 924 925 /* the command is no longer active */ 926 if (--sc->sc_nusedcmds == 0) 927 njsc32_led_off(sc); 928 } 929 930 static inline void 931 njsc32_cmd_load(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 932 { 933 struct njsc32_target *target; 934 struct scsipi_xfer *xs; 935 int i, control, lun; 936 u_int32_t msgoutreg; 937 #ifdef NJSC32_AUTOPARAM 938 struct njsc32_autoparam *ap; 939 #endif 940 941 xs = cmd->c_xs; 942 #ifdef NJSC32_AUTOPARAM 943 ap = &sc->sc_cmdpg->dp_ap; 944 #else 945 /* reset CDB pointer */ 946 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR); 947 #endif 948 949 /* CDB */ 950 TPRINTC(cmd, ("njsc32_cmd_load: CDB")); 951 for (i = 0; i < xs->cmdlen; i++) { 952 #ifdef NJSC32_AUTOPARAM 953 ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i]; 954 #else 955 njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA, 956 ((u_int8_t *)xs->cmd)[i]); 957 #endif 958 TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i])); 959 } 960 #ifdef NJSC32_AUTOPARAM /* XXX needed? */ 961 for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++) 962 ap->ap_cdb[i].cdb_data = 0; 963 #endif 964 965 control = xs->xs_control; 966 967 /* 968 * Message Out 969 */ 970 njsc32_init_msgout(sc); 971 972 /* Identify */ 973 lun = xs->xs_periph->periph_lun; 974 njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ? 975 MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1)); 976 977 /* tagged queueing */ 978 if (control & XS_CTL_TAGMASK) { 979 njsc32_add_msgout(sc, xs->xs_tag_type); 980 njsc32_add_msgout(sc, xs->xs_tag_id); 981 TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id)); 982 } 983 TPRINTF(("\n")); 984 985 target = cmd->c_target; 986 987 /* transfer negotiation */ 988 if (control & XS_CTL_REQSENSE) 989 target->t_state = NJSC32_TARST_INIT; 990 njsc32_negotiate_xfer(sc, target); 991 992 msgoutreg = njsc32_get_auto_msgout(sc); 993 994 #ifdef NJSC32_AUTOPARAM 995 ap->ap_msgout = htole32(msgoutreg); 996 997 ap->ap_sync = target->t_sync; 998 ap->ap_ackwidth = target->t_ackwidth; 999 ap->ap_targetid = target->t_targetid; 1000 ap->ap_sample = target->t_sample; 1001 1002 ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 1003 NJSC32_CMD_AUTO_COMMAND_PHASE | 1004 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1005 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1006 #ifdef NJSC32_DUALEDGE 1007 ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl); 1008 #else 1009 ap->ap_xferctl = htole16(cmd->c_xferctl); 1010 #endif 1011 ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr); 1012 1013 /* sync njsc32_autoparam */ 1014 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1015 offsetof(struct njsc32_dma_page, dp_ap), /* offset */ 1016 sizeof(struct njsc32_autoparam), 1017 BUS_DMASYNC_PREWRITE); 1018 1019 /* autoparam DMA address */ 1020 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma); 1021 1022 /* start command (autoparam) */ 1023 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1024 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER); 1025 1026 #else /* not NJSC32_AUTOPARAM */ 1027 1028 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg); 1029 1030 /* load parameters */ 1031 njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid); 1032 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1033 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1034 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1035 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1036 #ifdef NJSC32_DUALEDGE 1037 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1038 cmd->c_xferctl | target->t_xferctl); 1039 #else 1040 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1041 #endif 1042 /* start AutoSCSI */ 1043 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1044 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE | 1045 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1046 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1047 #endif /* not NJSC32_AUTOPARAM */ 1048 } 1049 1050 /* Note: must be called at splbio() */ 1051 static void 1052 njsc32_start(struct njsc32_softc *sc) 1053 { 1054 struct njsc32_cmd *cmd; 1055 1056 /* get a command to issue */ 1057 TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) { 1058 if (cmd->c_lu->lu_cmd == NULL && 1059 ((cmd->c_flags & NJSC32_CMD_TAGGED) || 1060 TAILQ_EMPTY(&cmd->c_lu->lu_q))) 1061 break; /* OK, the logical unit is free */ 1062 } 1063 if (!cmd) 1064 goto out; /* no work to do */ 1065 1066 /* request will always fail if not in bus free phase */ 1067 if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) != 1068 NJSC32_BUSMON_BUSFREE) 1069 goto busy; 1070 1071 /* clear parity error and enable parity detection */ 1072 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1073 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1074 1075 njsc32_cmd_load(sc, cmd); 1076 1077 if (sc->sc_nusedcmds++ == 0) 1078 njsc32_led_on(sc); 1079 1080 sc->sc_curcmd = cmd; 1081 sc->sc_stat = NJSC32_STAT_ARBIT; 1082 1083 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) { 1084 callout_reset(&cmd->c_xs->xs_callout, 1085 mstohz(cmd->c_xs->timeout), 1086 njsc32_cmdtimeout, cmd); 1087 } 1088 1089 return; 1090 1091 busy: /* XXX retry counter */ 1092 TPRINTF(("%s: njsc32_start: busy\n", sc->sc_dev.dv_xname)); 1093 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME); 1094 out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 1095 } 1096 1097 static void 1098 njsc32_run_xfer(struct njsc32_softc *sc, struct scsipi_xfer *xs) 1099 { 1100 struct scsipi_periph *periph; 1101 int control; 1102 int lun; 1103 struct njsc32_cmd *cmd; 1104 int s, i, error; 1105 1106 periph = xs->xs_periph; 1107 KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID); 1108 1109 control = xs->xs_control; 1110 lun = periph->periph_lun; 1111 1112 /* 1113 * get a free cmd 1114 * (scsipi layer knows the number of cmds, so this shall never fail) 1115 */ 1116 s = splbio(); 1117 cmd = TAILQ_FIRST(&sc->sc_freecmd); 1118 KASSERT(cmd); 1119 TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q); 1120 splx(s); 1121 1122 /* 1123 * build a request 1124 */ 1125 njsc32_cmd_init(cmd); 1126 cmd->c_xs = xs; 1127 cmd->c_target = &sc->sc_targets[periph->periph_target]; 1128 cmd->c_lu = &cmd->c_target->t_lus[lun]; 1129 1130 /* tagged queueing */ 1131 if (control & XS_CTL_TAGMASK) { 1132 cmd->c_flags |= NJSC32_CMD_TAGGED; 1133 if (control & XS_CTL_HEAD_TAG) 1134 cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD; 1135 } 1136 1137 /* map DMA buffer */ 1138 cmd->c_datacnt = xs->datalen; 1139 if (xs->datalen) { 1140 /* Is XS_CTL_DATA_UIO ever used anywhere? */ 1141 KASSERT((control & XS_CTL_DATA_UIO) == 0); 1142 1143 error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer, 1144 xs->data, xs->datalen, NULL, 1145 ((control & XS_CTL_NOSLEEP) ? 1146 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 1147 BUS_DMA_STREAMING | 1148 ((control & XS_CTL_DATA_IN) ? 1149 BUS_DMA_READ : BUS_DMA_WRITE)); 1150 1151 switch (error) { 1152 case 0: 1153 break; 1154 case ENOMEM: 1155 case EAGAIN: 1156 xs->error = XS_RESOURCE_SHORTAGE; 1157 goto map_failed; 1158 default: 1159 xs->error = XS_DRIVER_STUFFUP; 1160 map_failed: 1161 printf("%s: njsc32_run_xfer: map failed, error %d\n", 1162 sc->sc_dev.dv_xname, error); 1163 /* put it back to free command list */ 1164 s = splbio(); 1165 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1166 splx(s); 1167 /* abort this transfer */ 1168 scsipi_done(xs); 1169 return; 1170 } 1171 1172 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1173 0, cmd->c_dmamap_xfer->dm_mapsize, 1174 (control & XS_CTL_DATA_IN) ? 1175 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1176 1177 for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) { 1178 cmd->c_sgt[i].sg_addr = 1179 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr); 1180 cmd->c_sgt[i].sg_len = 1181 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len); 1182 } 1183 /* end mark */ 1184 cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK); 1185 1186 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1187 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1188 NJSC32_SIZE_SGT, 1189 BUS_DMASYNC_PREWRITE); 1190 1191 cmd->c_flags |= NJSC32_CMD_DMA_MAPPED; 1192 1193 /* enable transfer */ 1194 cmd->c_xferctl = 1195 NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START | 1196 NJSC32_XFR_ALL_COUNT_CLR; 1197 1198 /* XXX How can we specify the DMA direction? */ 1199 1200 #if 0 /* faster write mode? (doesn't work) */ 1201 if ((control & XS_CTL_DATA_IN) == 0) 1202 cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE; 1203 #endif 1204 } else { 1205 /* no data transfer */ 1206 cmd->c_xferctl = 0; 1207 } 1208 1209 /* queue request */ 1210 s = splbio(); 1211 TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q); 1212 1213 /* start the controller if idle */ 1214 if (sc->sc_stat == NJSC32_STAT_IDLE) 1215 njsc32_start(sc); 1216 1217 splx(s); 1218 1219 if (control & XS_CTL_POLL) { 1220 /* wait for completion */ 1221 /* XXX should handle timeout? */ 1222 while ((xs->xs_status & XS_STS_DONE) == 0) { 1223 delay(1000); 1224 njsc32_intr(sc); 1225 } 1226 } 1227 } 1228 1229 static void 1230 njsc32_end_cmd(struct njsc32_softc *sc, struct njsc32_cmd *cmd, 1231 scsipi_xfer_result_t result) 1232 { 1233 struct scsipi_xfer *xs; 1234 int s; 1235 #ifdef DIAGNOSTIC 1236 struct njsc32_cmd *c; 1237 #endif 1238 1239 KASSERT(cmd); 1240 1241 #ifdef DIAGNOSTIC 1242 s = splbio(); 1243 TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) { 1244 if (cmd == c) 1245 panic("njsc32_end_cmd: already in free list"); 1246 } 1247 splx(s); 1248 #endif 1249 xs = cmd->c_xs; 1250 1251 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) { 1252 if (cmd->c_datacnt) { 1253 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1254 0, cmd->c_dmamap_xfer->dm_mapsize, 1255 (xs->xs_control & XS_CTL_DATA_IN) ? 1256 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1257 1258 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1259 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, 1260 NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE); 1261 } 1262 1263 bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer); 1264 cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED; 1265 } 1266 1267 s = splbio(); 1268 if ((xs->xs_control & XS_CTL_POLL) == 0) 1269 callout_stop(&xs->xs_callout); 1270 1271 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1272 splx(s); 1273 1274 xs->error = result; 1275 scsipi_done(xs); 1276 1277 if (--sc->sc_nusedcmds == 0) 1278 njsc32_led_off(sc); 1279 } 1280 1281 /* 1282 * request from scsipi layer 1283 */ 1284 static void 1285 njsc32_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1286 void *arg) 1287 { 1288 struct njsc32_softc *sc; 1289 struct scsipi_xfer_mode *xm; 1290 struct njsc32_target *target; 1291 1292 sc = (void *)chan->chan_adapter->adapt_dev; 1293 1294 switch (req) { 1295 case ADAPTER_REQ_RUN_XFER: 1296 njsc32_run_xfer(sc, arg); 1297 break; 1298 1299 case ADAPTER_REQ_GROW_RESOURCES: 1300 /* not supported */ 1301 break; 1302 1303 case ADAPTER_REQ_SET_XFER_MODE: 1304 xm = arg; 1305 target = &sc->sc_targets[xm->xm_target]; 1306 1307 target->t_flags = 0; 1308 if (xm->xm_mode & PERIPH_CAP_TQING) 1309 target->t_flags |= NJSC32_TARF_TAG; 1310 if (xm->xm_mode & PERIPH_CAP_SYNC) { 1311 target->t_flags |= NJSC32_TARF_SYNC; 1312 #ifdef NJSC32_DUALEDGE 1313 if (sc->sc_model & NJSC32_FLAG_DUALEDGE) 1314 target->t_flags |= NJSC32_TARF_DE; 1315 #endif 1316 } 1317 #ifdef NJSC32_DUALEDGE 1318 target->t_xferctl = 0; 1319 #endif 1320 target->t_state = NJSC32_TARST_INIT; 1321 njsc32_target_async(sc, target); 1322 1323 break; 1324 default: 1325 break; 1326 } 1327 } 1328 1329 static void 1330 njsc32_scsipi_minphys(struct buf *bp) 1331 { 1332 1333 if (bp->b_bcount > NJSC32_MAX_XFER) 1334 bp->b_bcount = NJSC32_MAX_XFER; 1335 minphys(bp); 1336 } 1337 1338 static void 1339 njsc32_reset_bus(struct njsc32_softc *sc) 1340 { 1341 int s; 1342 1343 DPRINTF(("%s: njsc32_reset_bus:\n", sc->sc_dev.dv_xname)); 1344 1345 /* SCSI bus reset */ 1346 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST); 1347 delay(NJSC32_RESET_HOLD_TIME); 1348 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0); 1349 1350 /* clear transfer */ 1351 s = splbio(); 1352 njsc32_reset_detected(sc); 1353 splx(s); 1354 } 1355 1356 /* 1357 * clear running/disconnected commands 1358 */ 1359 static void 1360 njsc32_clear_cmds(struct njsc32_softc *sc, scsipi_xfer_result_t cmdresult) 1361 { 1362 struct njsc32_cmd *cmd; 1363 int id, lun; 1364 struct njsc32_lu *lu; 1365 1366 njsc32_arbitration_failed(sc); 1367 1368 /* clear current transfer */ 1369 if ((cmd = sc->sc_curcmd) != NULL) { 1370 sc->sc_curcmd = NULL; 1371 njsc32_end_cmd(sc, cmd, cmdresult); 1372 } 1373 1374 /* clear disconnected transfers */ 1375 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 1376 for (lun = 0; lun < NJSC32_NLU; lun++) { 1377 lu = &sc->sc_targets[id].t_lus[lun]; 1378 1379 if ((cmd = lu->lu_cmd) != NULL) { 1380 lu->lu_cmd = NULL; 1381 njsc32_end_cmd(sc, cmd, cmdresult); 1382 } 1383 while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) { 1384 TAILQ_REMOVE(&lu->lu_q, cmd, c_q); 1385 njsc32_end_cmd(sc, cmd, cmdresult); 1386 } 1387 } 1388 } 1389 } 1390 1391 static void 1392 njsc32_reset_detected(struct njsc32_softc *sc) 1393 { 1394 1395 njsc32_clear_cmds(sc, XS_RESET); 1396 njsc32_init_targets(sc); 1397 sc->sc_stat = NJSC32_STAT_IDLE; 1398 KASSERT(sc->sc_nusedcmds == 0); 1399 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL); 1400 } 1401 1402 static int 1403 njsc32_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd, 1404 void *addr, int flag, struct proc *p) 1405 { 1406 struct njsc32_softc *sc = (void *)chan->chan_adapter->adapt_dev; 1407 1408 switch (cmd) { 1409 case SCBUSIORESET: 1410 njsc32_init(sc, 0); 1411 return 0; 1412 default: 1413 break; 1414 } 1415 1416 return ENOTTY; 1417 } 1418 1419 /* 1420 * set current data pointer 1421 */ 1422 static inline void 1423 njsc32_set_cur_ptr(struct njsc32_cmd *cmd, u_int32_t pos) 1424 { 1425 1426 /* new current data pointer */ 1427 cmd->c_dp_cur = pos; 1428 1429 /* update number of bytes transferred */ 1430 if (pos > cmd->c_dp_max) 1431 cmd->c_dp_max = pos; 1432 } 1433 1434 /* 1435 * set data pointer for the next transfer 1436 */ 1437 static void 1438 njsc32_set_ptr(struct njsc32_softc *sc, struct njsc32_cmd *cmd, u_int32_t pos) 1439 { 1440 struct njsc32_sgtable *sg; 1441 unsigned sgte; 1442 u_int32_t len; 1443 1444 /* set current pointer */ 1445 njsc32_set_cur_ptr(cmd, pos); 1446 1447 /* undo previous fix if any */ 1448 if (cmd->c_sgfixcnt != 0) { 1449 sg = &cmd->c_sgt[cmd->c_sgoffset]; 1450 sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt); 1451 sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt); 1452 cmd->c_sgfixcnt = 0; 1453 } 1454 1455 if (pos >= cmd->c_datacnt) { 1456 /* transfer done */ 1457 #if 1 /*def DIAGNOSTIC*/ 1458 if (pos > cmd->c_datacnt) 1459 printf("%s: pos %u too large\n", 1460 sc->sc_dev.dv_xname, pos - cmd->c_datacnt); 1461 #endif 1462 cmd->c_xferctl = 0; /* XXX correct? */ 1463 1464 return; 1465 } 1466 1467 for (sgte = 0, sg = cmd->c_sgt; 1468 sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) { 1469 len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK; 1470 if (pos < len) { 1471 sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos); 1472 sg->sg_len = htole32(le32toh(sg->sg_len) - pos); 1473 cmd->c_sgfixcnt = pos; 1474 break; 1475 } 1476 pos -= len; 1477 #ifdef DIAGNOSTIC 1478 if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) { 1479 panic("njsc32_set_ptr: bad pos"); 1480 } 1481 #endif 1482 } 1483 #ifdef DIAGNOSTIC 1484 if (sgte >= NJSC32_NUM_SG) 1485 panic("njsc32_set_ptr: bad sg"); 1486 #endif 1487 if (cmd->c_sgoffset != sgte) { 1488 cmd->c_sgoffset = sgte; 1489 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte); 1490 } 1491 1492 /* XXX overkill */ 1493 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1494 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1495 NJSC32_SIZE_SGT, 1496 BUS_DMASYNC_PREWRITE); 1497 } 1498 1499 /* 1500 * save data pointer 1501 */ 1502 static inline void 1503 njsc32_save_ptr(struct njsc32_cmd *cmd) 1504 { 1505 1506 cmd->c_dp_saved = cmd->c_dp_cur; 1507 } 1508 1509 static void 1510 njsc32_assert_ack(struct njsc32_softc *sc) 1511 { 1512 u_int8_t reg; 1513 1514 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1515 reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE; 1516 #if 0 /* needed? */ 1517 reg |= NJSC32_SBCTL_AUTODIRECTION; 1518 #endif 1519 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1520 } 1521 1522 static void 1523 njsc32_negate_ack(struct njsc32_softc *sc) 1524 { 1525 u_int8_t reg; 1526 1527 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1528 #if 0 /* needed? */ 1529 reg |= NJSC32_SBCTL_ACK_ENABLE; 1530 reg |= NJSC32_SBCTL_AUTODIRECTION; 1531 #endif 1532 reg &= ~NJSC32_SBCTL_ACK; 1533 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1534 } 1535 1536 static void 1537 njsc32_wait_req_negate(struct njsc32_softc *sc) 1538 { 1539 int cnt; 1540 1541 for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) { 1542 if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 1543 NJSC32_BUSMON_REQ) == 0) 1544 return; 1545 delay(1); 1546 } 1547 printf("%s: njsc32_wait_req_negate: timed out\n", sc->sc_dev.dv_xname); 1548 } 1549 1550 static void 1551 njsc32_reconnect(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 1552 { 1553 struct scsipi_xfer *xs; 1554 1555 xs = cmd->c_xs; 1556 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1557 callout_stop(&xs->xs_callout); 1558 callout_reset(&xs->xs_callout, 1559 mstohz(xs->timeout), 1560 njsc32_cmdtimeout, cmd); 1561 } 1562 1563 /* Reconnection implies Restore Pointers */ 1564 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1565 } 1566 1567 static enum njsc32_reselstat 1568 njsc32_resel_identify(struct njsc32_softc *sc, int lun, 1569 struct njsc32_cmd **pcmd) 1570 { 1571 int targetid; 1572 struct njsc32_lu *plu; 1573 struct njsc32_cmd *cmd; 1574 1575 switch (sc->sc_stat) { 1576 case NJSC32_STAT_RESEL: 1577 break; /* OK */ 1578 1579 case NJSC32_STAT_RESEL_LUN: 1580 case NJSC32_STAT_RECONNECT: 1581 /* 1582 * accept and ignore if the LUN is the same as the current one, 1583 * reject otherwise. 1584 */ 1585 return sc->sc_resellun == lun ? 1586 NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR; 1587 1588 default: 1589 printf("%s: njsc32_resel_identify: not in reselection\n", 1590 sc->sc_dev.dv_xname); 1591 return NJSC32_RESEL_ERROR; 1592 } 1593 1594 targetid = sc->sc_reselid; 1595 TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n", 1596 sc->sc_dev.dv_xname, lun)); 1597 1598 if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU) 1599 return NJSC32_RESEL_ERROR; 1600 1601 sc->sc_resellun = lun; 1602 plu = &sc->sc_targets[targetid].t_lus[lun]; 1603 1604 if ((cmd = plu->lu_cmd) != NULL) { 1605 sc->sc_stat = NJSC32_STAT_RECONNECT; 1606 plu->lu_cmd = NULL; 1607 *pcmd = cmd; 1608 TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n")); 1609 njsc32_reconnect(sc, cmd); 1610 return NJSC32_RESEL_COMPLETE; 1611 } else if (!TAILQ_EMPTY(&plu->lu_q)) { 1612 /* wait for tag */ 1613 sc->sc_stat = NJSC32_STAT_RESEL_LUN; 1614 return NJSC32_RESEL_THROUGH; 1615 } 1616 1617 /* no disconnected commands */ 1618 return NJSC32_RESEL_ERROR; 1619 } 1620 1621 static enum njsc32_reselstat 1622 njsc32_resel_tag(struct njsc32_softc *sc, int tag, struct njsc32_cmd **pcmd) 1623 { 1624 struct njsc32_cmd_head *head; 1625 struct njsc32_cmd *cmd; 1626 1627 TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n", 1628 sc->sc_dev.dv_xname, tag)); 1629 if (sc->sc_stat != NJSC32_STAT_RESEL_LUN) 1630 return NJSC32_RESEL_ERROR; 1631 1632 head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q; 1633 1634 /* XXX slow? */ 1635 /* search for the command of the tag */ 1636 TAILQ_FOREACH(cmd, head, c_q) { 1637 if (cmd->c_xs->xs_tag_id == tag) { 1638 sc->sc_stat = NJSC32_STAT_RECONNECT; 1639 TAILQ_REMOVE(head, cmd, c_q); 1640 *pcmd = cmd; 1641 TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n")); 1642 njsc32_reconnect(sc, cmd); 1643 return NJSC32_RESEL_COMPLETE; 1644 } 1645 } 1646 1647 /* no disconnected commands */ 1648 return NJSC32_RESEL_ERROR; 1649 } 1650 1651 /* 1652 * Reload parameters and restart AutoSCSI. 1653 * 1654 * XXX autoparam doesn't work as expected and we can't use it here. 1655 */ 1656 static void 1657 njsc32_cmd_reload(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int cctl) 1658 { 1659 struct njsc32_target *target; 1660 1661 target = cmd->c_target; 1662 1663 /* clear parity error and enable parity detection */ 1664 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1665 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1666 1667 /* load parameters */ 1668 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1669 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1670 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1671 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1672 #ifdef NJSC32_DUALEDGE 1673 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1674 cmd->c_xferctl | target->t_xferctl); 1675 #else 1676 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1677 #endif 1678 /* start AutoSCSI */ 1679 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 1680 1681 sc->sc_curcmd = cmd; 1682 } 1683 1684 static void 1685 njsc32_update_xfer_mode(struct njsc32_softc *sc, struct njsc32_target *target) 1686 { 1687 struct scsipi_xfer_mode xm; 1688 1689 xm.xm_target = target - sc->sc_targets; /* target ID */ 1690 xm.xm_mode = 0; 1691 xm.xm_period = target->t_syncperiod; 1692 xm.xm_offset = target->t_syncoffset; 1693 if (xm.xm_offset != 0) 1694 xm.xm_mode |= PERIPH_CAP_SYNC; 1695 if (target->t_flags & NJSC32_TARF_TAG) 1696 xm.xm_mode |= PERIPH_CAP_TQING; 1697 1698 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 1699 } 1700 1701 static void 1702 njsc32_msgin(struct njsc32_softc *sc) 1703 { 1704 u_int8_t msg0, msg; 1705 int msgcnt; 1706 struct njsc32_cmd *cmd; 1707 enum njsc32_reselstat rstat; 1708 int cctl = 0; 1709 u_int32_t ptr; /* unsigned type ensures 2-complement calculation */ 1710 u_int32_t msgout = 0; 1711 bool reload_params = FALSE; 1712 struct njsc32_target *target; 1713 int idx, period, offset; 1714 1715 /* 1716 * we are in Message In, so the previous Message Out should have 1717 * been done. 1718 */ 1719 njsc32_init_msgout(sc); 1720 1721 /* get a byte of Message In */ 1722 msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN); 1723 TPRINTF(("%s: njsc32_msgin: got %#x\n", sc->sc_dev.dv_xname, msg)); 1724 if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN) 1725 sc->sc_msginbuf[sc->sc_msgincnt] = msg; 1726 1727 njsc32_assert_ack(sc); 1728 1729 msg0 = sc->sc_msginbuf[0]; 1730 cmd = sc->sc_curcmd; 1731 1732 /* check for parity error */ 1733 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 1734 NJSC32_PARITYSTATUS_ERROR_LSB) { 1735 1736 printf("%s: msgin: parity error\n", sc->sc_dev.dv_xname); 1737 1738 /* clear parity error */ 1739 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1740 NJSC32_PARITYCTL_CHECK_ENABLE | 1741 NJSC32_PARITYCTL_CLEAR_ERROR); 1742 1743 /* respond as Message Parity Error */ 1744 njsc32_add_msgout(sc, MSG_PARITY_ERROR); 1745 1746 /* clear Message In */ 1747 sc->sc_msgincnt = 0; 1748 goto reply; 1749 } 1750 1751 #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0) 1752 #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0) 1753 if (MSG_ISIDENTIFY(msg0)) { 1754 /* 1755 * Got Identify message from target. 1756 */ 1757 if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG || 1758 (rstat = njsc32_resel_identify(sc, msg0 & 1759 MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) { 1760 /* 1761 * invalid Identify -> Reject 1762 */ 1763 goto reject; 1764 } 1765 if (rstat == NJSC32_RESEL_COMPLETE) 1766 reload_params = TRUE; 1767 MSGCOMPLETE; 1768 } 1769 1770 if (msg0 == MSG_SIMPLE_Q_TAG) { 1771 if (msgcnt == 0) 1772 WAITNEXTMSG; 1773 1774 /* got whole message */ 1775 sc->sc_msgincnt = 0; 1776 1777 if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd)) 1778 == NJSC32_RESEL_ERROR) { 1779 /* 1780 * invalid Simple Queue Tag -> Abort Tag 1781 */ 1782 printf("%s: msgin: invalid tag\n", sc->sc_dev.dv_xname); 1783 njsc32_add_msgout(sc, MSG_ABORT_TAG); 1784 goto reply; 1785 } 1786 if (rstat == NJSC32_RESEL_COMPLETE) 1787 reload_params = TRUE; 1788 MSGCOMPLETE; 1789 } 1790 1791 /* I_T_L or I_T_L_Q nexus should be established now */ 1792 if (cmd == NULL) { 1793 printf("%s: msgin %#x without nexus -- sending abort\n", 1794 sc->sc_dev.dv_xname, msg0); 1795 njsc32_add_msgout(sc, MSG_ABORT); 1796 goto reply; 1797 } 1798 1799 /* 1800 * extended message 1801 * 0x01 <length (0 stands for 256)> <length bytes> 1802 * (<code> [<parameter> ...]) 1803 */ 1804 #define EXTLENOFF 1 1805 #define EXTCODEOFF 2 1806 if (msg0 == MSG_EXTENDED) { 1807 if (msgcnt < EXTLENOFF || 1808 msgcnt < EXTLENOFF + 1 + 1809 (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1)) 1810 WAITNEXTMSG; 1811 1812 /* got whole message */ 1813 sc->sc_msgincnt = 0; 1814 1815 switch (sc->sc_msginbuf[EXTCODEOFF]) { 1816 case 0: /* Modify Data Pointer */ 1817 if (msgcnt != 5 + EXTCODEOFF - 1) 1818 break; 1819 /* 1820 * parameter is 32bit big-endian signed (2-complement) 1821 * value 1822 */ 1823 ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) | 1824 (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) | 1825 (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) | 1826 sc->sc_msginbuf[EXTCODEOFF + 4]; 1827 1828 /* new pointer */ 1829 ptr += cmd->c_dp_cur; /* ignore overflow */ 1830 1831 /* reject if ptr is not in data buffer */ 1832 if (ptr > cmd->c_datacnt) 1833 break; 1834 1835 njsc32_set_ptr(sc, cmd, ptr); 1836 goto restart; 1837 1838 case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */ 1839 DPRINTC(cmd, ("SDTR %#x %#x\n", 1840 sc->sc_msginbuf[EXTCODEOFF + 1], 1841 sc->sc_msginbuf[EXTCODEOFF + 2])); 1842 if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1) 1843 break; /* reject */ 1844 1845 target = cmd->c_target; 1846 1847 /* lookup sync period parameters */ 1848 period = sc->sc_msginbuf[EXTCODEOFF + 1]; 1849 for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++) 1850 if (sc->sc_synct[idx].sp_period >= period) { 1851 period = sc->sc_synct[idx].sp_period; 1852 break; 1853 } 1854 if (idx >= NJSC32_NSYNCT) { 1855 /* 1856 * We can't meet the timing condition that 1857 * the target requests -- use async. 1858 */ 1859 njsc32_target_async(sc, target); 1860 njsc32_update_xfer_mode(sc, target); 1861 if (target->t_state == NJSC32_TARST_SDTR) { 1862 /* 1863 * We started SDTR exchange -- start 1864 * negotiation again and request async. 1865 */ 1866 target->t_state = NJSC32_TARST_ASYNC; 1867 njsc32_negotiate_xfer(sc, target); 1868 goto reply; 1869 } else { 1870 /* 1871 * The target started SDTR exchange 1872 * -- just reject and fallback 1873 * to async. 1874 */ 1875 goto reject; 1876 } 1877 } 1878 1879 /* check sync offset */ 1880 offset = sc->sc_msginbuf[EXTCODEOFF + 2]; 1881 if (offset > NJSC32_SYNCOFFSET_MAX) { 1882 if (target->t_state == NJSC32_TARST_SDTR) { 1883 printf("%s: wrong sync offset: %d\n", 1884 cmd->c_xs->xs_periph->periph_dev->dv_xname, 1885 offset); 1886 /* XXX what to do? */ 1887 } 1888 offset = NJSC32_SYNCOFFSET_MAX; 1889 } 1890 1891 target->t_ackwidth = sc->sc_synct[idx].sp_ackw; 1892 target->t_sample = sc->sc_synct[idx].sp_sample; 1893 target->t_syncperiod = period; 1894 target->t_syncoffset = offset; 1895 target->t_sync = NJSC32_SYNC_VAL(idx, offset); 1896 njsc32_update_xfer_mode(sc, target); 1897 1898 if (target->t_state == NJSC32_TARST_SDTR) { 1899 target->t_state = NJSC32_TARST_DONE; 1900 } else { 1901 njsc32_msgout_sdtr(sc, period, offset); 1902 goto reply; 1903 } 1904 goto restart; 1905 1906 case MSG_EXT_WDTR: /* Wide Data Transfer Request */ 1907 DPRINTC(cmd, 1908 ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1])); 1909 #ifdef NJSC32_DUALEDGE 1910 if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1) 1911 break; /* reject */ 1912 1913 /* 1914 * T->I of this message is not used for 1915 * DualEdge negotiation, so the device 1916 * must not be a DualEdge device. 1917 * 1918 * XXX correct? 1919 */ 1920 target = cmd->c_target; 1921 target->t_xferctl = 0; 1922 1923 switch (target->t_state) { 1924 case NJSC32_TARST_DE: 1925 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1926 MSG_EXT_WDTR_BUS_8_BIT) { 1927 /* 1928 * Oops, we got unexpected WDTR. 1929 * Negotiate for 8bit. 1930 */ 1931 target->t_state = NJSC32_TARST_WDTR; 1932 } else { 1933 target->t_state = NJSC32_TARST_SDTR; 1934 } 1935 njsc32_negotiate_xfer(sc, target); 1936 goto reply; 1937 1938 case NJSC32_TARST_WDTR: 1939 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1940 MSG_EXT_WDTR_BUS_8_BIT) { 1941 printf("%s: unexpected transfer width: %#x\n", 1942 cmd->c_xs->xs_periph->periph_dev->dv_xname, 1943 sc->sc_msginbuf[EXTCODEOFF + 1]); 1944 /* XXX what to do? */ 1945 } 1946 target->t_state = NJSC32_TARST_SDTR; 1947 njsc32_negotiate_xfer(sc, target); 1948 goto reply; 1949 1950 default: 1951 /* the target started WDTR exchange */ 1952 DPRINTC(cmd, ("WDTR from target\n")); 1953 1954 target->t_state = NJSC32_TARST_SDTR; 1955 njsc32_target_async(sc, target); 1956 1957 break; /* reject the WDTR (8bit transfer) */ 1958 } 1959 #endif /* NJSC32_DUALEDGE */ 1960 break; /* reject */ 1961 } 1962 DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n", 1963 sc->sc_msginbuf[EXTCODEOFF], msgcnt)); 1964 goto reject; 1965 } 1966 1967 /* 2byte messages */ 1968 if (MSG_IS2BYTE(msg0)) { 1969 if (msgcnt == 0) 1970 WAITNEXTMSG; 1971 1972 /* got whole message */ 1973 sc->sc_msgincnt = 0; 1974 } 1975 1976 switch (msg0) { 1977 case MSG_CMDCOMPLETE: /* 0x00 */ 1978 case MSG_SAVEDATAPOINTER: /* 0x02 */ 1979 case MSG_DISCONNECT: /* 0x04 */ 1980 /* handled by AutoSCSI */ 1981 PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0)); 1982 break; 1983 1984 case MSG_RESTOREPOINTERS: /* 0x03 */ 1985 /* restore data pointer to what was saved */ 1986 DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n")); 1987 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1988 reload_params = TRUE; 1989 MSGCOMPLETE; 1990 /* NOTREACHED */ 1991 break; 1992 1993 #if 0 /* handled above */ 1994 case MSG_EXTENDED: /* 0x01 */ 1995 #endif 1996 case MSG_MESSAGE_REJECT: /* 0x07 */ 1997 target = cmd->c_target; 1998 DPRINTC(cmd, ("Reject tarst %d\n", target->t_state)); 1999 switch (target->t_state) { 2000 #ifdef NJSC32_DUALEDGE 2001 case NJSC32_TARST_WDTR: 2002 case NJSC32_TARST_DE: 2003 target->t_xferctl = 0; 2004 target->t_state = NJSC32_TARST_SDTR; 2005 njsc32_negotiate_xfer(sc, target); 2006 goto reply; 2007 #endif 2008 case NJSC32_TARST_SDTR: 2009 case NJSC32_TARST_ASYNC: 2010 njsc32_target_async(sc, target); 2011 target->t_state = NJSC32_TARST_DONE; 2012 njsc32_update_xfer_mode(sc, target); 2013 break; 2014 default: 2015 break; 2016 } 2017 goto restart; 2018 2019 case MSG_NOOP: /* 0x08 */ 2020 #ifdef NJSC32_DUALEDGE 2021 target = cmd->c_target; 2022 if (target->t_state == NJSC32_TARST_DE) { 2023 aprint_normal("%s: DualEdge transfer\n", 2024 cmd->c_xs->xs_periph->periph_dev->dv_xname); 2025 target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE; 2026 /* go to next negotiation */ 2027 target->t_state = NJSC32_TARST_SDTR; 2028 njsc32_negotiate_xfer(sc, target); 2029 goto reply; 2030 } 2031 #endif 2032 goto restart; 2033 2034 case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */ 2035 case MSG_ABORT: /* 0x06 I->T only */ 2036 case MSG_PARITY_ERROR: /* 0x09 I->T only */ 2037 case MSG_LINK_CMD_COMPLETE: /* 0x0a */ 2038 case MSG_LINK_CMD_COMPLETEF: /* 0x0b */ 2039 case MSG_BUS_DEV_RESET: /* 0x0c I->T only */ 2040 case MSG_ABORT_TAG: /* 0x0d I->T only */ 2041 case MSG_CLEAR_QUEUE: /* 0x0e I->T only */ 2042 2043 #if 0 /* handled above */ 2044 case MSG_SIMPLE_Q_TAG: /* 0x20 */ 2045 #endif 2046 case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */ 2047 case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */ 2048 case MSG_IGN_WIDE_RESIDUE: /* 0x23 */ 2049 2050 default: 2051 #ifdef NJSC32_DEBUG 2052 PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0)); 2053 if (MSG_IS2BYTE(msg0)) 2054 printf(" %#x", msg); 2055 printf("\n"); 2056 #endif 2057 break; 2058 } 2059 2060 reject: 2061 njsc32_add_msgout(sc, MSG_MESSAGE_REJECT); 2062 2063 reply: 2064 msgout = njsc32_get_auto_msgout(sc); 2065 2066 restart: 2067 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2068 NJSC32_CMD_AUTO_COMMAND_PHASE | 2069 NJSC32_CMD_AUTO_SCSI_RESTART; 2070 2071 /* 2072 * Be careful the second and latter bytes of Message In 2073 * shall not be absorbed by AutoSCSI. 2074 */ 2075 if (sc->sc_msgincnt == 0) 2076 cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2077 2078 if (sc->sc_msgoutlen != 0) 2079 cctl |= NJSC32_CMD_AUTO_ATN; 2080 2081 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout); 2082 2083 /* (re)start AutoSCSI (may assert ATN) */ 2084 if (reload_params) { 2085 njsc32_cmd_reload(sc, cmd, cctl); 2086 } else { 2087 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2088 } 2089 2090 /* +ATN -> -REQ: need 90ns delay? */ 2091 2092 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2093 2094 njsc32_negate_ack(sc); 2095 2096 return; 2097 } 2098 2099 static void 2100 njsc32_msgout(struct njsc32_softc *sc) 2101 { 2102 int cctl; 2103 u_int8_t bus; 2104 unsigned n; 2105 2106 if (sc->sc_msgoutlen == 0) { 2107 /* target entered to Message Out on unexpected timing */ 2108 njsc32_add_msgout(sc, MSG_NOOP); 2109 } 2110 2111 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2112 NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART | 2113 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2114 2115 /* make sure target is in Message Out phase */ 2116 bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR); 2117 if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) { 2118 /* 2119 * Message Out is aborted by target. 2120 */ 2121 printf("%s: njsc32_msgout: phase change %#x\n", 2122 sc->sc_dev.dv_xname, bus); 2123 2124 /* XXX what to do? */ 2125 2126 /* restart AutoSCSI (negate ATN) */ 2127 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2128 2129 sc->sc_msgoutidx = 0; 2130 return; 2131 } 2132 2133 n = sc->sc_msgoutidx; 2134 if (n == sc->sc_msgoutlen - 1) { 2135 /* 2136 * negate ATN before sending ACK 2137 */ 2138 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0); 2139 2140 sc->sc_msgoutidx = 0; /* target may retry Message Out */ 2141 } else { 2142 cctl |= NJSC32_CMD_AUTO_ATN; 2143 sc->sc_msgoutidx++; 2144 } 2145 2146 /* Send Message Out */ 2147 njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]); 2148 2149 /* DBn -> +ACK: need 55ns delay? */ 2150 2151 njsc32_assert_ack(sc); 2152 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2153 2154 /* restart AutoSCSI */ 2155 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2156 2157 njsc32_negate_ack(sc); 2158 2159 /* 2160 * do not reset sc->sc_msgoutlen so the target 2161 * can retry Message Out phase 2162 */ 2163 } 2164 2165 static void 2166 njsc32_cmdtimeout(void *arg) 2167 { 2168 struct njsc32_cmd *cmd = arg; 2169 struct njsc32_softc *sc; 2170 int s; 2171 2172 PRINTC(cmd, ("command timeout\n")); 2173 2174 sc = cmd->c_sc; 2175 2176 s = splbio(); 2177 2178 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2179 njsc32_arbitration_failed(sc); 2180 else { 2181 sc->sc_curcmd = NULL; 2182 sc->sc_stat = NJSC32_STAT_IDLE; 2183 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2184 } 2185 2186 /* XXX? */ 2187 njsc32_init(sc, 1); /* bus reset */ 2188 2189 splx(s); 2190 } 2191 2192 static void 2193 njsc32_reseltimeout(void *arg) 2194 { 2195 struct njsc32_cmd *cmd = arg; 2196 struct njsc32_softc *sc; 2197 int s; 2198 2199 PRINTC(cmd, ("reselection timeout\n")); 2200 2201 sc = cmd->c_sc; 2202 2203 s = splbio(); 2204 2205 /* remove from disconnected list */ 2206 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2207 /* I_T_L_Q */ 2208 KASSERT(cmd->c_lu->lu_cmd == NULL); 2209 TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q); 2210 } else { 2211 /* I_T_L */ 2212 KASSERT(cmd->c_lu->lu_cmd == cmd); 2213 cmd->c_lu->lu_cmd = NULL; 2214 } 2215 2216 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2217 2218 /* XXX? */ 2219 njsc32_init(sc, 1); /* bus reset */ 2220 2221 splx(s); 2222 } 2223 2224 static inline void 2225 njsc32_end_auto(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int auto_phase) 2226 { 2227 struct scsipi_xfer *xs; 2228 2229 if (auto_phase & NJSC32_XPHASE_MSGIN_02) { 2230 /* Message In: 0x02 Save Data Pointer */ 2231 2232 /* 2233 * Adjust saved data pointer 2234 * if the command is not completed yet. 2235 */ 2236 if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 && 2237 (auto_phase & 2238 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) { 2239 njsc32_save_ptr(cmd); 2240 } 2241 TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2242 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2243 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2244 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2245 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT))); 2246 } 2247 2248 xs = cmd->c_xs; 2249 2250 if (auto_phase & NJSC32_XPHASE_MSGIN_00) { 2251 /* Command Complete */ 2252 TPRINTC(cmd, ("njsc32_intr: Command Complete\n")); 2253 switch (xs->status) { 2254 case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY: 2255 /* 2256 * scsipi layer will automatically handle the error 2257 */ 2258 njsc32_end_cmd(sc, cmd, XS_BUSY); 2259 break; 2260 default: 2261 xs->resid -= cmd->c_dp_max; 2262 njsc32_end_cmd(sc, cmd, XS_NOERROR); 2263 break; 2264 } 2265 } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) { 2266 /* Disconnect */ 2267 TPRINTC(cmd, ("njsc32_intr: Disconnect\n")); 2268 2269 /* for ill-designed devices */ 2270 if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0) 2271 njsc32_save_ptr(cmd); 2272 2273 /* 2274 * move current cmd to disconnected list 2275 */ 2276 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2277 /* I_T_L_Q */ 2278 if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD) 2279 TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q); 2280 else 2281 TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q); 2282 } else { 2283 /* I_T_L */ 2284 cmd->c_lu->lu_cmd = cmd; 2285 } 2286 2287 /* 2288 * schedule timeout -- avoid being 2289 * disconnected forever 2290 */ 2291 if ((xs->xs_control & XS_CTL_POLL) == 0) { 2292 callout_stop(&xs->xs_callout); 2293 callout_reset(&xs->xs_callout, mstohz(xs->timeout), 2294 njsc32_reseltimeout, cmd); 2295 } 2296 2297 } else { 2298 /* 2299 * target has come to Bus Free phase 2300 * probably to notify an error 2301 */ 2302 PRINTC(cmd, ("njsc32_intr: unexpected bus free\n")); 2303 /* try Request Sense */ 2304 xs->status = SCSI_CHECK; 2305 njsc32_end_cmd(sc, cmd, XS_BUSY); 2306 } 2307 } 2308 2309 int 2310 njsc32_intr(void *arg) 2311 { 2312 struct njsc32_softc *sc = arg; 2313 u_int16_t intr; 2314 u_int8_t arbstat, bus_phase; 2315 int auto_phase; 2316 int idbit; 2317 struct njsc32_cmd *cmd; 2318 2319 intr = njsc32_read_2(sc, NJSC32_REG_IRQ); 2320 if ((intr & NJSC32_IRQ_INTR_PENDING) == 0) 2321 return 0; /* not mine */ 2322 2323 TPRINTF(("%s: njsc32_intr: %#x\n", sc->sc_dev.dv_xname, intr)); 2324 2325 #if 0 /* I don't think this is required */ 2326 /* mask interrupts */ 2327 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 2328 #endif 2329 2330 /* we got an interrupt, so stop the timer */ 2331 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 2332 2333 if (intr & NJSC32_IRQ_SCSIRESET) { 2334 printf("%s: detected bus reset\n", sc->sc_dev.dv_xname); 2335 /* clear current request */ 2336 njsc32_reset_detected(sc); 2337 goto out; 2338 } 2339 2340 if (sc->sc_stat == NJSC32_STAT_ARBIT) { 2341 cmd = sc->sc_curcmd; 2342 KASSERT(cmd); 2343 arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT); 2344 if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) { 2345 /* 2346 * arbitration done 2347 */ 2348 /* clear arbitration status */ 2349 njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION, 2350 NJSC32_SETARB_CLEAR); 2351 2352 if (arbstat & NJSC32_ARBSTAT_WIN) { 2353 TPRINTC(cmd, 2354 ("njsc32_intr: arbitration won\n")); 2355 2356 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 2357 2358 sc->sc_stat = NJSC32_STAT_CONNECT; 2359 } else { 2360 TPRINTC(cmd, 2361 ("njsc32_intr: arbitration failed\n")); 2362 2363 njsc32_arbitration_failed(sc); 2364 2365 /* XXX delay */ 2366 /* XXX retry counter */ 2367 } 2368 } 2369 } 2370 2371 if (intr & NJSC32_IRQ_TIMER) { 2372 TPRINTF(("%s: njsc32_intr: timer interrupt\n", 2373 sc->sc_dev.dv_xname)); 2374 } 2375 2376 if (intr & NJSC32_IRQ_RESELECT) { 2377 /* Reselection from a target */ 2378 njsc32_arbitration_failed(sc); /* just in case */ 2379 if ((cmd = sc->sc_curcmd) != NULL) { 2380 /* ? */ 2381 printf("%s: unexpected reselection\n", 2382 sc->sc_dev.dv_xname); 2383 sc->sc_curcmd = NULL; 2384 sc->sc_stat = NJSC32_STAT_IDLE; 2385 njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP); 2386 } 2387 2388 idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID); 2389 if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 || 2390 (sc->sc_reselid = 2391 ffs(idbit & ~(1 << NJSC32_INITIATOR_ID)) - 1) < 0) { 2392 printf("%s: invalid reselection (id: %#x)\n", 2393 sc->sc_dev.dv_xname, idbit); 2394 sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */ 2395 } else { 2396 sc->sc_stat = NJSC32_STAT_RESEL; 2397 TPRINTF(("%s: njsc32_intr: reselection from %d\n", 2398 sc->sc_dev.dv_xname, sc->sc_reselid)); 2399 } 2400 } 2401 2402 if (intr & NJSC32_IRQ_PHASE_CHANGE) { 2403 #if 1 /* XXX probably not needed */ 2404 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2405 PRINTC(sc->sc_curcmd, 2406 ("njsc32_intr: cancel arbitration phase\n")); 2407 njsc32_arbitration_failed(sc); 2408 #endif 2409 /* current bus phase */ 2410 bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 2411 NJSC32_BUSMON_PHASE_MASK; 2412 2413 switch (bus_phase) { 2414 case NJSC32_PHASE_MESSAGE_IN: 2415 njsc32_msgin(sc); 2416 break; 2417 2418 /* 2419 * target may suddenly become Status / Bus Free phase 2420 * to notify an error condition 2421 */ 2422 case NJSC32_PHASE_STATUS: 2423 printf("%s: unexpected bus phase: Status\n", 2424 sc->sc_dev.dv_xname); 2425 if ((cmd = sc->sc_curcmd) != NULL) { 2426 cmd->c_xs->status = 2427 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2428 TPRINTC(cmd, ("njsc32_intr: Status %d\n", 2429 cmd->c_xs->status)); 2430 } 2431 break; 2432 case NJSC32_PHASE_BUSFREE: 2433 printf("%s: unexpected bus phase: Bus Free\n", 2434 sc->sc_dev.dv_xname); 2435 if ((cmd = sc->sc_curcmd) != NULL) { 2436 sc->sc_curcmd = NULL; 2437 sc->sc_stat = NJSC32_STAT_IDLE; 2438 if (cmd->c_xs->status != SCSI_QUEUE_FULL && 2439 cmd->c_xs->status != SCSI_BUSY) 2440 cmd->c_xs->status = SCSI_CHECK;/* XXX */ 2441 njsc32_end_cmd(sc, cmd, XS_BUSY); 2442 } 2443 goto out; 2444 default: 2445 #ifdef NJSC32_DEBUG 2446 printf("%s: unexpected bus phase: ", 2447 sc->sc_dev.dv_xname); 2448 switch (bus_phase) { 2449 case NJSC32_PHASE_COMMAND: 2450 printf("Command\n"); break; 2451 case NJSC32_PHASE_MESSAGE_OUT: 2452 printf("Message Out\n");break; 2453 case NJSC32_PHASE_DATA_IN: 2454 printf("Data In\n"); break; 2455 case NJSC32_PHASE_DATA_OUT: 2456 printf("Data Out\n"); break; 2457 case NJSC32_PHASE_RESELECT: 2458 printf("Reselect\n");break; 2459 default: printf("%#x\n", bus_phase); break; 2460 } 2461 #else 2462 printf("%s: unexpected bus phase: %#x", 2463 sc->sc_dev.dv_xname, bus_phase); 2464 #endif 2465 break; 2466 } 2467 } 2468 2469 if (intr & NJSC32_IRQ_AUTOSCSI) { 2470 /* 2471 * AutoSCSI interrupt 2472 */ 2473 auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE); 2474 TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n", 2475 sc->sc_dev.dv_xname, auto_phase)); 2476 njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0); 2477 2478 if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) { 2479 cmd = sc->sc_curcmd; 2480 if (cmd == NULL) { 2481 printf("%s: sel no cmd\n", 2482 sc->sc_dev.dv_xname); 2483 goto out; 2484 } 2485 DPRINTC(cmd, ("njsc32_intr: selection timeout\n")); 2486 2487 sc->sc_curcmd = NULL; 2488 sc->sc_stat = NJSC32_STAT_IDLE; 2489 njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT); 2490 2491 goto out; 2492 } 2493 2494 #ifdef NJSC32_TRACE 2495 if (auto_phase & NJSC32_XPHASE_COMMAND) { 2496 /* Command phase has been automatically processed */ 2497 TPRINTF(("%s: njsc32_intr: Command\n", 2498 sc->sc_dev.dv_xname)); 2499 } 2500 #endif 2501 #ifdef NJSC32_DEBUG 2502 if (auto_phase & NJSC32_XPHASE_ILLEGAL) { 2503 printf("%s: njsc32_intr: Illegal phase\n", 2504 sc->sc_dev.dv_xname); 2505 } 2506 #endif 2507 2508 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) { 2509 TPRINTF(("%s: njsc32_intr: Process Message In\n", 2510 sc->sc_dev.dv_xname)); 2511 njsc32_msgin(sc); 2512 } 2513 2514 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) { 2515 TPRINTF(("%s: njsc32_intr: Process Message Out\n", 2516 sc->sc_dev.dv_xname)); 2517 njsc32_msgout(sc); 2518 } 2519 2520 cmd = sc->sc_curcmd; 2521 if (cmd == NULL) { 2522 TPRINTF(("%s: njsc32_intr: no cmd\n", 2523 sc->sc_dev.dv_xname)); 2524 goto out; 2525 } 2526 2527 if (auto_phase & 2528 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) { 2529 u_int32_t sackcnt, cntoffset; 2530 2531 #ifdef NJSC32_TRACE 2532 if (auto_phase & NJSC32_XPHASE_DATA_IN) 2533 PRINTC(cmd, ("njsc32_intr: data in done\n")); 2534 if (auto_phase & NJSC32_XPHASE_DATA_OUT) 2535 PRINTC(cmd, ("njsc32_intr: data out done\n")); 2536 printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2537 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2538 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2539 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2540 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)); 2541 #endif 2542 2543 /* 2544 * detected parity error on data transfer? 2545 */ 2546 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 2547 (NJSC32_PARITYSTATUS_ERROR_LSB| 2548 NJSC32_PARITYSTATUS_ERROR_MSB)) { 2549 2550 PRINTC(cmd, ("datain: parity error\n")); 2551 2552 /* clear parity error */ 2553 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 2554 NJSC32_PARITYCTL_CHECK_ENABLE | 2555 NJSC32_PARITYCTL_CLEAR_ERROR); 2556 2557 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2558 /* 2559 * XXX command has already finished 2560 * -- what can we do? 2561 * 2562 * It is not clear current command 2563 * caused the error -- reset everything. 2564 */ 2565 njsc32_init(sc, 1); /* XXX */ 2566 } else { 2567 /* XXX does this case occur? */ 2568 #if 1 2569 printf("%s: datain: parity error\n", 2570 sc->sc_dev.dv_xname); 2571 #endif 2572 /* 2573 * Make attention condition and try 2574 * to send Initiator Detected Error 2575 * message. 2576 */ 2577 njsc32_init_msgout(sc); 2578 njsc32_add_msgout(sc, 2579 MSG_INITIATOR_DET_ERR); 2580 njsc32_write_4(sc, 2581 NJSC32_REG_SCSI_MSG_OUT, 2582 njsc32_get_auto_msgout(sc)); 2583 /* restart autoscsi with ATN */ 2584 njsc32_write_2(sc, 2585 NJSC32_REG_COMMAND_CONTROL, 2586 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2587 NJSC32_CMD_AUTO_COMMAND_PHASE | 2588 NJSC32_CMD_AUTO_SCSI_RESTART | 2589 NJSC32_CMD_AUTO_MSGIN_00_04 | 2590 NJSC32_CMD_AUTO_MSGIN_02 | 2591 NJSC32_CMD_AUTO_ATN); 2592 } 2593 goto out; 2594 } 2595 2596 /* 2597 * data has been transferred, and current pointer 2598 * is changed 2599 */ 2600 sackcnt = njsc32_read_4(sc, NJSC32_REG_SACK_CNT); 2601 2602 /* 2603 * The controller returns extra ACK count 2604 * if the DMA buffer is not 4byte aligned. 2605 */ 2606 cntoffset = le32toh(cmd->c_sgt[0].sg_addr) & 3; 2607 #ifdef NJSC32_DEBUG 2608 if (cntoffset != 0) { 2609 printf("sackcnt %u, cntoffset %u\n", 2610 sackcnt, cntoffset); 2611 } 2612 #endif 2613 /* advance SCSI pointer */ 2614 njsc32_set_cur_ptr(cmd, 2615 cmd->c_dp_cur + sackcnt - cntoffset); 2616 } 2617 2618 if (auto_phase & NJSC32_XPHASE_MSGOUT) { 2619 /* Message Out phase has been automatically processed */ 2620 TPRINTC(cmd, ("njsc32_intr: Message Out\n")); 2621 if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 && 2622 sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) { 2623 njsc32_init_msgout(sc); 2624 } 2625 } 2626 2627 if (auto_phase & NJSC32_XPHASE_STATUS) { 2628 /* Status phase has been automatically processed */ 2629 cmd->c_xs->status = 2630 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2631 TPRINTC(cmd, ("njsc32_intr: Status %#x\n", 2632 cmd->c_xs->status)); 2633 } 2634 2635 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2636 /* AutoSCSI is finished */ 2637 2638 TPRINTC(cmd, ("njsc32_intr: Bus Free\n")); 2639 2640 sc->sc_stat = NJSC32_STAT_IDLE; 2641 sc->sc_curcmd = NULL; 2642 2643 njsc32_end_auto(sc, cmd, auto_phase); 2644 } 2645 goto out; 2646 } 2647 2648 if (intr & NJSC32_IRQ_FIFO_THRESHOLD) { 2649 /* XXX We use DMA, and this shouldn't happen */ 2650 printf("%s: njsc32_intr: FIFO\n", sc->sc_dev.dv_xname); 2651 njsc32_init(sc, 1); 2652 goto out; 2653 } 2654 if (intr & NJSC32_IRQ_PCI) { 2655 /* XXX? */ 2656 printf("%s: njsc32_intr: PCI\n", sc->sc_dev.dv_xname); 2657 } 2658 if (intr & NJSC32_IRQ_BMCNTERR) { 2659 /* XXX? */ 2660 printf("%s: njsc32_intr: BM\n", sc->sc_dev.dv_xname); 2661 } 2662 2663 out: 2664 /* go next command if controller is idle */ 2665 if (sc->sc_stat == NJSC32_STAT_IDLE) 2666 njsc32_start(sc); 2667 2668 #if 0 2669 /* enable interrupts */ 2670 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 2671 #endif 2672 2673 return 1; /* processed */ 2674 } 2675
Indexes created Fri Sep 26 08:10:20 GMT 2025