ninjascsi32.c revision 1.16
1 /* $NetBSD: ninjascsi32.c,v 1.16 2008/04/08 12:07:27 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by ITOH Yasufumi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.16 2008/04/08 12:07:27 cegger Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/device.h> 46 #include <sys/kernel.h> 47 #include <sys/buf.h> 48 #include <sys/scsiio.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <sys/intr.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 /* 62 * DualEdge transfer support 63 */ 64 /* #define NJSC32_DUALEDGE */ /* XXX untested */ 65 66 /* 67 * Auto param loading does not work properly (it partially works (works on 68 * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51), 69 * and it doesn't improve the performance so much, 70 * forget about it. 71 */ 72 #undef NJSC32_AUTOPARAM 73 74 #include <dev/ic/ninjascsi32reg.h> 75 #include <dev/ic/ninjascsi32var.h> 76 77 /* #define NJSC32_DEBUG */ 78 /* #define NJSC32_TRACE */ 79 80 #ifdef NJSC32_DEBUG 81 #define DPRINTF(x) printf x 82 #define DPRINTC(cmd, x) PRINTC(cmd, x) 83 #else 84 #define DPRINTF(x) 85 #define DPRINTC(cmd, x) 86 #endif 87 #ifdef NJSC32_TRACE 88 #define TPRINTF(x) printf x 89 #define TPRINTC(cmd, x) PRINTC(cmd, x) 90 #else 91 #define TPRINTF(x) 92 #define TPRINTC(cmd, x) 93 #endif 94 95 #define PRINTC(cmd, x) do { \ 96 scsi_print_addr((cmd)->c_xs->xs_periph); \ 97 printf x; \ 98 } while (/* CONSTCOND */ 0) 99 100 static void njsc32_scsipi_request(struct scsipi_channel *, 101 scsipi_adapter_req_t, void *); 102 static void njsc32_scsipi_minphys(struct buf *); 103 static int njsc32_scsipi_ioctl(struct scsipi_channel *, u_long, void *, 104 int, struct proc *); 105 106 static void njsc32_init(struct njsc32_softc *, int nosleep); 107 static int njsc32_init_cmds(struct njsc32_softc *); 108 static void njsc32_target_async(struct njsc32_softc *, 109 struct njsc32_target *); 110 static void njsc32_init_targets(struct njsc32_softc *); 111 static void njsc32_add_msgout(struct njsc32_softc *, int); 112 static u_int32_t njsc32_get_auto_msgout(struct njsc32_softc *); 113 #ifdef NJSC32_DUALEDGE 114 static void njsc32_msgout_wdtr(struct njsc32_softc *, int); 115 #endif 116 static void njsc32_msgout_sdtr(struct njsc32_softc *, int period, 117 int offset); 118 static void njsc32_negotiate_xfer(struct njsc32_softc *, 119 struct njsc32_target *); 120 static void njsc32_arbitration_failed(struct njsc32_softc *); 121 static void njsc32_start(struct njsc32_softc *); 122 static void njsc32_run_xfer(struct njsc32_softc *, struct scsipi_xfer *); 123 static void njsc32_end_cmd(struct njsc32_softc *, struct njsc32_cmd *, 124 scsipi_xfer_result_t); 125 static void njsc32_wait_reset_release(void *); 126 static void njsc32_reset_bus(struct njsc32_softc *); 127 static void njsc32_clear_cmds(struct njsc32_softc *, 128 scsipi_xfer_result_t); 129 static void njsc32_set_ptr(struct njsc32_softc *, struct njsc32_cmd *, 130 u_int32_t); 131 static void njsc32_assert_ack(struct njsc32_softc *); 132 static void njsc32_negate_ack(struct njsc32_softc *); 133 static void njsc32_wait_req_negate(struct njsc32_softc *); 134 static void njsc32_reconnect(struct njsc32_softc *, struct njsc32_cmd *); 135 enum njsc32_reselstat { 136 NJSC32_RESEL_ERROR, /* to be rejected */ 137 NJSC32_RESEL_COMPLETE, /* reselection is just complete */ 138 NJSC32_RESEL_THROUGH /* this message is OK (no reply) */ 139 }; 140 static enum njsc32_reselstat njsc32_resel_identify(struct njsc32_softc *, 141 int lun, struct njsc32_cmd **); 142 static enum njsc32_reselstat njsc32_resel_tag(struct njsc32_softc *, 143 int tag, struct njsc32_cmd **); 144 static void njsc32_cmd_reload(struct njsc32_softc *, struct njsc32_cmd *, 145 int); 146 static void njsc32_update_xfer_mode(struct njsc32_softc *, 147 struct njsc32_target *); 148 static void njsc32_msgin(struct njsc32_softc *); 149 static void njsc32_msgout(struct njsc32_softc *); 150 static void njsc32_cmdtimeout(void *); 151 static void njsc32_reseltimeout(void *); 152 153 static inline unsigned 154 njsc32_read_1(struct njsc32_softc *sc, int no) 155 { 156 157 return bus_space_read_1(sc->sc_regt, sc->sc_regh, no); 158 } 159 160 static inline unsigned 161 njsc32_read_2(struct njsc32_softc *sc, int no) 162 { 163 164 return bus_space_read_2(sc->sc_regt, sc->sc_regh, no); 165 } 166 167 static inline u_int32_t 168 njsc32_read_4(struct njsc32_softc *sc, int no) 169 { 170 171 return bus_space_read_4(sc->sc_regt, sc->sc_regh, no); 172 } 173 174 static inline void 175 njsc32_write_1(struct njsc32_softc *sc, int no, int val) 176 { 177 178 bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val); 179 } 180 181 static inline void 182 njsc32_write_2(struct njsc32_softc *sc, int no, int val) 183 { 184 185 bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val); 186 } 187 188 static inline void 189 njsc32_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 190 { 191 192 bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val); 193 } 194 195 static inline unsigned 196 njsc32_ireg_read_1(struct njsc32_softc *sc, int no) 197 { 198 199 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 200 return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 201 } 202 203 static inline unsigned 204 njsc32_ireg_read_2(struct njsc32_softc *sc, int no) 205 { 206 207 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 208 return bus_space_read_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 209 } 210 211 static inline u_int32_t 212 njsc32_ireg_read_4(struct njsc32_softc *sc, int no) 213 { 214 u_int32_t val; 215 216 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 217 val = (u_int16_t)bus_space_read_2(sc->sc_regt, sc->sc_regh, 218 NJSC32_REG_DATA_LOW); 219 return val | (bus_space_read_2(sc->sc_regt, sc->sc_regh, 220 NJSC32_REG_DATA_HIGH) << 16); 221 } 222 223 static inline void 224 njsc32_ireg_write_1(struct njsc32_softc *sc, int no, int val) 225 { 226 227 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 228 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 229 } 230 231 static inline void 232 njsc32_ireg_write_2(struct njsc32_softc *sc, int no, int val) 233 { 234 235 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 236 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 237 } 238 239 static inline void 240 njsc32_ireg_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 241 { 242 243 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 244 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 245 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_HIGH, 246 val >> 16); 247 } 248 249 #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */ 250 #ifdef __STDC__ 251 # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK 252 # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \ 253 NJSC32_SREQ_SAMPLING_ENABLE) 254 #else 255 # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK 256 # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \ 257 NJSC32_SREQ_SAMPLING_ENABLE) 258 #endif 259 260 #define NJSC32_NSYNCT_MAXSYNC 1 261 #define NJSC32_NSYNCT 16 262 263 /* 40MHz (25ns) */ 264 static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = { 265 { 0, 0, 0 }, /* dummy for async */ 266 { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */ 267 { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */ 268 { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */ 269 { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */ 270 { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */ 271 { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */ 272 { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 273 { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */ 274 { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 275 { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */ 276 { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */ 277 { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */ 278 { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */ 279 { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */ 280 { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */ 281 }; 282 283 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 284 /* 20MHz (50ns) */ 285 static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = { 286 { 0, 0, 0 }, /* dummy for async */ 287 { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */ 288 { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */ 289 { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 290 { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 291 { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */ 292 { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */ 293 { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */ 294 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */ 295 { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */ 296 { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */ 297 { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */ 298 { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */ 299 { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */ 300 { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */ 301 { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */ 302 }; 303 304 /* 33.3MHz (30ns) */ 305 static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = { 306 { 0, 0, 0 }, /* dummy for async */ 307 { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */ 308 { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */ 309 { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */ 310 { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */ 311 { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */ 312 { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */ 313 { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */ 314 { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */ 315 { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */ 316 { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */ 317 { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */ 318 { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */ 319 { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */ 320 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */ 321 { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */ 322 }; 323 #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */ 324 325 #undef NS 326 #undef ACKW 327 #undef SMPL 328 329 /* initialize device */ 330 static void 331 njsc32_init(struct njsc32_softc *sc, int nosleep) 332 { 333 u_int16_t intstat; 334 int i; 335 336 /* block all interrupts */ 337 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 338 339 /* clear transfer */ 340 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 341 njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0); 342 343 /* make sure interrupts are cleared */ 344 for (i = 0; ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ)) 345 & NJSC32_IRQ_INTR_PENDING) && i < 5 /* just not forever */; i++) { 346 DPRINTF(("%s: njsc32_init: intr pending: %#x\n", 347 device_xname(&sc->sc_dev), intstat)); 348 } 349 350 /* FIFO threshold */ 351 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL, 352 NJSC32_FIFO_FULL_BUSMASTER); 353 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY, 354 NJSC32_FIFO_EMPTY_BUSMASTER); 355 356 /* clock source */ 357 njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk); 358 359 /* memory read multiple */ 360 njsc32_ireg_write_1(sc, NJSC32_IREG_BM, 361 NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD); 362 363 /* clear parity error and enable parity detection */ 364 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 365 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 366 367 /* misc configuration */ 368 njsc32_ireg_write_2(sc, NJSC32_IREG_MISC, 369 NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT | 370 NJSC32_MISC_DELAYED_BMSTART | 371 NJSC32_MISC_MASTER_TERMINATION_SELECT | 372 NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL | 373 NJSC32_MISC_AUTOSEL_TIMING_SEL | 374 NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE); 375 376 /* 377 * Check for termination power (32Bi and some versions of 32UDE). 378 */ 379 if (!nosleep || cold) { 380 DPRINTF(("%s: njsc32_init: checking TERMPWR\n", 381 device_xname(&sc->sc_dev))); 382 383 /* First, turn termination power off */ 384 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0); 385 386 /* give 0.5s to settle */ 387 if (nosleep) 388 delay(500000); 389 else 390 tsleep(sc, PWAIT, "njs_t1", hz / 2); 391 } 392 393 /* supply termination power if not supplied by other devices */ 394 if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) & 395 NJSC32_TERMPWR_SENSE) == 0) { 396 /* termination power is not present on the bus */ 397 if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) { 398 /* 399 * CardBus device must not supply termination power 400 * to avoid excessive power consumption. 401 */ 402 printf("%s: no termination power present\n", 403 device_xname(&sc->sc_dev)); 404 } else { 405 /* supply termination power */ 406 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 407 NJSC32_TERMPWR_BPWR); 408 409 DPRINTF(("%s: supplying termination power\n", 410 device_xname(&sc->sc_dev))); 411 412 /* give 0.5s to settle */ 413 if (!nosleep) 414 tsleep(sc, PWAIT, "njs_t2", hz / 2); 415 } 416 } 417 418 /* stop timer */ 419 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 420 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 421 422 /* default transfer parameter */ 423 njsc32_write_1(sc, NJSC32_REG_SYNC, 0); 424 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK); 425 njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT, 426 NJSC32_SEL_TIMEOUT_TIME); 427 428 /* select interrupt source */ 429 njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT, 430 NJSC32_IRQSEL_RESELECT | 431 NJSC32_IRQSEL_PHASE_CHANGE | 432 NJSC32_IRQSEL_SCSIRESET | 433 NJSC32_IRQSEL_TIMER | 434 NJSC32_IRQSEL_FIFO_THRESHOLD | 435 NJSC32_IRQSEL_TARGET_ABORT | 436 NJSC32_IRQSEL_MASTER_ABORT | 437 /* XXX not yet 438 NJSC32_IRQSEL_SERR | 439 NJSC32_IRQSEL_PERR | 440 NJSC32_IRQSEL_BMCNTERR | 441 */ 442 NJSC32_IRQSEL_AUTO_SCSI_SEQ); 443 444 /* interrupts will be unblocked later after bus reset */ 445 446 /* turn LED off */ 447 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR, 448 NJSC32_EXTPORT_LED_OFF); 449 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, 450 NJSC32_EXTPORT_LED_OFF); 451 452 /* reset SCSI bus so the targets become known state */ 453 njsc32_reset_bus(sc); 454 } 455 456 static int 457 njsc32_init_cmds(struct njsc32_softc *sc) 458 { 459 struct njsc32_cmd *cmd; 460 bus_addr_t dmaaddr; 461 int i, error; 462 463 /* 464 * allocate DMA area for command 465 */ 466 if ((error = bus_dmamem_alloc(sc->sc_dmat, 467 sizeof(struct njsc32_dma_page), PAGE_SIZE, 0, 468 &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) { 469 aprint_error_dev(&sc->sc_dev, "unable to allocate cmd page, error = %d\n", 470 error); 471 return 0; 472 } 473 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg, 474 sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page), 475 (void **)&sc->sc_cmdpg, 476 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 477 aprint_error_dev(&sc->sc_dev, "unable to map cmd page, error = %d\n", 478 error); 479 goto fail1; 480 } 481 if ((error = bus_dmamap_create(sc->sc_dmat, 482 sizeof(struct njsc32_dma_page), 1, 483 sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT, 484 &sc->sc_dmamap_cmdpg)) != 0) { 485 aprint_error_dev(&sc->sc_dev, "unable to create cmd DMA map, error = %d\n", 486 error); 487 goto fail2; 488 } 489 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg, 490 sc->sc_cmdpg, sizeof(struct njsc32_dma_page), 491 NULL, BUS_DMA_NOWAIT)) != 0) { 492 aprint_error_dev(&sc->sc_dev, "unable to load cmd DMA map, error = %d\n", 493 error); 494 goto fail3; 495 } 496 497 memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page)); 498 dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr; 499 500 #ifdef NJSC32_AUTOPARAM 501 sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap); 502 #endif 503 504 for (i = 0; i < NJSC32_NUM_CMD; i++) { 505 cmd = &sc->sc_cmds[i]; 506 cmd->c_sc = sc; 507 cmd->c_sgt = sc->sc_cmdpg->dp_sg[i]; 508 cmd->c_sgt_dma = dmaaddr + 509 offsetof(struct njsc32_dma_page, dp_sg[i]); 510 cmd->c_flags = 0; 511 512 error = bus_dmamap_create(sc->sc_dmat, 513 NJSC32_MAX_XFER, /* max total map size */ 514 NJSC32_NUM_SG, /* max number of segments */ 515 NJSC32_SGT_MAXSEGLEN, /* max size of a segment */ 516 0, /* boundary */ 517 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer); 518 if (error) { 519 aprint_error_dev(&sc->sc_dev, "only %d cmd descs available (error = %d)\n", 520 i, error); 521 break; 522 } 523 TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q); 524 } 525 526 if (i > 0) 527 return i; 528 529 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 530 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 531 fail2: bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cmdpg, 532 sizeof(struct njsc32_dma_page)); 533 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs); 534 535 return 0; 536 } 537 538 static void 539 njsc32_target_async(struct njsc32_softc *sc, struct njsc32_target *target) 540 { 541 542 target->t_sync = 543 NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC); 544 target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK; 545 target->t_sample = 0; /* disable */ 546 target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC; 547 target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC; 548 } 549 550 static void 551 njsc32_init_targets(struct njsc32_softc *sc) 552 { 553 int id, lun; 554 struct njsc32_lu *lu; 555 556 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 557 /* cancel negotiation status */ 558 sc->sc_targets[id].t_state = NJSC32_TARST_INIT; 559 560 /* default to async mode */ 561 njsc32_target_async(sc, &sc->sc_targets[id]); 562 563 #ifdef NJSC32_DUALEDGE 564 sc->sc_targets[id].t_xferctl = 0; 565 #endif 566 567 sc->sc_targets[id].t_targetid = 568 (1 << id) | (1 << NJSC32_INITIATOR_ID); 569 570 /* init logical units */ 571 for (lun = 0; lun < NJSC32_NLU; lun++) { 572 lu = &sc->sc_targets[id].t_lus[lun]; 573 lu->lu_cmd = NULL; 574 TAILQ_INIT(&lu->lu_q); 575 } 576 } 577 } 578 579 void 580 njsc32_attach(struct njsc32_softc *sc) 581 { 582 const char *str; 583 #if 1 /* test */ 584 int reg; 585 njsc32_model_t detected_model; 586 #endif 587 588 /* init */ 589 TAILQ_INIT(&sc->sc_freecmd); 590 TAILQ_INIT(&sc->sc_reqcmd); 591 callout_init(&sc->sc_callout, 0); 592 593 #if 1 /* test */ 594 /* 595 * try to distinguish 32Bi and 32UDE 596 */ 597 /* try to set DualEdge bit (exists on 32UDE only) and read it back */ 598 njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE); 599 if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) { 600 /* device was removed? */ 601 aprint_error_dev(&sc->sc_dev, "attach failed\n"); 602 return; 603 } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) { 604 detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE; 605 } else { 606 detected_model = NJSC32_MODEL_32BI; 607 } 608 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */ 609 610 #if 1/*def DIAGNOSTIC*/ 611 /* compare what is configured with what is detected */ 612 if ((sc->sc_model & NJSC32_MODEL_MASK) != 613 (detected_model & NJSC32_MODEL_MASK)) { 614 /* 615 * Please report this error if it happens. 616 */ 617 aprint_error_dev(&sc->sc_dev, "model mismatch: %#x vs %#x\n", 618 sc->sc_model, detected_model); 619 return; 620 } 621 #endif 622 #endif 623 624 /* check model */ 625 switch (sc->sc_model & NJSC32_MODEL_MASK) { 626 case NJSC32_MODEL_32BI: 627 str = "Bi"; 628 /* 32Bi doesn't support DualEdge transfer */ 629 KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0); 630 break; 631 case NJSC32_MODEL_32UDE: 632 str = "UDE"; 633 break; 634 default: 635 aprint_error_dev(&sc->sc_dev, "unknown model!\n"); 636 return; 637 } 638 aprint_normal_dev(&sc->sc_dev, "NJSC-32%s", str); 639 640 switch (sc->sc_clk) { 641 default: 642 #ifdef DIAGNOSTIC 643 panic("njsc32_attach: unknown clk %d", sc->sc_clk); 644 #endif 645 case NJSC32_CLOCK_DIV_4: 646 sc->sc_synct = njsc32_synct_40M; 647 str = "40MHz"; 648 break; 649 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 650 case NJSC32_CLOCK_DIV_2: 651 sc->sc_synct = njsc32_synct_20M; 652 str = "20MHz"; 653 break; 654 case NJSC32_CLOCK_PCICLK: 655 sc->sc_synct = njsc32_synct_pci; 656 str = "PCI"; 657 break; 658 #endif 659 } 660 aprint_normal(", G/A rev %#x, clk %s%s\n", 661 NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str, 662 (sc->sc_model & NJSC32_FLAG_DUALEDGE) ? 663 #ifdef NJSC32_DUALEDGE 664 ", DualEdge" 665 #else 666 ", DualEdge (no driver support)" 667 #endif 668 : ""); 669 670 /* allocate DMA resource */ 671 if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) { 672 aprint_error_dev(&sc->sc_dev, "no usable DMA map\n"); 673 return; 674 } 675 sc->sc_flags |= NJSC32_CMDPG_MAPPED; 676 677 sc->sc_curcmd = NULL; 678 sc->sc_nusedcmds = 0; 679 680 sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */ 681 682 /* initialize hardware and target structure */ 683 njsc32_init(sc, cold); 684 685 /* setup adapter */ 686 sc->sc_adapter.adapt_dev = &sc->sc_dev; 687 sc->sc_adapter.adapt_nchannels = 1; 688 sc->sc_adapter.adapt_request = njsc32_scsipi_request; 689 sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys; 690 sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl; 691 692 sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings = 693 sc->sc_ncmd; 694 695 /* setup channel */ 696 sc->sc_channel.chan_adapter = &sc->sc_adapter; 697 sc->sc_channel.chan_bustype = &scsi_bustype; 698 sc->sc_channel.chan_channel = 0; 699 sc->sc_channel.chan_ntargets = NJSC32_NTARGET; 700 sc->sc_channel.chan_nluns = NJSC32_NLU; 701 sc->sc_channel.chan_id = NJSC32_INITIATOR_ID; 702 703 sc->sc_scsi = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 704 } 705 706 int 707 njsc32_detach(struct njsc32_softc *sc, int flags) 708 { 709 int rv = 0; 710 int i, s; 711 struct njsc32_cmd *cmd; 712 713 callout_stop(&sc->sc_callout); 714 715 s = splbio(); 716 717 /* clear running/disconnected commands */ 718 njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP); 719 720 sc->sc_stat = NJSC32_STAT_DETACH; 721 722 /* clear pending commands */ 723 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 724 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 725 njsc32_end_cmd(sc, cmd, XS_RESET); 726 } 727 728 if (sc->sc_scsi != NULL) 729 rv = config_detach(sc->sc_scsi, flags); 730 731 splx(s); 732 733 /* free DMA resource */ 734 if (sc->sc_flags & NJSC32_CMDPG_MAPPED) { 735 for (i = 0; i < sc->sc_ncmd; i++) { 736 cmd = &sc->sc_cmds[i]; 737 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) 738 bus_dmamap_unload(sc->sc_dmat, 739 cmd->c_dmamap_xfer); 740 bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer); 741 } 742 743 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 744 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 745 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cmdpg, 746 sizeof(struct njsc32_dma_page)); 747 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, 748 sc->sc_cmdpg_nsegs); 749 } 750 751 return 0; 752 } 753 754 static inline void 755 njsc32_cmd_init(struct njsc32_cmd *cmd) 756 { 757 758 cmd->c_flags = 0; 759 760 /* scatter/gather table */ 761 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0); 762 cmd->c_sgoffset = 0; 763 cmd->c_sgfixcnt = 0; 764 765 /* data pointer */ 766 cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0; 767 } 768 769 static inline void 770 njsc32_init_msgout(struct njsc32_softc *sc) 771 { 772 773 sc->sc_msgoutlen = 0; 774 sc->sc_msgoutidx = 0; 775 } 776 777 static void 778 njsc32_add_msgout(struct njsc32_softc *sc, int byte) 779 { 780 781 if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) { 782 printf("njsc32_add_msgout: too many\n"); 783 return; 784 } 785 sc->sc_msgout[sc->sc_msgoutlen++] = byte; 786 } 787 788 static u_int32_t 789 njsc32_get_auto_msgout(struct njsc32_softc *sc) 790 { 791 u_int32_t val; 792 u_int8_t *p; 793 794 val = 0; 795 p = sc->sc_msgout; 796 switch (sc->sc_msgoutlen) { 797 /* 31-24 23-16 15-8 7 ... 1 0 */ 798 case 3: /* MSG3 MSG2 MSG1 V --- cnt */ 799 val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT; 800 /* FALLTHROUGH */ 801 802 case 2: /* MSG2 MSG1 --- V --- cnt */ 803 val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT; 804 /* FALLTHROUGH */ 805 806 case 1: /* MSG1 --- --- V --- cnt */ 807 val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT; 808 val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen; 809 break; 810 811 default: 812 break; 813 } 814 return val; 815 } 816 817 #ifdef NJSC32_DUALEDGE 818 /* add Wide Data Transfer Request to the next Message Out */ 819 static void 820 njsc32_msgout_wdtr(struct njsc32_softc *sc, int width) 821 { 822 823 njsc32_add_msgout(sc, MSG_EXTENDED); 824 njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN); 825 njsc32_add_msgout(sc, MSG_EXT_WDTR); 826 njsc32_add_msgout(sc, width); 827 } 828 #endif 829 830 /* add Synchronous Data Transfer Request to the next Message Out */ 831 static void 832 njsc32_msgout_sdtr(struct njsc32_softc *sc, int period, int offset) 833 { 834 835 njsc32_add_msgout(sc, MSG_EXTENDED); 836 njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN); 837 njsc32_add_msgout(sc, MSG_EXT_SDTR); 838 njsc32_add_msgout(sc, period); 839 njsc32_add_msgout(sc, offset); 840 } 841 842 static void 843 njsc32_negotiate_xfer(struct njsc32_softc *sc, struct njsc32_target *target) 844 { 845 846 /* initial negotiation state */ 847 if (target->t_state == NJSC32_TARST_INIT) { 848 #ifdef NJSC32_DUALEDGE 849 if (target->t_flags & NJSC32_TARF_DE) 850 target->t_state = NJSC32_TARST_DE; 851 else 852 #endif 853 if (target->t_flags & NJSC32_TARF_SYNC) 854 target->t_state = NJSC32_TARST_SDTR; 855 else 856 target->t_state = NJSC32_TARST_DONE; 857 } 858 859 switch (target->t_state) { 860 default: 861 case NJSC32_TARST_INIT: 862 #ifdef DIAGNOSTIC 863 panic("njsc32_negotiate_xfer"); 864 /* NOTREACHED */ 865 #endif 866 /* FALLTHROUGH */ 867 case NJSC32_TARST_DONE: 868 /* no more work */ 869 break; 870 871 #ifdef NJSC32_DUALEDGE 872 case NJSC32_TARST_DE: 873 njsc32_msgout_wdtr(sc, 0xde /* XXX? */); 874 break; 875 876 case NJSC32_TARST_WDTR: 877 njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT); 878 break; 879 #endif 880 881 case NJSC32_TARST_SDTR: 882 njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period, 883 NJSC32_SYNCOFFSET_MAX); 884 break; 885 886 case NJSC32_TARST_ASYNC: 887 njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC, 888 NJSC32_SYNCOFFSET_ASYNC); 889 break; 890 } 891 } 892 893 /* turn LED on */ 894 static inline void 895 njsc32_led_on(struct njsc32_softc *sc) 896 { 897 898 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON); 899 } 900 901 /* turn LED off */ 902 static inline void 903 njsc32_led_off(struct njsc32_softc *sc) 904 { 905 906 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF); 907 } 908 909 static void 910 njsc32_arbitration_failed(struct njsc32_softc *sc) 911 { 912 struct njsc32_cmd *cmd; 913 914 if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT) 915 return; 916 917 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) 918 callout_stop(&cmd->c_xs->xs_callout); 919 920 sc->sc_stat = NJSC32_STAT_IDLE; 921 sc->sc_curcmd = NULL; 922 923 /* the command is no longer active */ 924 if (--sc->sc_nusedcmds == 0) 925 njsc32_led_off(sc); 926 } 927 928 static inline void 929 njsc32_cmd_load(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 930 { 931 struct njsc32_target *target; 932 struct scsipi_xfer *xs; 933 int i, control, lun; 934 u_int32_t msgoutreg; 935 #ifdef NJSC32_AUTOPARAM 936 struct njsc32_autoparam *ap; 937 #endif 938 939 xs = cmd->c_xs; 940 #ifdef NJSC32_AUTOPARAM 941 ap = &sc->sc_cmdpg->dp_ap; 942 #else 943 /* reset CDB pointer */ 944 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR); 945 #endif 946 947 /* CDB */ 948 TPRINTC(cmd, ("njsc32_cmd_load: CDB")); 949 for (i = 0; i < xs->cmdlen; i++) { 950 #ifdef NJSC32_AUTOPARAM 951 ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i]; 952 #else 953 njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA, 954 ((u_int8_t *)xs->cmd)[i]); 955 #endif 956 TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i])); 957 } 958 #ifdef NJSC32_AUTOPARAM /* XXX needed? */ 959 for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++) 960 ap->ap_cdb[i].cdb_data = 0; 961 #endif 962 963 control = xs->xs_control; 964 965 /* 966 * Message Out 967 */ 968 njsc32_init_msgout(sc); 969 970 /* Identify */ 971 lun = xs->xs_periph->periph_lun; 972 njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ? 973 MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1)); 974 975 /* tagged queueing */ 976 if (control & XS_CTL_TAGMASK) { 977 njsc32_add_msgout(sc, xs->xs_tag_type); 978 njsc32_add_msgout(sc, xs->xs_tag_id); 979 TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id)); 980 } 981 TPRINTF(("\n")); 982 983 target = cmd->c_target; 984 985 /* transfer negotiation */ 986 if (control & XS_CTL_REQSENSE) 987 target->t_state = NJSC32_TARST_INIT; 988 njsc32_negotiate_xfer(sc, target); 989 990 msgoutreg = njsc32_get_auto_msgout(sc); 991 992 #ifdef NJSC32_AUTOPARAM 993 ap->ap_msgout = htole32(msgoutreg); 994 995 ap->ap_sync = target->t_sync; 996 ap->ap_ackwidth = target->t_ackwidth; 997 ap->ap_targetid = target->t_targetid; 998 ap->ap_sample = target->t_sample; 999 1000 ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 1001 NJSC32_CMD_AUTO_COMMAND_PHASE | 1002 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1003 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1004 #ifdef NJSC32_DUALEDGE 1005 ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl); 1006 #else 1007 ap->ap_xferctl = htole16(cmd->c_xferctl); 1008 #endif 1009 ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr); 1010 1011 /* sync njsc32_autoparam */ 1012 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1013 offsetof(struct njsc32_dma_page, dp_ap), /* offset */ 1014 sizeof(struct njsc32_autoparam), 1015 BUS_DMASYNC_PREWRITE); 1016 1017 /* autoparam DMA address */ 1018 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma); 1019 1020 /* start command (autoparam) */ 1021 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1022 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER); 1023 1024 #else /* not NJSC32_AUTOPARAM */ 1025 1026 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg); 1027 1028 /* load parameters */ 1029 njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid); 1030 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1031 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1032 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1033 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1034 #ifdef NJSC32_DUALEDGE 1035 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1036 cmd->c_xferctl | target->t_xferctl); 1037 #else 1038 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1039 #endif 1040 /* start AutoSCSI */ 1041 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1042 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE | 1043 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1044 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1045 #endif /* not NJSC32_AUTOPARAM */ 1046 } 1047 1048 /* Note: must be called at splbio() */ 1049 static void 1050 njsc32_start(struct njsc32_softc *sc) 1051 { 1052 struct njsc32_cmd *cmd; 1053 1054 /* get a command to issue */ 1055 TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) { 1056 if (cmd->c_lu->lu_cmd == NULL && 1057 ((cmd->c_flags & NJSC32_CMD_TAGGED) || 1058 TAILQ_EMPTY(&cmd->c_lu->lu_q))) 1059 break; /* OK, the logical unit is free */ 1060 } 1061 if (!cmd) 1062 goto out; /* no work to do */ 1063 1064 /* request will always fail if not in bus free phase */ 1065 if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) != 1066 NJSC32_BUSMON_BUSFREE) 1067 goto busy; 1068 1069 /* clear parity error and enable parity detection */ 1070 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1071 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1072 1073 njsc32_cmd_load(sc, cmd); 1074 1075 if (sc->sc_nusedcmds++ == 0) 1076 njsc32_led_on(sc); 1077 1078 sc->sc_curcmd = cmd; 1079 sc->sc_stat = NJSC32_STAT_ARBIT; 1080 1081 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) { 1082 callout_reset(&cmd->c_xs->xs_callout, 1083 mstohz(cmd->c_xs->timeout), 1084 njsc32_cmdtimeout, cmd); 1085 } 1086 1087 return; 1088 1089 busy: /* XXX retry counter */ 1090 TPRINTF(("%s: njsc32_start: busy\n", device_xname(&sc->sc_dev))); 1091 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME); 1092 out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 1093 } 1094 1095 static void 1096 njsc32_run_xfer(struct njsc32_softc *sc, struct scsipi_xfer *xs) 1097 { 1098 struct scsipi_periph *periph; 1099 int control; 1100 int lun; 1101 struct njsc32_cmd *cmd; 1102 int s, i, error; 1103 1104 periph = xs->xs_periph; 1105 KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID); 1106 1107 control = xs->xs_control; 1108 lun = periph->periph_lun; 1109 1110 /* 1111 * get a free cmd 1112 * (scsipi layer knows the number of cmds, so this shall never fail) 1113 */ 1114 s = splbio(); 1115 cmd = TAILQ_FIRST(&sc->sc_freecmd); 1116 KASSERT(cmd); 1117 TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q); 1118 splx(s); 1119 1120 /* 1121 * build a request 1122 */ 1123 njsc32_cmd_init(cmd); 1124 cmd->c_xs = xs; 1125 cmd->c_target = &sc->sc_targets[periph->periph_target]; 1126 cmd->c_lu = &cmd->c_target->t_lus[lun]; 1127 1128 /* tagged queueing */ 1129 if (control & XS_CTL_TAGMASK) { 1130 cmd->c_flags |= NJSC32_CMD_TAGGED; 1131 if (control & XS_CTL_HEAD_TAG) 1132 cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD; 1133 } 1134 1135 /* map DMA buffer */ 1136 cmd->c_datacnt = xs->datalen; 1137 if (xs->datalen) { 1138 /* Is XS_CTL_DATA_UIO ever used anywhere? */ 1139 KASSERT((control & XS_CTL_DATA_UIO) == 0); 1140 1141 error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer, 1142 xs->data, xs->datalen, NULL, 1143 ((control & XS_CTL_NOSLEEP) ? 1144 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 1145 BUS_DMA_STREAMING | 1146 ((control & XS_CTL_DATA_IN) ? 1147 BUS_DMA_READ : BUS_DMA_WRITE)); 1148 1149 switch (error) { 1150 case 0: 1151 break; 1152 case ENOMEM: 1153 case EAGAIN: 1154 xs->error = XS_RESOURCE_SHORTAGE; 1155 goto map_failed; 1156 default: 1157 xs->error = XS_DRIVER_STUFFUP; 1158 map_failed: 1159 aprint_error_dev(&sc->sc_dev, "njsc32_run_xfer: map failed, error %d\n", 1160 error); 1161 /* put it back to free command list */ 1162 s = splbio(); 1163 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1164 splx(s); 1165 /* abort this transfer */ 1166 scsipi_done(xs); 1167 return; 1168 } 1169 1170 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1171 0, cmd->c_dmamap_xfer->dm_mapsize, 1172 (control & XS_CTL_DATA_IN) ? 1173 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1174 1175 for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) { 1176 cmd->c_sgt[i].sg_addr = 1177 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr); 1178 cmd->c_sgt[i].sg_len = 1179 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len); 1180 } 1181 /* end mark */ 1182 cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK); 1183 1184 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1185 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1186 NJSC32_SIZE_SGT, 1187 BUS_DMASYNC_PREWRITE); 1188 1189 cmd->c_flags |= NJSC32_CMD_DMA_MAPPED; 1190 1191 /* enable transfer */ 1192 cmd->c_xferctl = 1193 NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START | 1194 NJSC32_XFR_ALL_COUNT_CLR; 1195 1196 /* XXX How can we specify the DMA direction? */ 1197 1198 #if 0 /* faster write mode? (doesn't work) */ 1199 if ((control & XS_CTL_DATA_IN) == 0) 1200 cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE; 1201 #endif 1202 } else { 1203 /* no data transfer */ 1204 cmd->c_xferctl = 0; 1205 } 1206 1207 /* queue request */ 1208 s = splbio(); 1209 TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q); 1210 1211 /* start the controller if idle */ 1212 if (sc->sc_stat == NJSC32_STAT_IDLE) 1213 njsc32_start(sc); 1214 1215 splx(s); 1216 1217 if (control & XS_CTL_POLL) { 1218 /* wait for completion */ 1219 /* XXX should handle timeout? */ 1220 while ((xs->xs_status & XS_STS_DONE) == 0) { 1221 delay(1000); 1222 njsc32_intr(sc); 1223 } 1224 } 1225 } 1226 1227 static void 1228 njsc32_end_cmd(struct njsc32_softc *sc, struct njsc32_cmd *cmd, 1229 scsipi_xfer_result_t result) 1230 { 1231 struct scsipi_xfer *xs; 1232 int s; 1233 #ifdef DIAGNOSTIC 1234 struct njsc32_cmd *c; 1235 #endif 1236 1237 KASSERT(cmd); 1238 1239 #ifdef DIAGNOSTIC 1240 s = splbio(); 1241 TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) { 1242 if (cmd == c) 1243 panic("njsc32_end_cmd: already in free list"); 1244 } 1245 splx(s); 1246 #endif 1247 xs = cmd->c_xs; 1248 1249 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) { 1250 if (cmd->c_datacnt) { 1251 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1252 0, cmd->c_dmamap_xfer->dm_mapsize, 1253 (xs->xs_control & XS_CTL_DATA_IN) ? 1254 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1255 1256 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1257 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, 1258 NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE); 1259 } 1260 1261 bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer); 1262 cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED; 1263 } 1264 1265 s = splbio(); 1266 if ((xs->xs_control & XS_CTL_POLL) == 0) 1267 callout_stop(&xs->xs_callout); 1268 1269 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1270 splx(s); 1271 1272 xs->error = result; 1273 scsipi_done(xs); 1274 1275 if (--sc->sc_nusedcmds == 0) 1276 njsc32_led_off(sc); 1277 } 1278 1279 /* 1280 * request from scsipi layer 1281 */ 1282 static void 1283 njsc32_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1284 void *arg) 1285 { 1286 struct njsc32_softc *sc; 1287 struct scsipi_xfer_mode *xm; 1288 struct njsc32_target *target; 1289 1290 sc = (void *)chan->chan_adapter->adapt_dev; 1291 1292 switch (req) { 1293 case ADAPTER_REQ_RUN_XFER: 1294 njsc32_run_xfer(sc, arg); 1295 break; 1296 1297 case ADAPTER_REQ_GROW_RESOURCES: 1298 /* not supported */ 1299 break; 1300 1301 case ADAPTER_REQ_SET_XFER_MODE: 1302 xm = arg; 1303 target = &sc->sc_targets[xm->xm_target]; 1304 1305 target->t_flags = 0; 1306 if (xm->xm_mode & PERIPH_CAP_TQING) 1307 target->t_flags |= NJSC32_TARF_TAG; 1308 if (xm->xm_mode & PERIPH_CAP_SYNC) { 1309 target->t_flags |= NJSC32_TARF_SYNC; 1310 #ifdef NJSC32_DUALEDGE 1311 if (sc->sc_model & NJSC32_FLAG_DUALEDGE) 1312 target->t_flags |= NJSC32_TARF_DE; 1313 #endif 1314 } 1315 #ifdef NJSC32_DUALEDGE 1316 target->t_xferctl = 0; 1317 #endif 1318 target->t_state = NJSC32_TARST_INIT; 1319 njsc32_target_async(sc, target); 1320 1321 break; 1322 default: 1323 break; 1324 } 1325 } 1326 1327 static void 1328 njsc32_scsipi_minphys(struct buf *bp) 1329 { 1330 1331 if (bp->b_bcount > NJSC32_MAX_XFER) 1332 bp->b_bcount = NJSC32_MAX_XFER; 1333 minphys(bp); 1334 } 1335 1336 /* 1337 * On some versions of 32UDE (probably the earlier ones), the controller 1338 * detects continuous bus reset when the termination power is absent. 1339 * Make sure the system won't hang on such situation. 1340 */ 1341 static void 1342 njsc32_wait_reset_release(void *arg) 1343 { 1344 struct njsc32_softc *sc = arg; 1345 struct njsc32_cmd *cmd; 1346 1347 /* clear pending commands */ 1348 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 1349 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 1350 njsc32_end_cmd(sc, cmd, XS_RESET); 1351 } 1352 1353 /* If Bus Reset is not released yet, schedule recheck. */ 1354 if (njsc32_read_2(sc, NJSC32_REG_IRQ) & NJSC32_IRQ_SCSIRESET) { 1355 switch (sc->sc_stat) { 1356 case NJSC32_STAT_RESET: 1357 sc->sc_stat = NJSC32_STAT_RESET1; 1358 break; 1359 case NJSC32_STAT_RESET1: 1360 /* print message if Bus Reset is detected twice */ 1361 sc->sc_stat = NJSC32_STAT_RESET2; 1362 printf("%s: detected excessive bus reset --- missing termination power?\n", 1363 device_xname(&sc->sc_dev)); 1364 break; 1365 default: 1366 break; 1367 } 1368 callout_reset(&sc->sc_callout, 1369 hz * 2 /* poll every 2s */, 1370 njsc32_wait_reset_release, sc); 1371 return; 1372 } 1373 1374 if (sc->sc_stat == NJSC32_STAT_RESET2) 1375 printf("%s: bus reset is released\n", device_xname(&sc->sc_dev)); 1376 1377 /* unblock interrupts */ 1378 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 1379 1380 sc->sc_stat = NJSC32_STAT_IDLE; 1381 } 1382 1383 static void 1384 njsc32_reset_bus(struct njsc32_softc *sc) 1385 { 1386 int s; 1387 1388 DPRINTF(("%s: njsc32_reset_bus:\n", device_xname(&sc->sc_dev))); 1389 1390 /* block interrupts */ 1391 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 1392 1393 sc->sc_stat = NJSC32_STAT_RESET; 1394 1395 /* hold SCSI bus reset */ 1396 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST); 1397 delay(NJSC32_RESET_HOLD_TIME); 1398 1399 /* clear transfer */ 1400 njsc32_clear_cmds(sc, XS_RESET); 1401 1402 /* initialize target structure */ 1403 njsc32_init_targets(sc); 1404 1405 s = splbio(); 1406 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL); 1407 splx(s); 1408 1409 /* release SCSI bus reset */ 1410 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0); 1411 1412 njsc32_wait_reset_release(sc); 1413 } 1414 1415 /* 1416 * clear running/disconnected commands 1417 */ 1418 static void 1419 njsc32_clear_cmds(struct njsc32_softc *sc, scsipi_xfer_result_t cmdresult) 1420 { 1421 struct njsc32_cmd *cmd; 1422 int id, lun; 1423 struct njsc32_lu *lu; 1424 1425 njsc32_arbitration_failed(sc); 1426 1427 /* clear current transfer */ 1428 if ((cmd = sc->sc_curcmd) != NULL) { 1429 sc->sc_curcmd = NULL; 1430 njsc32_end_cmd(sc, cmd, cmdresult); 1431 } 1432 1433 /* clear disconnected transfers */ 1434 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 1435 for (lun = 0; lun < NJSC32_NLU; lun++) { 1436 lu = &sc->sc_targets[id].t_lus[lun]; 1437 1438 if ((cmd = lu->lu_cmd) != NULL) { 1439 lu->lu_cmd = NULL; 1440 njsc32_end_cmd(sc, cmd, cmdresult); 1441 } 1442 while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) { 1443 TAILQ_REMOVE(&lu->lu_q, cmd, c_q); 1444 njsc32_end_cmd(sc, cmd, cmdresult); 1445 } 1446 } 1447 } 1448 } 1449 1450 static int 1451 njsc32_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd, 1452 void *addr, int flag, struct proc *p) 1453 { 1454 struct njsc32_softc *sc = (void *)chan->chan_adapter->adapt_dev; 1455 1456 switch (cmd) { 1457 case SCBUSIORESET: 1458 njsc32_init(sc, 0); 1459 return 0; 1460 default: 1461 break; 1462 } 1463 1464 return ENOTTY; 1465 } 1466 1467 /* 1468 * set current data pointer 1469 */ 1470 static inline void 1471 njsc32_set_cur_ptr(struct njsc32_cmd *cmd, u_int32_t pos) 1472 { 1473 1474 /* new current data pointer */ 1475 cmd->c_dp_cur = pos; 1476 1477 /* update number of bytes transferred */ 1478 if (pos > cmd->c_dp_max) 1479 cmd->c_dp_max = pos; 1480 } 1481 1482 /* 1483 * set data pointer for the next transfer 1484 */ 1485 static void 1486 njsc32_set_ptr(struct njsc32_softc *sc, struct njsc32_cmd *cmd, u_int32_t pos) 1487 { 1488 struct njsc32_sgtable *sg; 1489 unsigned sgte; 1490 u_int32_t len; 1491 1492 /* set current pointer */ 1493 njsc32_set_cur_ptr(cmd, pos); 1494 1495 /* undo previous fix if any */ 1496 if (cmd->c_sgfixcnt != 0) { 1497 sg = &cmd->c_sgt[cmd->c_sgoffset]; 1498 sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt); 1499 sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt); 1500 cmd->c_sgfixcnt = 0; 1501 } 1502 1503 if (pos >= cmd->c_datacnt) { 1504 /* transfer done */ 1505 #if 1 /*def DIAGNOSTIC*/ 1506 if (pos > cmd->c_datacnt) 1507 aprint_error_dev(&sc->sc_dev, "pos %u too large\n", 1508 pos - cmd->c_datacnt); 1509 #endif 1510 cmd->c_xferctl = 0; /* XXX correct? */ 1511 1512 return; 1513 } 1514 1515 for (sgte = 0, sg = cmd->c_sgt; 1516 sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) { 1517 len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK; 1518 if (pos < len) { 1519 sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos); 1520 sg->sg_len = htole32(le32toh(sg->sg_len) - pos); 1521 cmd->c_sgfixcnt = pos; 1522 break; 1523 } 1524 pos -= len; 1525 #ifdef DIAGNOSTIC 1526 if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) { 1527 panic("njsc32_set_ptr: bad pos"); 1528 } 1529 #endif 1530 } 1531 #ifdef DIAGNOSTIC 1532 if (sgte >= NJSC32_NUM_SG) 1533 panic("njsc32_set_ptr: bad sg"); 1534 #endif 1535 if (cmd->c_sgoffset != sgte) { 1536 cmd->c_sgoffset = sgte; 1537 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte); 1538 } 1539 1540 /* XXX overkill */ 1541 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1542 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1543 NJSC32_SIZE_SGT, 1544 BUS_DMASYNC_PREWRITE); 1545 } 1546 1547 /* 1548 * save data pointer 1549 */ 1550 static inline void 1551 njsc32_save_ptr(struct njsc32_cmd *cmd) 1552 { 1553 1554 cmd->c_dp_saved = cmd->c_dp_cur; 1555 } 1556 1557 static void 1558 njsc32_assert_ack(struct njsc32_softc *sc) 1559 { 1560 u_int8_t reg; 1561 1562 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1563 reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE; 1564 #if 0 /* needed? */ 1565 reg |= NJSC32_SBCTL_AUTODIRECTION; 1566 #endif 1567 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1568 } 1569 1570 static void 1571 njsc32_negate_ack(struct njsc32_softc *sc) 1572 { 1573 u_int8_t reg; 1574 1575 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1576 #if 0 /* needed? */ 1577 reg |= NJSC32_SBCTL_ACK_ENABLE; 1578 reg |= NJSC32_SBCTL_AUTODIRECTION; 1579 #endif 1580 reg &= ~NJSC32_SBCTL_ACK; 1581 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1582 } 1583 1584 static void 1585 njsc32_wait_req_negate(struct njsc32_softc *sc) 1586 { 1587 int cnt; 1588 1589 for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) { 1590 if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 1591 NJSC32_BUSMON_REQ) == 0) 1592 return; 1593 delay(1); 1594 } 1595 printf("%s: njsc32_wait_req_negate: timed out\n", device_xname(&sc->sc_dev)); 1596 } 1597 1598 static void 1599 njsc32_reconnect(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 1600 { 1601 struct scsipi_xfer *xs; 1602 1603 xs = cmd->c_xs; 1604 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1605 callout_stop(&xs->xs_callout); 1606 callout_reset(&xs->xs_callout, 1607 mstohz(xs->timeout), 1608 njsc32_cmdtimeout, cmd); 1609 } 1610 1611 /* Reconnection implies Restore Pointers */ 1612 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1613 } 1614 1615 static enum njsc32_reselstat 1616 njsc32_resel_identify(struct njsc32_softc *sc, int lun, 1617 struct njsc32_cmd **pcmd) 1618 { 1619 int targetid; 1620 struct njsc32_lu *plu; 1621 struct njsc32_cmd *cmd; 1622 1623 switch (sc->sc_stat) { 1624 case NJSC32_STAT_RESEL: 1625 break; /* OK */ 1626 1627 case NJSC32_STAT_RESEL_LUN: 1628 case NJSC32_STAT_RECONNECT: 1629 /* 1630 * accept and ignore if the LUN is the same as the current one, 1631 * reject otherwise. 1632 */ 1633 return sc->sc_resellun == lun ? 1634 NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR; 1635 1636 default: 1637 aprint_error_dev(&sc->sc_dev, "njsc32_resel_identify: not in reselection\n"); 1638 return NJSC32_RESEL_ERROR; 1639 } 1640 1641 targetid = sc->sc_reselid; 1642 TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n", 1643 device_xname(&sc->sc_dev), lun)); 1644 1645 if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU) 1646 return NJSC32_RESEL_ERROR; 1647 1648 sc->sc_resellun = lun; 1649 plu = &sc->sc_targets[targetid].t_lus[lun]; 1650 1651 if ((cmd = plu->lu_cmd) != NULL) { 1652 sc->sc_stat = NJSC32_STAT_RECONNECT; 1653 plu->lu_cmd = NULL; 1654 *pcmd = cmd; 1655 TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n")); 1656 njsc32_reconnect(sc, cmd); 1657 return NJSC32_RESEL_COMPLETE; 1658 } else if (!TAILQ_EMPTY(&plu->lu_q)) { 1659 /* wait for tag */ 1660 sc->sc_stat = NJSC32_STAT_RESEL_LUN; 1661 return NJSC32_RESEL_THROUGH; 1662 } 1663 1664 /* no disconnected commands */ 1665 return NJSC32_RESEL_ERROR; 1666 } 1667 1668 static enum njsc32_reselstat 1669 njsc32_resel_tag(struct njsc32_softc *sc, int tag, struct njsc32_cmd **pcmd) 1670 { 1671 struct njsc32_cmd_head *head; 1672 struct njsc32_cmd *cmd; 1673 1674 TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n", 1675 device_xname(&sc->sc_dev), tag)); 1676 if (sc->sc_stat != NJSC32_STAT_RESEL_LUN) 1677 return NJSC32_RESEL_ERROR; 1678 1679 head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q; 1680 1681 /* XXX slow? */ 1682 /* search for the command of the tag */ 1683 TAILQ_FOREACH(cmd, head, c_q) { 1684 if (cmd->c_xs->xs_tag_id == tag) { 1685 sc->sc_stat = NJSC32_STAT_RECONNECT; 1686 TAILQ_REMOVE(head, cmd, c_q); 1687 *pcmd = cmd; 1688 TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n")); 1689 njsc32_reconnect(sc, cmd); 1690 return NJSC32_RESEL_COMPLETE; 1691 } 1692 } 1693 1694 /* no disconnected commands */ 1695 return NJSC32_RESEL_ERROR; 1696 } 1697 1698 /* 1699 * Reload parameters and restart AutoSCSI. 1700 * 1701 * XXX autoparam doesn't work as expected and we can't use it here. 1702 */ 1703 static void 1704 njsc32_cmd_reload(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int cctl) 1705 { 1706 struct njsc32_target *target; 1707 1708 target = cmd->c_target; 1709 1710 /* clear parity error and enable parity detection */ 1711 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1712 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1713 1714 /* load parameters */ 1715 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1716 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1717 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1718 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1719 #ifdef NJSC32_DUALEDGE 1720 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1721 cmd->c_xferctl | target->t_xferctl); 1722 #else 1723 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1724 #endif 1725 /* start AutoSCSI */ 1726 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 1727 1728 sc->sc_curcmd = cmd; 1729 } 1730 1731 static void 1732 njsc32_update_xfer_mode(struct njsc32_softc *sc, struct njsc32_target *target) 1733 { 1734 struct scsipi_xfer_mode xm; 1735 1736 xm.xm_target = target - sc->sc_targets; /* target ID */ 1737 xm.xm_mode = 0; 1738 xm.xm_period = target->t_syncperiod; 1739 xm.xm_offset = target->t_syncoffset; 1740 if (xm.xm_offset != 0) 1741 xm.xm_mode |= PERIPH_CAP_SYNC; 1742 if (target->t_flags & NJSC32_TARF_TAG) 1743 xm.xm_mode |= PERIPH_CAP_TQING; 1744 1745 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 1746 } 1747 1748 static void 1749 njsc32_msgin(struct njsc32_softc *sc) 1750 { 1751 u_int8_t msg0, msg; 1752 int msgcnt; 1753 struct njsc32_cmd *cmd; 1754 enum njsc32_reselstat rstat; 1755 int cctl = 0; 1756 u_int32_t ptr; /* unsigned type ensures 2-complement calculation */ 1757 u_int32_t msgout = 0; 1758 bool reload_params = FALSE; 1759 struct njsc32_target *target; 1760 int idx, period, offset; 1761 1762 /* 1763 * we are in Message In, so the previous Message Out should have 1764 * been done. 1765 */ 1766 njsc32_init_msgout(sc); 1767 1768 /* get a byte of Message In */ 1769 msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN); 1770 TPRINTF(("%s: njsc32_msgin: got %#x\n", device_xname(&sc->sc_dev), msg)); 1771 if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN) 1772 sc->sc_msginbuf[sc->sc_msgincnt] = msg; 1773 1774 njsc32_assert_ack(sc); 1775 1776 msg0 = sc->sc_msginbuf[0]; 1777 cmd = sc->sc_curcmd; 1778 1779 /* check for parity error */ 1780 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 1781 NJSC32_PARITYSTATUS_ERROR_LSB) { 1782 1783 aprint_error_dev(&sc->sc_dev, "msgin: parity error\n"); 1784 1785 /* clear parity error */ 1786 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1787 NJSC32_PARITYCTL_CHECK_ENABLE | 1788 NJSC32_PARITYCTL_CLEAR_ERROR); 1789 1790 /* respond as Message Parity Error */ 1791 njsc32_add_msgout(sc, MSG_PARITY_ERROR); 1792 1793 /* clear Message In */ 1794 sc->sc_msgincnt = 0; 1795 goto reply; 1796 } 1797 1798 #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0) 1799 #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0) 1800 if (MSG_ISIDENTIFY(msg0)) { 1801 /* 1802 * Got Identify message from target. 1803 */ 1804 if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG || 1805 (rstat = njsc32_resel_identify(sc, msg0 & 1806 MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) { 1807 /* 1808 * invalid Identify -> Reject 1809 */ 1810 goto reject; 1811 } 1812 if (rstat == NJSC32_RESEL_COMPLETE) 1813 reload_params = TRUE; 1814 MSGCOMPLETE; 1815 } 1816 1817 if (msg0 == MSG_SIMPLE_Q_TAG) { 1818 if (msgcnt == 0) 1819 WAITNEXTMSG; 1820 1821 /* got whole message */ 1822 sc->sc_msgincnt = 0; 1823 1824 if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd)) 1825 == NJSC32_RESEL_ERROR) { 1826 /* 1827 * invalid Simple Queue Tag -> Abort Tag 1828 */ 1829 printf("%s: msgin: invalid tag\n", device_xname(&sc->sc_dev)); 1830 njsc32_add_msgout(sc, MSG_ABORT_TAG); 1831 goto reply; 1832 } 1833 if (rstat == NJSC32_RESEL_COMPLETE) 1834 reload_params = TRUE; 1835 MSGCOMPLETE; 1836 } 1837 1838 /* I_T_L or I_T_L_Q nexus should be established now */ 1839 if (cmd == NULL) { 1840 printf("%s: msgin %#x without nexus -- sending abort\n", 1841 device_xname(&sc->sc_dev), msg0); 1842 njsc32_add_msgout(sc, MSG_ABORT); 1843 goto reply; 1844 } 1845 1846 /* 1847 * extended message 1848 * 0x01 <length (0 stands for 256)> <length bytes> 1849 * (<code> [<parameter> ...]) 1850 */ 1851 #define EXTLENOFF 1 1852 #define EXTCODEOFF 2 1853 if (msg0 == MSG_EXTENDED) { 1854 if (msgcnt < EXTLENOFF || 1855 msgcnt < EXTLENOFF + 1 + 1856 (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1)) 1857 WAITNEXTMSG; 1858 1859 /* got whole message */ 1860 sc->sc_msgincnt = 0; 1861 1862 switch (sc->sc_msginbuf[EXTCODEOFF]) { 1863 case 0: /* Modify Data Pointer */ 1864 if (msgcnt != 5 + EXTCODEOFF - 1) 1865 break; 1866 /* 1867 * parameter is 32bit big-endian signed (2-complement) 1868 * value 1869 */ 1870 ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) | 1871 (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) | 1872 (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) | 1873 sc->sc_msginbuf[EXTCODEOFF + 4]; 1874 1875 /* new pointer */ 1876 ptr += cmd->c_dp_cur; /* ignore overflow */ 1877 1878 /* reject if ptr is not in data buffer */ 1879 if (ptr > cmd->c_datacnt) 1880 break; 1881 1882 njsc32_set_ptr(sc, cmd, ptr); 1883 goto restart; 1884 1885 case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */ 1886 DPRINTC(cmd, ("SDTR %#x %#x\n", 1887 sc->sc_msginbuf[EXTCODEOFF + 1], 1888 sc->sc_msginbuf[EXTCODEOFF + 2])); 1889 if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1) 1890 break; /* reject */ 1891 1892 target = cmd->c_target; 1893 1894 /* lookup sync period parameters */ 1895 period = sc->sc_msginbuf[EXTCODEOFF + 1]; 1896 for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++) 1897 if (sc->sc_synct[idx].sp_period >= period) { 1898 period = sc->sc_synct[idx].sp_period; 1899 break; 1900 } 1901 if (idx >= NJSC32_NSYNCT) { 1902 /* 1903 * We can't meet the timing condition that 1904 * the target requests -- use async. 1905 */ 1906 njsc32_target_async(sc, target); 1907 njsc32_update_xfer_mode(sc, target); 1908 if (target->t_state == NJSC32_TARST_SDTR) { 1909 /* 1910 * We started SDTR exchange -- start 1911 * negotiation again and request async. 1912 */ 1913 target->t_state = NJSC32_TARST_ASYNC; 1914 njsc32_negotiate_xfer(sc, target); 1915 goto reply; 1916 } else { 1917 /* 1918 * The target started SDTR exchange 1919 * -- just reject and fallback 1920 * to async. 1921 */ 1922 goto reject; 1923 } 1924 } 1925 1926 /* check sync offset */ 1927 offset = sc->sc_msginbuf[EXTCODEOFF + 2]; 1928 if (offset > NJSC32_SYNCOFFSET_MAX) { 1929 if (target->t_state == NJSC32_TARST_SDTR) { 1930 aprint_error_dev(cmd->c_xs->xs_periph->periph_dev, "wrong sync offset: %d\n", offset); 1931 /* XXX what to do? */ 1932 } 1933 offset = NJSC32_SYNCOFFSET_MAX; 1934 } 1935 1936 target->t_ackwidth = sc->sc_synct[idx].sp_ackw; 1937 target->t_sample = sc->sc_synct[idx].sp_sample; 1938 target->t_syncperiod = period; 1939 target->t_syncoffset = offset; 1940 target->t_sync = NJSC32_SYNC_VAL(idx, offset); 1941 njsc32_update_xfer_mode(sc, target); 1942 1943 if (target->t_state == NJSC32_TARST_SDTR) { 1944 target->t_state = NJSC32_TARST_DONE; 1945 } else { 1946 njsc32_msgout_sdtr(sc, period, offset); 1947 goto reply; 1948 } 1949 goto restart; 1950 1951 case MSG_EXT_WDTR: /* Wide Data Transfer Request */ 1952 DPRINTC(cmd, 1953 ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1])); 1954 #ifdef NJSC32_DUALEDGE 1955 if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1) 1956 break; /* reject */ 1957 1958 /* 1959 * T->I of this message is not used for 1960 * DualEdge negotiation, so the device 1961 * must not be a DualEdge device. 1962 * 1963 * XXX correct? 1964 */ 1965 target = cmd->c_target; 1966 target->t_xferctl = 0; 1967 1968 switch (target->t_state) { 1969 case NJSC32_TARST_DE: 1970 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1971 MSG_EXT_WDTR_BUS_8_BIT) { 1972 /* 1973 * Oops, we got unexpected WDTR. 1974 * Negotiate for 8bit. 1975 */ 1976 target->t_state = NJSC32_TARST_WDTR; 1977 } else { 1978 target->t_state = NJSC32_TARST_SDTR; 1979 } 1980 njsc32_negotiate_xfer(sc, target); 1981 goto reply; 1982 1983 case NJSC32_TARST_WDTR: 1984 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1985 MSG_EXT_WDTR_BUS_8_BIT) { 1986 aprint_error_dev(cmd->c_xs->xs_periph->periph_dev, "unexpected transfer width: %#x\n", 1987 sc->sc_msginbuf[EXTCODEOFF + 1]); 1988 /* XXX what to do? */ 1989 } 1990 target->t_state = NJSC32_TARST_SDTR; 1991 njsc32_negotiate_xfer(sc, target); 1992 goto reply; 1993 1994 default: 1995 /* the target started WDTR exchange */ 1996 DPRINTC(cmd, ("WDTR from target\n")); 1997 1998 target->t_state = NJSC32_TARST_SDTR; 1999 njsc32_target_async(sc, target); 2000 2001 break; /* reject the WDTR (8bit transfer) */ 2002 } 2003 #endif /* NJSC32_DUALEDGE */ 2004 break; /* reject */ 2005 } 2006 DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n", 2007 sc->sc_msginbuf[EXTCODEOFF], msgcnt)); 2008 goto reject; 2009 } 2010 2011 /* 2byte messages */ 2012 if (MSG_IS2BYTE(msg0)) { 2013 if (msgcnt == 0) 2014 WAITNEXTMSG; 2015 2016 /* got whole message */ 2017 sc->sc_msgincnt = 0; 2018 } 2019 2020 switch (msg0) { 2021 case MSG_CMDCOMPLETE: /* 0x00 */ 2022 case MSG_SAVEDATAPOINTER: /* 0x02 */ 2023 case MSG_DISCONNECT: /* 0x04 */ 2024 /* handled by AutoSCSI */ 2025 PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0)); 2026 break; 2027 2028 case MSG_RESTOREPOINTERS: /* 0x03 */ 2029 /* restore data pointer to what was saved */ 2030 DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n")); 2031 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 2032 reload_params = TRUE; 2033 MSGCOMPLETE; 2034 /* NOTREACHED */ 2035 break; 2036 2037 #if 0 /* handled above */ 2038 case MSG_EXTENDED: /* 0x01 */ 2039 #endif 2040 case MSG_MESSAGE_REJECT: /* 0x07 */ 2041 target = cmd->c_target; 2042 DPRINTC(cmd, ("Reject tarst %d\n", target->t_state)); 2043 switch (target->t_state) { 2044 #ifdef NJSC32_DUALEDGE 2045 case NJSC32_TARST_WDTR: 2046 case NJSC32_TARST_DE: 2047 target->t_xferctl = 0; 2048 target->t_state = NJSC32_TARST_SDTR; 2049 njsc32_negotiate_xfer(sc, target); 2050 goto reply; 2051 #endif 2052 case NJSC32_TARST_SDTR: 2053 case NJSC32_TARST_ASYNC: 2054 njsc32_target_async(sc, target); 2055 target->t_state = NJSC32_TARST_DONE; 2056 njsc32_update_xfer_mode(sc, target); 2057 break; 2058 default: 2059 break; 2060 } 2061 goto restart; 2062 2063 case MSG_NOOP: /* 0x08 */ 2064 #ifdef NJSC32_DUALEDGE 2065 target = cmd->c_target; 2066 if (target->t_state == NJSC32_TARST_DE) { 2067 aprint_normal_dev(&cmd->c_xs->xs_periph->periph_dev, 2068 "%s: DualEdge transfer\n"); 2069 target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE; 2070 /* go to next negotiation */ 2071 target->t_state = NJSC32_TARST_SDTR; 2072 njsc32_negotiate_xfer(sc, target); 2073 goto reply; 2074 } 2075 #endif 2076 goto restart; 2077 2078 case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */ 2079 case MSG_ABORT: /* 0x06 I->T only */ 2080 case MSG_PARITY_ERROR: /* 0x09 I->T only */ 2081 case MSG_LINK_CMD_COMPLETE: /* 0x0a */ 2082 case MSG_LINK_CMD_COMPLETEF: /* 0x0b */ 2083 case MSG_BUS_DEV_RESET: /* 0x0c I->T only */ 2084 case MSG_ABORT_TAG: /* 0x0d I->T only */ 2085 case MSG_CLEAR_QUEUE: /* 0x0e I->T only */ 2086 2087 #if 0 /* handled above */ 2088 case MSG_SIMPLE_Q_TAG: /* 0x20 */ 2089 #endif 2090 case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */ 2091 case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */ 2092 case MSG_IGN_WIDE_RESIDUE: /* 0x23 */ 2093 2094 default: 2095 #ifdef NJSC32_DEBUG 2096 PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0)); 2097 if (MSG_IS2BYTE(msg0)) 2098 printf(" %#x", msg); 2099 printf("\n"); 2100 #endif 2101 break; 2102 } 2103 2104 reject: 2105 njsc32_add_msgout(sc, MSG_MESSAGE_REJECT); 2106 2107 reply: 2108 msgout = njsc32_get_auto_msgout(sc); 2109 2110 restart: 2111 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2112 NJSC32_CMD_AUTO_COMMAND_PHASE | 2113 NJSC32_CMD_AUTO_SCSI_RESTART; 2114 2115 /* 2116 * Be careful the second and latter bytes of Message In 2117 * shall not be absorbed by AutoSCSI. 2118 */ 2119 if (sc->sc_msgincnt == 0) 2120 cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2121 2122 if (sc->sc_msgoutlen != 0) 2123 cctl |= NJSC32_CMD_AUTO_ATN; 2124 2125 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout); 2126 2127 /* (re)start AutoSCSI (may assert ATN) */ 2128 if (reload_params) { 2129 njsc32_cmd_reload(sc, cmd, cctl); 2130 } else { 2131 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2132 } 2133 2134 /* +ATN -> -REQ: need 90ns delay? */ 2135 2136 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2137 2138 njsc32_negate_ack(sc); 2139 2140 return; 2141 } 2142 2143 static void 2144 njsc32_msgout(struct njsc32_softc *sc) 2145 { 2146 int cctl; 2147 u_int8_t bus; 2148 unsigned n; 2149 2150 if (sc->sc_msgoutlen == 0) { 2151 /* target entered to Message Out on unexpected timing */ 2152 njsc32_add_msgout(sc, MSG_NOOP); 2153 } 2154 2155 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2156 NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART | 2157 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2158 2159 /* make sure target is in Message Out phase */ 2160 bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR); 2161 if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) { 2162 /* 2163 * Message Out is aborted by target. 2164 */ 2165 printf("%s: njsc32_msgout: phase change %#x\n", 2166 device_xname(&sc->sc_dev), bus); 2167 2168 /* XXX what to do? */ 2169 2170 /* restart AutoSCSI (negate ATN) */ 2171 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2172 2173 sc->sc_msgoutidx = 0; 2174 return; 2175 } 2176 2177 n = sc->sc_msgoutidx; 2178 if (n == sc->sc_msgoutlen - 1) { 2179 /* 2180 * negate ATN before sending ACK 2181 */ 2182 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0); 2183 2184 sc->sc_msgoutidx = 0; /* target may retry Message Out */ 2185 } else { 2186 cctl |= NJSC32_CMD_AUTO_ATN; 2187 sc->sc_msgoutidx++; 2188 } 2189 2190 /* Send Message Out */ 2191 njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]); 2192 2193 /* DBn -> +ACK: need 55ns delay? */ 2194 2195 njsc32_assert_ack(sc); 2196 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2197 2198 /* restart AutoSCSI */ 2199 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2200 2201 njsc32_negate_ack(sc); 2202 2203 /* 2204 * do not reset sc->sc_msgoutlen so the target 2205 * can retry Message Out phase 2206 */ 2207 } 2208 2209 static void 2210 njsc32_cmdtimeout(void *arg) 2211 { 2212 struct njsc32_cmd *cmd = arg; 2213 struct njsc32_softc *sc; 2214 int s; 2215 2216 PRINTC(cmd, ("command timeout\n")); 2217 2218 sc = cmd->c_sc; 2219 2220 s = splbio(); 2221 2222 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2223 njsc32_arbitration_failed(sc); 2224 else { 2225 sc->sc_curcmd = NULL; 2226 sc->sc_stat = NJSC32_STAT_IDLE; 2227 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2228 } 2229 2230 /* XXX? */ 2231 njsc32_init(sc, 1); /* bus reset */ 2232 2233 splx(s); 2234 } 2235 2236 static void 2237 njsc32_reseltimeout(void *arg) 2238 { 2239 struct njsc32_cmd *cmd = arg; 2240 struct njsc32_softc *sc; 2241 int s; 2242 2243 PRINTC(cmd, ("reselection timeout\n")); 2244 2245 sc = cmd->c_sc; 2246 2247 s = splbio(); 2248 2249 /* remove from disconnected list */ 2250 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2251 /* I_T_L_Q */ 2252 KASSERT(cmd->c_lu->lu_cmd == NULL); 2253 TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q); 2254 } else { 2255 /* I_T_L */ 2256 KASSERT(cmd->c_lu->lu_cmd == cmd); 2257 cmd->c_lu->lu_cmd = NULL; 2258 } 2259 2260 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2261 2262 /* XXX? */ 2263 njsc32_init(sc, 1); /* bus reset */ 2264 2265 splx(s); 2266 } 2267 2268 static inline void 2269 njsc32_end_auto(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int auto_phase) 2270 { 2271 struct scsipi_xfer *xs; 2272 2273 if (auto_phase & NJSC32_XPHASE_MSGIN_02) { 2274 /* Message In: 0x02 Save Data Pointer */ 2275 2276 /* 2277 * Adjust saved data pointer 2278 * if the command is not completed yet. 2279 */ 2280 if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 && 2281 (auto_phase & 2282 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) { 2283 njsc32_save_ptr(cmd); 2284 } 2285 TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2286 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2287 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2288 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2289 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT))); 2290 } 2291 2292 xs = cmd->c_xs; 2293 2294 if (auto_phase & NJSC32_XPHASE_MSGIN_00) { 2295 /* Command Complete */ 2296 TPRINTC(cmd, ("njsc32_intr: Command Complete\n")); 2297 switch (xs->status) { 2298 case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY: 2299 /* 2300 * scsipi layer will automatically handle the error 2301 */ 2302 njsc32_end_cmd(sc, cmd, XS_BUSY); 2303 break; 2304 default: 2305 xs->resid -= cmd->c_dp_max; 2306 njsc32_end_cmd(sc, cmd, XS_NOERROR); 2307 break; 2308 } 2309 } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) { 2310 /* Disconnect */ 2311 TPRINTC(cmd, ("njsc32_intr: Disconnect\n")); 2312 2313 /* for ill-designed devices */ 2314 if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0) 2315 njsc32_save_ptr(cmd); 2316 2317 /* 2318 * move current cmd to disconnected list 2319 */ 2320 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2321 /* I_T_L_Q */ 2322 if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD) 2323 TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q); 2324 else 2325 TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q); 2326 } else { 2327 /* I_T_L */ 2328 cmd->c_lu->lu_cmd = cmd; 2329 } 2330 2331 /* 2332 * schedule timeout -- avoid being 2333 * disconnected forever 2334 */ 2335 if ((xs->xs_control & XS_CTL_POLL) == 0) { 2336 callout_stop(&xs->xs_callout); 2337 callout_reset(&xs->xs_callout, mstohz(xs->timeout), 2338 njsc32_reseltimeout, cmd); 2339 } 2340 2341 } else { 2342 /* 2343 * target has come to Bus Free phase 2344 * probably to notify an error 2345 */ 2346 PRINTC(cmd, ("njsc32_intr: unexpected bus free\n")); 2347 /* try Request Sense */ 2348 xs->status = SCSI_CHECK; 2349 njsc32_end_cmd(sc, cmd, XS_BUSY); 2350 } 2351 } 2352 2353 int 2354 njsc32_intr(void *arg) 2355 { 2356 struct njsc32_softc *sc = arg; 2357 u_int16_t intr; 2358 u_int8_t arbstat, bus_phase; 2359 int auto_phase; 2360 int idbit; 2361 struct njsc32_cmd *cmd; 2362 2363 intr = njsc32_read_2(sc, NJSC32_REG_IRQ); 2364 if ((intr & NJSC32_IRQ_INTR_PENDING) == 0) 2365 return 0; /* not mine */ 2366 2367 TPRINTF(("%s: njsc32_intr: %#x\n", device_xname(&sc->sc_dev), intr)); 2368 2369 #if 0 /* I don't think this is required */ 2370 /* mask interrupts */ 2371 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 2372 #endif 2373 2374 /* we got an interrupt, so stop the timer */ 2375 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 2376 2377 if (intr & NJSC32_IRQ_SCSIRESET) { 2378 printf("%s: detected bus reset\n", device_xname(&sc->sc_dev)); 2379 /* make sure all devices on the bus are certainly reset */ 2380 njsc32_reset_bus(sc); 2381 goto out; 2382 } 2383 2384 if (sc->sc_stat == NJSC32_STAT_ARBIT) { 2385 cmd = sc->sc_curcmd; 2386 KASSERT(cmd); 2387 arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT); 2388 if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) { 2389 /* 2390 * arbitration done 2391 */ 2392 /* clear arbitration status */ 2393 njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION, 2394 NJSC32_SETARB_CLEAR); 2395 2396 if (arbstat & NJSC32_ARBSTAT_WIN) { 2397 TPRINTC(cmd, 2398 ("njsc32_intr: arbitration won\n")); 2399 2400 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 2401 2402 sc->sc_stat = NJSC32_STAT_CONNECT; 2403 } else { 2404 TPRINTC(cmd, 2405 ("njsc32_intr: arbitration failed\n")); 2406 2407 njsc32_arbitration_failed(sc); 2408 2409 /* XXX delay */ 2410 /* XXX retry counter */ 2411 } 2412 } 2413 } 2414 2415 if (intr & NJSC32_IRQ_TIMER) { 2416 TPRINTF(("%s: njsc32_intr: timer interrupt\n", 2417 device_xname(&sc->sc_dev))); 2418 } 2419 2420 if (intr & NJSC32_IRQ_RESELECT) { 2421 /* Reselection from a target */ 2422 njsc32_arbitration_failed(sc); /* just in case */ 2423 if ((cmd = sc->sc_curcmd) != NULL) { 2424 /* ? */ 2425 aprint_error_dev(&sc->sc_dev, "unexpected reselection\n"); 2426 sc->sc_curcmd = NULL; 2427 sc->sc_stat = NJSC32_STAT_IDLE; 2428 njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP); 2429 } 2430 2431 idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID); 2432 if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 || 2433 (sc->sc_reselid = 2434 ffs(idbit & ~(1 << NJSC32_INITIATOR_ID)) - 1) < 0) { 2435 aprint_error_dev(&sc->sc_dev, "invalid reselection (id: %#x)\n", 2436 idbit); 2437 sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */ 2438 } else { 2439 sc->sc_stat = NJSC32_STAT_RESEL; 2440 TPRINTF(("%s: njsc32_intr: reselection from %d\n", 2441 device_xname(&sc->sc_dev), sc->sc_reselid)); 2442 } 2443 } 2444 2445 if (intr & NJSC32_IRQ_PHASE_CHANGE) { 2446 #if 1 /* XXX probably not needed */ 2447 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2448 PRINTC(sc->sc_curcmd, 2449 ("njsc32_intr: cancel arbitration phase\n")); 2450 njsc32_arbitration_failed(sc); 2451 #endif 2452 /* current bus phase */ 2453 bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 2454 NJSC32_BUSMON_PHASE_MASK; 2455 2456 switch (bus_phase) { 2457 case NJSC32_PHASE_MESSAGE_IN: 2458 njsc32_msgin(sc); 2459 break; 2460 2461 /* 2462 * target may suddenly become Status / Bus Free phase 2463 * to notify an error condition 2464 */ 2465 case NJSC32_PHASE_STATUS: 2466 printf("%s: unexpected bus phase: Status\n", 2467 device_xname(&sc->sc_dev)); 2468 if ((cmd = sc->sc_curcmd) != NULL) { 2469 cmd->c_xs->status = 2470 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2471 TPRINTC(cmd, ("njsc32_intr: Status %d\n", 2472 cmd->c_xs->status)); 2473 } 2474 break; 2475 case NJSC32_PHASE_BUSFREE: 2476 aprint_error_dev(&sc->sc_dev, "unexpected bus phase: Bus Free\n"); 2477 if ((cmd = sc->sc_curcmd) != NULL) { 2478 sc->sc_curcmd = NULL; 2479 sc->sc_stat = NJSC32_STAT_IDLE; 2480 if (cmd->c_xs->status != SCSI_QUEUE_FULL && 2481 cmd->c_xs->status != SCSI_BUSY) 2482 cmd->c_xs->status = SCSI_CHECK;/* XXX */ 2483 njsc32_end_cmd(sc, cmd, XS_BUSY); 2484 } 2485 goto out; 2486 default: 2487 #ifdef NJSC32_DEBUG 2488 printf("%s: unexpected bus phase: ", 2489 device_xname(&sc->sc_dev)); 2490 switch (bus_phase) { 2491 case NJSC32_PHASE_COMMAND: 2492 printf("Command\n"); break; 2493 case NJSC32_PHASE_MESSAGE_OUT: 2494 printf("Message Out\n");break; 2495 case NJSC32_PHASE_DATA_IN: 2496 printf("Data In\n"); break; 2497 case NJSC32_PHASE_DATA_OUT: 2498 printf("Data Out\n"); break; 2499 case NJSC32_PHASE_RESELECT: 2500 printf("Reselect\n");break; 2501 default: printf("%#x\n", bus_phase); break; 2502 } 2503 #else 2504 aprint_error_dev(&sc->sc_dev, "unexpected bus phase: %#x", 2505 bus_phase); 2506 #endif 2507 break; 2508 } 2509 } 2510 2511 if (intr & NJSC32_IRQ_AUTOSCSI) { 2512 /* 2513 * AutoSCSI interrupt 2514 */ 2515 auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE); 2516 TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n", 2517 device_xname(&sc->sc_dev), auto_phase)); 2518 njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0); 2519 2520 if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) { 2521 cmd = sc->sc_curcmd; 2522 if (cmd == NULL) { 2523 aprint_error_dev(&sc->sc_dev, "sel no cmd\n"); 2524 goto out; 2525 } 2526 DPRINTC(cmd, ("njsc32_intr: selection timeout\n")); 2527 2528 sc->sc_curcmd = NULL; 2529 sc->sc_stat = NJSC32_STAT_IDLE; 2530 njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT); 2531 2532 goto out; 2533 } 2534 2535 #ifdef NJSC32_TRACE 2536 if (auto_phase & NJSC32_XPHASE_COMMAND) { 2537 /* Command phase has been automatically processed */ 2538 TPRINTF(("%s: njsc32_intr: Command\n", 2539 device_xname(&sc->sc_dev))); 2540 } 2541 #endif 2542 #ifdef NJSC32_DEBUG 2543 if (auto_phase & NJSC32_XPHASE_ILLEGAL) { 2544 printf("%s: njsc32_intr: Illegal phase\n", 2545 device_xname(&sc->sc_dev)); 2546 } 2547 #endif 2548 2549 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) { 2550 TPRINTF(("%s: njsc32_intr: Process Message In\n", 2551 device_xname(&sc->sc_dev))); 2552 njsc32_msgin(sc); 2553 } 2554 2555 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) { 2556 TPRINTF(("%s: njsc32_intr: Process Message Out\n", 2557 device_xname(&sc->sc_dev))); 2558 njsc32_msgout(sc); 2559 } 2560 2561 cmd = sc->sc_curcmd; 2562 if (cmd == NULL) { 2563 TPRINTF(("%s: njsc32_intr: no cmd\n", 2564 device_xname(&sc->sc_dev))); 2565 goto out; 2566 } 2567 2568 if (auto_phase & 2569 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) { 2570 u_int32_t sackcnt, cntoffset; 2571 2572 #ifdef NJSC32_TRACE 2573 if (auto_phase & NJSC32_XPHASE_DATA_IN) 2574 PRINTC(cmd, ("njsc32_intr: data in done\n")); 2575 if (auto_phase & NJSC32_XPHASE_DATA_OUT) 2576 PRINTC(cmd, ("njsc32_intr: data out done\n")); 2577 printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2578 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2579 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2580 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2581 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)); 2582 #endif 2583 2584 /* 2585 * detected parity error on data transfer? 2586 */ 2587 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 2588 (NJSC32_PARITYSTATUS_ERROR_LSB| 2589 NJSC32_PARITYSTATUS_ERROR_MSB)) { 2590 2591 PRINTC(cmd, ("datain: parity error\n")); 2592 2593 /* clear parity error */ 2594 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 2595 NJSC32_PARITYCTL_CHECK_ENABLE | 2596 NJSC32_PARITYCTL_CLEAR_ERROR); 2597 2598 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2599 /* 2600 * XXX command has already finished 2601 * -- what can we do? 2602 * 2603 * It is not clear current command 2604 * caused the error -- reset everything. 2605 */ 2606 njsc32_init(sc, 1); /* XXX */ 2607 } else { 2608 /* XXX does this case occur? */ 2609 #if 1 2610 aprint_error_dev(&sc->sc_dev, "datain: parity error\n"); 2611 #endif 2612 /* 2613 * Make attention condition and try 2614 * to send Initiator Detected Error 2615 * message. 2616 */ 2617 njsc32_init_msgout(sc); 2618 njsc32_add_msgout(sc, 2619 MSG_INITIATOR_DET_ERR); 2620 njsc32_write_4(sc, 2621 NJSC32_REG_SCSI_MSG_OUT, 2622 njsc32_get_auto_msgout(sc)); 2623 /* restart autoscsi with ATN */ 2624 njsc32_write_2(sc, 2625 NJSC32_REG_COMMAND_CONTROL, 2626 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2627 NJSC32_CMD_AUTO_COMMAND_PHASE | 2628 NJSC32_CMD_AUTO_SCSI_RESTART | 2629 NJSC32_CMD_AUTO_MSGIN_00_04 | 2630 NJSC32_CMD_AUTO_MSGIN_02 | 2631 NJSC32_CMD_AUTO_ATN); 2632 } 2633 goto out; 2634 } 2635 2636 /* 2637 * data has been transferred, and current pointer 2638 * is changed 2639 */ 2640 sackcnt = njsc32_read_4(sc, NJSC32_REG_SACK_CNT); 2641 2642 /* 2643 * The controller returns extra ACK count 2644 * if the DMA buffer is not 4byte aligned. 2645 */ 2646 cntoffset = le32toh(cmd->c_sgt[0].sg_addr) & 3; 2647 #ifdef NJSC32_DEBUG 2648 if (cntoffset != 0) { 2649 printf("sackcnt %u, cntoffset %u\n", 2650 sackcnt, cntoffset); 2651 } 2652 #endif 2653 /* advance SCSI pointer */ 2654 njsc32_set_cur_ptr(cmd, 2655 cmd->c_dp_cur + sackcnt - cntoffset); 2656 } 2657 2658 if (auto_phase & NJSC32_XPHASE_MSGOUT) { 2659 /* Message Out phase has been automatically processed */ 2660 TPRINTC(cmd, ("njsc32_intr: Message Out\n")); 2661 if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 && 2662 sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) { 2663 njsc32_init_msgout(sc); 2664 } 2665 } 2666 2667 if (auto_phase & NJSC32_XPHASE_STATUS) { 2668 /* Status phase has been automatically processed */ 2669 cmd->c_xs->status = 2670 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2671 TPRINTC(cmd, ("njsc32_intr: Status %#x\n", 2672 cmd->c_xs->status)); 2673 } 2674 2675 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2676 /* AutoSCSI is finished */ 2677 2678 TPRINTC(cmd, ("njsc32_intr: Bus Free\n")); 2679 2680 sc->sc_stat = NJSC32_STAT_IDLE; 2681 sc->sc_curcmd = NULL; 2682 2683 njsc32_end_auto(sc, cmd, auto_phase); 2684 } 2685 goto out; 2686 } 2687 2688 if (intr & NJSC32_IRQ_FIFO_THRESHOLD) { 2689 /* XXX We use DMA, and this shouldn't happen */ 2690 printf("%s: njsc32_intr: FIFO\n", device_xname(&sc->sc_dev)); 2691 njsc32_init(sc, 1); 2692 goto out; 2693 } 2694 if (intr & NJSC32_IRQ_PCI) { 2695 /* XXX? */ 2696 printf("%s: njsc32_intr: PCI\n", device_xname(&sc->sc_dev)); 2697 } 2698 if (intr & NJSC32_IRQ_BMCNTERR) { 2699 /* XXX? */ 2700 printf("%s: njsc32_intr: BM\n", device_xname(&sc->sc_dev)); 2701 } 2702 2703 out: 2704 /* go next command if controller is idle */ 2705 if (sc->sc_stat == NJSC32_STAT_IDLE) 2706 njsc32_start(sc); 2707 2708 #if 0 2709 /* enable interrupts */ 2710 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 2711 #endif 2712 2713 return 1; /* processed */ 2714 } 2715
Indexes created Mon Sep 29 21:09:56 GMT 2025