ninjascsi32.c revision 1.2.2.2
1 /* $NetBSD: ninjascsi32.c,v 1.2.2.2 2004/08/30 09:24:58 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by ITOH Yasufumi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.2.2.2 2004/08/30 09:24:58 tron Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/device.h> 46 #include <sys/kernel.h> 47 #include <sys/buf.h> 48 #include <sys/scsiio.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <dev/scsipi/scsi_message.h> 59 60 /* 61 * DualEdge transfer support 62 */ 63 /* #define NJSC32_DUALEDGE */ /* XXX untested */ 64 65 /* 66 * Auto param loading does not work properly (it partially works (works on 67 * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51), 68 * and it doesn't improve the performance so much, 69 * forget about it. 70 */ 71 #undef NJSC32_AUTOPARAM 72 73 #include <dev/ic/ninjascsi32reg.h> 74 #include <dev/ic/ninjascsi32var.h> 75 76 /* #define NJSC32_DEBUG */ 77 /* #define NJSC32_TRACE */ 78 79 #ifdef NJSC32_DEBUG 80 #define DPRINTF(x) printf x 81 #define DPRINTC(cmd, x) PRINTC(cmd, x) 82 #else 83 #define DPRINTF(x) 84 #define DPRINTC(cmd, x) 85 #endif 86 #ifdef NJSC32_TRACE 87 #define TPRINTF(x) printf x 88 #define TPRINTC(cmd, x) PRINTC(cmd, x) 89 #else 90 #define TPRINTF(x) 91 #define TPRINTC(cmd, x) 92 #endif 93 94 #define PRINTC(cmd, x) do { \ 95 scsi_print_addr((cmd)->c_xs->xs_periph); \ 96 printf x; \ 97 } while (/* CONSTCOND */ 0) 98 99 void njsc32_scsipi_request __P((struct scsipi_channel *, 100 scsipi_adapter_req_t, void *)); 101 void njsc32_scsipi_minphys __P((struct buf *buf)); 102 int njsc32_scsipi_ioctl __P((struct scsipi_channel *, u_long, caddr_t, 103 int, struct proc *)); 104 105 static void njsc32_init __P((struct njsc32_softc *, int nosleep)); 106 static int njsc32_init_cmds __P((struct njsc32_softc *)); 107 static void njsc32_target_async __P((struct njsc32_softc *, 108 struct njsc32_target *)); 109 static void njsc32_init_targets __P((struct njsc32_softc *)); 110 static __inline void njsc32_cmd_init __P((struct njsc32_cmd *)); 111 static __inline void njsc32_init_msgout __P((struct njsc32_softc *)); 112 static void njsc32_add_msgout __P((struct njsc32_softc *, int)); 113 static u_int32_t njsc32_get_auto_msgout __P((struct njsc32_softc *)); 114 #ifdef NJSC32_DUALEDGE 115 static void njsc32_msgout_wdtr __P((struct njsc32_softc *, int)); 116 #endif 117 static void njsc32_msgout_sdtr __P((struct njsc32_softc *, int period, 118 int offset)); 119 static void njsc32_negotiate_xfer __P((struct njsc32_softc *, 120 struct njsc32_target *)); 121 static __inline void njsc32_led_on __P((struct njsc32_softc *)); 122 static __inline void njsc32_led_off __P((struct njsc32_softc *)); 123 static void njsc32_arbitration_failed __P((struct njsc32_softc *)); 124 static __inline void njsc32_cmd_load __P((struct njsc32_softc *, 125 struct njsc32_cmd *)); 126 static void njsc32_start __P((struct njsc32_softc *)); 127 static void njsc32_run_xfer __P((struct njsc32_softc *, struct scsipi_xfer *)); 128 static void njsc32_end_cmd __P((struct njsc32_softc *, struct njsc32_cmd *, 129 scsipi_xfer_result_t)); 130 static void njsc32_reset_bus __P((struct njsc32_softc *)); 131 static void njsc32_clear_cmds __P((struct njsc32_softc *, 132 scsipi_xfer_result_t)); 133 static void njsc32_reset_detected __P((struct njsc32_softc *)); 134 static __inline void njsc32_set_cur_ptr __P((struct njsc32_cmd *, u_int32_t)); 135 static void njsc32_set_ptr __P((struct njsc32_softc *, struct njsc32_cmd *, 136 u_int32_t)); 137 static __inline void njsc32_save_ptr __P((struct njsc32_cmd *)); 138 static void njsc32_assert_ack __P((struct njsc32_softc *)); 139 static void njsc32_negate_ack __P((struct njsc32_softc *)); 140 static void njsc32_wait_req_negate __P((struct njsc32_softc *)); 141 static void njsc32_reconnect __P((struct njsc32_softc *, struct njsc32_cmd *)); 142 enum njsc32_reselstat { 143 NJSC32_RESEL_ERROR, /* to be rejected */ 144 NJSC32_RESEL_COMPLETE, /* reselection is just complete */ 145 NJSC32_RESEL_THROUGH /* this message is OK (no reply) */ 146 }; 147 static enum njsc32_reselstat njsc32_resel_identify __P((struct njsc32_softc *, 148 int lun, struct njsc32_cmd **)); 149 static enum njsc32_reselstat njsc32_resel_tag __P((struct njsc32_softc *, 150 int tag, struct njsc32_cmd **)); 151 static void njsc32_cmd_reload __P((struct njsc32_softc *, struct njsc32_cmd *, 152 int)); 153 static void njsc32_update_xfer_mode __P((struct njsc32_softc *, 154 struct njsc32_target *)); 155 static void njsc32_msgin __P((struct njsc32_softc *)); 156 static void njsc32_msgout __P((struct njsc32_softc *)); 157 static void njsc32_cmdtimeout __P((void *)); 158 static void njsc32_reseltimeout __P((void *)); 159 static __inline void njsc32_end_auto __P((struct njsc32_softc *, 160 struct njsc32_cmd *, int)); 161 162 static __inline unsigned njsc32_read_1 __P((struct njsc32_softc *, int)); 163 static __inline unsigned njsc32_read_2 __P((struct njsc32_softc *, int)); 164 static __inline u_int32_t njsc32_read_4 __P((struct njsc32_softc *, int)); 165 static __inline void njsc32_write_1 __P((struct njsc32_softc *, int, int)); 166 static __inline void njsc32_write_2 __P((struct njsc32_softc *, int, int)); 167 static __inline void njsc32_write_4 __P((struct njsc32_softc *, int, 168 u_int32_t)); 169 static __inline unsigned njsc32_ireg_read_1 __P((struct njsc32_softc *, int)); 170 static __inline unsigned njsc32_ireg_read_2 __P((struct njsc32_softc *, int)); 171 static __inline u_int32_t njsc32_ireg_read_4 __P((struct njsc32_softc *, int)); 172 static __inline void njsc32_ireg_write_1 __P((struct njsc32_softc *, int, int)); 173 static __inline void njsc32_ireg_write_2 __P((struct njsc32_softc *, int, int)); 174 static __inline void njsc32_ireg_write_4 __P((struct njsc32_softc *, int, 175 u_int32_t)); 176 177 static __inline unsigned 178 njsc32_read_1(sc, no) 179 struct njsc32_softc *sc; 180 int no; 181 { 182 183 return bus_space_read_1(sc->sc_regt, sc->sc_regh, no); 184 } 185 186 static __inline unsigned 187 njsc32_read_2(sc, no) 188 struct njsc32_softc *sc; 189 int no; 190 { 191 192 return bus_space_read_2(sc->sc_regt, sc->sc_regh, no); 193 } 194 195 static __inline u_int32_t 196 njsc32_read_4(sc, no) 197 struct njsc32_softc *sc; 198 int no; 199 { 200 201 return bus_space_read_4(sc->sc_regt, sc->sc_regh, no); 202 } 203 204 static __inline void 205 njsc32_write_1(sc, no, val) 206 struct njsc32_softc *sc; 207 int no, val; 208 { 209 210 bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val); 211 } 212 213 static __inline void 214 njsc32_write_2(sc, no, val) 215 struct njsc32_softc *sc; 216 int no, val; 217 { 218 219 bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val); 220 } 221 222 static __inline void 223 njsc32_write_4(sc, no, val) 224 struct njsc32_softc *sc; 225 int no; 226 u_int32_t val; 227 { 228 229 bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val); 230 } 231 232 static __inline unsigned 233 njsc32_ireg_read_1(sc, no) 234 struct njsc32_softc *sc; 235 int no; 236 { 237 238 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 239 return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 240 } 241 242 static __inline unsigned 243 njsc32_ireg_read_2(sc, no) 244 struct njsc32_softc *sc; 245 int no; 246 { 247 248 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 249 return bus_space_read_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 250 } 251 252 static __inline u_int32_t 253 njsc32_ireg_read_4(sc, no) 254 struct njsc32_softc *sc; 255 int no; 256 { 257 u_int32_t val; 258 259 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 260 val = (u_int16_t)bus_space_read_2(sc->sc_regt, sc->sc_regh, 261 NJSC32_REG_DATA_LOW); 262 return val | (bus_space_read_2(sc->sc_regt, sc->sc_regh, 263 NJSC32_REG_DATA_HIGH) << 16); 264 } 265 266 static __inline void 267 njsc32_ireg_write_1(sc, no, val) 268 struct njsc32_softc *sc; 269 int no, val; 270 { 271 272 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 273 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 274 } 275 276 static __inline void 277 njsc32_ireg_write_2(sc, no, val) 278 struct njsc32_softc *sc; 279 int no, val; 280 { 281 282 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 283 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 284 } 285 286 static __inline void 287 njsc32_ireg_write_4(sc, no, val) 288 struct njsc32_softc *sc; 289 int no; 290 u_int32_t val; 291 { 292 293 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 294 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 295 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_HIGH, 296 val >> 16); 297 } 298 299 #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */ 300 #ifdef __STDC__ 301 # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK 302 # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \ 303 NJSC32_SREQ_SAMPLING_ENABLE) 304 #else 305 # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK 306 # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \ 307 NJSC32_SREQ_SAMPLING_ENABLE) 308 #endif 309 310 #define NJSC32_NSYNCT_MAXSYNC 1 311 #define NJSC32_NSYNCT 16 312 313 /* 40MHz (25ns) */ 314 static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = { 315 { 0, 0, 0 }, /* dummy for async */ 316 { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */ 317 { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */ 318 { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */ 319 { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */ 320 { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */ 321 { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */ 322 { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 323 { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */ 324 { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 325 { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */ 326 { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */ 327 { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */ 328 { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */ 329 { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */ 330 { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */ 331 }; 332 333 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 334 /* 20MHz (50ns) */ 335 static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = { 336 { 0, 0, 0 }, /* dummy for async */ 337 { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */ 338 { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */ 339 { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 340 { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 341 { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */ 342 { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */ 343 { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */ 344 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */ 345 { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */ 346 { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */ 347 { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */ 348 { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */ 349 { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */ 350 { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */ 351 { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */ 352 }; 353 354 /* 33.3MHz (30ns) */ 355 static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = { 356 { 0, 0, 0 }, /* dummy for async */ 357 { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */ 358 { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */ 359 { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */ 360 { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */ 361 { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */ 362 { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */ 363 { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */ 364 { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */ 365 { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */ 366 { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */ 367 { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */ 368 { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */ 369 { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */ 370 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */ 371 { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */ 372 }; 373 #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */ 374 375 #undef NS 376 #undef ACKW 377 #undef SMPL 378 379 /* initialize device */ 380 static void 381 njsc32_init(sc, nosleep) 382 struct njsc32_softc *sc; 383 int nosleep; 384 { 385 u_int16_t intstat; 386 387 /* block all interrupts */ 388 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 389 390 /* clear transfer */ 391 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 392 njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0); 393 394 /* make sure interrupts are cleared */ 395 /* XXX loop forever? */ 396 while ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ)) & 397 NJSC32_IRQ_INTR_PENDING) { 398 DPRINTF(("%s: njsc32_init: intr pending: %#x\n", 399 sc->sc_dev.dv_xname, intstat)); 400 } 401 402 /* FIFO threshold */ 403 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL, 404 NJSC32_FIFO_FULL_BUSMASTER); 405 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY, 406 NJSC32_FIFO_EMPTY_BUSMASTER); 407 408 /* clock source */ 409 njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk); 410 411 /* memory read multiple */ 412 njsc32_ireg_write_1(sc, NJSC32_IREG_BM, 413 NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD); 414 415 /* clear parity error and enable parity detection */ 416 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 417 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 418 419 /* misc configuration */ 420 njsc32_ireg_write_2(sc, NJSC32_IREG_MISC, 421 NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT | 422 NJSC32_MISC_DELAYED_BMSTART | 423 NJSC32_MISC_MASTER_TERMINATION_SELECT | 424 NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL | 425 NJSC32_MISC_AUTOSEL_TIMING_SEL | 426 NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE); 427 428 /* 429 * Check for termination power (32Bi only?). 430 */ 431 if (!nosleep || cold) { 432 DPRINTF(("%s: njsc32_init: checking TERMPWR\n", 433 sc->sc_dev.dv_xname)); 434 435 /* First, turn termination power off */ 436 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0); 437 438 /* give 0.5s to settle */ 439 if (nosleep) 440 delay(500000); 441 else 442 tsleep(sc, PWAIT, "njs_t1", hz / 2); 443 } 444 445 /* supply termination power if not supplied by other devices */ 446 if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) & 447 NJSC32_TERMPWR_SENSE) == 0) { 448 /* termination power is not present on the bus */ 449 if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) { 450 /* 451 * CardBus device must not supply termination power 452 * to avoid excessive power consumption. 453 */ 454 printf("%s: no termination power present\n", 455 sc->sc_dev.dv_xname); 456 } else { 457 /* supply termination power */ 458 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 459 NJSC32_TERMPWR_BPWR); 460 461 DPRINTF(("%s: supplying termination power\n", 462 sc->sc_dev.dv_xname)); 463 464 /* give 0.5s to settle */ 465 if (!nosleep) 466 tsleep(sc, PWAIT, "njs_t2", hz / 2); 467 } 468 } 469 470 /* stop timer */ 471 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 472 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 473 474 /* default transfer parameter */ 475 njsc32_write_1(sc, NJSC32_REG_SYNC, 0); 476 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK); 477 njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT, 478 NJSC32_SEL_TIMEOUT_TIME); 479 480 /* select interrupt source */ 481 njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT, 482 NJSC32_IRQSEL_RESELECT | 483 NJSC32_IRQSEL_PHASE_CHANGE | 484 NJSC32_IRQSEL_SCSIRESET | 485 NJSC32_IRQSEL_TIMER | 486 NJSC32_IRQSEL_FIFO_THRESHOLD | 487 NJSC32_IRQSEL_TARGET_ABORT | 488 NJSC32_IRQSEL_MASTER_ABORT | 489 /* XXX not yet 490 NJSC32_IRQSEL_SERR | 491 NJSC32_IRQSEL_PERR | 492 NJSC32_IRQSEL_BMCNTERR | 493 */ 494 NJSC32_IRQSEL_AUTO_SCSI_SEQ); 495 496 /* unblock interrupts */ 497 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 498 499 /* turn LED off */ 500 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR, 501 NJSC32_EXTPORT_LED_OFF); 502 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, 503 NJSC32_EXTPORT_LED_OFF); 504 505 /* reset SCSI bus so the targets become known state */ 506 njsc32_reset_bus(sc); 507 } 508 509 static int 510 njsc32_init_cmds(sc) 511 struct njsc32_softc *sc; 512 { 513 struct njsc32_cmd *cmd; 514 bus_addr_t dmaaddr; 515 int i, error; 516 517 /* 518 * allocate DMA area for command 519 */ 520 if ((error = bus_dmamem_alloc(sc->sc_dmat, 521 sizeof(struct njsc32_dma_page), PAGE_SIZE, 0, 522 &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) { 523 printf("%s: unable to allocate cmd page, error = %d\n", 524 sc->sc_dev.dv_xname, error); 525 return 0; 526 } 527 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg, 528 sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page), 529 (caddr_t *)&sc->sc_cmdpg, 530 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 531 printf("%s: unable to map cmd page, error = %d\n", 532 sc->sc_dev.dv_xname, error); 533 goto fail1; 534 } 535 if ((error = bus_dmamap_create(sc->sc_dmat, 536 sizeof(struct njsc32_dma_page), 1, 537 sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT, 538 &sc->sc_dmamap_cmdpg)) != 0) { 539 printf("%s: unable to create cmd DMA map, error = %d\n", 540 sc->sc_dev.dv_xname, error); 541 goto fail2; 542 } 543 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg, 544 sc->sc_cmdpg, sizeof(struct njsc32_dma_page), 545 NULL, BUS_DMA_NOWAIT)) != 0) { 546 printf("%s: unable to load cmd DMA map, error = %d\n", 547 sc->sc_dev.dv_xname, error); 548 goto fail3; 549 } 550 551 memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page)); 552 dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr; 553 554 #ifdef NJSC32_AUTOPARAM 555 sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap); 556 #endif 557 558 for (i = 0; i < NJSC32_NUM_CMD; i++) { 559 cmd = &sc->sc_cmds[i]; 560 cmd->c_sc = sc; 561 cmd->c_sgt = sc->sc_cmdpg->dp_sg[i]; 562 cmd->c_sgt_dma = dmaaddr + 563 offsetof(struct njsc32_dma_page, dp_sg[i]); 564 cmd->c_flags = 0; 565 566 error = bus_dmamap_create(sc->sc_dmat, 567 NJSC32_MAX_XFER, /* max total map size */ 568 NJSC32_NUM_SG, /* max number of segments */ 569 NJSC32_SGT_MAXSEGLEN, /* max size of a segment */ 570 0, /* boundary */ 571 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer); 572 if (error) { 573 printf("%s: only %d cmd descs available (error = %d)\n", 574 sc->sc_dev.dv_xname, i, error); 575 break; 576 } 577 TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q); 578 } 579 580 if (i > 0) 581 return i; 582 583 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 584 fail2: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg, 585 sizeof(struct njsc32_dma_page)); 586 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs); 587 588 return 0; 589 } 590 591 static void 592 njsc32_target_async(sc, target) 593 struct njsc32_softc *sc; 594 struct njsc32_target *target; 595 { 596 597 target->t_sync = 598 NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC); 599 target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK; 600 target->t_sample = 0; /* disable */ 601 target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC; 602 target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC; 603 } 604 605 static void 606 njsc32_init_targets(sc) 607 struct njsc32_softc *sc; 608 { 609 int id, lun; 610 struct njsc32_lu *lu; 611 612 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 613 /* cancel negotiation status */ 614 sc->sc_targets[id].t_state = NJSC32_TARST_INIT; 615 616 /* default to async mode */ 617 njsc32_target_async(sc, &sc->sc_targets[id]); 618 619 #ifdef NJSC32_DUALEDGE 620 sc->sc_targets[id].t_xferctl = 0; 621 #endif 622 623 sc->sc_targets[id].t_targetid = 624 (1 << id) | (1 << NJSC32_INITIATOR_ID); 625 626 /* init logical units */ 627 for (lun = 0; lun < NJSC32_NLU; lun++) { 628 lu = &sc->sc_targets[id].t_lus[lun]; 629 lu->lu_cmd = NULL; 630 TAILQ_INIT(&lu->lu_q); 631 } 632 } 633 } 634 635 void 636 njsc32_attach(sc) 637 struct njsc32_softc *sc; 638 { 639 const char *str; 640 #if 1 /* test */ 641 int reg; 642 njsc32_model_t detected_model; 643 #endif 644 645 /* init */ 646 TAILQ_INIT(&sc->sc_freecmd); 647 TAILQ_INIT(&sc->sc_reqcmd); 648 649 #if 1 /* test */ 650 /* 651 * try to distinguish 32Bi and 32UDE 652 */ 653 /* try to set DualEdge bit (exists on 32UDE only) and read it back */ 654 njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE); 655 if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) { 656 /* device was removed? */ 657 aprint_error("%s: attach failed\n", sc->sc_dev.dv_xname); 658 return; 659 } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) { 660 detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE; 661 } else { 662 detected_model = NJSC32_MODEL_32BI; 663 } 664 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */ 665 666 #if 1/*def DIAGNOSTIC*/ 667 /* compare what is configured with what is detected */ 668 if ((sc->sc_model & NJSC32_MODEL_MASK) != 669 (detected_model & NJSC32_MODEL_MASK)) { 670 /* 671 * Please report this error if it happens. 672 */ 673 aprint_error("%s: model mismatch: %#x vs %#x\n", 674 sc->sc_dev.dv_xname, sc->sc_model, detected_model); 675 return; 676 } 677 #endif 678 #endif 679 680 /* check model */ 681 switch (sc->sc_model & NJSC32_MODEL_MASK) { 682 case NJSC32_MODEL_32BI: 683 str = "Bi"; 684 /* 32Bi doesn't support DualEdge transfer */ 685 KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0); 686 break; 687 case NJSC32_MODEL_32UDE: 688 str = "UDE"; 689 break; 690 default: 691 aprint_error("%s: unknown model!\n", sc->sc_dev.dv_xname); 692 return; 693 } 694 aprint_normal("%s: NJSC-32%s", sc->sc_dev.dv_xname, str); 695 696 switch (sc->sc_clk) { 697 default: 698 #ifdef DIAGNOSTIC 699 panic("njsc32_attach: unknown clk %d", sc->sc_clk); 700 #endif 701 case NJSC32_CLOCK_DIV_4: 702 sc->sc_synct = njsc32_synct_40M; 703 str = "40MHz"; 704 break; 705 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 706 case NJSC32_CLOCK_DIV_2: 707 sc->sc_synct = njsc32_synct_20M; 708 str = "20MHz"; 709 break; 710 case NJSC32_CLOCK_PCICLK: 711 sc->sc_synct = njsc32_synct_pci; 712 str = "PCI"; 713 break; 714 #endif 715 } 716 aprint_normal(", G/A rev %#x, clk %s%s\n", 717 NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str, 718 (sc->sc_model & NJSC32_FLAG_DUALEDGE) ? 719 #ifdef NJSC32_DUALEDGE 720 ", DualEdge" 721 #else 722 ", DualEdge (no driver support)" 723 #endif 724 : ""); 725 726 /* allocate DMA resource */ 727 if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) { 728 printf("%s: no usable DMA map\n", sc->sc_dev.dv_xname); 729 return; 730 } 731 sc->sc_flags |= NJSC32_CMDPG_MAPPED; 732 733 sc->sc_curcmd = NULL; 734 sc->sc_nusedcmds = 0; 735 sc->sc_stat = NJSC32_STAT_IDLE; 736 737 sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */ 738 739 /* initialize target structure */ 740 njsc32_init_targets(sc); 741 742 /* initialize hardware */ 743 njsc32_init(sc, cold); 744 745 /* setup adapter */ 746 sc->sc_adapter.adapt_dev = &sc->sc_dev; 747 sc->sc_adapter.adapt_nchannels = 1; 748 sc->sc_adapter.adapt_request = njsc32_scsipi_request; 749 sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys; 750 sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl; 751 752 sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings = 753 sc->sc_ncmd; 754 755 /* setup channel */ 756 sc->sc_channel.chan_adapter = &sc->sc_adapter; 757 sc->sc_channel.chan_bustype = &scsi_bustype; 758 sc->sc_channel.chan_channel = 0; 759 sc->sc_channel.chan_ntargets = NJSC32_NTARGET; 760 sc->sc_channel.chan_nluns = NJSC32_NLU; 761 sc->sc_channel.chan_id = NJSC32_INITIATOR_ID; 762 763 sc->sc_scsi = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 764 } 765 766 int 767 njsc32_detach(sc, flags) 768 struct njsc32_softc *sc; 769 int flags; 770 { 771 int rv = 0; 772 int i, s; 773 struct njsc32_cmd *cmd; 774 775 s = splbio(); 776 777 /* clear running/disconnected commands */ 778 njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP); 779 780 sc->sc_stat = NJSC32_STAT_DETACH; 781 782 /* clear pending commands */ 783 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 784 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 785 njsc32_end_cmd(sc, cmd, XS_RESET); 786 } 787 788 if (sc->sc_scsi != NULL) 789 rv = config_detach(sc->sc_scsi, flags); 790 791 splx(s); 792 793 /* free DMA resource */ 794 if (sc->sc_flags & NJSC32_CMDPG_MAPPED) { 795 for (i = 0; i < sc->sc_ncmd; i++) { 796 cmd = &sc->sc_cmds[i]; 797 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) 798 bus_dmamap_unload(sc->sc_dmat, 799 cmd->c_dmamap_xfer); 800 bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer); 801 } 802 803 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 804 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 805 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg, 806 sizeof(struct njsc32_dma_page)); 807 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, 808 sc->sc_cmdpg_nsegs); 809 } 810 811 return 0; 812 } 813 814 static __inline void 815 njsc32_cmd_init(cmd) 816 struct njsc32_cmd *cmd; 817 { 818 819 cmd->c_flags = 0; 820 821 /* scatter/gather table */ 822 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0); 823 cmd->c_sgoffset = 0; 824 cmd->c_sgfixcnt = 0; 825 826 /* data pointer */ 827 cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0; 828 } 829 830 static __inline void 831 njsc32_init_msgout(sc) 832 struct njsc32_softc *sc; 833 { 834 835 sc->sc_msgoutlen = 0; 836 sc->sc_msgoutidx = 0; 837 } 838 839 static void 840 njsc32_add_msgout(sc, byte) 841 struct njsc32_softc *sc; 842 int byte; 843 { 844 845 if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) { 846 printf("njsc32_add_msgout: too many\n"); 847 return; 848 } 849 sc->sc_msgout[sc->sc_msgoutlen++] = byte; 850 } 851 852 static u_int32_t 853 njsc32_get_auto_msgout(sc) 854 struct njsc32_softc *sc; 855 { 856 u_int32_t val; 857 u_int8_t *p; 858 859 val = 0; 860 p = sc->sc_msgout; 861 switch (sc->sc_msgoutlen) { 862 /* 31-24 23-16 15-8 7 ... 1 0 */ 863 case 3: /* MSG3 MSG2 MSG1 V --- cnt */ 864 val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT; 865 /* FALLTHROUGH */ 866 867 case 2: /* MSG2 MSG1 --- V --- cnt */ 868 val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT; 869 /* FALLTHROUGH */ 870 871 case 1: /* MSG1 --- --- V --- cnt */ 872 val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT; 873 val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen; 874 break; 875 876 default: 877 break; 878 } 879 return val; 880 } 881 882 #ifdef NJSC32_DUALEDGE 883 /* add Wide Data Transfer Request to the next Message Out */ 884 static void 885 njsc32_msgout_wdtr(sc, width) 886 struct njsc32_softc *sc; 887 int width; 888 { 889 890 njsc32_add_msgout(sc, MSG_EXTENDED); 891 njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN); 892 njsc32_add_msgout(sc, MSG_EXT_WDTR); 893 njsc32_add_msgout(sc, width); 894 } 895 #endif 896 897 /* add Synchronous Data Transfer Request to the next Message Out */ 898 static void 899 njsc32_msgout_sdtr(sc, period, offset) 900 struct njsc32_softc *sc; 901 int period, offset; 902 { 903 904 njsc32_add_msgout(sc, MSG_EXTENDED); 905 njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN); 906 njsc32_add_msgout(sc, MSG_EXT_SDTR); 907 njsc32_add_msgout(sc, period); 908 njsc32_add_msgout(sc, offset); 909 } 910 911 static void 912 njsc32_negotiate_xfer(sc, target) 913 struct njsc32_softc *sc; 914 struct njsc32_target *target; 915 { 916 917 /* initial negotiation state */ 918 if (target->t_state == NJSC32_TARST_INIT) { 919 #ifdef NJSC32_DUALEDGE 920 if (target->t_flags & NJSC32_TARF_DE) 921 target->t_state = NJSC32_TARST_DE; 922 else 923 #endif 924 if (target->t_flags & NJSC32_TARF_SYNC) 925 target->t_state = NJSC32_TARST_SDTR; 926 else 927 target->t_state = NJSC32_TARST_DONE; 928 } 929 930 switch (target->t_state) { 931 default: 932 case NJSC32_TARST_INIT: 933 #ifdef DIAGNOSTIC 934 panic("njsc32_negotiate_xfer"); 935 /* NOTREACHED */ 936 #endif 937 /* FALLTHROUGH */ 938 case NJSC32_TARST_DONE: 939 /* no more work */ 940 break; 941 942 #ifdef NJSC32_DUALEDGE 943 case NJSC32_TARST_DE: 944 njsc32_msgout_wdtr(sc, 0xde /* XXX? */); 945 break; 946 947 case NJSC32_TARST_WDTR: 948 njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT); 949 break; 950 #endif 951 952 case NJSC32_TARST_SDTR: 953 njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period, 954 NJSC32_SYNCOFFSET_MAX); 955 break; 956 957 case NJSC32_TARST_ASYNC: 958 njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC, 959 NJSC32_SYNCOFFSET_ASYNC); 960 break; 961 } 962 } 963 964 /* turn LED on */ 965 static __inline void 966 njsc32_led_on(sc) 967 struct njsc32_softc *sc; 968 { 969 970 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON); 971 } 972 973 /* turn LED off */ 974 static __inline void 975 njsc32_led_off(sc) 976 struct njsc32_softc *sc; 977 { 978 979 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF); 980 } 981 982 static void 983 njsc32_arbitration_failed(sc) 984 struct njsc32_softc *sc; 985 { 986 struct njsc32_cmd *cmd; 987 988 if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT) 989 return; 990 991 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) 992 callout_stop(&cmd->c_xs->xs_callout); 993 994 sc->sc_stat = NJSC32_STAT_IDLE; 995 sc->sc_curcmd = NULL; 996 997 /* the command is no longer active */ 998 if (--sc->sc_nusedcmds == 0) 999 njsc32_led_off(sc); 1000 } 1001 1002 static __inline void 1003 njsc32_cmd_load(sc, cmd) 1004 struct njsc32_softc *sc; 1005 struct njsc32_cmd *cmd; 1006 { 1007 struct njsc32_target *target; 1008 struct scsipi_xfer *xs; 1009 int i, control, lun; 1010 u_int32_t msgoutreg; 1011 #ifdef NJSC32_AUTOPARAM 1012 struct njsc32_autoparam *ap; 1013 #endif 1014 1015 xs = cmd->c_xs; 1016 #ifdef NJSC32_AUTOPARAM 1017 ap = &sc->sc_cmdpg->dp_ap; 1018 #else 1019 /* reset CDB pointer */ 1020 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR); 1021 #endif 1022 1023 /* CDB */ 1024 TPRINTC(cmd, ("njsc32_cmd_load: CDB")); 1025 for (i = 0; i < xs->cmdlen; i++) { 1026 #ifdef NJSC32_AUTOPARAM 1027 ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i]; 1028 #else 1029 njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA, 1030 ((u_int8_t *)xs->cmd)[i]); 1031 #endif 1032 TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i])); 1033 } 1034 #ifdef NJSC32_AUTOPARAM /* XXX needed? */ 1035 for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++) 1036 ap->ap_cdb[i].cdb_data = 0; 1037 #endif 1038 1039 control = xs->xs_control; 1040 1041 /* 1042 * Message Out 1043 */ 1044 njsc32_init_msgout(sc); 1045 1046 /* Identify */ 1047 lun = xs->xs_periph->periph_lun; 1048 njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ? 1049 MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1)); 1050 1051 /* tagged queueing */ 1052 if (control & XS_CTL_TAGMASK) { 1053 njsc32_add_msgout(sc, xs->xs_tag_type); 1054 njsc32_add_msgout(sc, xs->xs_tag_id); 1055 TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id)); 1056 } 1057 TPRINTF(("\n")); 1058 1059 target = cmd->c_target; 1060 1061 /* transfer negotiation */ 1062 if (control & XS_CTL_REQSENSE) 1063 target->t_state = NJSC32_TARST_INIT; 1064 njsc32_negotiate_xfer(sc, target); 1065 1066 msgoutreg = njsc32_get_auto_msgout(sc); 1067 1068 #ifdef NJSC32_AUTOPARAM 1069 ap->ap_msgout = htole32(msgoutreg); 1070 1071 ap->ap_sync = target->t_sync; 1072 ap->ap_ackwidth = target->t_ackwidth; 1073 ap->ap_targetid = target->t_targetid; 1074 ap->ap_sample = target->t_sample; 1075 1076 ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 1077 NJSC32_CMD_AUTO_COMMAND_PHASE | 1078 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1079 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1080 #ifdef NJSC32_DUALEDGE 1081 ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl); 1082 #else 1083 ap->ap_xferctl = htole16(cmd->c_xferctl); 1084 #endif 1085 ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr); 1086 1087 /* sync njsc32_autoparam */ 1088 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1089 offsetof(struct njsc32_dma_page, dp_ap), /* offset */ 1090 sizeof(struct njsc32_autoparam), 1091 BUS_DMASYNC_PREWRITE); 1092 1093 /* autoparam DMA address */ 1094 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma); 1095 1096 /* start command (autoparam) */ 1097 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1098 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER); 1099 1100 #else /* not NJSC32_AUTOPARAM */ 1101 1102 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg); 1103 1104 /* load parameters */ 1105 njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid); 1106 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1107 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1108 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1109 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1110 #ifdef NJSC32_DUALEDGE 1111 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1112 cmd->c_xferctl | target->t_xferctl); 1113 #else 1114 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1115 #endif 1116 /* start AutoSCSI */ 1117 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1118 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE | 1119 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1120 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1121 #endif /* not NJSC32_AUTOPARAM */ 1122 } 1123 1124 /* Note: must be called at splbio() */ 1125 static void 1126 njsc32_start(sc) 1127 struct njsc32_softc *sc; 1128 { 1129 struct njsc32_cmd *cmd; 1130 1131 /* get a command to issue */ 1132 TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) { 1133 if (cmd->c_lu->lu_cmd == NULL && 1134 ((cmd->c_flags & NJSC32_CMD_TAGGED) || 1135 TAILQ_EMPTY(&cmd->c_lu->lu_q))) 1136 break; /* OK, the logical unit is free */ 1137 } 1138 if (!cmd) 1139 goto out; /* no work to do */ 1140 1141 /* request will always fail if not in bus free phase */ 1142 if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) != 1143 NJSC32_BUSMON_BUSFREE) 1144 goto busy; 1145 1146 /* clear parity error and enable parity detection */ 1147 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1148 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1149 1150 njsc32_cmd_load(sc, cmd); 1151 1152 if (sc->sc_nusedcmds++ == 0) 1153 njsc32_led_on(sc); 1154 1155 sc->sc_curcmd = cmd; 1156 sc->sc_stat = NJSC32_STAT_ARBIT; 1157 1158 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) { 1159 callout_reset(&cmd->c_xs->xs_callout, 1160 mstohz(cmd->c_xs->timeout), 1161 njsc32_cmdtimeout, cmd); 1162 } 1163 1164 return; 1165 1166 busy: /* XXX retry counter */ 1167 TPRINTF(("%s: njsc32_start: busy\n", sc->sc_dev.dv_xname)); 1168 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME); 1169 out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 1170 } 1171 1172 static void 1173 njsc32_run_xfer(sc, xs) 1174 struct njsc32_softc *sc; 1175 struct scsipi_xfer *xs; 1176 { 1177 struct scsipi_periph *periph; 1178 int control; 1179 int lun; 1180 struct njsc32_cmd *cmd; 1181 int s, i, error; 1182 1183 periph = xs->xs_periph; 1184 KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID); 1185 1186 control = xs->xs_control; 1187 lun = periph->periph_lun; 1188 1189 /* 1190 * get a free cmd 1191 * (scsipi layer knows the number of cmds, so this shall never fail) 1192 */ 1193 s = splbio(); 1194 cmd = TAILQ_FIRST(&sc->sc_freecmd); 1195 KASSERT(cmd); 1196 TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q); 1197 splx(s); 1198 1199 /* 1200 * build a request 1201 */ 1202 njsc32_cmd_init(cmd); 1203 cmd->c_xs = xs; 1204 cmd->c_target = &sc->sc_targets[periph->periph_target]; 1205 cmd->c_lu = &cmd->c_target->t_lus[lun]; 1206 1207 /* tagged queueing */ 1208 if (control & XS_CTL_TAGMASK) { 1209 cmd->c_flags |= NJSC32_CMD_TAGGED; 1210 if (control & XS_CTL_HEAD_TAG) 1211 cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD; 1212 } 1213 1214 /* map DMA buffer */ 1215 cmd->c_datacnt = xs->datalen; 1216 if (xs->datalen) { 1217 /* Is XS_CTL_DATA_UIO ever used anywhere? */ 1218 KASSERT((control & XS_CTL_DATA_UIO) == 0); 1219 1220 error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer, 1221 xs->data, xs->datalen, NULL, 1222 ((control & XS_CTL_NOSLEEP) ? 1223 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 1224 BUS_DMA_STREAMING | 1225 ((control & XS_CTL_DATA_IN) ? 1226 BUS_DMA_READ : BUS_DMA_WRITE)); 1227 1228 switch (error) { 1229 case 0: 1230 break; 1231 case ENOMEM: 1232 case EAGAIN: 1233 xs->error = XS_RESOURCE_SHORTAGE; 1234 goto map_failed; 1235 default: 1236 xs->error = XS_DRIVER_STUFFUP; 1237 map_failed: 1238 printf("%s: njsc32_run_xfer: map failed, error %d\n", 1239 sc->sc_dev.dv_xname, error); 1240 /* put it back to free command list */ 1241 s = splbio(); 1242 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1243 splx(s); 1244 /* abort this transfer */ 1245 scsipi_done(xs); 1246 return; 1247 } 1248 1249 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1250 0, cmd->c_dmamap_xfer->dm_mapsize, 1251 (control & XS_CTL_DATA_IN) ? 1252 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1253 1254 for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) { 1255 cmd->c_sgt[i].sg_addr = 1256 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr); 1257 cmd->c_sgt[i].sg_len = 1258 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len); 1259 } 1260 /* end mark */ 1261 cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK); 1262 1263 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1264 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1265 NJSC32_SIZE_SGT, 1266 BUS_DMASYNC_PREWRITE); 1267 1268 cmd->c_flags |= NJSC32_CMD_DMA_MAPPED; 1269 1270 /* enable transfer */ 1271 cmd->c_xferctl = 1272 NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START | 1273 NJSC32_XFR_ALL_COUNT_CLR; 1274 1275 /* XXX How can we specify the DMA direction? */ 1276 1277 #if 0 /* faster write mode? (doesn't work) */ 1278 if ((control & XS_CTL_DATA_IN) == 0) 1279 cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE; 1280 #endif 1281 } else { 1282 /* no data transfer */ 1283 cmd->c_xferctl = 0; 1284 } 1285 1286 /* queue request */ 1287 s = splbio(); 1288 TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q); 1289 1290 /* start the controller if idle */ 1291 if (sc->sc_stat == NJSC32_STAT_IDLE) 1292 njsc32_start(sc); 1293 1294 splx(s); 1295 1296 if (control & XS_CTL_POLL) { 1297 /* wait for completion */ 1298 /* XXX should handle timeout? */ 1299 while ((xs->xs_status & XS_STS_DONE) == 0) { 1300 delay(1000); 1301 njsc32_intr(sc); 1302 } 1303 } 1304 } 1305 1306 static void 1307 njsc32_end_cmd(sc, cmd, result) 1308 struct njsc32_softc *sc; 1309 struct njsc32_cmd *cmd; 1310 scsipi_xfer_result_t result; 1311 { 1312 struct scsipi_xfer *xs; 1313 int s; 1314 #ifdef DIAGNOSTIC 1315 struct njsc32_cmd *c; 1316 #endif 1317 1318 KASSERT(cmd); 1319 1320 #ifdef DIAGNOSTIC 1321 s = splbio(); 1322 TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) { 1323 if (cmd == c) 1324 panic("njsc32_end_cmd: already in free list"); 1325 } 1326 splx(s); 1327 #endif 1328 xs = cmd->c_xs; 1329 1330 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) { 1331 if (cmd->c_datacnt) { 1332 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1333 0, cmd->c_dmamap_xfer->dm_mapsize, 1334 (xs->xs_control & XS_CTL_DATA_IN) ? 1335 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1336 1337 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1338 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, 1339 NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE); 1340 } 1341 1342 bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer); 1343 cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED; 1344 } 1345 1346 s = splbio(); 1347 if ((xs->xs_control & XS_CTL_POLL) == 0) 1348 callout_stop(&xs->xs_callout); 1349 1350 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1351 splx(s); 1352 1353 xs->error = result; 1354 scsipi_done(xs); 1355 1356 if (--sc->sc_nusedcmds == 0) 1357 njsc32_led_off(sc); 1358 } 1359 1360 /* 1361 * request from scsipi layer 1362 */ 1363 void 1364 njsc32_scsipi_request(chan, req, arg) 1365 struct scsipi_channel *chan; 1366 scsipi_adapter_req_t req; 1367 void *arg; 1368 { 1369 struct njsc32_softc *sc; 1370 struct scsipi_xfer_mode *xm; 1371 struct njsc32_target *target; 1372 1373 sc = (void *)chan->chan_adapter->adapt_dev; 1374 1375 switch (req) { 1376 case ADAPTER_REQ_RUN_XFER: 1377 njsc32_run_xfer(sc, arg); 1378 break; 1379 1380 case ADAPTER_REQ_GROW_RESOURCES: 1381 /* not supported */ 1382 break; 1383 1384 case ADAPTER_REQ_SET_XFER_MODE: 1385 xm = arg; 1386 target = &sc->sc_targets[xm->xm_target]; 1387 1388 target->t_flags = 0; 1389 if (xm->xm_mode & PERIPH_CAP_TQING) 1390 target->t_flags |= NJSC32_TARF_TAG; 1391 if (xm->xm_mode & PERIPH_CAP_SYNC) { 1392 target->t_flags |= NJSC32_TARF_SYNC; 1393 #ifdef NJSC32_DUALEDGE 1394 if (sc->sc_model & NJSC32_FLAG_DUALEDGE) 1395 target->t_flags |= NJSC32_TARF_DE; 1396 #endif 1397 } 1398 #ifdef NJSC32_DUALEDGE 1399 target->t_xferctl = 0; 1400 #endif 1401 target->t_state = NJSC32_TARST_INIT; 1402 njsc32_target_async(sc, target); 1403 1404 break; 1405 default: 1406 break; 1407 } 1408 } 1409 1410 void 1411 njsc32_scsipi_minphys(bp) 1412 struct buf *bp; 1413 { 1414 1415 if (bp->b_bcount > NJSC32_MAX_XFER) 1416 bp->b_bcount = NJSC32_MAX_XFER; 1417 minphys(bp); 1418 } 1419 1420 static void 1421 njsc32_reset_bus(sc) 1422 struct njsc32_softc *sc; 1423 { 1424 int s; 1425 1426 DPRINTF(("%s: njsc32_reset_bus:\n", sc->sc_dev.dv_xname)); 1427 1428 /* SCSI bus reset */ 1429 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST); 1430 delay(NJSC32_RESET_HOLD_TIME); 1431 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0); 1432 1433 /* clear transfer */ 1434 s = splbio(); 1435 njsc32_reset_detected(sc); 1436 splx(s); 1437 } 1438 1439 /* 1440 * clear running/disconnected commands 1441 */ 1442 static void 1443 njsc32_clear_cmds(sc, cmdresult) 1444 struct njsc32_softc *sc; 1445 scsipi_xfer_result_t cmdresult; 1446 { 1447 struct njsc32_cmd *cmd; 1448 int id, lun; 1449 struct njsc32_lu *lu; 1450 1451 njsc32_arbitration_failed(sc); 1452 1453 /* clear current transfer */ 1454 if ((cmd = sc->sc_curcmd) != NULL) { 1455 sc->sc_curcmd = NULL; 1456 njsc32_end_cmd(sc, cmd, cmdresult); 1457 } 1458 1459 /* clear disconnected transfers */ 1460 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 1461 for (lun = 0; lun < NJSC32_NLU; lun++) { 1462 lu = &sc->sc_targets[id].t_lus[lun]; 1463 1464 if ((cmd = lu->lu_cmd) != NULL) { 1465 lu->lu_cmd = NULL; 1466 njsc32_end_cmd(sc, cmd, cmdresult); 1467 } 1468 while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) { 1469 TAILQ_REMOVE(&lu->lu_q, cmd, c_q); 1470 njsc32_end_cmd(sc, cmd, cmdresult); 1471 } 1472 } 1473 } 1474 } 1475 1476 static void 1477 njsc32_reset_detected(sc) 1478 struct njsc32_softc *sc; 1479 { 1480 1481 njsc32_clear_cmds(sc, XS_RESET); 1482 njsc32_init_targets(sc); 1483 sc->sc_stat = NJSC32_STAT_IDLE; 1484 KASSERT(sc->sc_nusedcmds == 0); 1485 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL); 1486 } 1487 1488 int 1489 njsc32_scsipi_ioctl(chan, cmd, addr, flag, p) 1490 struct scsipi_channel *chan; 1491 u_long cmd; 1492 caddr_t addr; 1493 int flag; 1494 struct proc *p; 1495 { 1496 struct njsc32_softc *sc = (void *)chan->chan_adapter->adapt_dev; 1497 1498 switch (cmd) { 1499 case SCBUSIORESET: 1500 njsc32_init(sc, 0); 1501 return 0; 1502 default: 1503 break; 1504 } 1505 1506 return ENOTTY; 1507 } 1508 1509 /* 1510 * set current data pointer 1511 */ 1512 static __inline void 1513 njsc32_set_cur_ptr(cmd, pos) 1514 struct njsc32_cmd *cmd; 1515 u_int32_t pos; 1516 { 1517 1518 /* new current data pointer */ 1519 cmd->c_dp_cur = pos; 1520 1521 /* update number of bytes transferred */ 1522 if (pos > cmd->c_dp_max) 1523 cmd->c_dp_max = pos; 1524 } 1525 1526 /* 1527 * set data pointer for the next transfer 1528 */ 1529 static void 1530 njsc32_set_ptr(sc, cmd, pos) 1531 struct njsc32_softc *sc; 1532 struct njsc32_cmd *cmd; 1533 u_int32_t pos; 1534 { 1535 struct njsc32_sgtable *sg; 1536 unsigned sgte; 1537 u_int32_t len; 1538 1539 /* set current pointer */ 1540 njsc32_set_cur_ptr(cmd, pos); 1541 1542 /* undo previous fix if any */ 1543 if (cmd->c_sgfixcnt != 0) { 1544 sg = &cmd->c_sgt[cmd->c_sgoffset]; 1545 sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt); 1546 sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt); 1547 cmd->c_sgfixcnt = 0; 1548 } 1549 1550 if (pos >= cmd->c_datacnt) { 1551 /* transfer done */ 1552 #if 1 /*def DIAGNOSTIC*/ 1553 if (pos > cmd->c_datacnt) 1554 printf("%s: pos %u too large\n", 1555 sc->sc_dev.dv_xname, pos - cmd->c_datacnt); 1556 #endif 1557 cmd->c_xferctl = 0; /* XXX correct? */ 1558 1559 return; 1560 } 1561 1562 for (sgte = 0, sg = cmd->c_sgt; 1563 sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) { 1564 len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK; 1565 if (pos < len) { 1566 sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos); 1567 sg->sg_len = htole32(le32toh(sg->sg_len) - pos); 1568 cmd->c_sgfixcnt = pos; 1569 break; 1570 } 1571 pos -= len; 1572 #ifdef DIAGNOSTIC 1573 if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) { 1574 panic("njsc32_set_ptr: bad pos"); 1575 } 1576 #endif 1577 } 1578 #ifdef DIAGNOSTIC 1579 if (sgte >= NJSC32_NUM_SG) 1580 panic("njsc32_set_ptr: bad sg"); 1581 #endif 1582 if (cmd->c_sgoffset != sgte) { 1583 cmd->c_sgoffset = sgte; 1584 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte); 1585 } 1586 1587 /* XXX overkill */ 1588 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1589 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1590 NJSC32_SIZE_SGT, 1591 BUS_DMASYNC_PREWRITE); 1592 } 1593 1594 /* 1595 * save data pointer 1596 */ 1597 static __inline void 1598 njsc32_save_ptr(cmd) 1599 struct njsc32_cmd *cmd; 1600 { 1601 1602 cmd->c_dp_saved = cmd->c_dp_cur; 1603 } 1604 1605 static void 1606 njsc32_assert_ack(sc) 1607 struct njsc32_softc *sc; 1608 { 1609 u_int8_t reg; 1610 1611 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1612 reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE; 1613 #if 0 /* needed? */ 1614 reg |= NJSC32_SBCTL_AUTODIRECTION; 1615 #endif 1616 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1617 } 1618 1619 static void 1620 njsc32_negate_ack(sc) 1621 struct njsc32_softc *sc; 1622 { 1623 u_int8_t reg; 1624 1625 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1626 #if 0 /* needed? */ 1627 reg |= NJSC32_SBCTL_ACK_ENABLE; 1628 reg |= NJSC32_SBCTL_AUTODIRECTION; 1629 #endif 1630 reg &= ~NJSC32_SBCTL_ACK; 1631 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1632 } 1633 1634 static void 1635 njsc32_wait_req_negate(sc) 1636 struct njsc32_softc *sc; 1637 { 1638 int cnt; 1639 1640 for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) { 1641 if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 1642 NJSC32_BUSMON_REQ) == 0) 1643 return; 1644 delay(1); 1645 } 1646 printf("%s: njsc32_wait_req_negate: timed out\n", sc->sc_dev.dv_xname); 1647 } 1648 1649 static void 1650 njsc32_reconnect(sc, cmd) 1651 struct njsc32_softc *sc; 1652 struct njsc32_cmd *cmd; 1653 { 1654 struct scsipi_xfer *xs; 1655 1656 xs = cmd->c_xs; 1657 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1658 callout_stop(&xs->xs_callout); 1659 callout_reset(&xs->xs_callout, 1660 mstohz(xs->timeout), 1661 njsc32_cmdtimeout, cmd); 1662 } 1663 1664 /* Reconnection implies Restore Pointers */ 1665 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1666 } 1667 1668 static enum njsc32_reselstat 1669 njsc32_resel_identify(sc, lun, pcmd) 1670 struct njsc32_softc *sc; 1671 int lun; 1672 struct njsc32_cmd **pcmd; 1673 { 1674 int targetid; 1675 struct njsc32_lu *plu; 1676 struct njsc32_cmd *cmd; 1677 1678 switch (sc->sc_stat) { 1679 case NJSC32_STAT_RESEL: 1680 break; /* OK */ 1681 1682 case NJSC32_STAT_RESEL_LUN: 1683 case NJSC32_STAT_RECONNECT: 1684 /* 1685 * accept and ignore if the LUN is the same as the current one, 1686 * reject otherwise. 1687 */ 1688 return sc->sc_resellun == lun ? 1689 NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR; 1690 1691 default: 1692 printf("%s: njsc32_resel_identify: not in reselection\n", 1693 sc->sc_dev.dv_xname); 1694 return NJSC32_RESEL_ERROR; 1695 } 1696 1697 targetid = sc->sc_reselid; 1698 TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n", 1699 sc->sc_dev.dv_xname, lun)); 1700 1701 if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU) 1702 return NJSC32_RESEL_ERROR; 1703 1704 sc->sc_resellun = lun; 1705 plu = &sc->sc_targets[targetid].t_lus[lun]; 1706 1707 if ((cmd = plu->lu_cmd) != NULL) { 1708 sc->sc_stat = NJSC32_STAT_RECONNECT; 1709 plu->lu_cmd = NULL; 1710 *pcmd = cmd; 1711 TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n")); 1712 njsc32_reconnect(sc, cmd); 1713 return NJSC32_RESEL_COMPLETE; 1714 } else if (!TAILQ_EMPTY(&plu->lu_q)) { 1715 /* wait for tag */ 1716 sc->sc_stat = NJSC32_STAT_RESEL_LUN; 1717 return NJSC32_RESEL_THROUGH; 1718 } 1719 1720 /* no disconnected commands */ 1721 return NJSC32_RESEL_ERROR; 1722 } 1723 1724 static enum njsc32_reselstat 1725 njsc32_resel_tag(sc, tag, pcmd) 1726 struct njsc32_softc *sc; 1727 int tag; 1728 struct njsc32_cmd **pcmd; 1729 { 1730 struct njsc32_cmd_head *head; 1731 struct njsc32_cmd *cmd; 1732 1733 TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n", 1734 sc->sc_dev.dv_xname, tag)); 1735 if (sc->sc_stat != NJSC32_STAT_RESEL_LUN) 1736 return NJSC32_RESEL_ERROR; 1737 1738 head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q; 1739 1740 /* XXX slow? */ 1741 /* search for the command of the tag */ 1742 TAILQ_FOREACH(cmd, head, c_q) { 1743 if (cmd->c_xs->xs_tag_id == tag) { 1744 sc->sc_stat = NJSC32_STAT_RECONNECT; 1745 TAILQ_REMOVE(head, cmd, c_q); 1746 *pcmd = cmd; 1747 TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n")); 1748 njsc32_reconnect(sc, cmd); 1749 return NJSC32_RESEL_COMPLETE; 1750 } 1751 } 1752 1753 /* no disconnected commands */ 1754 return NJSC32_RESEL_ERROR; 1755 } 1756 1757 /* 1758 * Reload parameters and restart AutoSCSI. 1759 * 1760 * XXX autoparam doesn't work as expected and we can't use it here. 1761 */ 1762 static void 1763 njsc32_cmd_reload(sc, cmd, cctl) 1764 struct njsc32_softc *sc; 1765 struct njsc32_cmd *cmd; 1766 int cctl; 1767 { 1768 struct njsc32_target *target; 1769 1770 target = cmd->c_target; 1771 1772 /* clear parity error and enable parity detection */ 1773 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1774 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1775 1776 /* load parameters */ 1777 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1778 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1779 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1780 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1781 #ifdef NJSC32_DUALEDGE 1782 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1783 cmd->c_xferctl | target->t_xferctl); 1784 #else 1785 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1786 #endif 1787 /* start AutoSCSI */ 1788 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 1789 1790 sc->sc_curcmd = cmd; 1791 } 1792 1793 static void 1794 njsc32_update_xfer_mode(sc, target) 1795 struct njsc32_softc *sc; 1796 struct njsc32_target *target; 1797 { 1798 struct scsipi_xfer_mode xm; 1799 1800 xm.xm_target = target - sc->sc_targets; /* target ID */ 1801 xm.xm_mode = 0; 1802 xm.xm_period = target->t_syncperiod; 1803 xm.xm_offset = target->t_syncoffset; 1804 if (xm.xm_offset != 0) 1805 xm.xm_mode |= PERIPH_CAP_SYNC; 1806 if (target->t_flags & NJSC32_TARF_TAG) 1807 xm.xm_mode |= PERIPH_CAP_TQING; 1808 1809 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 1810 } 1811 1812 static void 1813 njsc32_msgin(sc) 1814 struct njsc32_softc *sc; 1815 { 1816 u_int8_t msg0, msg; 1817 int msgcnt; 1818 struct njsc32_cmd *cmd; 1819 enum njsc32_reselstat rstat; 1820 int cctl = 0; 1821 u_int32_t ptr; /* unsigned type ensures 2-complement calculation */ 1822 u_int32_t msgout = 0; 1823 boolean_t reload_params = FALSE; 1824 struct njsc32_target *target; 1825 int idx, period, offset; 1826 1827 /* 1828 * we are in Message In, so the previous Message Out should have 1829 * been done. 1830 */ 1831 njsc32_init_msgout(sc); 1832 1833 /* get a byte of Message In */ 1834 msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN); 1835 TPRINTF(("%s: njsc32_msgin: got %#x\n", sc->sc_dev.dv_xname, msg)); 1836 if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN) 1837 sc->sc_msginbuf[sc->sc_msgincnt] = msg; 1838 1839 njsc32_assert_ack(sc); 1840 1841 msg0 = sc->sc_msginbuf[0]; 1842 cmd = sc->sc_curcmd; 1843 1844 /* check for parity error */ 1845 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 1846 NJSC32_PARITYSTATUS_ERROR_LSB) { 1847 1848 printf("%s: msgin: parity error\n", sc->sc_dev.dv_xname); 1849 1850 /* clear parity error */ 1851 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1852 NJSC32_PARITYCTL_CHECK_ENABLE | 1853 NJSC32_PARITYCTL_CLEAR_ERROR); 1854 1855 /* respond as Message Parity Error */ 1856 njsc32_add_msgout(sc, MSG_PARITY_ERROR); 1857 1858 /* clear Message In */ 1859 sc->sc_msgincnt = 0; 1860 goto reply; 1861 } 1862 1863 #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0) 1864 #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0) 1865 if (MSG_ISIDENTIFY(msg0)) { 1866 /* 1867 * Got Identify message from target. 1868 */ 1869 if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG || 1870 (rstat = njsc32_resel_identify(sc, msg0 & 1871 MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) { 1872 /* 1873 * invalid Identify -> Reject 1874 */ 1875 goto reject; 1876 } 1877 if (rstat == NJSC32_RESEL_COMPLETE) 1878 reload_params = TRUE; 1879 MSGCOMPLETE; 1880 } 1881 1882 if (msg0 == MSG_SIMPLE_Q_TAG) { 1883 if (msgcnt == 0) 1884 WAITNEXTMSG; 1885 1886 /* got whole message */ 1887 sc->sc_msgincnt = 0; 1888 1889 if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd)) 1890 == NJSC32_RESEL_ERROR) { 1891 /* 1892 * invalid Simple Queue Tag -> Abort Tag 1893 */ 1894 printf("%s: msgin: invalid tag\n", sc->sc_dev.dv_xname); 1895 njsc32_add_msgout(sc, MSG_ABORT_TAG); 1896 goto reply; 1897 } 1898 if (rstat == NJSC32_RESEL_COMPLETE) 1899 reload_params = TRUE; 1900 MSGCOMPLETE; 1901 } 1902 1903 /* I_T_L or I_T_L_Q nexus should be established now */ 1904 if (cmd == NULL) { 1905 printf("%s: msgin %#x without nexus -- sending abort\n", 1906 sc->sc_dev.dv_xname, msg0); 1907 njsc32_add_msgout(sc, MSG_ABORT); 1908 goto reply; 1909 } 1910 1911 /* 1912 * extended message 1913 * 0x01 <length (0 stands for 256)> <length bytes> 1914 * (<code> [<parameter> ...]) 1915 */ 1916 #define EXTLENOFF 1 1917 #define EXTCODEOFF 2 1918 if (msg0 == MSG_EXTENDED) { 1919 if (msgcnt < EXTLENOFF || 1920 msgcnt < EXTLENOFF + 1 + 1921 (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1)) 1922 WAITNEXTMSG; 1923 1924 /* got whole message */ 1925 sc->sc_msgincnt = 0; 1926 1927 switch (sc->sc_msginbuf[EXTCODEOFF]) { 1928 case 0: /* Modify Data Pointer */ 1929 if (msgcnt != 5 + EXTCODEOFF - 1) 1930 break; 1931 /* 1932 * parameter is 32bit big-endian signed (2-complement) 1933 * value 1934 */ 1935 ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) | 1936 (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) | 1937 (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) | 1938 sc->sc_msginbuf[EXTCODEOFF + 4]; 1939 1940 /* new pointer */ 1941 ptr += cmd->c_dp_cur; /* ignore overflow */ 1942 1943 /* reject if ptr is not in data buffer */ 1944 if (ptr > cmd->c_datacnt) 1945 break; 1946 1947 njsc32_set_ptr(sc, cmd, ptr); 1948 goto restart; 1949 1950 case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */ 1951 DPRINTC(cmd, ("SDTR %#x %#x\n", 1952 sc->sc_msginbuf[EXTCODEOFF + 1], 1953 sc->sc_msginbuf[EXTCODEOFF + 2])); 1954 if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1) 1955 break; /* reject */ 1956 1957 target = cmd->c_target; 1958 1959 /* lookup sync period parameters */ 1960 period = sc->sc_msginbuf[EXTCODEOFF + 1]; 1961 for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++) 1962 if (sc->sc_synct[idx].sp_period >= period) { 1963 period = sc->sc_synct[idx].sp_period; 1964 break; 1965 } 1966 if (idx >= NJSC32_NSYNCT) { 1967 /* 1968 * We can't meet the timing condition that 1969 * the target requests -- use async. 1970 */ 1971 njsc32_target_async(sc, target); 1972 njsc32_update_xfer_mode(sc, target); 1973 if (target->t_state == NJSC32_TARST_SDTR) { 1974 /* 1975 * We started SDTR exchange -- start 1976 * negotiation again and request async. 1977 */ 1978 target->t_state = NJSC32_TARST_ASYNC; 1979 njsc32_negotiate_xfer(sc, target); 1980 goto reply; 1981 } else { 1982 /* 1983 * The target started SDTR exchange 1984 * -- just reject and fallback 1985 * to async. 1986 */ 1987 goto reject; 1988 } 1989 } 1990 1991 /* check sync offset */ 1992 offset = sc->sc_msginbuf[EXTCODEOFF + 2]; 1993 if (offset > NJSC32_SYNCOFFSET_MAX) { 1994 if (target->t_state == NJSC32_TARST_SDTR) { 1995 printf("%s: wrong sync offset: %d\n", 1996 cmd->c_xs->xs_periph->periph_dev->dv_xname, 1997 offset); 1998 /* XXX what to do? */ 1999 } 2000 offset = NJSC32_SYNCOFFSET_MAX; 2001 } 2002 2003 target->t_ackwidth = sc->sc_synct[idx].sp_ackw; 2004 target->t_sample = sc->sc_synct[idx].sp_sample; 2005 target->t_syncperiod = period; 2006 target->t_syncoffset = offset; 2007 target->t_sync = NJSC32_SYNC_VAL(idx, offset); 2008 njsc32_update_xfer_mode(sc, target); 2009 2010 if (target->t_state == NJSC32_TARST_SDTR) { 2011 target->t_state = NJSC32_TARST_DONE; 2012 } else { 2013 njsc32_msgout_sdtr(sc, period, offset); 2014 goto reply; 2015 } 2016 goto restart; 2017 2018 case MSG_EXT_WDTR: /* Wide Data Transfer Request */ 2019 DPRINTC(cmd, 2020 ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1])); 2021 #ifdef NJSC32_DUALEDGE 2022 if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1) 2023 break; /* reject */ 2024 2025 /* 2026 * T->I of this message is not used for 2027 * DualEdge negotiation, so the device 2028 * must not be a DualEdge device. 2029 * 2030 * XXX correct? 2031 */ 2032 target = cmd->c_target; 2033 target->t_xferctl = 0; 2034 2035 switch (target->t_state) { 2036 case NJSC32_TARST_DE: 2037 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 2038 MSG_EXT_WDTR_BUS_8_BIT) { 2039 /* 2040 * Oops, we got unexpected WDTR. 2041 * Negotiate for 8bit. 2042 */ 2043 target->t_state = NJSC32_TARST_WDTR; 2044 } else { 2045 target->t_state = NJSC32_TARST_SDTR; 2046 } 2047 njsc32_negotiate_xfer(sc, target); 2048 goto reply; 2049 2050 case NJSC32_TARST_WDTR: 2051 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 2052 MSG_EXT_WDTR_BUS_8_BIT) { 2053 printf("%s: unexpected transfer width: %#x\n", 2054 cmd->c_xs->xs_periph->periph_dev->dv_xname, 2055 sc->sc_msginbuf[EXTCODEOFF + 1]); 2056 /* XXX what to do? */ 2057 } 2058 target->t_state = NJSC32_TARST_SDTR; 2059 njsc32_negotiate_xfer(sc, target); 2060 goto reply; 2061 2062 default: 2063 /* the target started WDTR exchange */ 2064 DPRINTC(cmd, ("WDTR from target\n")); 2065 2066 target->t_state = NJSC32_TARST_SDTR; 2067 njsc32_target_async(sc, target); 2068 2069 break; /* reject the WDTR (8bit transfer) */ 2070 } 2071 #endif /* NJSC32_DUALEDGE */ 2072 break; /* reject */ 2073 } 2074 DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n", 2075 sc->sc_msginbuf[EXTCODEOFF], msgcnt)); 2076 goto reject; 2077 } 2078 2079 /* 2byte messages */ 2080 if (MSG_IS2BYTE(msg0)) { 2081 if (msgcnt == 0) 2082 WAITNEXTMSG; 2083 2084 /* got whole message */ 2085 sc->sc_msgincnt = 0; 2086 } 2087 2088 switch (msg0) { 2089 case MSG_CMDCOMPLETE: /* 0x00 */ 2090 case MSG_SAVEDATAPOINTER: /* 0x02 */ 2091 case MSG_DISCONNECT: /* 0x04 */ 2092 /* handled by AutoSCSI */ 2093 PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0)); 2094 break; 2095 2096 case MSG_RESTOREPOINTERS: /* 0x03 */ 2097 /* restore data pointer to what was saved */ 2098 DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n")); 2099 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 2100 reload_params = TRUE; 2101 MSGCOMPLETE; 2102 /* NOTREACHED */ 2103 break; 2104 2105 #if 0 /* handled above */ 2106 case MSG_EXTENDED: /* 0x01 */ 2107 #endif 2108 case MSG_MESSAGE_REJECT: /* 0x07 */ 2109 target = cmd->c_target; 2110 DPRINTC(cmd, ("Reject tarst %d\n", target->t_state)); 2111 switch (target->t_state) { 2112 #ifdef NJSC32_DUALEDGE 2113 case NJSC32_TARST_WDTR: 2114 case NJSC32_TARST_DE: 2115 target->t_xferctl = 0; 2116 target->t_state = NJSC32_TARST_SDTR; 2117 njsc32_negotiate_xfer(sc, target); 2118 goto reply; 2119 #endif 2120 case NJSC32_TARST_SDTR: 2121 case NJSC32_TARST_ASYNC: 2122 njsc32_target_async(sc, target); 2123 target->t_state = NJSC32_TARST_DONE; 2124 njsc32_update_xfer_mode(sc, target); 2125 break; 2126 default: 2127 break; 2128 } 2129 goto restart; 2130 2131 case MSG_NOOP: /* 0x08 */ 2132 #ifdef NJSC32_DUALEDGE 2133 target = cmd->c_target; 2134 if (target->t_state == NJSC32_TARST_DE) { 2135 aprint_normal("%s: DualEdge transfer\n", 2136 cmd->c_xs->xs_periph->periph_dev->dv_xname); 2137 target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE; 2138 /* go to next negotiation */ 2139 target->t_state = NJSC32_TARST_SDTR; 2140 njsc32_negotiate_xfer(sc, target); 2141 goto reply; 2142 } 2143 #endif 2144 goto restart; 2145 2146 case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */ 2147 case MSG_ABORT: /* 0x06 I->T only */ 2148 case MSG_PARITY_ERROR: /* 0x09 I->T only */ 2149 case MSG_LINK_CMD_COMPLETE: /* 0x0a */ 2150 case MSG_LINK_CMD_COMPLETEF: /* 0x0b */ 2151 case MSG_BUS_DEV_RESET: /* 0x0c I->T only */ 2152 case MSG_ABORT_TAG: /* 0x0d I->T only */ 2153 case MSG_CLEAR_QUEUE: /* 0x0e I->T only */ 2154 2155 #if 0 /* handled above */ 2156 case MSG_SIMPLE_Q_TAG: /* 0x20 */ 2157 #endif 2158 case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */ 2159 case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */ 2160 case MSG_IGN_WIDE_RESIDUE: /* 0x23 */ 2161 2162 default: 2163 #ifdef NJSC32_DEBUG 2164 PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0)); 2165 if (MSG_IS2BYTE(msg0)) 2166 printf(" %#x", msg); 2167 printf("\n"); 2168 #endif 2169 break; 2170 } 2171 2172 reject: 2173 njsc32_add_msgout(sc, MSG_MESSAGE_REJECT); 2174 2175 reply: 2176 msgout = njsc32_get_auto_msgout(sc); 2177 2178 restart: 2179 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2180 NJSC32_CMD_AUTO_COMMAND_PHASE | 2181 NJSC32_CMD_AUTO_SCSI_RESTART; 2182 2183 /* 2184 * Be careful the second and latter bytes of Message In 2185 * shall not be absorbed by AutoSCSI. 2186 */ 2187 if (sc->sc_msgincnt == 0) 2188 cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2189 2190 if (sc->sc_msgoutlen != 0) 2191 cctl |= NJSC32_CMD_AUTO_ATN; 2192 2193 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout); 2194 2195 /* (re)start AutoSCSI (may assert ATN) */ 2196 if (reload_params) { 2197 njsc32_cmd_reload(sc, cmd, cctl); 2198 } else { 2199 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2200 } 2201 2202 /* +ATN -> -REQ: need 90ns delay? */ 2203 2204 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2205 2206 njsc32_negate_ack(sc); 2207 2208 return; 2209 } 2210 2211 static void 2212 njsc32_msgout(sc) 2213 struct njsc32_softc *sc; 2214 { 2215 int cctl; 2216 u_int8_t bus; 2217 unsigned n; 2218 2219 if (sc->sc_msgoutlen == 0) { 2220 /* target entered to Message Out on unexpected timing */ 2221 njsc32_add_msgout(sc, MSG_NOOP); 2222 } 2223 2224 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2225 NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART | 2226 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2227 2228 /* make sure target is in Message Out phase */ 2229 bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR); 2230 if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) { 2231 /* 2232 * Message Out is aborted by target. 2233 */ 2234 printf("%s: njsc32_msgout: phase change %#x\n", 2235 sc->sc_dev.dv_xname, bus); 2236 2237 /* XXX what to do? */ 2238 2239 /* restart AutoSCSI (negate ATN) */ 2240 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2241 2242 sc->sc_msgoutidx = 0; 2243 return; 2244 } 2245 2246 n = sc->sc_msgoutidx; 2247 if (n == sc->sc_msgoutlen - 1) { 2248 /* 2249 * negate ATN before sending ACK 2250 */ 2251 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0); 2252 2253 sc->sc_msgoutidx = 0; /* target may retry Message Out */ 2254 } else { 2255 cctl |= NJSC32_CMD_AUTO_ATN; 2256 sc->sc_msgoutidx++; 2257 } 2258 2259 /* Send Message Out */ 2260 njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]); 2261 2262 /* DBn -> +ACK: need 55ns delay? */ 2263 2264 njsc32_assert_ack(sc); 2265 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2266 2267 /* restart AutoSCSI */ 2268 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2269 2270 njsc32_negate_ack(sc); 2271 2272 /* 2273 * do not reset sc->sc_msgoutlen so the target 2274 * can retry Message Out phase 2275 */ 2276 } 2277 2278 static void 2279 njsc32_cmdtimeout(arg) 2280 void *arg; 2281 { 2282 struct njsc32_cmd *cmd = arg; 2283 struct njsc32_softc *sc; 2284 int s; 2285 2286 PRINTC(cmd, ("command timeout\n")); 2287 2288 sc = cmd->c_sc; 2289 2290 s = splbio(); 2291 2292 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2293 njsc32_arbitration_failed(sc); 2294 else { 2295 sc->sc_curcmd = NULL; 2296 sc->sc_stat = NJSC32_STAT_IDLE; 2297 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2298 } 2299 2300 /* XXX? */ 2301 njsc32_init(sc, 1); /* bus reset */ 2302 2303 splx(s); 2304 } 2305 2306 static void 2307 njsc32_reseltimeout(arg) 2308 void *arg; 2309 { 2310 struct njsc32_cmd *cmd = arg; 2311 struct njsc32_softc *sc; 2312 int s; 2313 2314 PRINTC(cmd, ("reselection timeout\n")); 2315 2316 sc = cmd->c_sc; 2317 2318 s = splbio(); 2319 2320 /* remove from disconnected list */ 2321 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2322 /* I_T_L_Q */ 2323 KASSERT(cmd->c_lu->lu_cmd == NULL); 2324 TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q); 2325 } else { 2326 /* I_T_L */ 2327 KASSERT(cmd->c_lu->lu_cmd == cmd); 2328 cmd->c_lu->lu_cmd = NULL; 2329 } 2330 2331 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2332 2333 /* XXX? */ 2334 njsc32_init(sc, 1); /* bus reset */ 2335 2336 splx(s); 2337 } 2338 2339 static __inline void 2340 njsc32_end_auto(sc, cmd, auto_phase) 2341 struct njsc32_softc *sc; 2342 struct njsc32_cmd *cmd; 2343 int auto_phase; 2344 { 2345 struct scsipi_xfer *xs; 2346 2347 if (auto_phase & NJSC32_XPHASE_MSGIN_02) { 2348 /* Message In: 0x02 Save Data Pointer */ 2349 2350 /* 2351 * Adjust saved data pointer 2352 * if the command is not completed yet. 2353 */ 2354 if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 && 2355 (auto_phase & 2356 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) { 2357 njsc32_save_ptr(cmd); 2358 } 2359 TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2360 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2361 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2362 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2363 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT))); 2364 } 2365 2366 xs = cmd->c_xs; 2367 2368 if (auto_phase & NJSC32_XPHASE_MSGIN_00) { 2369 /* Command Complete */ 2370 TPRINTC(cmd, ("njsc32_intr: Command Complete\n")); 2371 switch (xs->status) { 2372 case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY: 2373 /* 2374 * scsipi layer will automatically handle the error 2375 */ 2376 njsc32_end_cmd(sc, cmd, XS_BUSY); 2377 break; 2378 default: 2379 xs->resid -= cmd->c_dp_max; 2380 njsc32_end_cmd(sc, cmd, XS_NOERROR); 2381 break; 2382 } 2383 } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) { 2384 /* Disconnect */ 2385 TPRINTC(cmd, ("njsc32_intr: Disconnect\n")); 2386 2387 /* for ill-designed devices */ 2388 if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0) 2389 njsc32_save_ptr(cmd); 2390 2391 /* 2392 * move current cmd to disconnected list 2393 */ 2394 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2395 /* I_T_L_Q */ 2396 if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD) 2397 TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q); 2398 else 2399 TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q); 2400 } else { 2401 /* I_T_L */ 2402 cmd->c_lu->lu_cmd = cmd; 2403 } 2404 2405 /* 2406 * schedule timeout -- avoid being 2407 * disconnected forever 2408 */ 2409 if ((xs->xs_control & XS_CTL_POLL) == 0) { 2410 callout_stop(&xs->xs_callout); 2411 callout_reset(&xs->xs_callout, mstohz(xs->timeout), 2412 njsc32_reseltimeout, cmd); 2413 } 2414 2415 } else { 2416 /* 2417 * target has come to Bus Free phase 2418 * probably to notify an error 2419 */ 2420 PRINTC(cmd, ("njsc32_intr: unexpected bus free\n")); 2421 /* try Request Sense */ 2422 xs->status = SCSI_CHECK; 2423 njsc32_end_cmd(sc, cmd, XS_BUSY); 2424 } 2425 } 2426 2427 int 2428 njsc32_intr(arg) 2429 void *arg; 2430 { 2431 struct njsc32_softc *sc = arg; 2432 u_int16_t intr; 2433 u_int8_t arbstat, bus_phase; 2434 int auto_phase; 2435 int idbit; 2436 struct njsc32_cmd *cmd; 2437 2438 intr = njsc32_read_2(sc, NJSC32_REG_IRQ); 2439 if ((intr & NJSC32_IRQ_INTR_PENDING) == 0) 2440 return 0; /* not mine */ 2441 2442 TPRINTF(("%s: njsc32_intr: %#x\n", sc->sc_dev.dv_xname, intr)); 2443 2444 #if 0 /* I don't think this is required */ 2445 /* mask interrupts */ 2446 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 2447 #endif 2448 2449 /* we got an interrupt, so stop the timer */ 2450 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 2451 2452 if (intr & NJSC32_IRQ_SCSIRESET) { 2453 printf("%s: detected bus reset\n", sc->sc_dev.dv_xname); 2454 /* clear current request */ 2455 njsc32_reset_detected(sc); 2456 goto out; 2457 } 2458 2459 if (sc->sc_stat == NJSC32_STAT_ARBIT) { 2460 cmd = sc->sc_curcmd; 2461 KASSERT(cmd); 2462 arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT); 2463 if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) { 2464 /* 2465 * arbitration done 2466 */ 2467 /* clear arbitration status */ 2468 njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION, 2469 NJSC32_SETARB_CLEAR); 2470 2471 if (arbstat & NJSC32_ARBSTAT_WIN) { 2472 TPRINTC(cmd, 2473 ("njsc32_intr: arbitration won\n")); 2474 2475 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 2476 2477 sc->sc_stat = NJSC32_STAT_CONNECT; 2478 } else { 2479 TPRINTC(cmd, 2480 ("njsc32_intr: arbitration failed\n")); 2481 2482 njsc32_arbitration_failed(sc); 2483 2484 /* XXX delay */ 2485 /* XXX retry counter */ 2486 } 2487 } 2488 } 2489 2490 if (intr & NJSC32_IRQ_TIMER) { 2491 TPRINTF(("%s: njsc32_intr: timer interrupt\n", 2492 sc->sc_dev.dv_xname)); 2493 } 2494 2495 if (intr & NJSC32_IRQ_RESELECT) { 2496 /* Reselection from a target */ 2497 njsc32_arbitration_failed(sc); /* just in case */ 2498 if ((cmd = sc->sc_curcmd) != NULL) { 2499 /* ? */ 2500 printf("%s: unexpected reselection\n", 2501 sc->sc_dev.dv_xname); 2502 sc->sc_curcmd = NULL; 2503 sc->sc_stat = NJSC32_STAT_IDLE; 2504 njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP); 2505 } 2506 2507 idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID); 2508 if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 || 2509 (sc->sc_reselid = ffs(idbit & ~NJSC32_INITIATOR_ID) -1) 2510 < 0) { 2511 printf("%s: invalid reselection (id: %#x)\n", 2512 sc->sc_dev.dv_xname, idbit); 2513 sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */ 2514 } else { 2515 sc->sc_stat = NJSC32_STAT_RESEL; 2516 TPRINTF(("%s: njsc32_intr: reselection from %d\n", 2517 sc->sc_dev.dv_xname, sc->sc_reselid)); 2518 } 2519 } 2520 2521 if (intr & NJSC32_IRQ_PHASE_CHANGE) { 2522 #if 1 /* XXX probably not needed */ 2523 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2524 PRINTC(sc->sc_curcmd, 2525 ("njsc32_intr: cancel arbitration phase\n")); 2526 njsc32_arbitration_failed(sc); 2527 #endif 2528 /* current bus phase */ 2529 bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 2530 NJSC32_BUSMON_PHASE_MASK; 2531 2532 switch (bus_phase) { 2533 case NJSC32_PHASE_MESSAGE_IN: 2534 njsc32_msgin(sc); 2535 break; 2536 2537 /* 2538 * target may suddenly become Status / Bus Free phase 2539 * to notify an error condition 2540 */ 2541 case NJSC32_PHASE_STATUS: 2542 printf("%s: unexpected bus phase: Status\n", 2543 sc->sc_dev.dv_xname); 2544 if ((cmd = sc->sc_curcmd) != NULL) { 2545 cmd->c_xs->status = 2546 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2547 TPRINTC(cmd, ("njsc32_intr: Status %d\n", 2548 cmd->c_xs->status)); 2549 } 2550 break; 2551 case NJSC32_PHASE_BUSFREE: 2552 printf("%s: unexpected bus phase: Bus Free\n", 2553 sc->sc_dev.dv_xname); 2554 if ((cmd = sc->sc_curcmd) != NULL) { 2555 sc->sc_curcmd = NULL; 2556 sc->sc_stat = NJSC32_STAT_IDLE; 2557 if (cmd->c_xs->status != SCSI_QUEUE_FULL && 2558 cmd->c_xs->status != SCSI_BUSY) 2559 cmd->c_xs->status = SCSI_CHECK;/* XXX */ 2560 njsc32_end_cmd(sc, cmd, XS_BUSY); 2561 } 2562 goto out; 2563 default: 2564 #ifdef NJSC32_DEBUG 2565 printf("%s: unexpected bus phase: ", 2566 sc->sc_dev.dv_xname); 2567 switch (bus_phase) { 2568 case NJSC32_PHASE_COMMAND: 2569 printf("Command\n"); break; 2570 case NJSC32_PHASE_MESSAGE_OUT: 2571 printf("Message Out\n");break; 2572 case NJSC32_PHASE_DATA_IN: 2573 printf("Data In\n"); break; 2574 case NJSC32_PHASE_DATA_OUT: 2575 printf("Data Out\n"); break; 2576 case NJSC32_PHASE_RESELECT: 2577 printf("Reselect\n");break; 2578 default: printf("%#x\n", bus_phase); break; 2579 } 2580 #else 2581 printf("%s: unexpected bus phase: %#x", 2582 sc->sc_dev.dv_xname, bus_phase); 2583 #endif 2584 break; 2585 } 2586 } 2587 2588 if (intr & NJSC32_IRQ_AUTOSCSI) { 2589 /* 2590 * AutoSCSI interrupt 2591 */ 2592 auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE); 2593 TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n", 2594 sc->sc_dev.dv_xname, auto_phase)); 2595 njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0); 2596 2597 if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) { 2598 cmd = sc->sc_curcmd; 2599 if (cmd == NULL) { 2600 printf("%s: sel no cmd\n", 2601 sc->sc_dev.dv_xname); 2602 goto out; 2603 } 2604 DPRINTC(cmd, ("njsc32_intr: selection timeout\n")); 2605 2606 sc->sc_curcmd = NULL; 2607 sc->sc_stat = NJSC32_STAT_IDLE; 2608 njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT); 2609 2610 goto out; 2611 } 2612 2613 #ifdef NJSC32_TRACE 2614 if (auto_phase & NJSC32_XPHASE_COMMAND) { 2615 /* Command phase has been automatically processed */ 2616 TPRINTF(("%s: njsc32_intr: Command\n", 2617 sc->sc_dev.dv_xname)); 2618 } 2619 #endif 2620 #ifdef NJSC32_DEBUG 2621 if (auto_phase & NJSC32_XPHASE_ILLEGAL) { 2622 printf("%s: njsc32_intr: Illegal phase\n", 2623 sc->sc_dev.dv_xname); 2624 } 2625 #endif 2626 2627 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) { 2628 TPRINTF(("%s: njsc32_intr: Process Message In\n", 2629 sc->sc_dev.dv_xname)); 2630 njsc32_msgin(sc); 2631 } 2632 2633 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) { 2634 TPRINTF(("%s: njsc32_intr: Process Message Out\n", 2635 sc->sc_dev.dv_xname)); 2636 njsc32_msgout(sc); 2637 } 2638 2639 cmd = sc->sc_curcmd; 2640 if (cmd == NULL) { 2641 TPRINTF(("%s: njsc32_intr: no cmd\n", 2642 sc->sc_dev.dv_xname)); 2643 goto out; 2644 } 2645 2646 if (auto_phase & 2647 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) { 2648 #ifdef NJSC32_TRACE 2649 if (auto_phase & NJSC32_XPHASE_DATA_IN) 2650 PRINTC(cmd, ("njsc32_intr: data in done\n")); 2651 if (auto_phase & NJSC32_XPHASE_DATA_OUT) 2652 PRINTC(cmd, ("njsc32_intr: data out done\n")); 2653 printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2654 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2655 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2656 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2657 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)); 2658 #endif 2659 2660 /* 2661 * detected parity error on data transfer? 2662 */ 2663 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 2664 (NJSC32_PARITYSTATUS_ERROR_LSB| 2665 NJSC32_PARITYSTATUS_ERROR_MSB)) { 2666 2667 PRINTC(cmd, ("datain: parity error\n")); 2668 2669 /* clear parity error */ 2670 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 2671 NJSC32_PARITYCTL_CHECK_ENABLE | 2672 NJSC32_PARITYCTL_CLEAR_ERROR); 2673 2674 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2675 /* 2676 * XXX command has already finished 2677 * -- what can we do? 2678 * 2679 * It is not clear current command 2680 * caused the error -- reset everything. 2681 */ 2682 njsc32_init(sc, 1); /* XXX */ 2683 } else { 2684 /* XXX does this case occur? */ 2685 #if 1 2686 printf("%s: datain: parity error\n", 2687 sc->sc_dev.dv_xname); 2688 #endif 2689 /* 2690 * Make attention condition and try 2691 * to send Initiator Detected Error 2692 * message. 2693 */ 2694 njsc32_init_msgout(sc); 2695 njsc32_add_msgout(sc, 2696 MSG_INITIATOR_DET_ERR); 2697 njsc32_write_4(sc, 2698 NJSC32_REG_SCSI_MSG_OUT, 2699 njsc32_get_auto_msgout(sc)); 2700 /* restart autoscsi with ATN */ 2701 njsc32_write_2(sc, 2702 NJSC32_REG_COMMAND_CONTROL, 2703 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2704 NJSC32_CMD_AUTO_COMMAND_PHASE | 2705 NJSC32_CMD_AUTO_SCSI_RESTART | 2706 NJSC32_CMD_AUTO_MSGIN_00_04 | 2707 NJSC32_CMD_AUTO_MSGIN_02 | 2708 NJSC32_CMD_AUTO_ATN); 2709 } 2710 goto out; 2711 } 2712 2713 /* 2714 * data has been transferred, and current pointer 2715 * is changed 2716 */ 2717 njsc32_set_cur_ptr(cmd, cmd->c_dp_cur + 2718 njsc32_read_4(sc, NJSC32_REG_SACK_CNT)); 2719 } 2720 2721 if (auto_phase & NJSC32_XPHASE_MSGOUT) { 2722 /* Message Out phase has been automatically processed */ 2723 TPRINTC(cmd, ("njsc32_intr: Message Out\n")); 2724 if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 && 2725 sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) { 2726 njsc32_init_msgout(sc); 2727 } 2728 } 2729 2730 if (auto_phase & NJSC32_XPHASE_STATUS) { 2731 /* Status phase has been automatically processed */ 2732 cmd->c_xs->status = 2733 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2734 TPRINTC(cmd, ("njsc32_intr: Status %#x\n", 2735 cmd->c_xs->status)); 2736 } 2737 2738 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2739 /* AutoSCSI is finished */ 2740 2741 TPRINTC(cmd, ("njsc32_intr: Bus Free\n")); 2742 2743 sc->sc_stat = NJSC32_STAT_IDLE; 2744 sc->sc_curcmd = NULL; 2745 2746 njsc32_end_auto(sc, cmd, auto_phase); 2747 } 2748 goto out; 2749 } 2750 2751 if (intr & NJSC32_IRQ_FIFO_THRESHOLD) { 2752 /* XXX We use DMA, and this shouldn't happen */ 2753 printf("%s: njsc32_intr: FIFO\n", sc->sc_dev.dv_xname); 2754 njsc32_init(sc, 1); 2755 goto out; 2756 } 2757 if (intr & NJSC32_IRQ_PCI) { 2758 /* XXX? */ 2759 printf("%s: njsc32_intr: PCI\n", sc->sc_dev.dv_xname); 2760 } 2761 if (intr & NJSC32_IRQ_BMCNTERR) { 2762 /* XXX? */ 2763 printf("%s: njsc32_intr: BM\n", sc->sc_dev.dv_xname); 2764 } 2765 2766 out: 2767 /* go next command if controller is idle */ 2768 if (sc->sc_stat == NJSC32_STAT_IDLE) 2769 njsc32_start(sc); 2770 2771 #if 0 2772 /* enable interrupts */ 2773 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 2774 #endif 2775 2776 return 1; /* processed */ 2777 } 2778
Indexes created Mon Oct 27 17:09:47 GMT 2025