ninjascsi32.c revision 1.2.6.3
1 /* $NetBSD: ninjascsi32.c,v 1.2.6.3 2006/01/20 22:20:50 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by ITOH Yasufumi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.2.6.3 2006/01/20 22:20:50 tron Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/device.h> 46 #include <sys/kernel.h> 47 #include <sys/buf.h> 48 #include <sys/scsiio.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <dev/scsipi/scsi_message.h> 59 60 /* 61 * DualEdge transfer support 62 */ 63 /* #define NJSC32_DUALEDGE */ /* XXX untested */ 64 65 /* 66 * Auto param loading does not work properly (it partially works (works on 67 * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51), 68 * and it doesn't improve the performance so much, 69 * forget about it. 70 */ 71 #undef NJSC32_AUTOPARAM 72 73 #include <dev/ic/ninjascsi32reg.h> 74 #include <dev/ic/ninjascsi32var.h> 75 76 /* #define NJSC32_DEBUG */ 77 /* #define NJSC32_TRACE */ 78 79 #ifdef NJSC32_DEBUG 80 #define DPRINTF(x) printf x 81 #define DPRINTC(cmd, x) PRINTC(cmd, x) 82 #else 83 #define DPRINTF(x) 84 #define DPRINTC(cmd, x) 85 #endif 86 #ifdef NJSC32_TRACE 87 #define TPRINTF(x) printf x 88 #define TPRINTC(cmd, x) PRINTC(cmd, x) 89 #else 90 #define TPRINTF(x) 91 #define TPRINTC(cmd, x) 92 #endif 93 94 #define PRINTC(cmd, x) do { \ 95 scsi_print_addr((cmd)->c_xs->xs_periph); \ 96 printf x; \ 97 } while (/* CONSTCOND */ 0) 98 99 static void njsc32_scsipi_request(struct scsipi_channel *, 100 scsipi_adapter_req_t, void *); 101 static void njsc32_scsipi_minphys(struct buf *buf); 102 static int njsc32_scsipi_ioctl(struct scsipi_channel *, u_long, caddr_t, 103 int, struct proc *); 104 105 static void njsc32_init(struct njsc32_softc *, int nosleep); 106 static int njsc32_init_cmds(struct njsc32_softc *); 107 static void njsc32_target_async(struct njsc32_softc *, 108 struct njsc32_target *); 109 static void njsc32_init_targets(struct njsc32_softc *); 110 static void njsc32_add_msgout(struct njsc32_softc *, int); 111 static u_int32_t njsc32_get_auto_msgout(struct njsc32_softc *); 112 #ifdef NJSC32_DUALEDGE 113 static void njsc32_msgout_wdtr(struct njsc32_softc *, int); 114 #endif 115 static void njsc32_msgout_sdtr(struct njsc32_softc *, int period, 116 int offset); 117 static void njsc32_negotiate_xfer(struct njsc32_softc *, 118 struct njsc32_target *); 119 static void njsc32_arbitration_failed(struct njsc32_softc *); 120 static void njsc32_start(struct njsc32_softc *); 121 static void njsc32_run_xfer(struct njsc32_softc *, struct scsipi_xfer *); 122 static void njsc32_end_cmd(struct njsc32_softc *, struct njsc32_cmd *, 123 scsipi_xfer_result_t); 124 static void njsc32_reset_bus(struct njsc32_softc *); 125 static void njsc32_clear_cmds(struct njsc32_softc *, 126 scsipi_xfer_result_t); 127 static void njsc32_reset_detected(struct njsc32_softc *); 128 static void njsc32_set_ptr(struct njsc32_softc *, struct njsc32_cmd *, 129 u_int32_t); 130 static void njsc32_assert_ack(struct njsc32_softc *); 131 static void njsc32_negate_ack(struct njsc32_softc *); 132 static void njsc32_wait_req_negate(struct njsc32_softc *); 133 static void njsc32_reconnect(struct njsc32_softc *, struct njsc32_cmd *); 134 enum njsc32_reselstat { 135 NJSC32_RESEL_ERROR, /* to be rejected */ 136 NJSC32_RESEL_COMPLETE, /* reselection is just complete */ 137 NJSC32_RESEL_THROUGH /* this message is OK (no reply) */ 138 }; 139 static enum njsc32_reselstat njsc32_resel_identify(struct njsc32_softc *, 140 int lun, struct njsc32_cmd **); 141 static enum njsc32_reselstat njsc32_resel_tag(struct njsc32_softc *, 142 int tag, struct njsc32_cmd **); 143 static void njsc32_cmd_reload(struct njsc32_softc *, struct njsc32_cmd *, 144 int); 145 static void njsc32_update_xfer_mode(struct njsc32_softc *, 146 struct njsc32_target *); 147 static void njsc32_msgin(struct njsc32_softc *); 148 static void njsc32_msgout(struct njsc32_softc *); 149 static void njsc32_cmdtimeout(void *); 150 static void njsc32_reseltimeout(void *); 151 152 static __inline unsigned 153 njsc32_read_1(struct njsc32_softc *sc, int no) 154 { 155 156 return bus_space_read_1(sc->sc_regt, sc->sc_regh, no); 157 } 158 159 static __inline unsigned 160 njsc32_read_2(struct njsc32_softc *sc, int no) 161 { 162 163 return bus_space_read_2(sc->sc_regt, sc->sc_regh, no); 164 } 165 166 static __inline u_int32_t 167 njsc32_read_4(struct njsc32_softc *sc, int no) 168 { 169 170 return bus_space_read_4(sc->sc_regt, sc->sc_regh, no); 171 } 172 173 static __inline void 174 njsc32_write_1(struct njsc32_softc *sc, int no, int val) 175 { 176 177 bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val); 178 } 179 180 static __inline void 181 njsc32_write_2(struct njsc32_softc *sc, int no, int val) 182 { 183 184 bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val); 185 } 186 187 static __inline void 188 njsc32_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 189 { 190 191 bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val); 192 } 193 194 static __inline unsigned 195 njsc32_ireg_read_1(struct njsc32_softc *sc, int no) 196 { 197 198 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 199 return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 200 } 201 202 static __inline unsigned 203 njsc32_ireg_read_2(struct njsc32_softc *sc, int no) 204 { 205 206 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 207 return bus_space_read_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 208 } 209 210 static __inline u_int32_t 211 njsc32_ireg_read_4(struct njsc32_softc *sc, int no) 212 { 213 u_int32_t val; 214 215 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 216 val = (u_int16_t)bus_space_read_2(sc->sc_regt, sc->sc_regh, 217 NJSC32_REG_DATA_LOW); 218 return val | (bus_space_read_2(sc->sc_regt, sc->sc_regh, 219 NJSC32_REG_DATA_HIGH) << 16); 220 } 221 222 static __inline void 223 njsc32_ireg_write_1(struct njsc32_softc *sc, int no, int val) 224 { 225 226 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 227 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 228 } 229 230 static __inline void 231 njsc32_ireg_write_2(struct njsc32_softc *sc, int no, int val) 232 { 233 234 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 235 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 236 } 237 238 static __inline void 239 njsc32_ireg_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 240 { 241 242 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 243 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 244 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_HIGH, 245 val >> 16); 246 } 247 248 #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */ 249 #ifdef __STDC__ 250 # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK 251 # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \ 252 NJSC32_SREQ_SAMPLING_ENABLE) 253 #else 254 # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK 255 # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \ 256 NJSC32_SREQ_SAMPLING_ENABLE) 257 #endif 258 259 #define NJSC32_NSYNCT_MAXSYNC 1 260 #define NJSC32_NSYNCT 16 261 262 /* 40MHz (25ns) */ 263 static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = { 264 { 0, 0, 0 }, /* dummy for async */ 265 { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */ 266 { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */ 267 { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */ 268 { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */ 269 { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */ 270 { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */ 271 { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 272 { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */ 273 { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 274 { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */ 275 { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */ 276 { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */ 277 { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */ 278 { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */ 279 { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */ 280 }; 281 282 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 283 /* 20MHz (50ns) */ 284 static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = { 285 { 0, 0, 0 }, /* dummy for async */ 286 { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */ 287 { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */ 288 { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 289 { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 290 { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */ 291 { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */ 292 { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */ 293 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */ 294 { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */ 295 { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */ 296 { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */ 297 { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */ 298 { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */ 299 { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */ 300 { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */ 301 }; 302 303 /* 33.3MHz (30ns) */ 304 static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = { 305 { 0, 0, 0 }, /* dummy for async */ 306 { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */ 307 { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */ 308 { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */ 309 { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */ 310 { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */ 311 { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */ 312 { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */ 313 { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */ 314 { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */ 315 { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */ 316 { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */ 317 { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */ 318 { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */ 319 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */ 320 { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */ 321 }; 322 #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */ 323 324 #undef NS 325 #undef ACKW 326 #undef SMPL 327 328 /* initialize device */ 329 static void 330 njsc32_init(struct njsc32_softc *sc, int nosleep) 331 { 332 u_int16_t intstat; 333 334 /* block all interrupts */ 335 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 336 337 /* clear transfer */ 338 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 339 njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0); 340 341 /* make sure interrupts are cleared */ 342 /* XXX loop forever? */ 343 while ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ)) & 344 NJSC32_IRQ_INTR_PENDING) { 345 DPRINTF(("%s: njsc32_init: intr pending: %#x\n", 346 sc->sc_dev.dv_xname, intstat)); 347 } 348 349 /* FIFO threshold */ 350 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL, 351 NJSC32_FIFO_FULL_BUSMASTER); 352 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY, 353 NJSC32_FIFO_EMPTY_BUSMASTER); 354 355 /* clock source */ 356 njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk); 357 358 /* memory read multiple */ 359 njsc32_ireg_write_1(sc, NJSC32_IREG_BM, 360 NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD); 361 362 /* clear parity error and enable parity detection */ 363 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 364 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 365 366 /* misc configuration */ 367 njsc32_ireg_write_2(sc, NJSC32_IREG_MISC, 368 NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT | 369 NJSC32_MISC_DELAYED_BMSTART | 370 NJSC32_MISC_MASTER_TERMINATION_SELECT | 371 NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL | 372 NJSC32_MISC_AUTOSEL_TIMING_SEL | 373 NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE); 374 375 /* 376 * Check for termination power (32Bi only?). 377 */ 378 if (!nosleep || cold) { 379 DPRINTF(("%s: njsc32_init: checking TERMPWR\n", 380 sc->sc_dev.dv_xname)); 381 382 /* First, turn termination power off */ 383 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0); 384 385 /* give 0.5s to settle */ 386 if (nosleep) 387 delay(500000); 388 else 389 tsleep(sc, PWAIT, "njs_t1", hz / 2); 390 } 391 392 /* supply termination power if not supplied by other devices */ 393 if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) & 394 NJSC32_TERMPWR_SENSE) == 0) { 395 /* termination power is not present on the bus */ 396 if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) { 397 /* 398 * CardBus device must not supply termination power 399 * to avoid excessive power consumption. 400 */ 401 printf("%s: no termination power present\n", 402 sc->sc_dev.dv_xname); 403 } else { 404 /* supply termination power */ 405 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 406 NJSC32_TERMPWR_BPWR); 407 408 DPRINTF(("%s: supplying termination power\n", 409 sc->sc_dev.dv_xname)); 410 411 /* give 0.5s to settle */ 412 if (!nosleep) 413 tsleep(sc, PWAIT, "njs_t2", hz / 2); 414 } 415 } 416 417 /* stop timer */ 418 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 419 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 420 421 /* default transfer parameter */ 422 njsc32_write_1(sc, NJSC32_REG_SYNC, 0); 423 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK); 424 njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT, 425 NJSC32_SEL_TIMEOUT_TIME); 426 427 /* select interrupt source */ 428 njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT, 429 NJSC32_IRQSEL_RESELECT | 430 NJSC32_IRQSEL_PHASE_CHANGE | 431 NJSC32_IRQSEL_SCSIRESET | 432 NJSC32_IRQSEL_TIMER | 433 NJSC32_IRQSEL_FIFO_THRESHOLD | 434 NJSC32_IRQSEL_TARGET_ABORT | 435 NJSC32_IRQSEL_MASTER_ABORT | 436 /* XXX not yet 437 NJSC32_IRQSEL_SERR | 438 NJSC32_IRQSEL_PERR | 439 NJSC32_IRQSEL_BMCNTERR | 440 */ 441 NJSC32_IRQSEL_AUTO_SCSI_SEQ); 442 443 /* unblock interrupts */ 444 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 445 446 /* turn LED off */ 447 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR, 448 NJSC32_EXTPORT_LED_OFF); 449 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, 450 NJSC32_EXTPORT_LED_OFF); 451 452 /* reset SCSI bus so the targets become known state */ 453 njsc32_reset_bus(sc); 454 } 455 456 static int 457 njsc32_init_cmds(struct njsc32_softc *sc) 458 { 459 struct njsc32_cmd *cmd; 460 bus_addr_t dmaaddr; 461 int i, error; 462 463 /* 464 * allocate DMA area for command 465 */ 466 if ((error = bus_dmamem_alloc(sc->sc_dmat, 467 sizeof(struct njsc32_dma_page), PAGE_SIZE, 0, 468 &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) { 469 printf("%s: unable to allocate cmd page, error = %d\n", 470 sc->sc_dev.dv_xname, error); 471 return 0; 472 } 473 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg, 474 sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page), 475 (caddr_t *)&sc->sc_cmdpg, 476 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 477 printf("%s: unable to map cmd page, error = %d\n", 478 sc->sc_dev.dv_xname, error); 479 goto fail1; 480 } 481 if ((error = bus_dmamap_create(sc->sc_dmat, 482 sizeof(struct njsc32_dma_page), 1, 483 sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT, 484 &sc->sc_dmamap_cmdpg)) != 0) { 485 printf("%s: unable to create cmd DMA map, error = %d\n", 486 sc->sc_dev.dv_xname, error); 487 goto fail2; 488 } 489 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg, 490 sc->sc_cmdpg, sizeof(struct njsc32_dma_page), 491 NULL, BUS_DMA_NOWAIT)) != 0) { 492 printf("%s: unable to load cmd DMA map, error = %d\n", 493 sc->sc_dev.dv_xname, error); 494 goto fail3; 495 } 496 497 memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page)); 498 dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr; 499 500 #ifdef NJSC32_AUTOPARAM 501 sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap); 502 #endif 503 504 for (i = 0; i < NJSC32_NUM_CMD; i++) { 505 cmd = &sc->sc_cmds[i]; 506 cmd->c_sc = sc; 507 cmd->c_sgt = sc->sc_cmdpg->dp_sg[i]; 508 cmd->c_sgt_dma = dmaaddr + 509 offsetof(struct njsc32_dma_page, dp_sg[i]); 510 cmd->c_flags = 0; 511 512 error = bus_dmamap_create(sc->sc_dmat, 513 NJSC32_MAX_XFER, /* max total map size */ 514 NJSC32_NUM_SG, /* max number of segments */ 515 NJSC32_SGT_MAXSEGLEN, /* max size of a segment */ 516 0, /* boundary */ 517 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer); 518 if (error) { 519 printf("%s: only %d cmd descs available (error = %d)\n", 520 sc->sc_dev.dv_xname, i, error); 521 break; 522 } 523 TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q); 524 } 525 526 if (i > 0) 527 return i; 528 529 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 530 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 531 fail2: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg, 532 sizeof(struct njsc32_dma_page)); 533 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs); 534 535 return 0; 536 } 537 538 static void 539 njsc32_target_async(struct njsc32_softc *sc, struct njsc32_target *target) 540 { 541 542 target->t_sync = 543 NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC); 544 target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK; 545 target->t_sample = 0; /* disable */ 546 target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC; 547 target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC; 548 } 549 550 static void 551 njsc32_init_targets(struct njsc32_softc *sc) 552 { 553 int id, lun; 554 struct njsc32_lu *lu; 555 556 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 557 /* cancel negotiation status */ 558 sc->sc_targets[id].t_state = NJSC32_TARST_INIT; 559 560 /* default to async mode */ 561 njsc32_target_async(sc, &sc->sc_targets[id]); 562 563 #ifdef NJSC32_DUALEDGE 564 sc->sc_targets[id].t_xferctl = 0; 565 #endif 566 567 sc->sc_targets[id].t_targetid = 568 (1 << id) | (1 << NJSC32_INITIATOR_ID); 569 570 /* init logical units */ 571 for (lun = 0; lun < NJSC32_NLU; lun++) { 572 lu = &sc->sc_targets[id].t_lus[lun]; 573 lu->lu_cmd = NULL; 574 TAILQ_INIT(&lu->lu_q); 575 } 576 } 577 } 578 579 void 580 njsc32_attach(struct njsc32_softc *sc) 581 { 582 const char *str; 583 #if 1 /* test */ 584 int reg; 585 njsc32_model_t detected_model; 586 #endif 587 588 /* init */ 589 TAILQ_INIT(&sc->sc_freecmd); 590 TAILQ_INIT(&sc->sc_reqcmd); 591 592 #if 1 /* test */ 593 /* 594 * try to distinguish 32Bi and 32UDE 595 */ 596 /* try to set DualEdge bit (exists on 32UDE only) and read it back */ 597 njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE); 598 if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) { 599 /* device was removed? */ 600 printf("%s: attach failed\n", sc->sc_dev.dv_xname); 601 return; 602 } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) { 603 detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE; 604 } else { 605 detected_model = NJSC32_MODEL_32BI; 606 } 607 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */ 608 609 #if 1/*def DIAGNOSTIC*/ 610 /* compare what is configured with what is detected */ 611 if ((sc->sc_model & NJSC32_MODEL_MASK) != 612 (detected_model & NJSC32_MODEL_MASK)) { 613 /* 614 * Please report this error if it happens. 615 */ 616 printf("%s: model mismatch: %#x vs %#x\n", 617 sc->sc_dev.dv_xname, sc->sc_model, detected_model); 618 return; 619 } 620 #endif 621 #endif 622 623 /* check model */ 624 switch (sc->sc_model & NJSC32_MODEL_MASK) { 625 case NJSC32_MODEL_32BI: 626 str = "Bi"; 627 /* 32Bi doesn't support DualEdge transfer */ 628 KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0); 629 break; 630 case NJSC32_MODEL_32UDE: 631 str = "UDE"; 632 break; 633 default: 634 printf("%s: unknown model!\n", sc->sc_dev.dv_xname); 635 return; 636 } 637 printf("%s: NJSC-32%s", sc->sc_dev.dv_xname, str); 638 639 switch (sc->sc_clk) { 640 default: 641 #ifdef DIAGNOSTIC 642 panic("njsc32_attach: unknown clk %d", sc->sc_clk); 643 #endif 644 case NJSC32_CLOCK_DIV_4: 645 sc->sc_synct = njsc32_synct_40M; 646 str = "40MHz"; 647 break; 648 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 649 case NJSC32_CLOCK_DIV_2: 650 sc->sc_synct = njsc32_synct_20M; 651 str = "20MHz"; 652 break; 653 case NJSC32_CLOCK_PCICLK: 654 sc->sc_synct = njsc32_synct_pci; 655 str = "PCI"; 656 break; 657 #endif 658 } 659 printf(", G/A rev %#x, clk %s%s\n", 660 NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str, 661 (sc->sc_model & NJSC32_FLAG_DUALEDGE) ? 662 #ifdef NJSC32_DUALEDGE 663 ", DualEdge" 664 #else 665 ", DualEdge (no driver support)" 666 #endif 667 : ""); 668 669 /* allocate DMA resource */ 670 if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) { 671 printf("%s: no usable DMA map\n", sc->sc_dev.dv_xname); 672 return; 673 } 674 sc->sc_flags |= NJSC32_CMDPG_MAPPED; 675 676 sc->sc_curcmd = NULL; 677 sc->sc_nusedcmds = 0; 678 sc->sc_stat = NJSC32_STAT_IDLE; 679 680 sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */ 681 682 /* initialize target structure */ 683 njsc32_init_targets(sc); 684 685 /* initialize hardware */ 686 njsc32_init(sc, cold); 687 688 /* setup adapter */ 689 sc->sc_adapter.adapt_dev = &sc->sc_dev; 690 sc->sc_adapter.adapt_nchannels = 1; 691 sc->sc_adapter.adapt_request = njsc32_scsipi_request; 692 sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys; 693 sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl; 694 695 sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings = 696 sc->sc_ncmd; 697 698 /* setup channel */ 699 sc->sc_channel.chan_adapter = &sc->sc_adapter; 700 sc->sc_channel.chan_bustype = &scsi_bustype; 701 sc->sc_channel.chan_channel = 0; 702 sc->sc_channel.chan_ntargets = NJSC32_NTARGET; 703 sc->sc_channel.chan_nluns = NJSC32_NLU; 704 sc->sc_channel.chan_id = NJSC32_INITIATOR_ID; 705 706 sc->sc_scsi = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 707 } 708 709 int 710 njsc32_detach(struct njsc32_softc *sc, int flags) 711 { 712 int rv = 0; 713 int i, s; 714 struct njsc32_cmd *cmd; 715 716 s = splbio(); 717 718 /* clear running/disconnected commands */ 719 njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP); 720 721 sc->sc_stat = NJSC32_STAT_DETACH; 722 723 /* clear pending commands */ 724 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 725 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 726 njsc32_end_cmd(sc, cmd, XS_RESET); 727 } 728 729 if (sc->sc_scsi != NULL) 730 rv = config_detach(sc->sc_scsi, flags); 731 732 splx(s); 733 734 /* free DMA resource */ 735 if (sc->sc_flags & NJSC32_CMDPG_MAPPED) { 736 for (i = 0; i < sc->sc_ncmd; i++) { 737 cmd = &sc->sc_cmds[i]; 738 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) 739 bus_dmamap_unload(sc->sc_dmat, 740 cmd->c_dmamap_xfer); 741 bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer); 742 } 743 744 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 745 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 746 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg, 747 sizeof(struct njsc32_dma_page)); 748 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, 749 sc->sc_cmdpg_nsegs); 750 } 751 752 return 0; 753 } 754 755 static __inline void 756 njsc32_cmd_init(struct njsc32_cmd *cmd) 757 { 758 759 cmd->c_flags = 0; 760 761 /* scatter/gather table */ 762 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0); 763 cmd->c_sgoffset = 0; 764 cmd->c_sgfixcnt = 0; 765 766 /* data pointer */ 767 cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0; 768 } 769 770 static __inline void 771 njsc32_init_msgout(struct njsc32_softc *sc) 772 { 773 774 sc->sc_msgoutlen = 0; 775 sc->sc_msgoutidx = 0; 776 } 777 778 static void 779 njsc32_add_msgout(struct njsc32_softc *sc, int byte) 780 { 781 782 if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) { 783 printf("njsc32_add_msgout: too many\n"); 784 return; 785 } 786 sc->sc_msgout[sc->sc_msgoutlen++] = byte; 787 } 788 789 static u_int32_t 790 njsc32_get_auto_msgout(struct njsc32_softc *sc) 791 { 792 u_int32_t val; 793 u_int8_t *p; 794 795 val = 0; 796 p = sc->sc_msgout; 797 switch (sc->sc_msgoutlen) { 798 /* 31-24 23-16 15-8 7 ... 1 0 */ 799 case 3: /* MSG3 MSG2 MSG1 V --- cnt */ 800 val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT; 801 /* FALLTHROUGH */ 802 803 case 2: /* MSG2 MSG1 --- V --- cnt */ 804 val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT; 805 /* FALLTHROUGH */ 806 807 case 1: /* MSG1 --- --- V --- cnt */ 808 val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT; 809 val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen; 810 break; 811 812 default: 813 break; 814 } 815 return val; 816 } 817 818 #ifdef NJSC32_DUALEDGE 819 /* add Wide Data Transfer Request to the next Message Out */ 820 static void 821 njsc32_msgout_wdtr(struct njsc32_softc *sc, int width) 822 { 823 824 njsc32_add_msgout(sc, MSG_EXTENDED); 825 njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN); 826 njsc32_add_msgout(sc, MSG_EXT_WDTR); 827 njsc32_add_msgout(sc, width); 828 } 829 #endif 830 831 /* add Synchronous Data Transfer Request to the next Message Out */ 832 static void 833 njsc32_msgout_sdtr(struct njsc32_softc *sc, int period, int offset) 834 { 835 836 njsc32_add_msgout(sc, MSG_EXTENDED); 837 njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN); 838 njsc32_add_msgout(sc, MSG_EXT_SDTR); 839 njsc32_add_msgout(sc, period); 840 njsc32_add_msgout(sc, offset); 841 } 842 843 static void 844 njsc32_negotiate_xfer(struct njsc32_softc *sc, struct njsc32_target *target) 845 { 846 847 /* initial negotiation state */ 848 if (target->t_state == NJSC32_TARST_INIT) { 849 #ifdef NJSC32_DUALEDGE 850 if (target->t_flags & NJSC32_TARF_DE) 851 target->t_state = NJSC32_TARST_DE; 852 else 853 #endif 854 if (target->t_flags & NJSC32_TARF_SYNC) 855 target->t_state = NJSC32_TARST_SDTR; 856 else 857 target->t_state = NJSC32_TARST_DONE; 858 } 859 860 switch (target->t_state) { 861 default: 862 case NJSC32_TARST_INIT: 863 #ifdef DIAGNOSTIC 864 panic("njsc32_negotiate_xfer"); 865 /* NOTREACHED */ 866 #endif 867 /* FALLTHROUGH */ 868 case NJSC32_TARST_DONE: 869 /* no more work */ 870 break; 871 872 #ifdef NJSC32_DUALEDGE 873 case NJSC32_TARST_DE: 874 njsc32_msgout_wdtr(sc, 0xde /* XXX? */); 875 break; 876 877 case NJSC32_TARST_WDTR: 878 njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT); 879 break; 880 #endif 881 882 case NJSC32_TARST_SDTR: 883 njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period, 884 NJSC32_SYNCOFFSET_MAX); 885 break; 886 887 case NJSC32_TARST_ASYNC: 888 njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC, 889 NJSC32_SYNCOFFSET_ASYNC); 890 break; 891 } 892 } 893 894 /* turn LED on */ 895 static __inline void 896 njsc32_led_on(struct njsc32_softc *sc) 897 { 898 899 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON); 900 } 901 902 /* turn LED off */ 903 static __inline void 904 njsc32_led_off(struct njsc32_softc *sc) 905 { 906 907 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF); 908 } 909 910 static void 911 njsc32_arbitration_failed(struct njsc32_softc *sc) 912 { 913 struct njsc32_cmd *cmd; 914 915 if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT) 916 return; 917 918 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) 919 callout_stop(&cmd->c_xs->xs_callout); 920 921 sc->sc_stat = NJSC32_STAT_IDLE; 922 sc->sc_curcmd = NULL; 923 924 /* the command is no longer active */ 925 if (--sc->sc_nusedcmds == 0) 926 njsc32_led_off(sc); 927 } 928 929 static __inline void 930 njsc32_cmd_load(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 931 { 932 struct njsc32_target *target; 933 struct scsipi_xfer *xs; 934 int i, control, lun; 935 u_int32_t msgoutreg; 936 #ifdef NJSC32_AUTOPARAM 937 struct njsc32_autoparam *ap; 938 #endif 939 940 xs = cmd->c_xs; 941 #ifdef NJSC32_AUTOPARAM 942 ap = &sc->sc_cmdpg->dp_ap; 943 #else 944 /* reset CDB pointer */ 945 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR); 946 #endif 947 948 /* CDB */ 949 TPRINTC(cmd, ("njsc32_cmd_load: CDB")); 950 for (i = 0; i < xs->cmdlen; i++) { 951 #ifdef NJSC32_AUTOPARAM 952 ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i]; 953 #else 954 njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA, 955 ((u_int8_t *)xs->cmd)[i]); 956 #endif 957 TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i])); 958 } 959 #ifdef NJSC32_AUTOPARAM /* XXX needed? */ 960 for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++) 961 ap->ap_cdb[i].cdb_data = 0; 962 #endif 963 964 control = xs->xs_control; 965 966 /* 967 * Message Out 968 */ 969 njsc32_init_msgout(sc); 970 971 /* Identify */ 972 lun = xs->xs_periph->periph_lun; 973 njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ? 974 MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1)); 975 976 /* tagged queueing */ 977 if (control & XS_CTL_TAGMASK) { 978 njsc32_add_msgout(sc, xs->xs_tag_type); 979 njsc32_add_msgout(sc, xs->xs_tag_id); 980 TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id)); 981 } 982 TPRINTF(("\n")); 983 984 target = cmd->c_target; 985 986 /* transfer negotiation */ 987 if (control & XS_CTL_REQSENSE) 988 target->t_state = NJSC32_TARST_INIT; 989 njsc32_negotiate_xfer(sc, target); 990 991 msgoutreg = njsc32_get_auto_msgout(sc); 992 993 #ifdef NJSC32_AUTOPARAM 994 ap->ap_msgout = htole32(msgoutreg); 995 996 ap->ap_sync = target->t_sync; 997 ap->ap_ackwidth = target->t_ackwidth; 998 ap->ap_targetid = target->t_targetid; 999 ap->ap_sample = target->t_sample; 1000 1001 ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 1002 NJSC32_CMD_AUTO_COMMAND_PHASE | 1003 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1004 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1005 #ifdef NJSC32_DUALEDGE 1006 ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl); 1007 #else 1008 ap->ap_xferctl = htole16(cmd->c_xferctl); 1009 #endif 1010 ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr); 1011 1012 /* sync njsc32_autoparam */ 1013 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1014 offsetof(struct njsc32_dma_page, dp_ap), /* offset */ 1015 sizeof(struct njsc32_autoparam), 1016 BUS_DMASYNC_PREWRITE); 1017 1018 /* autoparam DMA address */ 1019 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma); 1020 1021 /* start command (autoparam) */ 1022 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1023 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER); 1024 1025 #else /* not NJSC32_AUTOPARAM */ 1026 1027 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg); 1028 1029 /* load parameters */ 1030 njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid); 1031 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1032 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1033 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1034 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1035 #ifdef NJSC32_DUALEDGE 1036 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1037 cmd->c_xferctl | target->t_xferctl); 1038 #else 1039 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1040 #endif 1041 /* start AutoSCSI */ 1042 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1043 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE | 1044 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1045 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1046 #endif /* not NJSC32_AUTOPARAM */ 1047 } 1048 1049 /* Note: must be called at splbio() */ 1050 static void 1051 njsc32_start(struct njsc32_softc *sc) 1052 { 1053 struct njsc32_cmd *cmd; 1054 1055 /* get a command to issue */ 1056 TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) { 1057 if (cmd->c_lu->lu_cmd == NULL && 1058 ((cmd->c_flags & NJSC32_CMD_TAGGED) || 1059 TAILQ_EMPTY(&cmd->c_lu->lu_q))) 1060 break; /* OK, the logical unit is free */ 1061 } 1062 if (!cmd) 1063 goto out; /* no work to do */ 1064 1065 /* request will always fail if not in bus free phase */ 1066 if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) != 1067 NJSC32_BUSMON_BUSFREE) 1068 goto busy; 1069 1070 /* clear parity error and enable parity detection */ 1071 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1072 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1073 1074 njsc32_cmd_load(sc, cmd); 1075 1076 if (sc->sc_nusedcmds++ == 0) 1077 njsc32_led_on(sc); 1078 1079 sc->sc_curcmd = cmd; 1080 sc->sc_stat = NJSC32_STAT_ARBIT; 1081 1082 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) { 1083 callout_reset(&cmd->c_xs->xs_callout, 1084 mstohz(cmd->c_xs->timeout), 1085 njsc32_cmdtimeout, cmd); 1086 } 1087 1088 return; 1089 1090 busy: /* XXX retry counter */ 1091 TPRINTF(("%s: njsc32_start: busy\n", sc->sc_dev.dv_xname)); 1092 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME); 1093 out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 1094 } 1095 1096 static void 1097 njsc32_run_xfer(struct njsc32_softc *sc, struct scsipi_xfer *xs) 1098 { 1099 struct scsipi_periph *periph; 1100 int control; 1101 int lun; 1102 struct njsc32_cmd *cmd; 1103 int s, i, error; 1104 1105 periph = xs->xs_periph; 1106 KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID); 1107 1108 control = xs->xs_control; 1109 lun = periph->periph_lun; 1110 1111 /* 1112 * get a free cmd 1113 * (scsipi layer knows the number of cmds, so this shall never fail) 1114 */ 1115 s = splbio(); 1116 cmd = TAILQ_FIRST(&sc->sc_freecmd); 1117 KASSERT(cmd); 1118 TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q); 1119 splx(s); 1120 1121 /* 1122 * build a request 1123 */ 1124 njsc32_cmd_init(cmd); 1125 cmd->c_xs = xs; 1126 cmd->c_target = &sc->sc_targets[periph->periph_target]; 1127 cmd->c_lu = &cmd->c_target->t_lus[lun]; 1128 1129 /* tagged queueing */ 1130 if (control & XS_CTL_TAGMASK) { 1131 cmd->c_flags |= NJSC32_CMD_TAGGED; 1132 if (control & XS_CTL_HEAD_TAG) 1133 cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD; 1134 } 1135 1136 /* map DMA buffer */ 1137 cmd->c_datacnt = xs->datalen; 1138 if (xs->datalen) { 1139 /* Is XS_CTL_DATA_UIO ever used anywhere? */ 1140 KASSERT((control & XS_CTL_DATA_UIO) == 0); 1141 1142 error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer, 1143 xs->data, xs->datalen, NULL, 1144 ((control & XS_CTL_NOSLEEP) ? 1145 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 1146 BUS_DMA_STREAMING | 1147 ((control & XS_CTL_DATA_IN) ? 1148 BUS_DMA_READ : BUS_DMA_WRITE)); 1149 1150 switch (error) { 1151 case 0: 1152 break; 1153 case ENOMEM: 1154 case EAGAIN: 1155 xs->error = XS_RESOURCE_SHORTAGE; 1156 goto map_failed; 1157 default: 1158 xs->error = XS_DRIVER_STUFFUP; 1159 map_failed: 1160 printf("%s: njsc32_run_xfer: map failed, error %d\n", 1161 sc->sc_dev.dv_xname, error); 1162 /* put it back to free command list */ 1163 s = splbio(); 1164 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1165 splx(s); 1166 /* abort this transfer */ 1167 scsipi_done(xs); 1168 return; 1169 } 1170 1171 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1172 0, cmd->c_dmamap_xfer->dm_mapsize, 1173 (control & XS_CTL_DATA_IN) ? 1174 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1175 1176 for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) { 1177 cmd->c_sgt[i].sg_addr = 1178 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr); 1179 cmd->c_sgt[i].sg_len = 1180 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len); 1181 } 1182 /* end mark */ 1183 cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK); 1184 1185 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1186 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1187 NJSC32_SIZE_SGT, 1188 BUS_DMASYNC_PREWRITE); 1189 1190 cmd->c_flags |= NJSC32_CMD_DMA_MAPPED; 1191 1192 /* enable transfer */ 1193 cmd->c_xferctl = 1194 NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START | 1195 NJSC32_XFR_ALL_COUNT_CLR; 1196 1197 /* XXX How can we specify the DMA direction? */ 1198 1199 #if 0 /* faster write mode? (doesn't work) */ 1200 if ((control & XS_CTL_DATA_IN) == 0) 1201 cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE; 1202 #endif 1203 } else { 1204 /* no data transfer */ 1205 cmd->c_xferctl = 0; 1206 } 1207 1208 /* queue request */ 1209 s = splbio(); 1210 TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q); 1211 1212 /* start the controller if idle */ 1213 if (sc->sc_stat == NJSC32_STAT_IDLE) 1214 njsc32_start(sc); 1215 1216 splx(s); 1217 1218 if (control & XS_CTL_POLL) { 1219 /* wait for completion */ 1220 /* XXX should handle timeout? */ 1221 while ((xs->xs_status & XS_STS_DONE) == 0) { 1222 delay(1000); 1223 njsc32_intr(sc); 1224 } 1225 } 1226 } 1227 1228 static void 1229 njsc32_end_cmd(struct njsc32_softc *sc, struct njsc32_cmd *cmd, 1230 scsipi_xfer_result_t result) 1231 { 1232 struct scsipi_xfer *xs; 1233 int s; 1234 #ifdef DIAGNOSTIC 1235 struct njsc32_cmd *c; 1236 #endif 1237 1238 KASSERT(cmd); 1239 1240 #ifdef DIAGNOSTIC 1241 s = splbio(); 1242 TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) { 1243 if (cmd == c) 1244 panic("njsc32_end_cmd: already in free list"); 1245 } 1246 splx(s); 1247 #endif 1248 xs = cmd->c_xs; 1249 1250 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) { 1251 if (cmd->c_datacnt) { 1252 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1253 0, cmd->c_dmamap_xfer->dm_mapsize, 1254 (xs->xs_control & XS_CTL_DATA_IN) ? 1255 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1256 1257 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1258 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, 1259 NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE); 1260 } 1261 1262 bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer); 1263 cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED; 1264 } 1265 1266 s = splbio(); 1267 if ((xs->xs_control & XS_CTL_POLL) == 0) 1268 callout_stop(&xs->xs_callout); 1269 1270 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1271 splx(s); 1272 1273 xs->error = result; 1274 scsipi_done(xs); 1275 1276 if (--sc->sc_nusedcmds == 0) 1277 njsc32_led_off(sc); 1278 } 1279 1280 /* 1281 * request from scsipi layer 1282 */ 1283 static void 1284 njsc32_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1285 void *arg) 1286 { 1287 struct njsc32_softc *sc; 1288 struct scsipi_xfer_mode *xm; 1289 struct njsc32_target *target; 1290 1291 sc = (void *)chan->chan_adapter->adapt_dev; 1292 1293 switch (req) { 1294 case ADAPTER_REQ_RUN_XFER: 1295 njsc32_run_xfer(sc, arg); 1296 break; 1297 1298 case ADAPTER_REQ_GROW_RESOURCES: 1299 /* not supported */ 1300 break; 1301 1302 case ADAPTER_REQ_SET_XFER_MODE: 1303 xm = arg; 1304 target = &sc->sc_targets[xm->xm_target]; 1305 1306 target->t_flags = 0; 1307 if (xm->xm_mode & PERIPH_CAP_TQING) 1308 target->t_flags |= NJSC32_TARF_TAG; 1309 if (xm->xm_mode & PERIPH_CAP_SYNC) { 1310 target->t_flags |= NJSC32_TARF_SYNC; 1311 #ifdef NJSC32_DUALEDGE 1312 if (sc->sc_model & NJSC32_FLAG_DUALEDGE) 1313 target->t_flags |= NJSC32_TARF_DE; 1314 #endif 1315 } 1316 #ifdef NJSC32_DUALEDGE 1317 target->t_xferctl = 0; 1318 #endif 1319 target->t_state = NJSC32_TARST_INIT; 1320 njsc32_target_async(sc, target); 1321 1322 break; 1323 default: 1324 break; 1325 } 1326 } 1327 1328 static void 1329 njsc32_scsipi_minphys(struct buf *bp) 1330 { 1331 1332 if (bp->b_bcount > NJSC32_MAX_XFER) 1333 bp->b_bcount = NJSC32_MAX_XFER; 1334 minphys(bp); 1335 } 1336 1337 static void 1338 njsc32_reset_bus(struct njsc32_softc *sc) 1339 { 1340 int s; 1341 1342 DPRINTF(("%s: njsc32_reset_bus:\n", sc->sc_dev.dv_xname)); 1343 1344 /* SCSI bus reset */ 1345 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST); 1346 delay(NJSC32_RESET_HOLD_TIME); 1347 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0); 1348 1349 /* clear transfer */ 1350 s = splbio(); 1351 njsc32_reset_detected(sc); 1352 splx(s); 1353 } 1354 1355 /* 1356 * clear running/disconnected commands 1357 */ 1358 static void 1359 njsc32_clear_cmds(struct njsc32_softc *sc, scsipi_xfer_result_t cmdresult) 1360 { 1361 struct njsc32_cmd *cmd; 1362 int id, lun; 1363 struct njsc32_lu *lu; 1364 1365 njsc32_arbitration_failed(sc); 1366 1367 /* clear current transfer */ 1368 if ((cmd = sc->sc_curcmd) != NULL) { 1369 sc->sc_curcmd = NULL; 1370 njsc32_end_cmd(sc, cmd, cmdresult); 1371 } 1372 1373 /* clear disconnected transfers */ 1374 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 1375 for (lun = 0; lun < NJSC32_NLU; lun++) { 1376 lu = &sc->sc_targets[id].t_lus[lun]; 1377 1378 if ((cmd = lu->lu_cmd) != NULL) { 1379 lu->lu_cmd = NULL; 1380 njsc32_end_cmd(sc, cmd, cmdresult); 1381 } 1382 while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) { 1383 TAILQ_REMOVE(&lu->lu_q, cmd, c_q); 1384 njsc32_end_cmd(sc, cmd, cmdresult); 1385 } 1386 } 1387 } 1388 } 1389 1390 static void 1391 njsc32_reset_detected(struct njsc32_softc *sc) 1392 { 1393 1394 njsc32_clear_cmds(sc, XS_RESET); 1395 njsc32_init_targets(sc); 1396 sc->sc_stat = NJSC32_STAT_IDLE; 1397 KASSERT(sc->sc_nusedcmds == 0); 1398 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL); 1399 } 1400 1401 static int 1402 njsc32_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd, caddr_t addr, 1403 int flag, struct proc *p) 1404 { 1405 struct njsc32_softc *sc = (void *)chan->chan_adapter->adapt_dev; 1406 1407 switch (cmd) { 1408 case SCBUSIORESET: 1409 njsc32_init(sc, 0); 1410 return 0; 1411 default: 1412 break; 1413 } 1414 1415 return ENOTTY; 1416 } 1417 1418 /* 1419 * set current data pointer 1420 */ 1421 static __inline void 1422 njsc32_set_cur_ptr(struct njsc32_cmd *cmd, u_int32_t pos) 1423 { 1424 1425 /* new current data pointer */ 1426 cmd->c_dp_cur = pos; 1427 1428 /* update number of bytes transferred */ 1429 if (pos > cmd->c_dp_max) 1430 cmd->c_dp_max = pos; 1431 } 1432 1433 /* 1434 * set data pointer for the next transfer 1435 */ 1436 static void 1437 njsc32_set_ptr(struct njsc32_softc *sc, struct njsc32_cmd *cmd, u_int32_t pos) 1438 { 1439 struct njsc32_sgtable *sg; 1440 unsigned sgte; 1441 u_int32_t len; 1442 1443 /* set current pointer */ 1444 njsc32_set_cur_ptr(cmd, pos); 1445 1446 /* undo previous fix if any */ 1447 if (cmd->c_sgfixcnt != 0) { 1448 sg = &cmd->c_sgt[cmd->c_sgoffset]; 1449 sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt); 1450 sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt); 1451 cmd->c_sgfixcnt = 0; 1452 } 1453 1454 if (pos >= cmd->c_datacnt) { 1455 /* transfer done */ 1456 #if 1 /*def DIAGNOSTIC*/ 1457 if (pos > cmd->c_datacnt) 1458 printf("%s: pos %u too large\n", 1459 sc->sc_dev.dv_xname, pos - cmd->c_datacnt); 1460 #endif 1461 cmd->c_xferctl = 0; /* XXX correct? */ 1462 1463 return; 1464 } 1465 1466 for (sgte = 0, sg = cmd->c_sgt; 1467 sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) { 1468 len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK; 1469 if (pos < len) { 1470 sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos); 1471 sg->sg_len = htole32(le32toh(sg->sg_len) - pos); 1472 cmd->c_sgfixcnt = pos; 1473 break; 1474 } 1475 pos -= len; 1476 #ifdef DIAGNOSTIC 1477 if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) { 1478 panic("njsc32_set_ptr: bad pos"); 1479 } 1480 #endif 1481 } 1482 #ifdef DIAGNOSTIC 1483 if (sgte >= NJSC32_NUM_SG) 1484 panic("njsc32_set_ptr: bad sg"); 1485 #endif 1486 if (cmd->c_sgoffset != sgte) { 1487 cmd->c_sgoffset = sgte; 1488 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte); 1489 } 1490 1491 /* XXX overkill */ 1492 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1493 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1494 NJSC32_SIZE_SGT, 1495 BUS_DMASYNC_PREWRITE); 1496 } 1497 1498 /* 1499 * save data pointer 1500 */ 1501 static __inline void 1502 njsc32_save_ptr(struct njsc32_cmd *cmd) 1503 { 1504 1505 cmd->c_dp_saved = cmd->c_dp_cur; 1506 } 1507 1508 static void 1509 njsc32_assert_ack(struct njsc32_softc *sc) 1510 { 1511 u_int8_t reg; 1512 1513 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1514 reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE; 1515 #if 0 /* needed? */ 1516 reg |= NJSC32_SBCTL_AUTODIRECTION; 1517 #endif 1518 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1519 } 1520 1521 static void 1522 njsc32_negate_ack(struct njsc32_softc *sc) 1523 { 1524 u_int8_t reg; 1525 1526 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1527 #if 0 /* needed? */ 1528 reg |= NJSC32_SBCTL_ACK_ENABLE; 1529 reg |= NJSC32_SBCTL_AUTODIRECTION; 1530 #endif 1531 reg &= ~NJSC32_SBCTL_ACK; 1532 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1533 } 1534 1535 static void 1536 njsc32_wait_req_negate(struct njsc32_softc *sc) 1537 { 1538 int cnt; 1539 1540 for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) { 1541 if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 1542 NJSC32_BUSMON_REQ) == 0) 1543 return; 1544 delay(1); 1545 } 1546 printf("%s: njsc32_wait_req_negate: timed out\n", sc->sc_dev.dv_xname); 1547 } 1548 1549 static void 1550 njsc32_reconnect(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 1551 { 1552 struct scsipi_xfer *xs; 1553 1554 xs = cmd->c_xs; 1555 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1556 callout_stop(&xs->xs_callout); 1557 callout_reset(&xs->xs_callout, 1558 mstohz(xs->timeout), 1559 njsc32_cmdtimeout, cmd); 1560 } 1561 1562 /* Reconnection implies Restore Pointers */ 1563 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1564 } 1565 1566 static enum njsc32_reselstat 1567 njsc32_resel_identify(struct njsc32_softc *sc, int lun, 1568 struct njsc32_cmd **pcmd) 1569 { 1570 int targetid; 1571 struct njsc32_lu *plu; 1572 struct njsc32_cmd *cmd; 1573 1574 switch (sc->sc_stat) { 1575 case NJSC32_STAT_RESEL: 1576 break; /* OK */ 1577 1578 case NJSC32_STAT_RESEL_LUN: 1579 case NJSC32_STAT_RECONNECT: 1580 /* 1581 * accept and ignore if the LUN is the same as the current one, 1582 * reject otherwise. 1583 */ 1584 return sc->sc_resellun == lun ? 1585 NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR; 1586 1587 default: 1588 printf("%s: njsc32_resel_identify: not in reselection\n", 1589 sc->sc_dev.dv_xname); 1590 return NJSC32_RESEL_ERROR; 1591 } 1592 1593 targetid = sc->sc_reselid; 1594 TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n", 1595 sc->sc_dev.dv_xname, lun)); 1596 1597 if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU) 1598 return NJSC32_RESEL_ERROR; 1599 1600 sc->sc_resellun = lun; 1601 plu = &sc->sc_targets[targetid].t_lus[lun]; 1602 1603 if ((cmd = plu->lu_cmd) != NULL) { 1604 sc->sc_stat = NJSC32_STAT_RECONNECT; 1605 plu->lu_cmd = NULL; 1606 *pcmd = cmd; 1607 TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n")); 1608 njsc32_reconnect(sc, cmd); 1609 return NJSC32_RESEL_COMPLETE; 1610 } else if (!TAILQ_EMPTY(&plu->lu_q)) { 1611 /* wait for tag */ 1612 sc->sc_stat = NJSC32_STAT_RESEL_LUN; 1613 return NJSC32_RESEL_THROUGH; 1614 } 1615 1616 /* no disconnected commands */ 1617 return NJSC32_RESEL_ERROR; 1618 } 1619 1620 static enum njsc32_reselstat 1621 njsc32_resel_tag(struct njsc32_softc *sc, int tag, struct njsc32_cmd **pcmd) 1622 { 1623 struct njsc32_cmd_head *head; 1624 struct njsc32_cmd *cmd; 1625 1626 TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n", 1627 sc->sc_dev.dv_xname, tag)); 1628 if (sc->sc_stat != NJSC32_STAT_RESEL_LUN) 1629 return NJSC32_RESEL_ERROR; 1630 1631 head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q; 1632 1633 /* XXX slow? */ 1634 /* search for the command of the tag */ 1635 TAILQ_FOREACH(cmd, head, c_q) { 1636 if (cmd->c_xs->xs_tag_id == tag) { 1637 sc->sc_stat = NJSC32_STAT_RECONNECT; 1638 TAILQ_REMOVE(head, cmd, c_q); 1639 *pcmd = cmd; 1640 TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n")); 1641 njsc32_reconnect(sc, cmd); 1642 return NJSC32_RESEL_COMPLETE; 1643 } 1644 } 1645 1646 /* no disconnected commands */ 1647 return NJSC32_RESEL_ERROR; 1648 } 1649 1650 /* 1651 * Reload parameters and restart AutoSCSI. 1652 * 1653 * XXX autoparam doesn't work as expected and we can't use it here. 1654 */ 1655 static void 1656 njsc32_cmd_reload(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int cctl) 1657 { 1658 struct njsc32_target *target; 1659 1660 target = cmd->c_target; 1661 1662 /* clear parity error and enable parity detection */ 1663 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1664 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1665 1666 /* load parameters */ 1667 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1668 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1669 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1670 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1671 #ifdef NJSC32_DUALEDGE 1672 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1673 cmd->c_xferctl | target->t_xferctl); 1674 #else 1675 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1676 #endif 1677 /* start AutoSCSI */ 1678 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 1679 1680 sc->sc_curcmd = cmd; 1681 } 1682 1683 static void 1684 njsc32_update_xfer_mode(struct njsc32_softc *sc, struct njsc32_target *target) 1685 { 1686 struct scsipi_xfer_mode xm; 1687 1688 xm.xm_target = target - sc->sc_targets; /* target ID */ 1689 xm.xm_mode = 0; 1690 xm.xm_period = target->t_syncperiod; 1691 xm.xm_offset = target->t_syncoffset; 1692 if (xm.xm_offset != 0) 1693 xm.xm_mode |= PERIPH_CAP_SYNC; 1694 if (target->t_flags & NJSC32_TARF_TAG) 1695 xm.xm_mode |= PERIPH_CAP_TQING; 1696 1697 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 1698 } 1699 1700 static void 1701 njsc32_msgin(struct njsc32_softc *sc) 1702 { 1703 u_int8_t msg0, msg; 1704 int msgcnt; 1705 struct njsc32_cmd *cmd; 1706 enum njsc32_reselstat rstat; 1707 int cctl = 0; 1708 u_int32_t ptr; /* unsigned type ensures 2-complement calculation */ 1709 u_int32_t msgout = 0; 1710 boolean_t reload_params = FALSE; 1711 struct njsc32_target *target; 1712 int idx, period, offset; 1713 1714 /* 1715 * we are in Message In, so the previous Message Out should have 1716 * been done. 1717 */ 1718 njsc32_init_msgout(sc); 1719 1720 /* get a byte of Message In */ 1721 msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN); 1722 TPRINTF(("%s: njsc32_msgin: got %#x\n", sc->sc_dev.dv_xname, msg)); 1723 if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN) 1724 sc->sc_msginbuf[sc->sc_msgincnt] = msg; 1725 1726 njsc32_assert_ack(sc); 1727 1728 msg0 = sc->sc_msginbuf[0]; 1729 cmd = sc->sc_curcmd; 1730 1731 /* check for parity error */ 1732 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 1733 NJSC32_PARITYSTATUS_ERROR_LSB) { 1734 1735 printf("%s: msgin: parity error\n", sc->sc_dev.dv_xname); 1736 1737 /* clear parity error */ 1738 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1739 NJSC32_PARITYCTL_CHECK_ENABLE | 1740 NJSC32_PARITYCTL_CLEAR_ERROR); 1741 1742 /* respond as Message Parity Error */ 1743 njsc32_add_msgout(sc, MSG_PARITY_ERROR); 1744 1745 /* clear Message In */ 1746 sc->sc_msgincnt = 0; 1747 goto reply; 1748 } 1749 1750 #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0) 1751 #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0) 1752 if (MSG_ISIDENTIFY(msg0)) { 1753 /* 1754 * Got Identify message from target. 1755 */ 1756 #define MSG_IDENTIFY_LUNMASK 0x3f 1757 if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG || 1758 (rstat = njsc32_resel_identify(sc, msg0 & 1759 MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) { 1760 /* 1761 * invalid Identify -> Reject 1762 */ 1763 goto reject; 1764 } 1765 if (rstat == NJSC32_RESEL_COMPLETE) 1766 reload_params = TRUE; 1767 MSGCOMPLETE; 1768 } 1769 1770 if (msg0 == MSG_SIMPLE_Q_TAG) { 1771 if (msgcnt == 0) 1772 WAITNEXTMSG; 1773 1774 /* got whole message */ 1775 sc->sc_msgincnt = 0; 1776 1777 if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd)) 1778 == NJSC32_RESEL_ERROR) { 1779 /* 1780 * invalid Simple Queue Tag -> Abort Tag 1781 */ 1782 printf("%s: msgin: invalid tag\n", sc->sc_dev.dv_xname); 1783 njsc32_add_msgout(sc, MSG_ABORT_TAG); 1784 goto reply; 1785 } 1786 if (rstat == NJSC32_RESEL_COMPLETE) 1787 reload_params = TRUE; 1788 MSGCOMPLETE; 1789 } 1790 1791 /* I_T_L or I_T_L_Q nexus should be established now */ 1792 if (cmd == NULL) { 1793 printf("%s: msgin %#x without nexus -- sending abort\n", 1794 sc->sc_dev.dv_xname, msg0); 1795 njsc32_add_msgout(sc, MSG_ABORT); 1796 goto reply; 1797 } 1798 1799 /* 1800 * extended message 1801 * 0x01 <length (0 stands for 256)> <length bytes> 1802 * (<code> [<parameter> ...]) 1803 */ 1804 #define EXTLENOFF 1 1805 #define EXTCODEOFF 2 1806 if (msg0 == MSG_EXTENDED) { 1807 if (msgcnt < EXTLENOFF || 1808 msgcnt < EXTLENOFF + 1 + 1809 (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1)) 1810 WAITNEXTMSG; 1811 1812 /* got whole message */ 1813 sc->sc_msgincnt = 0; 1814 1815 switch (sc->sc_msginbuf[EXTCODEOFF]) { 1816 case 0: /* Modify Data Pointer */ 1817 if (msgcnt != 5 + EXTCODEOFF - 1) 1818 break; 1819 /* 1820 * parameter is 32bit big-endian signed (2-complement) 1821 * value 1822 */ 1823 ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) | 1824 (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) | 1825 (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) | 1826 sc->sc_msginbuf[EXTCODEOFF + 4]; 1827 1828 /* new pointer */ 1829 ptr += cmd->c_dp_cur; /* ignore overflow */ 1830 1831 /* reject if ptr is not in data buffer */ 1832 if (ptr > cmd->c_datacnt) 1833 break; 1834 1835 njsc32_set_ptr(sc, cmd, ptr); 1836 goto restart; 1837 1838 case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */ 1839 DPRINTC(cmd, ("SDTR %#x %#x\n", 1840 sc->sc_msginbuf[EXTCODEOFF + 1], 1841 sc->sc_msginbuf[EXTCODEOFF + 2])); 1842 if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1) 1843 break; /* reject */ 1844 1845 target = cmd->c_target; 1846 1847 /* lookup sync period parameters */ 1848 period = sc->sc_msginbuf[EXTCODEOFF + 1]; 1849 for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++) 1850 if (sc->sc_synct[idx].sp_period >= period) { 1851 period = sc->sc_synct[idx].sp_period; 1852 break; 1853 } 1854 if (idx >= NJSC32_NSYNCT) { 1855 /* 1856 * We can't meet the timing condition that 1857 * the target requests -- use async. 1858 */ 1859 njsc32_target_async(sc, target); 1860 njsc32_update_xfer_mode(sc, target); 1861 if (target->t_state == NJSC32_TARST_SDTR) { 1862 /* 1863 * We started SDTR exchange -- start 1864 * negotiation again and request async. 1865 */ 1866 target->t_state = NJSC32_TARST_ASYNC; 1867 njsc32_negotiate_xfer(sc, target); 1868 goto reply; 1869 } else { 1870 /* 1871 * The target started SDTR exchange 1872 * -- just reject and fallback 1873 * to async. 1874 */ 1875 goto reject; 1876 } 1877 } 1878 1879 /* check sync offset */ 1880 offset = sc->sc_msginbuf[EXTCODEOFF + 2]; 1881 if (offset > NJSC32_SYNCOFFSET_MAX) { 1882 if (target->t_state == NJSC32_TARST_SDTR) { 1883 printf("%s: wrong sync offset: %d\n", 1884 cmd->c_xs->xs_periph->periph_dev->dv_xname, 1885 offset); 1886 /* XXX what to do? */ 1887 } 1888 offset = NJSC32_SYNCOFFSET_MAX; 1889 } 1890 1891 target->t_ackwidth = sc->sc_synct[idx].sp_ackw; 1892 target->t_sample = sc->sc_synct[idx].sp_sample; 1893 target->t_syncperiod = period; 1894 target->t_syncoffset = offset; 1895 target->t_sync = NJSC32_SYNC_VAL(idx, offset); 1896 njsc32_update_xfer_mode(sc, target); 1897 1898 if (target->t_state == NJSC32_TARST_SDTR) { 1899 target->t_state = NJSC32_TARST_DONE; 1900 } else { 1901 njsc32_msgout_sdtr(sc, period, offset); 1902 goto reply; 1903 } 1904 goto restart; 1905 1906 case MSG_EXT_WDTR: /* Wide Data Transfer Request */ 1907 DPRINTC(cmd, 1908 ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1])); 1909 #ifdef NJSC32_DUALEDGE 1910 if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1) 1911 break; /* reject */ 1912 1913 /* 1914 * T->I of this message is not used for 1915 * DualEdge negotiation, so the device 1916 * must not be a DualEdge device. 1917 * 1918 * XXX correct? 1919 */ 1920 target = cmd->c_target; 1921 target->t_xferctl = 0; 1922 1923 switch (target->t_state) { 1924 case NJSC32_TARST_DE: 1925 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1926 MSG_EXT_WDTR_BUS_8_BIT) { 1927 /* 1928 * Oops, we got unexpected WDTR. 1929 * Negotiate for 8bit. 1930 */ 1931 target->t_state = NJSC32_TARST_WDTR; 1932 } else { 1933 target->t_state = NJSC32_TARST_SDTR; 1934 } 1935 njsc32_negotiate_xfer(sc, target); 1936 goto reply; 1937 1938 case NJSC32_TARST_WDTR: 1939 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1940 MSG_EXT_WDTR_BUS_8_BIT) { 1941 printf("%s: unexpected transfer width: %#x\n", 1942 cmd->c_xs->xs_periph->periph_dev->dv_xname, 1943 sc->sc_msginbuf[EXTCODEOFF + 1]); 1944 /* XXX what to do? */ 1945 } 1946 target->t_state = NJSC32_TARST_SDTR; 1947 njsc32_negotiate_xfer(sc, target); 1948 goto reply; 1949 1950 default: 1951 /* the target started WDTR exchange */ 1952 DPRINTC(cmd, ("WDTR from target\n")); 1953 1954 target->t_state = NJSC32_TARST_SDTR; 1955 njsc32_target_async(sc, target); 1956 1957 break; /* reject the WDTR (8bit transfer) */ 1958 } 1959 #endif /* NJSC32_DUALEDGE */ 1960 break; /* reject */ 1961 } 1962 DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n", 1963 sc->sc_msginbuf[EXTCODEOFF], msgcnt)); 1964 goto reject; 1965 } 1966 1967 /* 2byte messages */ 1968 if (MSG_IS2BYTE(msg0)) { 1969 if (msgcnt == 0) 1970 WAITNEXTMSG; 1971 1972 /* got whole message */ 1973 sc->sc_msgincnt = 0; 1974 } 1975 1976 switch (msg0) { 1977 case MSG_CMDCOMPLETE: /* 0x00 */ 1978 case MSG_SAVEDATAPOINTER: /* 0x02 */ 1979 case MSG_DISCONNECT: /* 0x04 */ 1980 /* handled by AutoSCSI */ 1981 PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0)); 1982 break; 1983 1984 case MSG_RESTOREPOINTERS: /* 0x03 */ 1985 /* restore data pointer to what was saved */ 1986 DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n")); 1987 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1988 reload_params = TRUE; 1989 MSGCOMPLETE; 1990 /* NOTREACHED */ 1991 break; 1992 1993 #if 0 /* handled above */ 1994 case MSG_EXTENDED: /* 0x01 */ 1995 #endif 1996 case MSG_MESSAGE_REJECT: /* 0x07 */ 1997 target = cmd->c_target; 1998 DPRINTC(cmd, ("Reject tarst %d\n", target->t_state)); 1999 switch (target->t_state) { 2000 #ifdef NJSC32_DUALEDGE 2001 case NJSC32_TARST_WDTR: 2002 case NJSC32_TARST_DE: 2003 target->t_xferctl = 0; 2004 target->t_state = NJSC32_TARST_SDTR; 2005 njsc32_negotiate_xfer(sc, target); 2006 goto reply; 2007 #endif 2008 case NJSC32_TARST_SDTR: 2009 case NJSC32_TARST_ASYNC: 2010 njsc32_target_async(sc, target); 2011 target->t_state = NJSC32_TARST_DONE; 2012 njsc32_update_xfer_mode(sc, target); 2013 break; 2014 default: 2015 break; 2016 } 2017 goto restart; 2018 2019 case MSG_NOOP: /* 0x08 */ 2020 #ifdef NJSC32_DUALEDGE 2021 target = cmd->c_target; 2022 if (target->t_state == NJSC32_TARST_DE) { 2023 printf("%s: DualEdge transfer\n", 2024 cmd->c_xs->xs_periph->periph_dev->dv_xname); 2025 target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE; 2026 /* go to next negotiation */ 2027 target->t_state = NJSC32_TARST_SDTR; 2028 njsc32_negotiate_xfer(sc, target); 2029 goto reply; 2030 } 2031 #endif 2032 goto restart; 2033 2034 case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */ 2035 case MSG_ABORT: /* 0x06 I->T only */ 2036 case MSG_PARITY_ERROR: /* 0x09 I->T only */ 2037 case MSG_LINK_CMD_COMPLETE: /* 0x0a */ 2038 case MSG_LINK_CMD_COMPLETEF: /* 0x0b */ 2039 case MSG_BUS_DEV_RESET: /* 0x0c I->T only */ 2040 case MSG_ABORT_TAG: /* 0x0d I->T only */ 2041 case MSG_CLEAR_QUEUE: /* 0x0e I->T only */ 2042 2043 #if 0 /* handled above */ 2044 case MSG_SIMPLE_Q_TAG: /* 0x20 */ 2045 #endif 2046 case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */ 2047 case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */ 2048 case MSG_IGN_WIDE_RESIDUE: /* 0x23 */ 2049 2050 default: 2051 #ifdef NJSC32_DEBUG 2052 PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0)); 2053 if (MSG_IS2BYTE(msg0)) 2054 printf(" %#x", msg); 2055 printf("\n"); 2056 #endif 2057 break; 2058 } 2059 2060 reject: 2061 njsc32_add_msgout(sc, MSG_MESSAGE_REJECT); 2062 2063 reply: 2064 msgout = njsc32_get_auto_msgout(sc); 2065 2066 restart: 2067 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2068 NJSC32_CMD_AUTO_COMMAND_PHASE | 2069 NJSC32_CMD_AUTO_SCSI_RESTART; 2070 2071 /* 2072 * Be careful the second and latter bytes of Message In 2073 * shall not be absorbed by AutoSCSI. 2074 */ 2075 if (sc->sc_msgincnt == 0) 2076 cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2077 2078 if (sc->sc_msgoutlen != 0) 2079 cctl |= NJSC32_CMD_AUTO_ATN; 2080 2081 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout); 2082 2083 /* (re)start AutoSCSI (may assert ATN) */ 2084 if (reload_params) { 2085 njsc32_cmd_reload(sc, cmd, cctl); 2086 } else { 2087 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2088 } 2089 2090 /* +ATN -> -REQ: need 90ns delay? */ 2091 2092 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2093 2094 njsc32_negate_ack(sc); 2095 2096 return; 2097 } 2098 2099 static void 2100 njsc32_msgout(struct njsc32_softc *sc) 2101 { 2102 int cctl; 2103 u_int8_t bus; 2104 unsigned n; 2105 2106 if (sc->sc_msgoutlen == 0) { 2107 /* target entered to Message Out on unexpected timing */ 2108 njsc32_add_msgout(sc, MSG_NOOP); 2109 } 2110 2111 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2112 NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART | 2113 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2114 2115 /* make sure target is in Message Out phase */ 2116 bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR); 2117 if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) { 2118 /* 2119 * Message Out is aborted by target. 2120 */ 2121 printf("%s: njsc32_msgout: phase change %#x\n", 2122 sc->sc_dev.dv_xname, bus); 2123 2124 /* XXX what to do? */ 2125 2126 /* restart AutoSCSI (negate ATN) */ 2127 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2128 2129 sc->sc_msgoutidx = 0; 2130 return; 2131 } 2132 2133 n = sc->sc_msgoutidx; 2134 if (n == sc->sc_msgoutlen - 1) { 2135 /* 2136 * negate ATN before sending ACK 2137 */ 2138 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0); 2139 2140 sc->sc_msgoutidx = 0; /* target may retry Message Out */ 2141 } else { 2142 cctl |= NJSC32_CMD_AUTO_ATN; 2143 sc->sc_msgoutidx++; 2144 } 2145 2146 /* Send Message Out */ 2147 njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]); 2148 2149 /* DBn -> +ACK: need 55ns delay? */ 2150 2151 njsc32_assert_ack(sc); 2152 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2153 2154 /* restart AutoSCSI */ 2155 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2156 2157 njsc32_negate_ack(sc); 2158 2159 /* 2160 * do not reset sc->sc_msgoutlen so the target 2161 * can retry Message Out phase 2162 */ 2163 } 2164 2165 static void 2166 njsc32_cmdtimeout(void *arg) 2167 { 2168 struct njsc32_cmd *cmd = arg; 2169 struct njsc32_softc *sc; 2170 int s; 2171 2172 PRINTC(cmd, ("command timeout\n")); 2173 2174 sc = cmd->c_sc; 2175 2176 s = splbio(); 2177 2178 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2179 njsc32_arbitration_failed(sc); 2180 else { 2181 sc->sc_curcmd = NULL; 2182 sc->sc_stat = NJSC32_STAT_IDLE; 2183 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2184 } 2185 2186 /* XXX? */ 2187 njsc32_init(sc, 1); /* bus reset */ 2188 2189 splx(s); 2190 } 2191 2192 static void 2193 njsc32_reseltimeout(void *arg) 2194 { 2195 struct njsc32_cmd *cmd = arg; 2196 struct njsc32_softc *sc; 2197 int s; 2198 2199 PRINTC(cmd, ("reselection timeout\n")); 2200 2201 sc = cmd->c_sc; 2202 2203 s = splbio(); 2204 2205 /* remove from disconnected list */ 2206 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2207 /* I_T_L_Q */ 2208 KASSERT(cmd->c_lu->lu_cmd == NULL); 2209 TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q); 2210 } else { 2211 /* I_T_L */ 2212 KASSERT(cmd->c_lu->lu_cmd == cmd); 2213 cmd->c_lu->lu_cmd = NULL; 2214 } 2215 2216 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2217 2218 /* XXX? */ 2219 njsc32_init(sc, 1); /* bus reset */ 2220 2221 splx(s); 2222 } 2223 2224 static __inline void 2225 njsc32_end_auto(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int auto_phase) 2226 { 2227 struct scsipi_xfer *xs; 2228 2229 if (auto_phase & NJSC32_XPHASE_MSGIN_02) { 2230 /* Message In: 0x02 Save Data Pointer */ 2231 2232 /* 2233 * Adjust saved data pointer 2234 * if the command is not completed yet. 2235 */ 2236 if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 && 2237 (auto_phase & 2238 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) { 2239 njsc32_save_ptr(cmd); 2240 } 2241 TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2242 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2243 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2244 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2245 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT))); 2246 } 2247 2248 xs = cmd->c_xs; 2249 2250 if (auto_phase & NJSC32_XPHASE_MSGIN_00) { 2251 /* Command Complete */ 2252 TPRINTC(cmd, ("njsc32_intr: Command Complete\n")); 2253 switch (xs->status) { 2254 case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY: 2255 /* 2256 * scsipi layer will automatically handle the error 2257 */ 2258 njsc32_end_cmd(sc, cmd, XS_BUSY); 2259 break; 2260 default: 2261 xs->resid -= cmd->c_dp_max; 2262 njsc32_end_cmd(sc, cmd, XS_NOERROR); 2263 break; 2264 } 2265 } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) { 2266 /* Disconnect */ 2267 TPRINTC(cmd, ("njsc32_intr: Disconnect\n")); 2268 2269 /* for ill-designed devices */ 2270 if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0) 2271 njsc32_save_ptr(cmd); 2272 2273 /* 2274 * move current cmd to disconnected list 2275 */ 2276 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2277 /* I_T_L_Q */ 2278 if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD) 2279 TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q); 2280 else 2281 TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q); 2282 } else { 2283 /* I_T_L */ 2284 cmd->c_lu->lu_cmd = cmd; 2285 } 2286 2287 /* 2288 * schedule timeout -- avoid being 2289 * disconnected forever 2290 */ 2291 if ((xs->xs_control & XS_CTL_POLL) == 0) { 2292 callout_stop(&xs->xs_callout); 2293 callout_reset(&xs->xs_callout, mstohz(xs->timeout), 2294 njsc32_reseltimeout, cmd); 2295 } 2296 2297 } else { 2298 /* 2299 * target has come to Bus Free phase 2300 * probably to notify an error 2301 */ 2302 PRINTC(cmd, ("njsc32_intr: unexpected bus free\n")); 2303 /* try Request Sense */ 2304 xs->status = SCSI_CHECK; 2305 njsc32_end_cmd(sc, cmd, XS_BUSY); 2306 } 2307 } 2308 2309 int 2310 njsc32_intr(void *arg) 2311 { 2312 struct njsc32_softc *sc = arg; 2313 u_int16_t intr; 2314 u_int8_t arbstat, bus_phase; 2315 int auto_phase; 2316 int idbit; 2317 struct njsc32_cmd *cmd; 2318 2319 intr = njsc32_read_2(sc, NJSC32_REG_IRQ); 2320 if ((intr & NJSC32_IRQ_INTR_PENDING) == 0) 2321 return 0; /* not mine */ 2322 2323 TPRINTF(("%s: njsc32_intr: %#x\n", sc->sc_dev.dv_xname, intr)); 2324 2325 #if 0 /* I don't think this is required */ 2326 /* mask interrupts */ 2327 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 2328 #endif 2329 2330 /* we got an interrupt, so stop the timer */ 2331 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 2332 2333 if (intr & NJSC32_IRQ_SCSIRESET) { 2334 printf("%s: detected bus reset\n", sc->sc_dev.dv_xname); 2335 /* clear current request */ 2336 njsc32_reset_detected(sc); 2337 goto out; 2338 } 2339 2340 if (sc->sc_stat == NJSC32_STAT_ARBIT) { 2341 cmd = sc->sc_curcmd; 2342 KASSERT(cmd); 2343 arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT); 2344 if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) { 2345 /* 2346 * arbitration done 2347 */ 2348 /* clear arbitration status */ 2349 njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION, 2350 NJSC32_SETARB_CLEAR); 2351 2352 if (arbstat & NJSC32_ARBSTAT_WIN) { 2353 TPRINTC(cmd, 2354 ("njsc32_intr: arbitration won\n")); 2355 2356 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 2357 2358 sc->sc_stat = NJSC32_STAT_CONNECT; 2359 } else { 2360 TPRINTC(cmd, 2361 ("njsc32_intr: arbitration failed\n")); 2362 2363 njsc32_arbitration_failed(sc); 2364 2365 /* XXX delay */ 2366 /* XXX retry counter */ 2367 } 2368 } 2369 } 2370 2371 if (intr & NJSC32_IRQ_TIMER) { 2372 TPRINTF(("%s: njsc32_intr: timer interrupt\n", 2373 sc->sc_dev.dv_xname)); 2374 } 2375 2376 if (intr & NJSC32_IRQ_RESELECT) { 2377 /* Reselection from a target */ 2378 njsc32_arbitration_failed(sc); /* just in case */ 2379 if ((cmd = sc->sc_curcmd) != NULL) { 2380 /* ? */ 2381 printf("%s: unexpected reselection\n", 2382 sc->sc_dev.dv_xname); 2383 sc->sc_curcmd = NULL; 2384 sc->sc_stat = NJSC32_STAT_IDLE; 2385 njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP); 2386 } 2387 2388 idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID); 2389 if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 || 2390 (sc->sc_reselid = ffs(idbit & ~NJSC32_INITIATOR_ID) -1) 2391 < 0) { 2392 printf("%s: invalid reselection (id: %#x)\n", 2393 sc->sc_dev.dv_xname, idbit); 2394 sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */ 2395 } else { 2396 sc->sc_stat = NJSC32_STAT_RESEL; 2397 TPRINTF(("%s: njsc32_intr: reselection from %d\n", 2398 sc->sc_dev.dv_xname, sc->sc_reselid)); 2399 } 2400 } 2401 2402 if (intr & NJSC32_IRQ_PHASE_CHANGE) { 2403 #if 1 /* XXX probably not needed */ 2404 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2405 PRINTC(sc->sc_curcmd, 2406 ("njsc32_intr: cancel arbitration phase\n")); 2407 njsc32_arbitration_failed(sc); 2408 #endif 2409 /* current bus phase */ 2410 bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 2411 NJSC32_BUSMON_PHASE_MASK; 2412 2413 switch (bus_phase) { 2414 case NJSC32_PHASE_MESSAGE_IN: 2415 njsc32_msgin(sc); 2416 break; 2417 2418 /* 2419 * target may suddenly become Status / Bus Free phase 2420 * to notify an error condition 2421 */ 2422 case NJSC32_PHASE_STATUS: 2423 printf("%s: unexpected bus phase: Status\n", 2424 sc->sc_dev.dv_xname); 2425 if ((cmd = sc->sc_curcmd) != NULL) { 2426 cmd->c_xs->status = 2427 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2428 TPRINTC(cmd, ("njsc32_intr: Status %d\n", 2429 cmd->c_xs->status)); 2430 } 2431 break; 2432 case NJSC32_PHASE_BUSFREE: 2433 printf("%s: unexpected bus phase: Bus Free\n", 2434 sc->sc_dev.dv_xname); 2435 if ((cmd = sc->sc_curcmd) != NULL) { 2436 sc->sc_curcmd = NULL; 2437 sc->sc_stat = NJSC32_STAT_IDLE; 2438 if (cmd->c_xs->status != SCSI_QUEUE_FULL && 2439 cmd->c_xs->status != SCSI_BUSY) 2440 cmd->c_xs->status = SCSI_CHECK;/* XXX */ 2441 njsc32_end_cmd(sc, cmd, XS_BUSY); 2442 } 2443 goto out; 2444 default: 2445 #ifdef NJSC32_DEBUG 2446 printf("%s: unexpected bus phase: ", 2447 sc->sc_dev.dv_xname); 2448 switch (bus_phase) { 2449 case NJSC32_PHASE_COMMAND: 2450 printf("Command\n"); break; 2451 case NJSC32_PHASE_MESSAGE_OUT: 2452 printf("Message Out\n");break; 2453 case NJSC32_PHASE_DATA_IN: 2454 printf("Data In\n"); break; 2455 case NJSC32_PHASE_DATA_OUT: 2456 printf("Data Out\n"); break; 2457 case NJSC32_PHASE_RESELECT: 2458 printf("Reselect\n");break; 2459 default: printf("%#x\n", bus_phase); break; 2460 } 2461 #else 2462 printf("%s: unexpected bus phase: %#x", 2463 sc->sc_dev.dv_xname, bus_phase); 2464 #endif 2465 break; 2466 } 2467 } 2468 2469 if (intr & NJSC32_IRQ_AUTOSCSI) { 2470 /* 2471 * AutoSCSI interrupt 2472 */ 2473 auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE); 2474 TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n", 2475 sc->sc_dev.dv_xname, auto_phase)); 2476 njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0); 2477 2478 if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) { 2479 cmd = sc->sc_curcmd; 2480 if (cmd == NULL) { 2481 printf("%s: sel no cmd\n", 2482 sc->sc_dev.dv_xname); 2483 goto out; 2484 } 2485 DPRINTC(cmd, ("njsc32_intr: selection timeout\n")); 2486 2487 sc->sc_curcmd = NULL; 2488 sc->sc_stat = NJSC32_STAT_IDLE; 2489 njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT); 2490 2491 goto out; 2492 } 2493 2494 #ifdef NJSC32_TRACE 2495 if (auto_phase & NJSC32_XPHASE_COMMAND) { 2496 /* Command phase has been automatically processed */ 2497 TPRINTF(("%s: njsc32_intr: Command\n", 2498 sc->sc_dev.dv_xname)); 2499 } 2500 #endif 2501 #ifdef NJSC32_DEBUG 2502 if (auto_phase & NJSC32_XPHASE_ILLEGAL) { 2503 printf("%s: njsc32_intr: Illegal phase\n", 2504 sc->sc_dev.dv_xname); 2505 } 2506 #endif 2507 2508 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) { 2509 TPRINTF(("%s: njsc32_intr: Process Message In\n", 2510 sc->sc_dev.dv_xname)); 2511 njsc32_msgin(sc); 2512 } 2513 2514 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) { 2515 TPRINTF(("%s: njsc32_intr: Process Message Out\n", 2516 sc->sc_dev.dv_xname)); 2517 njsc32_msgout(sc); 2518 } 2519 2520 cmd = sc->sc_curcmd; 2521 if (cmd == NULL) { 2522 TPRINTF(("%s: njsc32_intr: no cmd\n", 2523 sc->sc_dev.dv_xname)); 2524 goto out; 2525 } 2526 2527 if (auto_phase & 2528 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) { 2529 u_int32_t sackcnt, cntoffset; 2530 2531 #ifdef NJSC32_TRACE 2532 if (auto_phase & NJSC32_XPHASE_DATA_IN) 2533 PRINTC(cmd, ("njsc32_intr: data in done\n")); 2534 if (auto_phase & NJSC32_XPHASE_DATA_OUT) 2535 PRINTC(cmd, ("njsc32_intr: data out done\n")); 2536 printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2537 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2538 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2539 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2540 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)); 2541 #endif 2542 2543 /* 2544 * detected parity error on data transfer? 2545 */ 2546 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 2547 (NJSC32_PARITYSTATUS_ERROR_LSB| 2548 NJSC32_PARITYSTATUS_ERROR_MSB)) { 2549 2550 PRINTC(cmd, ("datain: parity error\n")); 2551 2552 /* clear parity error */ 2553 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 2554 NJSC32_PARITYCTL_CHECK_ENABLE | 2555 NJSC32_PARITYCTL_CLEAR_ERROR); 2556 2557 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2558 /* 2559 * XXX command has already finished 2560 * -- what can we do? 2561 * 2562 * It is not clear current command 2563 * caused the error -- reset everything. 2564 */ 2565 njsc32_init(sc, 1); /* XXX */ 2566 } else { 2567 /* XXX does this case occur? */ 2568 #if 1 2569 printf("%s: datain: parity error\n", 2570 sc->sc_dev.dv_xname); 2571 #endif 2572 /* 2573 * Make attention condition and try 2574 * to send Initiator Detected Error 2575 * message. 2576 */ 2577 njsc32_init_msgout(sc); 2578 njsc32_add_msgout(sc, 2579 MSG_INITIATOR_DET_ERR); 2580 njsc32_write_4(sc, 2581 NJSC32_REG_SCSI_MSG_OUT, 2582 njsc32_get_auto_msgout(sc)); 2583 /* restart autoscsi with ATN */ 2584 njsc32_write_2(sc, 2585 NJSC32_REG_COMMAND_CONTROL, 2586 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2587 NJSC32_CMD_AUTO_COMMAND_PHASE | 2588 NJSC32_CMD_AUTO_SCSI_RESTART | 2589 NJSC32_CMD_AUTO_MSGIN_00_04 | 2590 NJSC32_CMD_AUTO_MSGIN_02 | 2591 NJSC32_CMD_AUTO_ATN); 2592 } 2593 goto out; 2594 } 2595 2596 /* 2597 * data has been transferred, and current pointer 2598 * is changed 2599 */ 2600 sackcnt = njsc32_read_4(sc, NJSC32_REG_SACK_CNT); 2601 2602 /* 2603 * The controller returns extra ACK count 2604 * if the DMA buffer is not 4byte aligned. 2605 */ 2606 cntoffset = le32toh(cmd->c_sgt[0].sg_addr) & 3; 2607 #ifdef NJSC32_DEBUG 2608 if (cntoffset != 0) { 2609 printf("sackcnt %u, cntoffset %u\n", 2610 sackcnt, cntoffset); 2611 } 2612 #endif 2613 /* advance SCSI pointer */ 2614 njsc32_set_cur_ptr(cmd, 2615 cmd->c_dp_cur + sackcnt - cntoffset); 2616 } 2617 2618 if (auto_phase & NJSC32_XPHASE_MSGOUT) { 2619 /* Message Out phase has been automatically processed */ 2620 TPRINTC(cmd, ("njsc32_intr: Message Out\n")); 2621 if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 && 2622 sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) { 2623 njsc32_init_msgout(sc); 2624 } 2625 } 2626 2627 if (auto_phase & NJSC32_XPHASE_STATUS) { 2628 /* Status phase has been automatically processed */ 2629 cmd->c_xs->status = 2630 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2631 TPRINTC(cmd, ("njsc32_intr: Status %#x\n", 2632 cmd->c_xs->status)); 2633 } 2634 2635 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2636 /* AutoSCSI is finished */ 2637 2638 TPRINTC(cmd, ("njsc32_intr: Bus Free\n")); 2639 2640 sc->sc_stat = NJSC32_STAT_IDLE; 2641 sc->sc_curcmd = NULL; 2642 2643 njsc32_end_auto(sc, cmd, auto_phase); 2644 } 2645 goto out; 2646 } 2647 2648 if (intr & NJSC32_IRQ_FIFO_THRESHOLD) { 2649 /* XXX We use DMA, and this shouldn't happen */ 2650 printf("%s: njsc32_intr: FIFO\n", sc->sc_dev.dv_xname); 2651 njsc32_init(sc, 1); 2652 goto out; 2653 } 2654 if (intr & NJSC32_IRQ_PCI) { 2655 /* XXX? */ 2656 printf("%s: njsc32_intr: PCI\n", sc->sc_dev.dv_xname); 2657 } 2658 if (intr & NJSC32_IRQ_BMCNTERR) { 2659 /* XXX? */ 2660 printf("%s: njsc32_intr: BM\n", sc->sc_dev.dv_xname); 2661 } 2662 2663 out: 2664 /* go next command if controller is idle */ 2665 if (sc->sc_stat == NJSC32_STAT_IDLE) 2666 njsc32_start(sc); 2667 2668 #if 0 2669 /* enable interrupts */ 2670 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 2671 #endif 2672 2673 return 1; /* processed */ 2674 } 2675
Indexes created Sat Oct 25 16:10:12 GMT 2025