ninjascsi32.c revision 1.22
1 /* $NetBSD: ninjascsi32.c,v 1.22 2012/03/10 20:54:21 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by ITOH Yasufumi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.22 2012/03/10 20:54:21 mrg Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/callout.h> 38 #include <sys/device.h> 39 #include <sys/kernel.h> 40 #include <sys/buf.h> 41 #include <sys/scsiio.h> 42 #include <sys/proc.h> 43 44 #include <sys/bus.h> 45 #include <sys/intr.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 /* 53 * DualEdge transfer support 54 */ 55 /* #define NJSC32_DUALEDGE */ /* XXX untested */ 56 57 /* 58 * Auto param loading does not work properly (it partially works (works on 59 * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51), 60 * and it doesn't improve the performance so much, 61 * forget about it. 62 */ 63 #undef NJSC32_AUTOPARAM 64 65 #include <dev/ic/ninjascsi32reg.h> 66 #include <dev/ic/ninjascsi32var.h> 67 68 /* #define NJSC32_DEBUG */ 69 /* #define NJSC32_TRACE */ 70 71 #ifdef NJSC32_DEBUG 72 #define DPRINTF(x) printf x 73 #define DPRINTC(cmd, x) PRINTC(cmd, x) 74 #else 75 #define DPRINTF(x) 76 #define DPRINTC(cmd, x) 77 #endif 78 #ifdef NJSC32_TRACE 79 #define TPRINTF(x) printf x 80 #define TPRINTC(cmd, x) PRINTC(cmd, x) 81 #else 82 #define TPRINTF(x) 83 #define TPRINTC(cmd, x) 84 #endif 85 86 #define PRINTC(cmd, x) do { \ 87 scsi_print_addr((cmd)->c_xs->xs_periph); \ 88 printf x; \ 89 } while (/* CONSTCOND */ 0) 90 91 static void njsc32_scsipi_request(struct scsipi_channel *, 92 scsipi_adapter_req_t, void *); 93 static void njsc32_scsipi_minphys(struct buf *); 94 static int njsc32_scsipi_ioctl(struct scsipi_channel *, u_long, void *, 95 int, struct proc *); 96 97 static void njsc32_init(struct njsc32_softc *, int nosleep); 98 static int njsc32_init_cmds(struct njsc32_softc *); 99 static void njsc32_target_async(struct njsc32_softc *, 100 struct njsc32_target *); 101 static void njsc32_init_targets(struct njsc32_softc *); 102 static void njsc32_add_msgout(struct njsc32_softc *, int); 103 static u_int32_t njsc32_get_auto_msgout(struct njsc32_softc *); 104 #ifdef NJSC32_DUALEDGE 105 static void njsc32_msgout_wdtr(struct njsc32_softc *, int); 106 #endif 107 static void njsc32_msgout_sdtr(struct njsc32_softc *, int period, 108 int offset); 109 static void njsc32_negotiate_xfer(struct njsc32_softc *, 110 struct njsc32_target *); 111 static void njsc32_arbitration_failed(struct njsc32_softc *); 112 static void njsc32_start(struct njsc32_softc *); 113 static void njsc32_run_xfer(struct njsc32_softc *, struct scsipi_xfer *); 114 static void njsc32_end_cmd(struct njsc32_softc *, struct njsc32_cmd *, 115 scsipi_xfer_result_t); 116 static void njsc32_wait_reset_release(void *); 117 static void njsc32_reset_bus(struct njsc32_softc *); 118 static void njsc32_clear_cmds(struct njsc32_softc *, 119 scsipi_xfer_result_t); 120 static void njsc32_set_ptr(struct njsc32_softc *, struct njsc32_cmd *, 121 u_int32_t); 122 static void njsc32_assert_ack(struct njsc32_softc *); 123 static void njsc32_negate_ack(struct njsc32_softc *); 124 static void njsc32_wait_req_negate(struct njsc32_softc *); 125 static void njsc32_reconnect(struct njsc32_softc *, struct njsc32_cmd *); 126 enum njsc32_reselstat { 127 NJSC32_RESEL_ERROR, /* to be rejected */ 128 NJSC32_RESEL_COMPLETE, /* reselection is just complete */ 129 NJSC32_RESEL_THROUGH /* this message is OK (no reply) */ 130 }; 131 static enum njsc32_reselstat njsc32_resel_identify(struct njsc32_softc *, 132 int lun, struct njsc32_cmd **); 133 static enum njsc32_reselstat njsc32_resel_tag(struct njsc32_softc *, 134 int tag, struct njsc32_cmd **); 135 static void njsc32_cmd_reload(struct njsc32_softc *, struct njsc32_cmd *, 136 int); 137 static void njsc32_update_xfer_mode(struct njsc32_softc *, 138 struct njsc32_target *); 139 static void njsc32_msgin(struct njsc32_softc *); 140 static void njsc32_msgout(struct njsc32_softc *); 141 static void njsc32_cmdtimeout(void *); 142 static void njsc32_reseltimeout(void *); 143 144 static inline unsigned 145 njsc32_read_1(struct njsc32_softc *sc, int no) 146 { 147 148 return bus_space_read_1(sc->sc_regt, sc->sc_regh, no); 149 } 150 151 static inline unsigned 152 njsc32_read_2(struct njsc32_softc *sc, int no) 153 { 154 155 return bus_space_read_2(sc->sc_regt, sc->sc_regh, no); 156 } 157 158 static inline u_int32_t 159 njsc32_read_4(struct njsc32_softc *sc, int no) 160 { 161 162 return bus_space_read_4(sc->sc_regt, sc->sc_regh, no); 163 } 164 165 static inline void 166 njsc32_write_1(struct njsc32_softc *sc, int no, int val) 167 { 168 169 bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val); 170 } 171 172 static inline void 173 njsc32_write_2(struct njsc32_softc *sc, int no, int val) 174 { 175 176 bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val); 177 } 178 179 static inline void 180 njsc32_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 181 { 182 183 bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val); 184 } 185 186 static inline unsigned 187 njsc32_ireg_read_1(struct njsc32_softc *sc, int no) 188 { 189 190 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 191 return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 192 } 193 194 static inline unsigned 195 njsc32_ireg_read_2(struct njsc32_softc *sc, int no) 196 { 197 198 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 199 return bus_space_read_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 200 } 201 202 static inline u_int32_t 203 njsc32_ireg_read_4(struct njsc32_softc *sc, int no) 204 { 205 u_int32_t val; 206 207 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 208 val = (u_int16_t)bus_space_read_2(sc->sc_regt, sc->sc_regh, 209 NJSC32_REG_DATA_LOW); 210 return val | (bus_space_read_2(sc->sc_regt, sc->sc_regh, 211 NJSC32_REG_DATA_HIGH) << 16); 212 } 213 214 static inline void 215 njsc32_ireg_write_1(struct njsc32_softc *sc, int no, int val) 216 { 217 218 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 219 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 220 } 221 222 static inline void 223 njsc32_ireg_write_2(struct njsc32_softc *sc, int no, int val) 224 { 225 226 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 227 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 228 } 229 230 static inline void 231 njsc32_ireg_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 232 { 233 234 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 235 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 236 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_HIGH, 237 val >> 16); 238 } 239 240 #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */ 241 #ifdef __STDC__ 242 # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK 243 # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \ 244 NJSC32_SREQ_SAMPLING_ENABLE) 245 #else 246 # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK 247 # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \ 248 NJSC32_SREQ_SAMPLING_ENABLE) 249 #endif 250 251 #define NJSC32_NSYNCT_MAXSYNC 1 252 #define NJSC32_NSYNCT 16 253 254 /* 40MHz (25ns) */ 255 static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = { 256 { 0, 0, 0 }, /* dummy for async */ 257 { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */ 258 { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */ 259 { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */ 260 { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */ 261 { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */ 262 { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */ 263 { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 264 { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */ 265 { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 266 { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */ 267 { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */ 268 { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */ 269 { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */ 270 { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */ 271 { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */ 272 }; 273 274 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 275 /* 20MHz (50ns) */ 276 static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = { 277 { 0, 0, 0 }, /* dummy for async */ 278 { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */ 279 { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */ 280 { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 281 { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 282 { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */ 283 { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */ 284 { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */ 285 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */ 286 { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */ 287 { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */ 288 { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */ 289 { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */ 290 { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */ 291 { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */ 292 { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */ 293 }; 294 295 /* 33.3MHz (30ns) */ 296 static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = { 297 { 0, 0, 0 }, /* dummy for async */ 298 { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */ 299 { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */ 300 { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */ 301 { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */ 302 { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */ 303 { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */ 304 { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */ 305 { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */ 306 { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */ 307 { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */ 308 { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */ 309 { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */ 310 { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */ 311 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */ 312 { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */ 313 }; 314 #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */ 315 316 #undef NS 317 #undef ACKW 318 #undef SMPL 319 320 /* initialize device */ 321 static void 322 njsc32_init(struct njsc32_softc *sc, int nosleep) 323 { 324 u_int16_t intstat; 325 int i; 326 327 /* block all interrupts */ 328 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 329 330 /* clear transfer */ 331 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 332 njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0); 333 334 /* make sure interrupts are cleared */ 335 for (i = 0; ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ)) 336 & NJSC32_IRQ_INTR_PENDING) && i < 5 /* just not forever */; i++) { 337 DPRINTF(("%s: njsc32_init: intr pending: %#x\n", 338 device_xname(sc->sc_dev), intstat)); 339 } 340 341 /* FIFO threshold */ 342 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL, 343 NJSC32_FIFO_FULL_BUSMASTER); 344 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY, 345 NJSC32_FIFO_EMPTY_BUSMASTER); 346 347 /* clock source */ 348 njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk); 349 350 /* memory read multiple */ 351 njsc32_ireg_write_1(sc, NJSC32_IREG_BM, 352 NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD); 353 354 /* clear parity error and enable parity detection */ 355 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 356 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 357 358 /* misc configuration */ 359 njsc32_ireg_write_2(sc, NJSC32_IREG_MISC, 360 NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT | 361 NJSC32_MISC_DELAYED_BMSTART | 362 NJSC32_MISC_MASTER_TERMINATION_SELECT | 363 NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL | 364 NJSC32_MISC_AUTOSEL_TIMING_SEL | 365 NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE); 366 367 /* 368 * Check for termination power (32Bi and some versions of 32UDE). 369 */ 370 if (!nosleep || cold) { 371 DPRINTF(("%s: njsc32_init: checking TERMPWR\n", 372 device_xname(sc->sc_dev))); 373 374 /* First, turn termination power off */ 375 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0); 376 377 /* give 0.5s to settle */ 378 if (nosleep) 379 delay(500000); 380 else 381 tsleep(sc, PWAIT, "njs_t1", hz / 2); 382 } 383 384 /* supply termination power if not supplied by other devices */ 385 if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) & 386 NJSC32_TERMPWR_SENSE) == 0) { 387 /* termination power is not present on the bus */ 388 if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) { 389 /* 390 * CardBus device must not supply termination power 391 * to avoid excessive power consumption. 392 */ 393 printf("%s: no termination power present\n", 394 device_xname(sc->sc_dev)); 395 } else { 396 /* supply termination power */ 397 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 398 NJSC32_TERMPWR_BPWR); 399 400 DPRINTF(("%s: supplying termination power\n", 401 device_xname(sc->sc_dev))); 402 403 /* give 0.5s to settle */ 404 if (!nosleep) 405 tsleep(sc, PWAIT, "njs_t2", hz / 2); 406 } 407 } 408 409 /* stop timer */ 410 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 411 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 412 413 /* default transfer parameter */ 414 njsc32_write_1(sc, NJSC32_REG_SYNC, 0); 415 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK); 416 njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT, 417 NJSC32_SEL_TIMEOUT_TIME); 418 419 /* select interrupt source */ 420 njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT, 421 NJSC32_IRQSEL_RESELECT | 422 NJSC32_IRQSEL_PHASE_CHANGE | 423 NJSC32_IRQSEL_SCSIRESET | 424 NJSC32_IRQSEL_TIMER | 425 NJSC32_IRQSEL_FIFO_THRESHOLD | 426 NJSC32_IRQSEL_TARGET_ABORT | 427 NJSC32_IRQSEL_MASTER_ABORT | 428 /* XXX not yet 429 NJSC32_IRQSEL_SERR | 430 NJSC32_IRQSEL_PERR | 431 NJSC32_IRQSEL_BMCNTERR | 432 */ 433 NJSC32_IRQSEL_AUTO_SCSI_SEQ); 434 435 /* interrupts will be unblocked later after bus reset */ 436 437 /* turn LED off */ 438 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR, 439 NJSC32_EXTPORT_LED_OFF); 440 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, 441 NJSC32_EXTPORT_LED_OFF); 442 443 /* reset SCSI bus so the targets become known state */ 444 njsc32_reset_bus(sc); 445 } 446 447 static int 448 njsc32_init_cmds(struct njsc32_softc *sc) 449 { 450 struct njsc32_cmd *cmd; 451 bus_addr_t dmaaddr; 452 int i, error; 453 454 /* 455 * allocate DMA area for command 456 */ 457 if ((error = bus_dmamem_alloc(sc->sc_dmat, 458 sizeof(struct njsc32_dma_page), PAGE_SIZE, 0, 459 &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) { 460 aprint_error_dev(sc->sc_dev, 461 "unable to allocate cmd page, error = %d\n", 462 error); 463 return 0; 464 } 465 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg, 466 sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page), 467 (void **)&sc->sc_cmdpg, 468 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 469 aprint_error_dev(sc->sc_dev, 470 "unable to map cmd page, error = %d\n", 471 error); 472 goto fail1; 473 } 474 if ((error = bus_dmamap_create(sc->sc_dmat, 475 sizeof(struct njsc32_dma_page), 1, 476 sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT, 477 &sc->sc_dmamap_cmdpg)) != 0) { 478 aprint_error_dev(sc->sc_dev, 479 "unable to create cmd DMA map, error = %d\n", 480 error); 481 goto fail2; 482 } 483 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg, 484 sc->sc_cmdpg, sizeof(struct njsc32_dma_page), 485 NULL, BUS_DMA_NOWAIT)) != 0) { 486 aprint_error_dev(sc->sc_dev, 487 "unable to load cmd DMA map, error = %d\n", 488 error); 489 goto fail3; 490 } 491 492 memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page)); 493 dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr; 494 495 #ifdef NJSC32_AUTOPARAM 496 sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap); 497 #endif 498 499 for (i = 0; i < NJSC32_NUM_CMD; i++) { 500 cmd = &sc->sc_cmds[i]; 501 cmd->c_sc = sc; 502 cmd->c_sgt = sc->sc_cmdpg->dp_sg[i]; 503 cmd->c_sgt_dma = dmaaddr + 504 offsetof(struct njsc32_dma_page, dp_sg[i]); 505 cmd->c_flags = 0; 506 507 error = bus_dmamap_create(sc->sc_dmat, 508 NJSC32_MAX_XFER, /* max total map size */ 509 NJSC32_NUM_SG, /* max number of segments */ 510 NJSC32_SGT_MAXSEGLEN, /* max size of a segment */ 511 0, /* boundary */ 512 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer); 513 if (error) { 514 aprint_error_dev(sc->sc_dev, 515 "only %d cmd descs available (error = %d)\n", 516 i, error); 517 break; 518 } 519 TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q); 520 } 521 522 if (i > 0) 523 return i; 524 525 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 526 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 527 fail2: bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cmdpg, 528 sizeof(struct njsc32_dma_page)); 529 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs); 530 531 return 0; 532 } 533 534 static void 535 njsc32_target_async(struct njsc32_softc *sc, struct njsc32_target *target) 536 { 537 538 target->t_sync = 539 NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC); 540 target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK; 541 target->t_sample = 0; /* disable */ 542 target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC; 543 target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC; 544 } 545 546 static void 547 njsc32_init_targets(struct njsc32_softc *sc) 548 { 549 int id, lun; 550 struct njsc32_lu *lu; 551 552 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 553 /* cancel negotiation status */ 554 sc->sc_targets[id].t_state = NJSC32_TARST_INIT; 555 556 /* default to async mode */ 557 njsc32_target_async(sc, &sc->sc_targets[id]); 558 559 #ifdef NJSC32_DUALEDGE 560 sc->sc_targets[id].t_xferctl = 0; 561 #endif 562 563 sc->sc_targets[id].t_targetid = 564 (1 << id) | (1 << NJSC32_INITIATOR_ID); 565 566 /* init logical units */ 567 for (lun = 0; lun < NJSC32_NLU; lun++) { 568 lu = &sc->sc_targets[id].t_lus[lun]; 569 lu->lu_cmd = NULL; 570 TAILQ_INIT(&lu->lu_q); 571 } 572 } 573 } 574 575 void 576 njsc32_attach(struct njsc32_softc *sc) 577 { 578 const char *str; 579 #if 1 /* test */ 580 int reg; 581 njsc32_model_t detected_model; 582 #endif 583 584 /* init */ 585 TAILQ_INIT(&sc->sc_freecmd); 586 TAILQ_INIT(&sc->sc_reqcmd); 587 callout_init(&sc->sc_callout, 0); 588 589 #if 1 /* test */ 590 /* 591 * try to distinguish 32Bi and 32UDE 592 */ 593 /* try to set DualEdge bit (exists on 32UDE only) and read it back */ 594 njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE); 595 if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) { 596 /* device was removed? */ 597 aprint_error_dev(sc->sc_dev, "attach failed\n"); 598 return; 599 } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) { 600 detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE; 601 } else { 602 detected_model = NJSC32_MODEL_32BI; 603 } 604 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */ 605 606 #if 1/*def DIAGNOSTIC*/ 607 /* compare what is configured with what is detected */ 608 if ((sc->sc_model & NJSC32_MODEL_MASK) != 609 (detected_model & NJSC32_MODEL_MASK)) { 610 /* 611 * Please report this error if it happens. 612 */ 613 aprint_error_dev(sc->sc_dev, "model mismatch: %#x vs %#x\n", 614 sc->sc_model, detected_model); 615 return; 616 } 617 #endif 618 #endif 619 620 /* check model */ 621 switch (sc->sc_model & NJSC32_MODEL_MASK) { 622 case NJSC32_MODEL_32BI: 623 str = "Bi"; 624 /* 32Bi doesn't support DualEdge transfer */ 625 KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0); 626 break; 627 case NJSC32_MODEL_32UDE: 628 str = "UDE"; 629 break; 630 default: 631 aprint_error_dev(sc->sc_dev, "unknown model!\n"); 632 return; 633 } 634 aprint_normal_dev(sc->sc_dev, "NJSC-32%s", str); 635 636 switch (sc->sc_clk) { 637 default: 638 #ifdef DIAGNOSTIC 639 panic("njsc32_attach: unknown clk %d", sc->sc_clk); 640 #endif 641 case NJSC32_CLOCK_DIV_4: 642 sc->sc_synct = njsc32_synct_40M; 643 str = "40MHz"; 644 break; 645 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 646 case NJSC32_CLOCK_DIV_2: 647 sc->sc_synct = njsc32_synct_20M; 648 str = "20MHz"; 649 break; 650 case NJSC32_CLOCK_PCICLK: 651 sc->sc_synct = njsc32_synct_pci; 652 str = "PCI"; 653 break; 654 #endif 655 } 656 aprint_normal(", G/A rev %#x, clk %s%s\n", 657 NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str, 658 (sc->sc_model & NJSC32_FLAG_DUALEDGE) ? 659 #ifdef NJSC32_DUALEDGE 660 ", DualEdge" 661 #else 662 ", DualEdge (no driver support)" 663 #endif 664 : ""); 665 666 /* allocate DMA resource */ 667 if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) { 668 aprint_error_dev(sc->sc_dev, "no usable DMA map\n"); 669 return; 670 } 671 sc->sc_flags |= NJSC32_CMDPG_MAPPED; 672 673 sc->sc_curcmd = NULL; 674 sc->sc_nusedcmds = 0; 675 676 sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */ 677 678 /* initialize hardware and target structure */ 679 njsc32_init(sc, cold); 680 681 /* setup adapter */ 682 sc->sc_adapter.adapt_dev = sc->sc_dev; 683 sc->sc_adapter.adapt_nchannels = 1; 684 sc->sc_adapter.adapt_request = njsc32_scsipi_request; 685 sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys; 686 sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl; 687 688 sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings = 689 sc->sc_ncmd; 690 691 /* setup channel */ 692 sc->sc_channel.chan_adapter = &sc->sc_adapter; 693 sc->sc_channel.chan_bustype = &scsi_bustype; 694 sc->sc_channel.chan_channel = 0; 695 sc->sc_channel.chan_ntargets = NJSC32_NTARGET; 696 sc->sc_channel.chan_nluns = NJSC32_NLU; 697 sc->sc_channel.chan_id = NJSC32_INITIATOR_ID; 698 699 sc->sc_scsi = config_found(sc->sc_dev, &sc->sc_channel, scsiprint); 700 } 701 702 int 703 njsc32_detach(struct njsc32_softc *sc, int flags) 704 { 705 int rv = 0; 706 int i, s; 707 struct njsc32_cmd *cmd; 708 709 callout_stop(&sc->sc_callout); 710 711 s = splbio(); 712 713 /* clear running/disconnected commands */ 714 njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP); 715 716 sc->sc_stat = NJSC32_STAT_DETACH; 717 718 /* clear pending commands */ 719 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 720 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 721 njsc32_end_cmd(sc, cmd, XS_RESET); 722 } 723 724 if (sc->sc_scsi != NULL) 725 rv = config_detach(sc->sc_scsi, flags); 726 727 splx(s); 728 729 /* free DMA resource */ 730 if (sc->sc_flags & NJSC32_CMDPG_MAPPED) { 731 for (i = 0; i < sc->sc_ncmd; i++) { 732 cmd = &sc->sc_cmds[i]; 733 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) 734 bus_dmamap_unload(sc->sc_dmat, 735 cmd->c_dmamap_xfer); 736 bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer); 737 } 738 739 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 740 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 741 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cmdpg, 742 sizeof(struct njsc32_dma_page)); 743 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, 744 sc->sc_cmdpg_nsegs); 745 } 746 747 return 0; 748 } 749 750 static inline void 751 njsc32_cmd_init(struct njsc32_cmd *cmd) 752 { 753 754 cmd->c_flags = 0; 755 756 /* scatter/gather table */ 757 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0); 758 cmd->c_sgoffset = 0; 759 cmd->c_sgfixcnt = 0; 760 761 /* data pointer */ 762 cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0; 763 } 764 765 static inline void 766 njsc32_init_msgout(struct njsc32_softc *sc) 767 { 768 769 sc->sc_msgoutlen = 0; 770 sc->sc_msgoutidx = 0; 771 } 772 773 static void 774 njsc32_add_msgout(struct njsc32_softc *sc, int byte) 775 { 776 777 if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) { 778 printf("njsc32_add_msgout: too many\n"); 779 return; 780 } 781 sc->sc_msgout[sc->sc_msgoutlen++] = byte; 782 } 783 784 static u_int32_t 785 njsc32_get_auto_msgout(struct njsc32_softc *sc) 786 { 787 u_int32_t val; 788 u_int8_t *p; 789 790 val = 0; 791 p = sc->sc_msgout; 792 switch (sc->sc_msgoutlen) { 793 /* 31-24 23-16 15-8 7 ... 1 0 */ 794 case 3: /* MSG3 MSG2 MSG1 V --- cnt */ 795 val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT; 796 /* FALLTHROUGH */ 797 798 case 2: /* MSG2 MSG1 --- V --- cnt */ 799 val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT; 800 /* FALLTHROUGH */ 801 802 case 1: /* MSG1 --- --- V --- cnt */ 803 val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT; 804 val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen; 805 break; 806 807 default: 808 break; 809 } 810 return val; 811 } 812 813 #ifdef NJSC32_DUALEDGE 814 /* add Wide Data Transfer Request to the next Message Out */ 815 static void 816 njsc32_msgout_wdtr(struct njsc32_softc *sc, int width) 817 { 818 819 njsc32_add_msgout(sc, MSG_EXTENDED); 820 njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN); 821 njsc32_add_msgout(sc, MSG_EXT_WDTR); 822 njsc32_add_msgout(sc, width); 823 } 824 #endif 825 826 /* add Synchronous Data Transfer Request to the next Message Out */ 827 static void 828 njsc32_msgout_sdtr(struct njsc32_softc *sc, int period, int offset) 829 { 830 831 njsc32_add_msgout(sc, MSG_EXTENDED); 832 njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN); 833 njsc32_add_msgout(sc, MSG_EXT_SDTR); 834 njsc32_add_msgout(sc, period); 835 njsc32_add_msgout(sc, offset); 836 } 837 838 static void 839 njsc32_negotiate_xfer(struct njsc32_softc *sc, struct njsc32_target *target) 840 { 841 842 /* initial negotiation state */ 843 if (target->t_state == NJSC32_TARST_INIT) { 844 #ifdef NJSC32_DUALEDGE 845 if (target->t_flags & NJSC32_TARF_DE) 846 target->t_state = NJSC32_TARST_DE; 847 else 848 #endif 849 if (target->t_flags & NJSC32_TARF_SYNC) 850 target->t_state = NJSC32_TARST_SDTR; 851 else 852 target->t_state = NJSC32_TARST_DONE; 853 } 854 855 switch (target->t_state) { 856 default: 857 case NJSC32_TARST_INIT: 858 #ifdef DIAGNOSTIC 859 panic("njsc32_negotiate_xfer"); 860 /* NOTREACHED */ 861 #endif 862 /* FALLTHROUGH */ 863 case NJSC32_TARST_DONE: 864 /* no more work */ 865 break; 866 867 #ifdef NJSC32_DUALEDGE 868 case NJSC32_TARST_DE: 869 njsc32_msgout_wdtr(sc, 0xde /* XXX? */); 870 break; 871 872 case NJSC32_TARST_WDTR: 873 njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT); 874 break; 875 #endif 876 877 case NJSC32_TARST_SDTR: 878 njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period, 879 NJSC32_SYNCOFFSET_MAX); 880 break; 881 882 case NJSC32_TARST_ASYNC: 883 njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC, 884 NJSC32_SYNCOFFSET_ASYNC); 885 break; 886 } 887 } 888 889 /* turn LED on */ 890 static inline void 891 njsc32_led_on(struct njsc32_softc *sc) 892 { 893 894 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON); 895 } 896 897 /* turn LED off */ 898 static inline void 899 njsc32_led_off(struct njsc32_softc *sc) 900 { 901 902 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF); 903 } 904 905 static void 906 njsc32_arbitration_failed(struct njsc32_softc *sc) 907 { 908 struct njsc32_cmd *cmd; 909 910 if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT) 911 return; 912 913 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) 914 callout_stop(&cmd->c_xs->xs_callout); 915 916 sc->sc_stat = NJSC32_STAT_IDLE; 917 sc->sc_curcmd = NULL; 918 919 /* the command is no longer active */ 920 if (--sc->sc_nusedcmds == 0) 921 njsc32_led_off(sc); 922 } 923 924 static inline void 925 njsc32_cmd_load(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 926 { 927 struct njsc32_target *target; 928 struct scsipi_xfer *xs; 929 int i, control, lun; 930 u_int32_t msgoutreg; 931 #ifdef NJSC32_AUTOPARAM 932 struct njsc32_autoparam *ap; 933 #endif 934 935 xs = cmd->c_xs; 936 #ifdef NJSC32_AUTOPARAM 937 ap = &sc->sc_cmdpg->dp_ap; 938 #else 939 /* reset CDB pointer */ 940 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR); 941 #endif 942 943 /* CDB */ 944 TPRINTC(cmd, ("njsc32_cmd_load: CDB")); 945 for (i = 0; i < xs->cmdlen; i++) { 946 #ifdef NJSC32_AUTOPARAM 947 ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i]; 948 #else 949 njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA, 950 ((u_int8_t *)xs->cmd)[i]); 951 #endif 952 TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i])); 953 } 954 #ifdef NJSC32_AUTOPARAM /* XXX needed? */ 955 for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++) 956 ap->ap_cdb[i].cdb_data = 0; 957 #endif 958 959 control = xs->xs_control; 960 961 /* 962 * Message Out 963 */ 964 njsc32_init_msgout(sc); 965 966 /* Identify */ 967 lun = xs->xs_periph->periph_lun; 968 njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ? 969 MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1)); 970 971 /* tagged queueing */ 972 if (control & XS_CTL_TAGMASK) { 973 njsc32_add_msgout(sc, xs->xs_tag_type); 974 njsc32_add_msgout(sc, xs->xs_tag_id); 975 TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id)); 976 } 977 TPRINTF(("\n")); 978 979 target = cmd->c_target; 980 981 /* transfer negotiation */ 982 if (control & XS_CTL_REQSENSE) 983 target->t_state = NJSC32_TARST_INIT; 984 njsc32_negotiate_xfer(sc, target); 985 986 msgoutreg = njsc32_get_auto_msgout(sc); 987 988 #ifdef NJSC32_AUTOPARAM 989 ap->ap_msgout = htole32(msgoutreg); 990 991 ap->ap_sync = target->t_sync; 992 ap->ap_ackwidth = target->t_ackwidth; 993 ap->ap_targetid = target->t_targetid; 994 ap->ap_sample = target->t_sample; 995 996 ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 997 NJSC32_CMD_AUTO_COMMAND_PHASE | 998 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 999 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1000 #ifdef NJSC32_DUALEDGE 1001 ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl); 1002 #else 1003 ap->ap_xferctl = htole16(cmd->c_xferctl); 1004 #endif 1005 ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr); 1006 1007 /* sync njsc32_autoparam */ 1008 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1009 offsetof(struct njsc32_dma_page, dp_ap), /* offset */ 1010 sizeof(struct njsc32_autoparam), 1011 BUS_DMASYNC_PREWRITE); 1012 1013 /* autoparam DMA address */ 1014 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma); 1015 1016 /* start command (autoparam) */ 1017 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1018 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER); 1019 1020 #else /* not NJSC32_AUTOPARAM */ 1021 1022 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg); 1023 1024 /* load parameters */ 1025 njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid); 1026 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1027 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1028 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1029 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1030 #ifdef NJSC32_DUALEDGE 1031 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1032 cmd->c_xferctl | target->t_xferctl); 1033 #else 1034 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1035 #endif 1036 /* start AutoSCSI */ 1037 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1038 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE | 1039 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1040 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1041 #endif /* not NJSC32_AUTOPARAM */ 1042 } 1043 1044 /* Note: must be called at splbio() */ 1045 static void 1046 njsc32_start(struct njsc32_softc *sc) 1047 { 1048 struct njsc32_cmd *cmd; 1049 1050 /* get a command to issue */ 1051 TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) { 1052 if (cmd->c_lu->lu_cmd == NULL && 1053 ((cmd->c_flags & NJSC32_CMD_TAGGED) || 1054 TAILQ_EMPTY(&cmd->c_lu->lu_q))) 1055 break; /* OK, the logical unit is free */ 1056 } 1057 if (!cmd) 1058 goto out; /* no work to do */ 1059 1060 /* request will always fail if not in bus free phase */ 1061 if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) != 1062 NJSC32_BUSMON_BUSFREE) 1063 goto busy; 1064 1065 /* clear parity error and enable parity detection */ 1066 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1067 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1068 1069 njsc32_cmd_load(sc, cmd); 1070 1071 if (sc->sc_nusedcmds++ == 0) 1072 njsc32_led_on(sc); 1073 1074 sc->sc_curcmd = cmd; 1075 sc->sc_stat = NJSC32_STAT_ARBIT; 1076 1077 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) { 1078 callout_reset(&cmd->c_xs->xs_callout, 1079 mstohz(cmd->c_xs->timeout), 1080 njsc32_cmdtimeout, cmd); 1081 } 1082 1083 return; 1084 1085 busy: /* XXX retry counter */ 1086 TPRINTF(("%s: njsc32_start: busy\n", device_xname(sc->sc_dev))); 1087 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME); 1088 out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 1089 } 1090 1091 static void 1092 njsc32_run_xfer(struct njsc32_softc *sc, struct scsipi_xfer *xs) 1093 { 1094 struct scsipi_periph *periph; 1095 int control; 1096 int lun; 1097 struct njsc32_cmd *cmd; 1098 int s, i, error; 1099 1100 periph = xs->xs_periph; 1101 KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID); 1102 1103 control = xs->xs_control; 1104 lun = periph->periph_lun; 1105 1106 /* 1107 * get a free cmd 1108 * (scsipi layer knows the number of cmds, so this shall never fail) 1109 */ 1110 s = splbio(); 1111 cmd = TAILQ_FIRST(&sc->sc_freecmd); 1112 KASSERT(cmd); 1113 TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q); 1114 splx(s); 1115 1116 /* 1117 * build a request 1118 */ 1119 njsc32_cmd_init(cmd); 1120 cmd->c_xs = xs; 1121 cmd->c_target = &sc->sc_targets[periph->periph_target]; 1122 cmd->c_lu = &cmd->c_target->t_lus[lun]; 1123 1124 /* tagged queueing */ 1125 if (control & XS_CTL_TAGMASK) { 1126 cmd->c_flags |= NJSC32_CMD_TAGGED; 1127 if (control & XS_CTL_HEAD_TAG) 1128 cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD; 1129 } 1130 1131 /* map DMA buffer */ 1132 cmd->c_datacnt = xs->datalen; 1133 if (xs->datalen) { 1134 /* Is XS_CTL_DATA_UIO ever used anywhere? */ 1135 KASSERT((control & XS_CTL_DATA_UIO) == 0); 1136 1137 error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer, 1138 xs->data, xs->datalen, NULL, 1139 ((control & XS_CTL_NOSLEEP) ? 1140 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 1141 BUS_DMA_STREAMING | 1142 ((control & XS_CTL_DATA_IN) ? 1143 BUS_DMA_READ : BUS_DMA_WRITE)); 1144 1145 switch (error) { 1146 case 0: 1147 break; 1148 case ENOMEM: 1149 case EAGAIN: 1150 xs->error = XS_RESOURCE_SHORTAGE; 1151 goto map_failed; 1152 default: 1153 xs->error = XS_DRIVER_STUFFUP; 1154 map_failed: 1155 printf("%s: njsc32_run_xfer: map failed, error %d\n", 1156 device_xname(sc->sc_dev), error); 1157 /* put it back to free command list */ 1158 s = splbio(); 1159 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1160 splx(s); 1161 /* abort this transfer */ 1162 scsipi_done(xs); 1163 return; 1164 } 1165 1166 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1167 0, cmd->c_dmamap_xfer->dm_mapsize, 1168 (control & XS_CTL_DATA_IN) ? 1169 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1170 1171 for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) { 1172 cmd->c_sgt[i].sg_addr = 1173 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr); 1174 cmd->c_sgt[i].sg_len = 1175 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len); 1176 } 1177 /* end mark */ 1178 cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK); 1179 1180 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1181 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1182 NJSC32_SIZE_SGT, 1183 BUS_DMASYNC_PREWRITE); 1184 1185 cmd->c_flags |= NJSC32_CMD_DMA_MAPPED; 1186 1187 /* enable transfer */ 1188 cmd->c_xferctl = 1189 NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START | 1190 NJSC32_XFR_ALL_COUNT_CLR; 1191 1192 /* XXX How can we specify the DMA direction? */ 1193 1194 #if 0 /* faster write mode? (doesn't work) */ 1195 if ((control & XS_CTL_DATA_IN) == 0) 1196 cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE; 1197 #endif 1198 } else { 1199 /* no data transfer */ 1200 cmd->c_xferctl = 0; 1201 } 1202 1203 /* queue request */ 1204 s = splbio(); 1205 TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q); 1206 1207 /* start the controller if idle */ 1208 if (sc->sc_stat == NJSC32_STAT_IDLE) 1209 njsc32_start(sc); 1210 1211 splx(s); 1212 1213 if (control & XS_CTL_POLL) { 1214 /* wait for completion */ 1215 /* XXX should handle timeout? */ 1216 while ((xs->xs_status & XS_STS_DONE) == 0) { 1217 delay(1000); 1218 njsc32_intr(sc); 1219 } 1220 } 1221 } 1222 1223 static void 1224 njsc32_end_cmd(struct njsc32_softc *sc, struct njsc32_cmd *cmd, 1225 scsipi_xfer_result_t result) 1226 { 1227 struct scsipi_xfer *xs; 1228 int s; 1229 #ifdef DIAGNOSTIC 1230 struct njsc32_cmd *c; 1231 #endif 1232 1233 KASSERT(cmd); 1234 1235 #ifdef DIAGNOSTIC 1236 s = splbio(); 1237 TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) { 1238 if (cmd == c) 1239 panic("njsc32_end_cmd: already in free list"); 1240 } 1241 splx(s); 1242 #endif 1243 xs = cmd->c_xs; 1244 1245 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) { 1246 if (cmd->c_datacnt) { 1247 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1248 0, cmd->c_dmamap_xfer->dm_mapsize, 1249 (xs->xs_control & XS_CTL_DATA_IN) ? 1250 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1251 1252 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1253 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, 1254 NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE); 1255 } 1256 1257 bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer); 1258 cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED; 1259 } 1260 1261 s = splbio(); 1262 if ((xs->xs_control & XS_CTL_POLL) == 0) 1263 callout_stop(&xs->xs_callout); 1264 1265 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1266 splx(s); 1267 1268 xs->error = result; 1269 scsipi_done(xs); 1270 1271 if (--sc->sc_nusedcmds == 0) 1272 njsc32_led_off(sc); 1273 } 1274 1275 /* 1276 * request from scsipi layer 1277 */ 1278 static void 1279 njsc32_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1280 void *arg) 1281 { 1282 struct njsc32_softc *sc; 1283 struct scsipi_xfer_mode *xm; 1284 struct njsc32_target *target; 1285 1286 sc = device_private(chan->chan_adapter->adapt_dev); 1287 1288 switch (req) { 1289 case ADAPTER_REQ_RUN_XFER: 1290 njsc32_run_xfer(sc, arg); 1291 break; 1292 1293 case ADAPTER_REQ_GROW_RESOURCES: 1294 /* not supported */ 1295 break; 1296 1297 case ADAPTER_REQ_SET_XFER_MODE: 1298 xm = arg; 1299 target = &sc->sc_targets[xm->xm_target]; 1300 1301 target->t_flags = 0; 1302 if (xm->xm_mode & PERIPH_CAP_TQING) 1303 target->t_flags |= NJSC32_TARF_TAG; 1304 if (xm->xm_mode & PERIPH_CAP_SYNC) { 1305 target->t_flags |= NJSC32_TARF_SYNC; 1306 #ifdef NJSC32_DUALEDGE 1307 if (sc->sc_model & NJSC32_FLAG_DUALEDGE) 1308 target->t_flags |= NJSC32_TARF_DE; 1309 #endif 1310 } 1311 #ifdef NJSC32_DUALEDGE 1312 target->t_xferctl = 0; 1313 #endif 1314 target->t_state = NJSC32_TARST_INIT; 1315 njsc32_target_async(sc, target); 1316 1317 break; 1318 default: 1319 break; 1320 } 1321 } 1322 1323 static void 1324 njsc32_scsipi_minphys(struct buf *bp) 1325 { 1326 1327 if (bp->b_bcount > NJSC32_MAX_XFER) 1328 bp->b_bcount = NJSC32_MAX_XFER; 1329 minphys(bp); 1330 } 1331 1332 /* 1333 * On some versions of 32UDE (probably the earlier ones), the controller 1334 * detects continuous bus reset when the termination power is absent. 1335 * Make sure the system won't hang on such situation. 1336 */ 1337 static void 1338 njsc32_wait_reset_release(void *arg) 1339 { 1340 struct njsc32_softc *sc = arg; 1341 struct njsc32_cmd *cmd; 1342 1343 /* clear pending commands */ 1344 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 1345 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 1346 njsc32_end_cmd(sc, cmd, XS_RESET); 1347 } 1348 1349 /* If Bus Reset is not released yet, schedule recheck. */ 1350 if (njsc32_read_2(sc, NJSC32_REG_IRQ) & NJSC32_IRQ_SCSIRESET) { 1351 switch (sc->sc_stat) { 1352 case NJSC32_STAT_RESET: 1353 sc->sc_stat = NJSC32_STAT_RESET1; 1354 break; 1355 case NJSC32_STAT_RESET1: 1356 /* print message if Bus Reset is detected twice */ 1357 sc->sc_stat = NJSC32_STAT_RESET2; 1358 printf("%s: detected excessive bus reset " 1359 "--- missing termination power?\n", 1360 device_xname(sc->sc_dev)); 1361 break; 1362 default: 1363 break; 1364 } 1365 callout_reset(&sc->sc_callout, 1366 hz * 2 /* poll every 2s */, 1367 njsc32_wait_reset_release, sc); 1368 return; 1369 } 1370 1371 if (sc->sc_stat == NJSC32_STAT_RESET2) 1372 printf("%s: bus reset is released\n", device_xname(sc->sc_dev)); 1373 1374 /* unblock interrupts */ 1375 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 1376 1377 sc->sc_stat = NJSC32_STAT_IDLE; 1378 } 1379 1380 static void 1381 njsc32_reset_bus(struct njsc32_softc *sc) 1382 { 1383 int s; 1384 1385 DPRINTF(("%s: njsc32_reset_bus:\n", device_xname(sc->sc_dev))); 1386 1387 /* block interrupts */ 1388 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 1389 1390 sc->sc_stat = NJSC32_STAT_RESET; 1391 1392 /* hold SCSI bus reset */ 1393 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST); 1394 delay(NJSC32_RESET_HOLD_TIME); 1395 1396 /* clear transfer */ 1397 njsc32_clear_cmds(sc, XS_RESET); 1398 1399 /* initialize target structure */ 1400 njsc32_init_targets(sc); 1401 1402 /* XXXSMP scsipi */ 1403 KERNEL_LOCK(1, curlwp); 1404 s = splbio(); 1405 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL); 1406 splx(s); 1407 /* XXXSMP scsipi */ 1408 KERNEL_UNLOCK_ONE(curlwp); 1409 1410 /* release SCSI bus reset */ 1411 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0); 1412 1413 njsc32_wait_reset_release(sc); 1414 } 1415 1416 /* 1417 * clear running/disconnected commands 1418 */ 1419 static void 1420 njsc32_clear_cmds(struct njsc32_softc *sc, scsipi_xfer_result_t cmdresult) 1421 { 1422 struct njsc32_cmd *cmd; 1423 int id, lun; 1424 struct njsc32_lu *lu; 1425 1426 njsc32_arbitration_failed(sc); 1427 1428 /* clear current transfer */ 1429 if ((cmd = sc->sc_curcmd) != NULL) { 1430 sc->sc_curcmd = NULL; 1431 njsc32_end_cmd(sc, cmd, cmdresult); 1432 } 1433 1434 /* clear disconnected transfers */ 1435 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 1436 for (lun = 0; lun < NJSC32_NLU; lun++) { 1437 lu = &sc->sc_targets[id].t_lus[lun]; 1438 1439 if ((cmd = lu->lu_cmd) != NULL) { 1440 lu->lu_cmd = NULL; 1441 njsc32_end_cmd(sc, cmd, cmdresult); 1442 } 1443 while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) { 1444 TAILQ_REMOVE(&lu->lu_q, cmd, c_q); 1445 njsc32_end_cmd(sc, cmd, cmdresult); 1446 } 1447 } 1448 } 1449 } 1450 1451 static int 1452 njsc32_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd, 1453 void *addr, int flag, struct proc *p) 1454 { 1455 struct njsc32_softc *sc; 1456 1457 sc = device_private(chan->chan_adapter->adapt_dev); 1458 1459 switch (cmd) { 1460 case SCBUSIORESET: 1461 njsc32_init(sc, 0); 1462 return 0; 1463 default: 1464 break; 1465 } 1466 1467 return ENOTTY; 1468 } 1469 1470 /* 1471 * set current data pointer 1472 */ 1473 static inline void 1474 njsc32_set_cur_ptr(struct njsc32_cmd *cmd, u_int32_t pos) 1475 { 1476 1477 /* new current data pointer */ 1478 cmd->c_dp_cur = pos; 1479 1480 /* update number of bytes transferred */ 1481 if (pos > cmd->c_dp_max) 1482 cmd->c_dp_max = pos; 1483 } 1484 1485 /* 1486 * set data pointer for the next transfer 1487 */ 1488 static void 1489 njsc32_set_ptr(struct njsc32_softc *sc, struct njsc32_cmd *cmd, u_int32_t pos) 1490 { 1491 struct njsc32_sgtable *sg; 1492 unsigned sgte; 1493 u_int32_t len; 1494 1495 /* set current pointer */ 1496 njsc32_set_cur_ptr(cmd, pos); 1497 1498 /* undo previous fix if any */ 1499 if (cmd->c_sgfixcnt != 0) { 1500 sg = &cmd->c_sgt[cmd->c_sgoffset]; 1501 sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt); 1502 sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt); 1503 cmd->c_sgfixcnt = 0; 1504 } 1505 1506 if (pos >= cmd->c_datacnt) { 1507 /* transfer done */ 1508 #if 1 /*def DIAGNOSTIC*/ 1509 if (pos > cmd->c_datacnt) 1510 printf("%s: pos %u too large\n", 1511 device_xname(sc->sc_dev), pos - cmd->c_datacnt); 1512 #endif 1513 cmd->c_xferctl = 0; /* XXX correct? */ 1514 1515 return; 1516 } 1517 1518 for (sgte = 0, sg = cmd->c_sgt; 1519 sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) { 1520 len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK; 1521 if (pos < len) { 1522 sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos); 1523 sg->sg_len = htole32(le32toh(sg->sg_len) - pos); 1524 cmd->c_sgfixcnt = pos; 1525 break; 1526 } 1527 pos -= len; 1528 #ifdef DIAGNOSTIC 1529 if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) { 1530 panic("njsc32_set_ptr: bad pos"); 1531 } 1532 #endif 1533 } 1534 #ifdef DIAGNOSTIC 1535 if (sgte >= NJSC32_NUM_SG) 1536 panic("njsc32_set_ptr: bad sg"); 1537 #endif 1538 if (cmd->c_sgoffset != sgte) { 1539 cmd->c_sgoffset = sgte; 1540 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte); 1541 } 1542 1543 /* XXX overkill */ 1544 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1545 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1546 NJSC32_SIZE_SGT, 1547 BUS_DMASYNC_PREWRITE); 1548 } 1549 1550 /* 1551 * save data pointer 1552 */ 1553 static inline void 1554 njsc32_save_ptr(struct njsc32_cmd *cmd) 1555 { 1556 1557 cmd->c_dp_saved = cmd->c_dp_cur; 1558 } 1559 1560 static void 1561 njsc32_assert_ack(struct njsc32_softc *sc) 1562 { 1563 u_int8_t reg; 1564 1565 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1566 reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE; 1567 #if 0 /* needed? */ 1568 reg |= NJSC32_SBCTL_AUTODIRECTION; 1569 #endif 1570 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1571 } 1572 1573 static void 1574 njsc32_negate_ack(struct njsc32_softc *sc) 1575 { 1576 u_int8_t reg; 1577 1578 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1579 #if 0 /* needed? */ 1580 reg |= NJSC32_SBCTL_ACK_ENABLE; 1581 reg |= NJSC32_SBCTL_AUTODIRECTION; 1582 #endif 1583 reg &= ~NJSC32_SBCTL_ACK; 1584 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1585 } 1586 1587 static void 1588 njsc32_wait_req_negate(struct njsc32_softc *sc) 1589 { 1590 int cnt; 1591 1592 for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) { 1593 if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 1594 NJSC32_BUSMON_REQ) == 0) 1595 return; 1596 delay(1); 1597 } 1598 printf("%s: njsc32_wait_req_negate: timed out\n", 1599 device_xname(sc->sc_dev)); 1600 } 1601 1602 static void 1603 njsc32_reconnect(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 1604 { 1605 struct scsipi_xfer *xs; 1606 1607 xs = cmd->c_xs; 1608 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1609 callout_stop(&xs->xs_callout); 1610 callout_reset(&xs->xs_callout, 1611 mstohz(xs->timeout), 1612 njsc32_cmdtimeout, cmd); 1613 } 1614 1615 /* Reconnection implies Restore Pointers */ 1616 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1617 } 1618 1619 static enum njsc32_reselstat 1620 njsc32_resel_identify(struct njsc32_softc *sc, int lun, 1621 struct njsc32_cmd **pcmd) 1622 { 1623 int targetid; 1624 struct njsc32_lu *plu; 1625 struct njsc32_cmd *cmd; 1626 1627 switch (sc->sc_stat) { 1628 case NJSC32_STAT_RESEL: 1629 break; /* OK */ 1630 1631 case NJSC32_STAT_RESEL_LUN: 1632 case NJSC32_STAT_RECONNECT: 1633 /* 1634 * accept and ignore if the LUN is the same as the current one, 1635 * reject otherwise. 1636 */ 1637 return sc->sc_resellun == lun ? 1638 NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR; 1639 1640 default: 1641 printf("%s: njsc32_resel_identify: not in reselection\n", 1642 device_xname(sc->sc_dev)); 1643 return NJSC32_RESEL_ERROR; 1644 } 1645 1646 targetid = sc->sc_reselid; 1647 TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n", 1648 device_xname(sc->sc_dev), lun)); 1649 1650 if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU) 1651 return NJSC32_RESEL_ERROR; 1652 1653 sc->sc_resellun = lun; 1654 plu = &sc->sc_targets[targetid].t_lus[lun]; 1655 1656 if ((cmd = plu->lu_cmd) != NULL) { 1657 sc->sc_stat = NJSC32_STAT_RECONNECT; 1658 plu->lu_cmd = NULL; 1659 *pcmd = cmd; 1660 TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n")); 1661 njsc32_reconnect(sc, cmd); 1662 return NJSC32_RESEL_COMPLETE; 1663 } else if (!TAILQ_EMPTY(&plu->lu_q)) { 1664 /* wait for tag */ 1665 sc->sc_stat = NJSC32_STAT_RESEL_LUN; 1666 return NJSC32_RESEL_THROUGH; 1667 } 1668 1669 /* no disconnected commands */ 1670 return NJSC32_RESEL_ERROR; 1671 } 1672 1673 static enum njsc32_reselstat 1674 njsc32_resel_tag(struct njsc32_softc *sc, int tag, struct njsc32_cmd **pcmd) 1675 { 1676 struct njsc32_cmd_head *head; 1677 struct njsc32_cmd *cmd; 1678 1679 TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n", 1680 device_xname(sc->sc_dev), tag)); 1681 if (sc->sc_stat != NJSC32_STAT_RESEL_LUN) 1682 return NJSC32_RESEL_ERROR; 1683 1684 head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q; 1685 1686 /* XXX slow? */ 1687 /* search for the command of the tag */ 1688 TAILQ_FOREACH(cmd, head, c_q) { 1689 if (cmd->c_xs->xs_tag_id == tag) { 1690 sc->sc_stat = NJSC32_STAT_RECONNECT; 1691 TAILQ_REMOVE(head, cmd, c_q); 1692 *pcmd = cmd; 1693 TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n")); 1694 njsc32_reconnect(sc, cmd); 1695 return NJSC32_RESEL_COMPLETE; 1696 } 1697 } 1698 1699 /* no disconnected commands */ 1700 return NJSC32_RESEL_ERROR; 1701 } 1702 1703 /* 1704 * Reload parameters and restart AutoSCSI. 1705 * 1706 * XXX autoparam doesn't work as expected and we can't use it here. 1707 */ 1708 static void 1709 njsc32_cmd_reload(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int cctl) 1710 { 1711 struct njsc32_target *target; 1712 1713 target = cmd->c_target; 1714 1715 /* clear parity error and enable parity detection */ 1716 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1717 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1718 1719 /* load parameters */ 1720 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1721 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1722 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1723 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1724 #ifdef NJSC32_DUALEDGE 1725 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1726 cmd->c_xferctl | target->t_xferctl); 1727 #else 1728 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1729 #endif 1730 /* start AutoSCSI */ 1731 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 1732 1733 sc->sc_curcmd = cmd; 1734 } 1735 1736 static void 1737 njsc32_update_xfer_mode(struct njsc32_softc *sc, struct njsc32_target *target) 1738 { 1739 struct scsipi_xfer_mode xm; 1740 1741 xm.xm_target = target - sc->sc_targets; /* target ID */ 1742 xm.xm_mode = 0; 1743 xm.xm_period = target->t_syncperiod; 1744 xm.xm_offset = target->t_syncoffset; 1745 if (xm.xm_offset != 0) 1746 xm.xm_mode |= PERIPH_CAP_SYNC; 1747 if (target->t_flags & NJSC32_TARF_TAG) 1748 xm.xm_mode |= PERIPH_CAP_TQING; 1749 1750 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 1751 } 1752 1753 static void 1754 njsc32_msgin(struct njsc32_softc *sc) 1755 { 1756 u_int8_t msg0, msg; 1757 int msgcnt; 1758 struct njsc32_cmd *cmd; 1759 enum njsc32_reselstat rstat; 1760 int cctl = 0; 1761 u_int32_t ptr; /* unsigned type ensures 2-complement calculation */ 1762 u_int32_t msgout = 0; 1763 bool reload_params = FALSE; 1764 struct njsc32_target *target; 1765 int idx, period, offset; 1766 1767 /* 1768 * we are in Message In, so the previous Message Out should have 1769 * been done. 1770 */ 1771 njsc32_init_msgout(sc); 1772 1773 /* get a byte of Message In */ 1774 msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN); 1775 TPRINTF(("%s: njsc32_msgin: got %#x\n", device_xname(sc->sc_dev), msg)); 1776 if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN) 1777 sc->sc_msginbuf[sc->sc_msgincnt] = msg; 1778 1779 njsc32_assert_ack(sc); 1780 1781 msg0 = sc->sc_msginbuf[0]; 1782 cmd = sc->sc_curcmd; 1783 1784 /* check for parity error */ 1785 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 1786 NJSC32_PARITYSTATUS_ERROR_LSB) { 1787 1788 printf("%s: msgin: parity error\n", device_xname(sc->sc_dev)); 1789 1790 /* clear parity error */ 1791 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1792 NJSC32_PARITYCTL_CHECK_ENABLE | 1793 NJSC32_PARITYCTL_CLEAR_ERROR); 1794 1795 /* respond as Message Parity Error */ 1796 njsc32_add_msgout(sc, MSG_PARITY_ERROR); 1797 1798 /* clear Message In */ 1799 sc->sc_msgincnt = 0; 1800 goto reply; 1801 } 1802 1803 #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0) 1804 #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0) 1805 if (MSG_ISIDENTIFY(msg0)) { 1806 /* 1807 * Got Identify message from target. 1808 */ 1809 if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG || 1810 (rstat = njsc32_resel_identify(sc, msg0 & 1811 MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) { 1812 /* 1813 * invalid Identify -> Reject 1814 */ 1815 goto reject; 1816 } 1817 if (rstat == NJSC32_RESEL_COMPLETE) 1818 reload_params = TRUE; 1819 MSGCOMPLETE; 1820 } 1821 1822 if (msg0 == MSG_SIMPLE_Q_TAG) { 1823 if (msgcnt == 0) 1824 WAITNEXTMSG; 1825 1826 /* got whole message */ 1827 sc->sc_msgincnt = 0; 1828 1829 if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd)) 1830 == NJSC32_RESEL_ERROR) { 1831 /* 1832 * invalid Simple Queue Tag -> Abort Tag 1833 */ 1834 printf("%s: msgin: invalid tag\n", 1835 device_xname(sc->sc_dev)); 1836 njsc32_add_msgout(sc, MSG_ABORT_TAG); 1837 goto reply; 1838 } 1839 if (rstat == NJSC32_RESEL_COMPLETE) 1840 reload_params = TRUE; 1841 MSGCOMPLETE; 1842 } 1843 1844 /* I_T_L or I_T_L_Q nexus should be established now */ 1845 if (cmd == NULL) { 1846 printf("%s: msgin %#x without nexus -- sending abort\n", 1847 device_xname(sc->sc_dev), msg0); 1848 njsc32_add_msgout(sc, MSG_ABORT); 1849 goto reply; 1850 } 1851 1852 /* 1853 * extended message 1854 * 0x01 <length (0 stands for 256)> <length bytes> 1855 * (<code> [<parameter> ...]) 1856 */ 1857 #define EXTLENOFF 1 1858 #define EXTCODEOFF 2 1859 if (msg0 == MSG_EXTENDED) { 1860 if (msgcnt < EXTLENOFF || 1861 msgcnt < EXTLENOFF + 1 + 1862 (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1)) 1863 WAITNEXTMSG; 1864 1865 /* got whole message */ 1866 sc->sc_msgincnt = 0; 1867 1868 switch (sc->sc_msginbuf[EXTCODEOFF]) { 1869 case 0: /* Modify Data Pointer */ 1870 if (msgcnt != 5 + EXTCODEOFF - 1) 1871 break; 1872 /* 1873 * parameter is 32bit big-endian signed (2-complement) 1874 * value 1875 */ 1876 ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) | 1877 (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) | 1878 (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) | 1879 sc->sc_msginbuf[EXTCODEOFF + 4]; 1880 1881 /* new pointer */ 1882 ptr += cmd->c_dp_cur; /* ignore overflow */ 1883 1884 /* reject if ptr is not in data buffer */ 1885 if (ptr > cmd->c_datacnt) 1886 break; 1887 1888 njsc32_set_ptr(sc, cmd, ptr); 1889 goto restart; 1890 1891 case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */ 1892 DPRINTC(cmd, ("SDTR %#x %#x\n", 1893 sc->sc_msginbuf[EXTCODEOFF + 1], 1894 sc->sc_msginbuf[EXTCODEOFF + 2])); 1895 if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1) 1896 break; /* reject */ 1897 1898 target = cmd->c_target; 1899 1900 /* lookup sync period parameters */ 1901 period = sc->sc_msginbuf[EXTCODEOFF + 1]; 1902 for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++) 1903 if (sc->sc_synct[idx].sp_period >= period) { 1904 period = sc->sc_synct[idx].sp_period; 1905 break; 1906 } 1907 if (idx >= NJSC32_NSYNCT) { 1908 /* 1909 * We can't meet the timing condition that 1910 * the target requests -- use async. 1911 */ 1912 njsc32_target_async(sc, target); 1913 njsc32_update_xfer_mode(sc, target); 1914 if (target->t_state == NJSC32_TARST_SDTR) { 1915 /* 1916 * We started SDTR exchange -- start 1917 * negotiation again and request async. 1918 */ 1919 target->t_state = NJSC32_TARST_ASYNC; 1920 njsc32_negotiate_xfer(sc, target); 1921 goto reply; 1922 } else { 1923 /* 1924 * The target started SDTR exchange 1925 * -- just reject and fallback 1926 * to async. 1927 */ 1928 goto reject; 1929 } 1930 } 1931 1932 /* check sync offset */ 1933 offset = sc->sc_msginbuf[EXTCODEOFF + 2]; 1934 if (offset > NJSC32_SYNCOFFSET_MAX) { 1935 if (target->t_state == NJSC32_TARST_SDTR) { 1936 printf("%s: wrong sync offset: %d\n", 1937 device_xname(sc->sc_dev), offset); 1938 /* XXX what to do? */ 1939 } 1940 offset = NJSC32_SYNCOFFSET_MAX; 1941 } 1942 1943 target->t_ackwidth = sc->sc_synct[idx].sp_ackw; 1944 target->t_sample = sc->sc_synct[idx].sp_sample; 1945 target->t_syncperiod = period; 1946 target->t_syncoffset = offset; 1947 target->t_sync = NJSC32_SYNC_VAL(idx, offset); 1948 njsc32_update_xfer_mode(sc, target); 1949 1950 if (target->t_state == NJSC32_TARST_SDTR) { 1951 target->t_state = NJSC32_TARST_DONE; 1952 } else { 1953 njsc32_msgout_sdtr(sc, period, offset); 1954 goto reply; 1955 } 1956 goto restart; 1957 1958 case MSG_EXT_WDTR: /* Wide Data Transfer Request */ 1959 DPRINTC(cmd, 1960 ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1])); 1961 #ifdef NJSC32_DUALEDGE 1962 if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1) 1963 break; /* reject */ 1964 1965 /* 1966 * T->I of this message is not used for 1967 * DualEdge negotiation, so the device 1968 * must not be a DualEdge device. 1969 * 1970 * XXX correct? 1971 */ 1972 target = cmd->c_target; 1973 target->t_xferctl = 0; 1974 1975 switch (target->t_state) { 1976 case NJSC32_TARST_DE: 1977 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1978 MSG_EXT_WDTR_BUS_8_BIT) { 1979 /* 1980 * Oops, we got unexpected WDTR. 1981 * Negotiate for 8bit. 1982 */ 1983 target->t_state = NJSC32_TARST_WDTR; 1984 } else { 1985 target->t_state = NJSC32_TARST_SDTR; 1986 } 1987 njsc32_negotiate_xfer(sc, target); 1988 goto reply; 1989 1990 case NJSC32_TARST_WDTR: 1991 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1992 MSG_EXT_WDTR_BUS_8_BIT) { 1993 printf("%s: unexpected transfer width:" 1994 " %#x\n", device_xname(sc->sc_dev), 1995 sc->sc_msginbuf[EXTCODEOFF + 1]); 1996 /* XXX what to do? */ 1997 } 1998 target->t_state = NJSC32_TARST_SDTR; 1999 njsc32_negotiate_xfer(sc, target); 2000 goto reply; 2001 2002 default: 2003 /* the target started WDTR exchange */ 2004 DPRINTC(cmd, ("WDTR from target\n")); 2005 2006 target->t_state = NJSC32_TARST_SDTR; 2007 njsc32_target_async(sc, target); 2008 2009 break; /* reject the WDTR (8bit transfer) */ 2010 } 2011 #endif /* NJSC32_DUALEDGE */ 2012 break; /* reject */ 2013 } 2014 DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n", 2015 sc->sc_msginbuf[EXTCODEOFF], msgcnt)); 2016 goto reject; 2017 } 2018 2019 /* 2byte messages */ 2020 if (MSG_IS2BYTE(msg0)) { 2021 if (msgcnt == 0) 2022 WAITNEXTMSG; 2023 2024 /* got whole message */ 2025 sc->sc_msgincnt = 0; 2026 } 2027 2028 switch (msg0) { 2029 case MSG_CMDCOMPLETE: /* 0x00 */ 2030 case MSG_SAVEDATAPOINTER: /* 0x02 */ 2031 case MSG_DISCONNECT: /* 0x04 */ 2032 /* handled by AutoSCSI */ 2033 PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0)); 2034 break; 2035 2036 case MSG_RESTOREPOINTERS: /* 0x03 */ 2037 /* restore data pointer to what was saved */ 2038 DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n")); 2039 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 2040 reload_params = TRUE; 2041 MSGCOMPLETE; 2042 /* NOTREACHED */ 2043 break; 2044 2045 #if 0 /* handled above */ 2046 case MSG_EXTENDED: /* 0x01 */ 2047 #endif 2048 case MSG_MESSAGE_REJECT: /* 0x07 */ 2049 target = cmd->c_target; 2050 DPRINTC(cmd, ("Reject tarst %d\n", target->t_state)); 2051 switch (target->t_state) { 2052 #ifdef NJSC32_DUALEDGE 2053 case NJSC32_TARST_WDTR: 2054 case NJSC32_TARST_DE: 2055 target->t_xferctl = 0; 2056 target->t_state = NJSC32_TARST_SDTR; 2057 njsc32_negotiate_xfer(sc, target); 2058 goto reply; 2059 #endif 2060 case NJSC32_TARST_SDTR: 2061 case NJSC32_TARST_ASYNC: 2062 njsc32_target_async(sc, target); 2063 target->t_state = NJSC32_TARST_DONE; 2064 njsc32_update_xfer_mode(sc, target); 2065 break; 2066 default: 2067 break; 2068 } 2069 goto restart; 2070 2071 case MSG_NOOP: /* 0x08 */ 2072 #ifdef NJSC32_DUALEDGE 2073 target = cmd->c_target; 2074 if (target->t_state == NJSC32_TARST_DE) { 2075 printf("%s: DualEdge transfer\n", 2076 device_xname(sc->sc_dev)); 2077 target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE; 2078 /* go to next negotiation */ 2079 target->t_state = NJSC32_TARST_SDTR; 2080 njsc32_negotiate_xfer(sc, target); 2081 goto reply; 2082 } 2083 #endif 2084 goto restart; 2085 2086 case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */ 2087 case MSG_ABORT: /* 0x06 I->T only */ 2088 case MSG_PARITY_ERROR: /* 0x09 I->T only */ 2089 case MSG_LINK_CMD_COMPLETE: /* 0x0a */ 2090 case MSG_LINK_CMD_COMPLETEF: /* 0x0b */ 2091 case MSG_BUS_DEV_RESET: /* 0x0c I->T only */ 2092 case MSG_ABORT_TAG: /* 0x0d I->T only */ 2093 case MSG_CLEAR_QUEUE: /* 0x0e I->T only */ 2094 2095 #if 0 /* handled above */ 2096 case MSG_SIMPLE_Q_TAG: /* 0x20 */ 2097 #endif 2098 case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */ 2099 case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */ 2100 case MSG_IGN_WIDE_RESIDUE: /* 0x23 */ 2101 2102 default: 2103 #ifdef NJSC32_DEBUG 2104 PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0)); 2105 if (MSG_IS2BYTE(msg0)) 2106 printf(" %#x", msg); 2107 printf("\n"); 2108 #endif 2109 break; 2110 } 2111 2112 reject: 2113 njsc32_add_msgout(sc, MSG_MESSAGE_REJECT); 2114 2115 reply: 2116 msgout = njsc32_get_auto_msgout(sc); 2117 2118 restart: 2119 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2120 NJSC32_CMD_AUTO_COMMAND_PHASE | 2121 NJSC32_CMD_AUTO_SCSI_RESTART; 2122 2123 /* 2124 * Be careful the second and latter bytes of Message In 2125 * shall not be absorbed by AutoSCSI. 2126 */ 2127 if (sc->sc_msgincnt == 0) 2128 cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2129 2130 if (sc->sc_msgoutlen != 0) 2131 cctl |= NJSC32_CMD_AUTO_ATN; 2132 2133 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout); 2134 2135 /* (re)start AutoSCSI (may assert ATN) */ 2136 if (reload_params) { 2137 njsc32_cmd_reload(sc, cmd, cctl); 2138 } else { 2139 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2140 } 2141 2142 /* +ATN -> -REQ: need 90ns delay? */ 2143 2144 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2145 2146 njsc32_negate_ack(sc); 2147 2148 return; 2149 } 2150 2151 static void 2152 njsc32_msgout(struct njsc32_softc *sc) 2153 { 2154 int cctl; 2155 u_int8_t bus; 2156 unsigned n; 2157 2158 if (sc->sc_msgoutlen == 0) { 2159 /* target entered to Message Out on unexpected timing */ 2160 njsc32_add_msgout(sc, MSG_NOOP); 2161 } 2162 2163 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2164 NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART | 2165 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2166 2167 /* make sure target is in Message Out phase */ 2168 bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR); 2169 if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) { 2170 /* 2171 * Message Out is aborted by target. 2172 */ 2173 printf("%s: njsc32_msgout: phase change %#x\n", 2174 device_xname(sc->sc_dev), bus); 2175 2176 /* XXX what to do? */ 2177 2178 /* restart AutoSCSI (negate ATN) */ 2179 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2180 2181 sc->sc_msgoutidx = 0; 2182 return; 2183 } 2184 2185 n = sc->sc_msgoutidx; 2186 if (n == sc->sc_msgoutlen - 1) { 2187 /* 2188 * negate ATN before sending ACK 2189 */ 2190 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0); 2191 2192 sc->sc_msgoutidx = 0; /* target may retry Message Out */ 2193 } else { 2194 cctl |= NJSC32_CMD_AUTO_ATN; 2195 sc->sc_msgoutidx++; 2196 } 2197 2198 /* Send Message Out */ 2199 njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]); 2200 2201 /* DBn -> +ACK: need 55ns delay? */ 2202 2203 njsc32_assert_ack(sc); 2204 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2205 2206 /* restart AutoSCSI */ 2207 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2208 2209 njsc32_negate_ack(sc); 2210 2211 /* 2212 * do not reset sc->sc_msgoutlen so the target 2213 * can retry Message Out phase 2214 */ 2215 } 2216 2217 static void 2218 njsc32_cmdtimeout(void *arg) 2219 { 2220 struct njsc32_cmd *cmd = arg; 2221 struct njsc32_softc *sc; 2222 int s; 2223 2224 PRINTC(cmd, ("command timeout\n")); 2225 2226 sc = cmd->c_sc; 2227 2228 s = splbio(); 2229 2230 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2231 njsc32_arbitration_failed(sc); 2232 else { 2233 sc->sc_curcmd = NULL; 2234 sc->sc_stat = NJSC32_STAT_IDLE; 2235 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2236 } 2237 2238 /* XXX? */ 2239 njsc32_init(sc, 1); /* bus reset */ 2240 2241 splx(s); 2242 } 2243 2244 static void 2245 njsc32_reseltimeout(void *arg) 2246 { 2247 struct njsc32_cmd *cmd = arg; 2248 struct njsc32_softc *sc; 2249 int s; 2250 2251 PRINTC(cmd, ("reselection timeout\n")); 2252 2253 sc = cmd->c_sc; 2254 2255 s = splbio(); 2256 2257 /* remove from disconnected list */ 2258 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2259 /* I_T_L_Q */ 2260 KASSERT(cmd->c_lu->lu_cmd == NULL); 2261 TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q); 2262 } else { 2263 /* I_T_L */ 2264 KASSERT(cmd->c_lu->lu_cmd == cmd); 2265 cmd->c_lu->lu_cmd = NULL; 2266 } 2267 2268 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2269 2270 /* XXX? */ 2271 njsc32_init(sc, 1); /* bus reset */ 2272 2273 splx(s); 2274 } 2275 2276 static inline void 2277 njsc32_end_auto(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int auto_phase) 2278 { 2279 struct scsipi_xfer *xs; 2280 2281 if (auto_phase & NJSC32_XPHASE_MSGIN_02) { 2282 /* Message In: 0x02 Save Data Pointer */ 2283 2284 /* 2285 * Adjust saved data pointer 2286 * if the command is not completed yet. 2287 */ 2288 if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 && 2289 (auto_phase & 2290 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) { 2291 njsc32_save_ptr(cmd); 2292 } 2293 TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2294 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2295 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2296 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2297 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT))); 2298 } 2299 2300 xs = cmd->c_xs; 2301 2302 if (auto_phase & NJSC32_XPHASE_MSGIN_00) { 2303 /* Command Complete */ 2304 TPRINTC(cmd, ("njsc32_intr: Command Complete\n")); 2305 switch (xs->status) { 2306 case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY: 2307 /* 2308 * scsipi layer will automatically handle the error 2309 */ 2310 njsc32_end_cmd(sc, cmd, XS_BUSY); 2311 break; 2312 default: 2313 xs->resid -= cmd->c_dp_max; 2314 njsc32_end_cmd(sc, cmd, XS_NOERROR); 2315 break; 2316 } 2317 } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) { 2318 /* Disconnect */ 2319 TPRINTC(cmd, ("njsc32_intr: Disconnect\n")); 2320 2321 /* for ill-designed devices */ 2322 if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0) 2323 njsc32_save_ptr(cmd); 2324 2325 /* 2326 * move current cmd to disconnected list 2327 */ 2328 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2329 /* I_T_L_Q */ 2330 if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD) 2331 TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q); 2332 else 2333 TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q); 2334 } else { 2335 /* I_T_L */ 2336 cmd->c_lu->lu_cmd = cmd; 2337 } 2338 2339 /* 2340 * schedule timeout -- avoid being 2341 * disconnected forever 2342 */ 2343 if ((xs->xs_control & XS_CTL_POLL) == 0) { 2344 callout_stop(&xs->xs_callout); 2345 callout_reset(&xs->xs_callout, mstohz(xs->timeout), 2346 njsc32_reseltimeout, cmd); 2347 } 2348 2349 } else { 2350 /* 2351 * target has come to Bus Free phase 2352 * probably to notify an error 2353 */ 2354 PRINTC(cmd, ("njsc32_intr: unexpected bus free\n")); 2355 /* try Request Sense */ 2356 xs->status = SCSI_CHECK; 2357 njsc32_end_cmd(sc, cmd, XS_BUSY); 2358 } 2359 } 2360 2361 int 2362 njsc32_intr(void *arg) 2363 { 2364 struct njsc32_softc *sc = arg; 2365 u_int16_t intr; 2366 u_int8_t arbstat, bus_phase; 2367 int auto_phase; 2368 int idbit; 2369 struct njsc32_cmd *cmd; 2370 2371 intr = njsc32_read_2(sc, NJSC32_REG_IRQ); 2372 if ((intr & NJSC32_IRQ_INTR_PENDING) == 0) 2373 return 0; /* not mine */ 2374 2375 TPRINTF(("%s: njsc32_intr: %#x\n", device_xname(sc->sc_dev), intr)); 2376 2377 #if 0 /* I don't think this is required */ 2378 /* mask interrupts */ 2379 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 2380 #endif 2381 2382 /* we got an interrupt, so stop the timer */ 2383 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 2384 2385 if (intr & NJSC32_IRQ_SCSIRESET) { 2386 printf("%s: detected bus reset\n", device_xname(sc->sc_dev)); 2387 /* make sure all devices on the bus are certainly reset */ 2388 njsc32_reset_bus(sc); 2389 goto out; 2390 } 2391 2392 if (sc->sc_stat == NJSC32_STAT_ARBIT) { 2393 cmd = sc->sc_curcmd; 2394 KASSERT(cmd); 2395 arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT); 2396 if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) { 2397 /* 2398 * arbitration done 2399 */ 2400 /* clear arbitration status */ 2401 njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION, 2402 NJSC32_SETARB_CLEAR); 2403 2404 if (arbstat & NJSC32_ARBSTAT_WIN) { 2405 TPRINTC(cmd, 2406 ("njsc32_intr: arbitration won\n")); 2407 2408 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 2409 2410 sc->sc_stat = NJSC32_STAT_CONNECT; 2411 } else { 2412 TPRINTC(cmd, 2413 ("njsc32_intr: arbitration failed\n")); 2414 2415 njsc32_arbitration_failed(sc); 2416 2417 /* XXX delay */ 2418 /* XXX retry counter */ 2419 } 2420 } 2421 } 2422 2423 if (intr & NJSC32_IRQ_TIMER) { 2424 TPRINTF(("%s: njsc32_intr: timer interrupt\n", 2425 device_xname(sc->sc_dev))); 2426 } 2427 2428 if (intr & NJSC32_IRQ_RESELECT) { 2429 /* Reselection from a target */ 2430 njsc32_arbitration_failed(sc); /* just in case */ 2431 if ((cmd = sc->sc_curcmd) != NULL) { 2432 /* ? */ 2433 printf("%s: unexpected reselection\n", 2434 device_xname(sc->sc_dev)); 2435 sc->sc_curcmd = NULL; 2436 sc->sc_stat = NJSC32_STAT_IDLE; 2437 njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP); 2438 } 2439 2440 idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID); 2441 if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 || 2442 (sc->sc_reselid = 2443 ffs(idbit & ~(1 << NJSC32_INITIATOR_ID)) - 1) < 0) { 2444 printf("%s: invalid reselection (id: %#x)\n", 2445 device_xname(sc->sc_dev), idbit); 2446 sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */ 2447 } else { 2448 sc->sc_stat = NJSC32_STAT_RESEL; 2449 TPRINTF(("%s: njsc32_intr: reselection from %d\n", 2450 device_xname(sc->sc_dev), sc->sc_reselid)); 2451 } 2452 } 2453 2454 if (intr & NJSC32_IRQ_PHASE_CHANGE) { 2455 #if 1 /* XXX probably not needed */ 2456 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2457 PRINTC(sc->sc_curcmd, 2458 ("njsc32_intr: cancel arbitration phase\n")); 2459 njsc32_arbitration_failed(sc); 2460 #endif 2461 /* current bus phase */ 2462 bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 2463 NJSC32_BUSMON_PHASE_MASK; 2464 2465 switch (bus_phase) { 2466 case NJSC32_PHASE_MESSAGE_IN: 2467 njsc32_msgin(sc); 2468 break; 2469 2470 /* 2471 * target may suddenly become Status / Bus Free phase 2472 * to notify an error condition 2473 */ 2474 case NJSC32_PHASE_STATUS: 2475 printf("%s: unexpected bus phase: Status\n", 2476 device_xname(sc->sc_dev)); 2477 if ((cmd = sc->sc_curcmd) != NULL) { 2478 cmd->c_xs->status = 2479 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2480 TPRINTC(cmd, ("njsc32_intr: Status %d\n", 2481 cmd->c_xs->status)); 2482 } 2483 break; 2484 case NJSC32_PHASE_BUSFREE: 2485 printf("%s: unexpected bus phase: Bus Free\n", 2486 device_xname(sc->sc_dev)); 2487 if ((cmd = sc->sc_curcmd) != NULL) { 2488 sc->sc_curcmd = NULL; 2489 sc->sc_stat = NJSC32_STAT_IDLE; 2490 if (cmd->c_xs->status != SCSI_QUEUE_FULL && 2491 cmd->c_xs->status != SCSI_BUSY) 2492 cmd->c_xs->status = SCSI_CHECK;/* XXX */ 2493 njsc32_end_cmd(sc, cmd, XS_BUSY); 2494 } 2495 goto out; 2496 default: 2497 #ifdef NJSC32_DEBUG 2498 printf("%s: unexpected bus phase: ", 2499 device_xname(sc->sc_dev)); 2500 switch (bus_phase) { 2501 case NJSC32_PHASE_COMMAND: 2502 printf("Command\n"); 2503 break; 2504 case NJSC32_PHASE_MESSAGE_OUT: 2505 printf("Message Out\n"); 2506 break; 2507 case NJSC32_PHASE_DATA_IN: 2508 printf("Data In\n"); 2509 break; 2510 case NJSC32_PHASE_DATA_OUT: 2511 printf("Data Out\n"); 2512 break; 2513 case NJSC32_PHASE_RESELECT: 2514 printf("Reselect\n"); 2515 break; 2516 default: 2517 printf("%#x\n", bus_phase); 2518 break; 2519 } 2520 #else 2521 printf("%s: unexpected bus phase: %#x", 2522 device_xname(sc->sc_dev), bus_phase); 2523 #endif 2524 break; 2525 } 2526 } 2527 2528 if (intr & NJSC32_IRQ_AUTOSCSI) { 2529 /* 2530 * AutoSCSI interrupt 2531 */ 2532 auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE); 2533 TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n", 2534 device_xname(sc->sc_dev), auto_phase)); 2535 njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0); 2536 2537 if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) { 2538 cmd = sc->sc_curcmd; 2539 if (cmd == NULL) { 2540 printf("%s: sel no cmd\n", 2541 device_xname(sc->sc_dev)); 2542 goto out; 2543 } 2544 DPRINTC(cmd, ("njsc32_intr: selection timeout\n")); 2545 2546 sc->sc_curcmd = NULL; 2547 sc->sc_stat = NJSC32_STAT_IDLE; 2548 njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT); 2549 2550 goto out; 2551 } 2552 2553 #ifdef NJSC32_TRACE 2554 if (auto_phase & NJSC32_XPHASE_COMMAND) { 2555 /* Command phase has been automatically processed */ 2556 TPRINTF(("%s: njsc32_intr: Command\n", 2557 device_xname(sc->sc_dev))); 2558 } 2559 #endif 2560 #ifdef NJSC32_DEBUG 2561 if (auto_phase & NJSC32_XPHASE_ILLEGAL) { 2562 printf("%s: njsc32_intr: Illegal phase\n", 2563 device_xname(sc->sc_dev)); 2564 } 2565 #endif 2566 2567 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) { 2568 TPRINTF(("%s: njsc32_intr: Process Message In\n", 2569 device_xname(sc->sc_dev))); 2570 njsc32_msgin(sc); 2571 } 2572 2573 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) { 2574 TPRINTF(("%s: njsc32_intr: Process Message Out\n", 2575 device_xname(sc->sc_dev))); 2576 njsc32_msgout(sc); 2577 } 2578 2579 cmd = sc->sc_curcmd; 2580 if (cmd == NULL) { 2581 TPRINTF(("%s: njsc32_intr: no cmd\n", 2582 device_xname(sc->sc_dev))); 2583 goto out; 2584 } 2585 2586 if (auto_phase & 2587 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) { 2588 u_int32_t sackcnt, cntoffset; 2589 2590 #ifdef NJSC32_TRACE 2591 if (auto_phase & NJSC32_XPHASE_DATA_IN) 2592 PRINTC(cmd, ("njsc32_intr: data in done\n")); 2593 if (auto_phase & NJSC32_XPHASE_DATA_OUT) 2594 PRINTC(cmd, ("njsc32_intr: data out done\n")); 2595 printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2596 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2597 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2598 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2599 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)); 2600 #endif 2601 2602 /* 2603 * detected parity error on data transfer? 2604 */ 2605 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 2606 (NJSC32_PARITYSTATUS_ERROR_LSB| 2607 NJSC32_PARITYSTATUS_ERROR_MSB)) { 2608 2609 PRINTC(cmd, ("datain: parity error\n")); 2610 2611 /* clear parity error */ 2612 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 2613 NJSC32_PARITYCTL_CHECK_ENABLE | 2614 NJSC32_PARITYCTL_CLEAR_ERROR); 2615 2616 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2617 /* 2618 * XXX command has already finished 2619 * -- what can we do? 2620 * 2621 * It is not clear current command 2622 * caused the error -- reset everything. 2623 */ 2624 njsc32_init(sc, 1); /* XXX */ 2625 } else { 2626 /* XXX does this case occur? */ 2627 #if 1 2628 printf("%s: datain: parity error\n", 2629 device_xname(sc->sc_dev)); 2630 #endif 2631 /* 2632 * Make attention condition and try 2633 * to send Initiator Detected Error 2634 * message. 2635 */ 2636 njsc32_init_msgout(sc); 2637 njsc32_add_msgout(sc, 2638 MSG_INITIATOR_DET_ERR); 2639 njsc32_write_4(sc, 2640 NJSC32_REG_SCSI_MSG_OUT, 2641 njsc32_get_auto_msgout(sc)); 2642 /* restart autoscsi with ATN */ 2643 njsc32_write_2(sc, 2644 NJSC32_REG_COMMAND_CONTROL, 2645 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2646 NJSC32_CMD_AUTO_COMMAND_PHASE | 2647 NJSC32_CMD_AUTO_SCSI_RESTART | 2648 NJSC32_CMD_AUTO_MSGIN_00_04 | 2649 NJSC32_CMD_AUTO_MSGIN_02 | 2650 NJSC32_CMD_AUTO_ATN); 2651 } 2652 goto out; 2653 } 2654 2655 /* 2656 * data has been transferred, and current pointer 2657 * is changed 2658 */ 2659 sackcnt = njsc32_read_4(sc, NJSC32_REG_SACK_CNT); 2660 2661 /* 2662 * The controller returns extra ACK count 2663 * if the DMA buffer is not 4byte aligned. 2664 */ 2665 cntoffset = le32toh(cmd->c_sgt[0].sg_addr) & 3; 2666 #ifdef NJSC32_DEBUG 2667 if (cntoffset != 0) { 2668 printf("sackcnt %u, cntoffset %u\n", 2669 sackcnt, cntoffset); 2670 } 2671 #endif 2672 /* advance SCSI pointer */ 2673 njsc32_set_cur_ptr(cmd, 2674 cmd->c_dp_cur + sackcnt - cntoffset); 2675 } 2676 2677 if (auto_phase & NJSC32_XPHASE_MSGOUT) { 2678 /* Message Out phase has been automatically processed */ 2679 TPRINTC(cmd, ("njsc32_intr: Message Out\n")); 2680 if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 && 2681 sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) { 2682 njsc32_init_msgout(sc); 2683 } 2684 } 2685 2686 if (auto_phase & NJSC32_XPHASE_STATUS) { 2687 /* Status phase has been automatically processed */ 2688 cmd->c_xs->status = 2689 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2690 TPRINTC(cmd, ("njsc32_intr: Status %#x\n", 2691 cmd->c_xs->status)); 2692 } 2693 2694 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2695 /* AutoSCSI is finished */ 2696 2697 TPRINTC(cmd, ("njsc32_intr: Bus Free\n")); 2698 2699 sc->sc_stat = NJSC32_STAT_IDLE; 2700 sc->sc_curcmd = NULL; 2701 2702 njsc32_end_auto(sc, cmd, auto_phase); 2703 } 2704 goto out; 2705 } 2706 2707 if (intr & NJSC32_IRQ_FIFO_THRESHOLD) { 2708 /* XXX We use DMA, and this shouldn't happen */ 2709 printf("%s: njsc32_intr: FIFO\n", device_xname(sc->sc_dev)); 2710 njsc32_init(sc, 1); 2711 goto out; 2712 } 2713 if (intr & NJSC32_IRQ_PCI) { 2714 /* XXX? */ 2715 printf("%s: njsc32_intr: PCI\n", device_xname(sc->sc_dev)); 2716 } 2717 if (intr & NJSC32_IRQ_BMCNTERR) { 2718 /* XXX? */ 2719 printf("%s: njsc32_intr: BM\n", device_xname(sc->sc_dev)); 2720 } 2721 2722 out: 2723 /* go next command if controller is idle */ 2724 if (sc->sc_stat == NJSC32_STAT_IDLE) 2725 njsc32_start(sc); 2726 2727 #if 0 2728 /* enable interrupts */ 2729 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 2730 #endif 2731 2732 return 1; /* processed */ 2733 } 2734
Indexes created Mon Sep 29 21:09:56 GMT 2025