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nslm7xvar.h revision 1.25.6.1
      1  1.25.6.1     haad /*	$NetBSD: nslm7xvar.h,v 1.25.6.1 2008/10/19 22:16:27 haad Exp $ */
      2       1.1     groo 
      3       1.1     groo /*-
      4       1.1     groo  * Copyright (c) 2000 The NetBSD Foundation, Inc.
      5       1.1     groo  * All rights reserved.
      6       1.1     groo  *
      7       1.1     groo  * This code is derived from software contributed to The NetBSD Foundation
      8       1.1     groo  * by Bill Squier.
      9       1.1     groo  *
     10       1.1     groo  * Redistribution and use in source and binary forms, with or without
     11       1.1     groo  * modification, are permitted provided that the following conditions
     12       1.1     groo  * are met:
     13       1.1     groo  * 1. Redistributions of source code must retain the above copyright
     14       1.1     groo  *    notice, this list of conditions and the following disclaimer.
     15       1.1     groo  * 2. Redistributions in binary form must reproduce the above copyright
     16       1.1     groo  *    notice, this list of conditions and the following disclaimer in the
     17       1.1     groo  *    documentation and/or other materials provided with the distribution.
     18       1.1     groo  *
     19       1.1     groo  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20       1.1     groo  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21       1.1     groo  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22       1.1     groo  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23       1.1     groo  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24       1.1     groo  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25       1.1     groo  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26       1.1     groo  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27       1.1     groo  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28       1.1     groo  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29       1.1     groo  * POSSIBILITY OF SUCH DAMAGE.
     30       1.1     groo  */
     31       1.1     groo 
     32       1.1     groo #ifndef _DEV_ISA_NSLM7XVAR_H_
     33       1.1     groo #define _DEV_ISA_NSLM7XVAR_H_
     34       1.1     groo 
     35      1.19  xtraeme /*
     36      1.19  xtraeme  * National Semiconductor LM78/79/81 registers.
     37      1.19  xtraeme  */
     38      1.19  xtraeme 
     39      1.19  xtraeme /* Control registers */
     40       1.1     groo 
     41       1.1     groo #define LMC_ADDR	0x05
     42       1.1     groo #define LMC_DATA	0x06
     43       1.1     groo 
     44      1.19  xtraeme /* Data registers */
     45       1.1     groo 
     46      1.19  xtraeme #define LMD_POST_RAM	0x00	/* POST RAM occupies 0x00 -- 0x1f */
     47      1.19  xtraeme #define LMD_VALUE_RAM	0x20	/* Value RAM occupies 0x20 -- 0x3f */
     48      1.19  xtraeme #define LMD_FAN1	0x28	/* FAN1 reading */
     49      1.19  xtraeme #define LMD_FAN2	0x29	/* FAN2 reading */
     50      1.19  xtraeme #define LMD_FAN3	0x2a	/* FAN3 reading */
     51       1.1     groo 
     52      1.14    perry #define LMD_CONFIG	0x40	/* Configuration */
     53       1.1     groo #define LMD_ISR1	0x41	/* Interrupt Status 1 */
     54       1.1     groo #define LMD_ISR2	0x42	/* Interrupt Status 2 */
     55       1.1     groo #define LMD_SMI1	0x43	/* SMI Mask 1 */
     56       1.1     groo #define LMD_SMI2	0x44	/* SMI Mask 2 */
     57       1.1     groo #define LMD_NMI1	0x45	/* NMI Mask 1 */
     58       1.1     groo #define LMD_NMI2	0x46	/* NMI Mask 2 */
     59       1.1     groo #define LMD_VIDFAN	0x47	/* VID/Fan Divisor */
     60       1.1     groo #define LMD_SBUSADDR	0x48	/* Serial Bus Address */
     61       1.1     groo #define LMD_CHIPID	0x49	/* Chip Reset/ID */
     62       1.1     groo 
     63      1.19  xtraeme /* Chip IDs */
     64       1.1     groo 
     65       1.1     groo #define LM_NUM_SENSORS	11
     66       1.1     groo #define LM_ID_LM78	0x00
     67       1.1     groo #define LM_ID_LM78J	0x40
     68       1.1     groo #define LM_ID_LM79	0xC0
     69       1.8   bouyer #define LM_ID_LM81	0x80
     70       1.1     groo #define LM_ID_MASK	0xFE
     71       1.1     groo 
     72      1.19  xtraeme 
     73       1.5   bouyer /*
     74      1.19  xtraeme  * Winbond registers
     75      1.19  xtraeme  *
     76      1.19  xtraeme  * Several models exists.  The W83781D is mostly compatible with the
     77      1.19  xtraeme  * LM78, but has two extra temperatures.  Later models add extra
     78      1.19  xtraeme  * voltage sensors, fans and bigger fan divisors to accomodate slow
     79      1.19  xtraeme  * running fans.  To accomodate the extra sensors some models have
     80      1.19  xtraeme  * different memory banks.
     81       1.5   bouyer  */
     82      1.19  xtraeme 
     83      1.19  xtraeme #define WB_T23ADDR	0x4a	/* Temperature 2 and 3 Serial Bus Address */
     84      1.19  xtraeme #define WB_PIN		0x4b	/* Pin Control */
     85      1.19  xtraeme #define WB_BANKSEL	0x4e	/* Bank Select */
     86      1.19  xtraeme #define WB_VENDID	0x4f	/* Vendor ID */
     87      1.19  xtraeme 
     88      1.19  xtraeme /* Bank 0 regs */
     89      1.19  xtraeme #define WB_BANK0_CHIPID	0x58	/* Chip ID */
     90      1.19  xtraeme #define WB_BANK0_FAN45	0x5c	/* Fan 4/5 Divisor Control (W83791D only) */
     91      1.19  xtraeme #define WB_BANK0_VBAT	0x5d	/* VBAT Monitor Control */
     92      1.19  xtraeme #define WB_BANK0_FAN4	0xba	/* Fan 4 reading (W83791D only) */
     93      1.19  xtraeme #define WB_BANK0_FAN5	0xbb	/* Fan 5 reading (W83791D only) */
     94      1.19  xtraeme 
     95      1.19  xtraeme #define WB_BANK0_CONFIG	0x18	/* VRM & OVT Config (W83627THF/W83637HF) */
     96      1.19  xtraeme 
     97      1.19  xtraeme /* Bank 1 registers */
     98      1.19  xtraeme #define WB_BANK1_T2H	0x50	/* Temperature 2 High Byte */
     99      1.19  xtraeme #define WB_BANK1_T2L	0x51	/* Temperature 2 Low Byte */
    100      1.19  xtraeme 
    101      1.19  xtraeme /* Bank 2 registers */
    102      1.19  xtraeme #define WB_BANK2_T3H	0x50	/* Temperature 3 High Byte */
    103      1.19  xtraeme #define WB_BANK2_T3L	0x51	/* Temperature 3 Low Byte */
    104      1.19  xtraeme 
    105      1.19  xtraeme /* Bank 4 registers (W83782D/W83627HF and later models only) */
    106      1.19  xtraeme #define WB_BANK4_T1OFF	0x54	/* Temperature 1 Offset */
    107      1.19  xtraeme #define WB_BANK4_T2OFF	0x55	/* Temperature 2 Offset */
    108      1.19  xtraeme #define WB_BANK4_T3OFF	0x56	/* Temperature 3 Offset */
    109      1.19  xtraeme 
    110      1.19  xtraeme /* Bank 5 registers (W83782D/W83627HF and later models only) */
    111      1.19  xtraeme #define WB_BANK5_5VSB	0x50	/* 5VSB reading */
    112      1.19  xtraeme #define WB_BANK5_VBAT	0x51	/* VBAT reading */
    113      1.19  xtraeme 
    114      1.19  xtraeme /* Bank selection */
    115      1.19  xtraeme #define WB_BANKSEL_B0	0x00	/* Bank 0 */
    116      1.19  xtraeme #define WB_BANKSEL_B1	0x01	/* Bank 1 */
    117      1.19  xtraeme #define WB_BANKSEL_B2	0x02	/* Bank 2 */
    118      1.19  xtraeme #define WB_BANKSEL_B3	0x03	/* Bank 3 */
    119      1.19  xtraeme #define WB_BANKSEL_B4	0x04	/* Bank 4 */
    120      1.19  xtraeme #define WB_BANKSEL_B5	0x05	/* Bank 5 */
    121      1.19  xtraeme #define WB_BANKSEL_HBAC	0x80	/* Register 0x4f High Byte Access */
    122      1.19  xtraeme 
    123      1.19  xtraeme /* Vendor IDs */
    124      1.19  xtraeme #define WB_VENDID_WINBOND	0x5ca3	/* Winbond */
    125      1.19  xtraeme #define WB_VENDID_ASUS		0x12c3	/* ASUS */
    126      1.19  xtraeme 
    127      1.19  xtraeme /* Chip IDs */
    128      1.19  xtraeme #define WB_CHIPID_W83781D	0x10
    129      1.19  xtraeme #define WB_CHIPID_W83781D_2	0x11
    130      1.19  xtraeme #define WB_CHIPID_W83627HF	0x21
    131      1.19  xtraeme #define WB_CHIPID_AS99127F	0x31	/* Asus W83781D clone */
    132      1.19  xtraeme #define WB_CHIPID_W83782D	0x30
    133      1.19  xtraeme #define WB_CHIPID_W83783S	0x40
    134      1.19  xtraeme #define WB_CHIPID_W83697HF	0x60
    135      1.19  xtraeme #define WB_CHIPID_W83791D	0x71
    136      1.19  xtraeme #define WB_CHIPID_W83791SD	0x72
    137      1.19  xtraeme #define WB_CHIPID_W83792D	0x7a
    138      1.19  xtraeme #define WB_CHIPID_W83637HF	0x80
    139      1.21  xtraeme #define WB_CHIPID_W83627EHF_A	0x88 /* early version, only for ASUS MBs */
    140      1.19  xtraeme #define WB_CHIPID_W83627THF	0x90
    141      1.19  xtraeme #define WB_CHIPID_W83627EHF	0xa1
    142      1.19  xtraeme #define WB_CHIPID_W83627DHG	0xc1
    143      1.19  xtraeme 
    144      1.19  xtraeme /* Config bits */
    145      1.19  xtraeme #define WB_CONFIG_VMR9		0x01
    146      1.19  xtraeme 
    147      1.19  xtraeme /* Reference voltage (mV) */
    148      1.19  xtraeme #define WB_VREF			3600
    149      1.19  xtraeme #define WB_W83627EHF_VREF	2048
    150      1.19  xtraeme 
    151      1.19  xtraeme #define WB_MAX_SENSORS		19
    152       1.4   bouyer 
    153       1.1     groo struct lm_softc {
    154      1.24  xtraeme 	device_t sc_dev;
    155       1.1     groo 
    156      1.22  xtraeme 	callout_t sc_callout;
    157      1.19  xtraeme 
    158      1.20  xtraeme 	envsys_data_t sensors[WB_MAX_SENSORS];
    159      1.23  xtraeme 	struct sysmon_envsys *sc_sme;
    160      1.19  xtraeme 	uint8_t numsensors;
    161      1.19  xtraeme 
    162      1.22  xtraeme 	void (*refresh_sensor_data)(struct lm_softc *);
    163      1.10       ad 
    164      1.19  xtraeme 	uint8_t (*lm_readreg)(struct lm_softc *, int);
    165      1.10       ad 	void (*lm_writereg)(struct lm_softc *, int, int);
    166       1.3  thorpej 
    167      1.19  xtraeme 	struct lm_sensor *lm_sensors;
    168      1.19  xtraeme 	uint8_t	chipid;
    169      1.19  xtraeme 	uint8_t	vrm9;
    170      1.19  xtraeme };
    171      1.19  xtraeme 
    172      1.19  xtraeme struct lm_sensor {
    173      1.19  xtraeme 	const char *desc;
    174      1.19  xtraeme 	enum envsys_units type;
    175      1.19  xtraeme 	uint8_t bank;
    176      1.19  xtraeme 	uint8_t reg;
    177      1.19  xtraeme 	void (*refresh)(struct lm_softc *, int);
    178      1.19  xtraeme 	int rfact;
    179       1.1     groo };
    180       1.1     groo 
    181      1.22  xtraeme void 	lm_attach(struct lm_softc *);
    182      1.22  xtraeme void	lm_detach(struct lm_softc *);
    183  1.25.6.1     haad int 	lm_probe(struct lm_softc *);
    184       1.1     groo 
    185       1.1     groo #endif /* _DEV_ISA_NSLM7XVAR_H_ */
    186