nvme.c revision 1.41
1 /* $NetBSD: nvme.c,v 1.41 2018/12/01 15:07:58 jdolecek Exp $ */ 2 /* $OpenBSD: nvme.c,v 1.49 2016/04/18 05:59:50 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2014 David Gwynne <dlg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __KERNEL_RCSID(0, "$NetBSD: nvme.c,v 1.41 2018/12/01 15:07:58 jdolecek Exp $"); 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/kernel.h> 26 #include <sys/atomic.h> 27 #include <sys/bus.h> 28 #include <sys/buf.h> 29 #include <sys/conf.h> 30 #include <sys/device.h> 31 #include <sys/kmem.h> 32 #include <sys/once.h> 33 #include <sys/proc.h> 34 #include <sys/queue.h> 35 #include <sys/mutex.h> 36 37 #include <uvm/uvm_extern.h> 38 39 #include <dev/ic/nvmereg.h> 40 #include <dev/ic/nvmevar.h> 41 #include <dev/ic/nvmeio.h> 42 43 #include "ioconf.h" 44 45 #define B4_CHK_RDY_DELAY_MS 2300 /* workaround controller bug */ 46 47 int nvme_adminq_size = 32; 48 int nvme_ioq_size = 1024; 49 50 static int nvme_print(void *, const char *); 51 52 static int nvme_ready(struct nvme_softc *, uint32_t); 53 static int nvme_enable(struct nvme_softc *, u_int); 54 static int nvme_disable(struct nvme_softc *); 55 static int nvme_shutdown(struct nvme_softc *); 56 57 #ifdef NVME_DEBUG 58 static void nvme_dumpregs(struct nvme_softc *); 59 #endif 60 static int nvme_identify(struct nvme_softc *, u_int); 61 static void nvme_fill_identify(struct nvme_queue *, struct nvme_ccb *, 62 void *); 63 64 static int nvme_ccbs_alloc(struct nvme_queue *, uint16_t); 65 static void nvme_ccbs_free(struct nvme_queue *); 66 67 static struct nvme_ccb * 68 nvme_ccb_get(struct nvme_queue *, bool); 69 static void nvme_ccb_put(struct nvme_queue *, struct nvme_ccb *); 70 71 static int nvme_poll(struct nvme_softc *, struct nvme_queue *, 72 struct nvme_ccb *, void (*)(struct nvme_queue *, 73 struct nvme_ccb *, void *), int); 74 static void nvme_poll_fill(struct nvme_queue *, struct nvme_ccb *, void *); 75 static void nvme_poll_done(struct nvme_queue *, struct nvme_ccb *, 76 struct nvme_cqe *); 77 static void nvme_sqe_fill(struct nvme_queue *, struct nvme_ccb *, void *); 78 static void nvme_empty_done(struct nvme_queue *, struct nvme_ccb *, 79 struct nvme_cqe *); 80 81 static struct nvme_queue * 82 nvme_q_alloc(struct nvme_softc *, uint16_t, u_int, u_int); 83 static int nvme_q_create(struct nvme_softc *, struct nvme_queue *); 84 static int nvme_q_delete(struct nvme_softc *, struct nvme_queue *); 85 static void nvme_q_submit(struct nvme_softc *, struct nvme_queue *, 86 struct nvme_ccb *, void (*)(struct nvme_queue *, 87 struct nvme_ccb *, void *)); 88 static int nvme_q_complete(struct nvme_softc *, struct nvme_queue *q); 89 static void nvme_q_free(struct nvme_softc *, struct nvme_queue *); 90 static void nvme_q_wait_complete(struct nvme_softc *, struct nvme_queue *, 91 bool (*)(void *), void *); 92 93 static struct nvme_dmamem * 94 nvme_dmamem_alloc(struct nvme_softc *, size_t); 95 static void nvme_dmamem_free(struct nvme_softc *, struct nvme_dmamem *); 96 static void nvme_dmamem_sync(struct nvme_softc *, struct nvme_dmamem *, 97 int); 98 99 static void nvme_ns_io_fill(struct nvme_queue *, struct nvme_ccb *, 100 void *); 101 static void nvme_ns_io_done(struct nvme_queue *, struct nvme_ccb *, 102 struct nvme_cqe *); 103 static void nvme_ns_sync_fill(struct nvme_queue *, struct nvme_ccb *, 104 void *); 105 static void nvme_ns_sync_done(struct nvme_queue *, struct nvme_ccb *, 106 struct nvme_cqe *); 107 static void nvme_getcache_fill(struct nvme_queue *, struct nvme_ccb *, 108 void *); 109 static void nvme_getcache_done(struct nvme_queue *, struct nvme_ccb *, 110 struct nvme_cqe *); 111 112 static void nvme_pt_fill(struct nvme_queue *, struct nvme_ccb *, 113 void *); 114 static void nvme_pt_done(struct nvme_queue *, struct nvme_ccb *, 115 struct nvme_cqe *); 116 static int nvme_command_passthrough(struct nvme_softc *, 117 struct nvme_pt_command *, uint16_t, struct lwp *, bool); 118 119 static int nvme_get_number_of_queues(struct nvme_softc *, u_int *); 120 121 #define NVME_TIMO_QOP 5 /* queue create and delete timeout */ 122 #define NVME_TIMO_IDENT 10 /* probe identify timeout */ 123 #define NVME_TIMO_PT -1 /* passthrough cmd timeout */ 124 #define NVME_TIMO_SY 60 /* sync cache timeout */ 125 126 #define nvme_read4(_s, _r) \ 127 bus_space_read_4((_s)->sc_iot, (_s)->sc_ioh, (_r)) 128 #define nvme_write4(_s, _r, _v) \ 129 bus_space_write_4((_s)->sc_iot, (_s)->sc_ioh, (_r), (_v)) 130 /* 131 * Some controllers, at least Apple NVMe, always require split 132 * transfers, so don't use bus_space_{read,write}_8() on LP64. 133 */ 134 static inline uint64_t 135 nvme_read8(struct nvme_softc *sc, bus_size_t r) 136 { 137 uint64_t v; 138 uint32_t *a = (uint32_t *)&v; 139 140 #if _BYTE_ORDER == _LITTLE_ENDIAN 141 a[0] = nvme_read4(sc, r); 142 a[1] = nvme_read4(sc, r + 4); 143 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 144 a[1] = nvme_read4(sc, r); 145 a[0] = nvme_read4(sc, r + 4); 146 #endif 147 148 return v; 149 } 150 151 static inline void 152 nvme_write8(struct nvme_softc *sc, bus_size_t r, uint64_t v) 153 { 154 uint32_t *a = (uint32_t *)&v; 155 156 #if _BYTE_ORDER == _LITTLE_ENDIAN 157 nvme_write4(sc, r, a[0]); 158 nvme_write4(sc, r + 4, a[1]); 159 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 160 nvme_write4(sc, r, a[1]); 161 nvme_write4(sc, r + 4, a[0]); 162 #endif 163 } 164 #define nvme_barrier(_s, _r, _l, _f) \ 165 bus_space_barrier((_s)->sc_iot, (_s)->sc_ioh, (_r), (_l), (_f)) 166 167 #ifdef NVME_DEBUG 168 static __used void 169 nvme_dumpregs(struct nvme_softc *sc) 170 { 171 uint64_t r8; 172 uint32_t r4; 173 174 #define DEVNAME(_sc) device_xname((_sc)->sc_dev) 175 r8 = nvme_read8(sc, NVME_CAP); 176 printf("%s: cap 0x%016"PRIx64"\n", DEVNAME(sc), nvme_read8(sc, NVME_CAP)); 177 printf("%s: mpsmax %u (%u)\n", DEVNAME(sc), 178 (u_int)NVME_CAP_MPSMAX(r8), (1 << NVME_CAP_MPSMAX(r8))); 179 printf("%s: mpsmin %u (%u)\n", DEVNAME(sc), 180 (u_int)NVME_CAP_MPSMIN(r8), (1 << NVME_CAP_MPSMIN(r8))); 181 printf("%s: css %"PRIu64"\n", DEVNAME(sc), NVME_CAP_CSS(r8)); 182 printf("%s: nssrs %"PRIu64"\n", DEVNAME(sc), NVME_CAP_NSSRS(r8)); 183 printf("%s: dstrd %"PRIu64"\n", DEVNAME(sc), NVME_CAP_DSTRD(r8)); 184 printf("%s: to %"PRIu64" msec\n", DEVNAME(sc), NVME_CAP_TO(r8)); 185 printf("%s: ams %"PRIu64"\n", DEVNAME(sc), NVME_CAP_AMS(r8)); 186 printf("%s: cqr %"PRIu64"\n", DEVNAME(sc), NVME_CAP_CQR(r8)); 187 printf("%s: mqes %"PRIu64"\n", DEVNAME(sc), NVME_CAP_MQES(r8)); 188 189 printf("%s: vs 0x%04x\n", DEVNAME(sc), nvme_read4(sc, NVME_VS)); 190 191 r4 = nvme_read4(sc, NVME_CC); 192 printf("%s: cc 0x%04x\n", DEVNAME(sc), r4); 193 printf("%s: iocqes %u (%u)\n", DEVNAME(sc), NVME_CC_IOCQES_R(r4), 194 (1 << NVME_CC_IOCQES_R(r4))); 195 printf("%s: iosqes %u (%u)\n", DEVNAME(sc), NVME_CC_IOSQES_R(r4), 196 (1 << NVME_CC_IOSQES_R(r4))); 197 printf("%s: shn %u\n", DEVNAME(sc), NVME_CC_SHN_R(r4)); 198 printf("%s: ams %u\n", DEVNAME(sc), NVME_CC_AMS_R(r4)); 199 printf("%s: mps %u (%u)\n", DEVNAME(sc), NVME_CC_MPS_R(r4), 200 (1 << NVME_CC_MPS_R(r4))); 201 printf("%s: css %u\n", DEVNAME(sc), NVME_CC_CSS_R(r4)); 202 printf("%s: en %u\n", DEVNAME(sc), ISSET(r4, NVME_CC_EN) ? 1 : 0); 203 204 r4 = nvme_read4(sc, NVME_CSTS); 205 printf("%s: csts 0x%08x\n", DEVNAME(sc), r4); 206 printf("%s: rdy %u\n", DEVNAME(sc), r4 & NVME_CSTS_RDY); 207 printf("%s: cfs %u\n", DEVNAME(sc), r4 & NVME_CSTS_CFS); 208 printf("%s: shst %x\n", DEVNAME(sc), r4 & NVME_CSTS_SHST_MASK); 209 210 r4 = nvme_read4(sc, NVME_AQA); 211 printf("%s: aqa 0x%08x\n", DEVNAME(sc), r4); 212 printf("%s: acqs %u\n", DEVNAME(sc), NVME_AQA_ACQS_R(r4)); 213 printf("%s: asqs %u\n", DEVNAME(sc), NVME_AQA_ASQS_R(r4)); 214 215 printf("%s: asq 0x%016"PRIx64"\n", DEVNAME(sc), nvme_read8(sc, NVME_ASQ)); 216 printf("%s: acq 0x%016"PRIx64"\n", DEVNAME(sc), nvme_read8(sc, NVME_ACQ)); 217 #undef DEVNAME 218 } 219 #endif /* NVME_DEBUG */ 220 221 static int 222 nvme_ready(struct nvme_softc *sc, uint32_t rdy) 223 { 224 u_int i = 0; 225 226 while ((nvme_read4(sc, NVME_CSTS) & NVME_CSTS_RDY) != rdy) { 227 if (i++ > sc->sc_rdy_to) 228 return ENXIO; 229 230 delay(1000); 231 nvme_barrier(sc, NVME_CSTS, 4, BUS_SPACE_BARRIER_READ); 232 } 233 234 return 0; 235 } 236 237 static int 238 nvme_enable(struct nvme_softc *sc, u_int mps) 239 { 240 uint32_t cc, csts; 241 int error; 242 243 cc = nvme_read4(sc, NVME_CC); 244 csts = nvme_read4(sc, NVME_CSTS); 245 246 /* 247 * See note in nvme_disable. Short circuit if we're already enabled. 248 */ 249 if (ISSET(cc, NVME_CC_EN)) { 250 if (ISSET(csts, NVME_CSTS_RDY)) 251 return 0; 252 253 goto waitready; 254 } else { 255 /* EN == 0 already wait for RDY == 0 or fail */ 256 error = nvme_ready(sc, 0); 257 if (error) 258 return error; 259 } 260 261 nvme_write8(sc, NVME_ASQ, NVME_DMA_DVA(sc->sc_admin_q->q_sq_dmamem)); 262 nvme_barrier(sc, 0, sc->sc_ios, BUS_SPACE_BARRIER_WRITE); 263 delay(5000); 264 nvme_write8(sc, NVME_ACQ, NVME_DMA_DVA(sc->sc_admin_q->q_cq_dmamem)); 265 nvme_barrier(sc, 0, sc->sc_ios, BUS_SPACE_BARRIER_WRITE); 266 delay(5000); 267 268 nvme_write4(sc, NVME_AQA, NVME_AQA_ACQS(sc->sc_admin_q->q_entries) | 269 NVME_AQA_ASQS(sc->sc_admin_q->q_entries)); 270 nvme_barrier(sc, 0, sc->sc_ios, BUS_SPACE_BARRIER_WRITE); 271 delay(5000); 272 273 CLR(cc, NVME_CC_IOCQES_MASK | NVME_CC_IOSQES_MASK | NVME_CC_SHN_MASK | 274 NVME_CC_AMS_MASK | NVME_CC_MPS_MASK | NVME_CC_CSS_MASK); 275 SET(cc, NVME_CC_IOSQES(ffs(64) - 1) | NVME_CC_IOCQES(ffs(16) - 1)); 276 SET(cc, NVME_CC_SHN(NVME_CC_SHN_NONE)); 277 SET(cc, NVME_CC_CSS(NVME_CC_CSS_NVM)); 278 SET(cc, NVME_CC_AMS(NVME_CC_AMS_RR)); 279 SET(cc, NVME_CC_MPS(mps)); 280 SET(cc, NVME_CC_EN); 281 282 nvme_write4(sc, NVME_CC, cc); 283 nvme_barrier(sc, 0, sc->sc_ios, 284 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 285 286 waitready: 287 return nvme_ready(sc, NVME_CSTS_RDY); 288 } 289 290 static int 291 nvme_disable(struct nvme_softc *sc) 292 { 293 uint32_t cc, csts; 294 int error; 295 296 cc = nvme_read4(sc, NVME_CC); 297 csts = nvme_read4(sc, NVME_CSTS); 298 299 /* 300 * Per 3.1.5 in NVME 1.3 spec, transitioning CC.EN from 0 to 1 301 * when CSTS.RDY is 1 or transitioning CC.EN from 1 to 0 when 302 * CSTS.RDY is 0 "has undefined results" So make sure that CSTS.RDY 303 * isn't the desired value. Short circuit if we're already disabled. 304 */ 305 if (ISSET(cc, NVME_CC_EN)) { 306 if (!ISSET(csts, NVME_CSTS_RDY)) { 307 /* EN == 1, wait for RDY == 1 or fail */ 308 error = nvme_ready(sc, NVME_CSTS_RDY); 309 if (error) 310 return error; 311 } 312 } else { 313 /* EN == 0 already wait for RDY == 0 */ 314 if (!ISSET(csts, NVME_CSTS_RDY)) 315 return 0; 316 317 goto waitready; 318 } 319 320 CLR(cc, NVME_CC_EN); 321 nvme_write4(sc, NVME_CC, cc); 322 nvme_barrier(sc, 0, sc->sc_ios, BUS_SPACE_BARRIER_READ); 323 324 /* 325 * Some drives have issues with accessing the mmio after we disable, 326 * so delay for a bit after we write the bit to cope with these issues. 327 */ 328 if (ISSET(sc->sc_quirks, NVME_QUIRK_DELAY_B4_CHK_RDY)) 329 delay(B4_CHK_RDY_DELAY_MS); 330 331 waitready: 332 return nvme_ready(sc, 0); 333 } 334 335 int 336 nvme_attach(struct nvme_softc *sc) 337 { 338 uint64_t cap; 339 uint32_t reg; 340 u_int dstrd; 341 u_int mps = PAGE_SHIFT; 342 u_int ioq_allocated; 343 uint16_t adminq_entries = nvme_adminq_size; 344 uint16_t ioq_entries = nvme_ioq_size; 345 int i; 346 347 reg = nvme_read4(sc, NVME_VS); 348 if (reg == 0xffffffff) { 349 aprint_error_dev(sc->sc_dev, "invalid mapping\n"); 350 return 1; 351 } 352 353 if (NVME_VS_TER(reg) == 0) 354 aprint_normal_dev(sc->sc_dev, "NVMe %d.%d\n", NVME_VS_MJR(reg), 355 NVME_VS_MNR(reg)); 356 else 357 aprint_normal_dev(sc->sc_dev, "NVMe %d.%d.%d\n", NVME_VS_MJR(reg), 358 NVME_VS_MNR(reg), NVME_VS_TER(reg)); 359 360 cap = nvme_read8(sc, NVME_CAP); 361 dstrd = NVME_CAP_DSTRD(cap); 362 if (NVME_CAP_MPSMIN(cap) > PAGE_SHIFT) { 363 aprint_error_dev(sc->sc_dev, "NVMe minimum page size %u " 364 "is greater than CPU page size %u\n", 365 1 << NVME_CAP_MPSMIN(cap), 1 << PAGE_SHIFT); 366 return 1; 367 } 368 if (NVME_CAP_MPSMAX(cap) < mps) 369 mps = NVME_CAP_MPSMAX(cap); 370 if (ioq_entries > NVME_CAP_MQES(cap)) 371 ioq_entries = NVME_CAP_MQES(cap); 372 373 /* set initial values to be used for admin queue during probe */ 374 sc->sc_rdy_to = NVME_CAP_TO(cap); 375 sc->sc_mps = 1 << mps; 376 sc->sc_mdts = MAXPHYS; 377 sc->sc_max_sgl = 2; 378 379 if (nvme_disable(sc) != 0) { 380 aprint_error_dev(sc->sc_dev, "unable to disable controller\n"); 381 return 1; 382 } 383 384 sc->sc_admin_q = nvme_q_alloc(sc, NVME_ADMIN_Q, adminq_entries, dstrd); 385 if (sc->sc_admin_q == NULL) { 386 aprint_error_dev(sc->sc_dev, 387 "unable to allocate admin queue\n"); 388 return 1; 389 } 390 if (sc->sc_intr_establish(sc, NVME_ADMIN_Q, sc->sc_admin_q)) 391 goto free_admin_q; 392 393 if (nvme_enable(sc, mps) != 0) { 394 aprint_error_dev(sc->sc_dev, "unable to enable controller\n"); 395 goto disestablish_admin_q; 396 } 397 398 if (nvme_identify(sc, NVME_CAP_MPSMIN(cap)) != 0) { 399 aprint_error_dev(sc->sc_dev, "unable to identify controller\n"); 400 goto disable; 401 } 402 403 /* we know how big things are now */ 404 sc->sc_max_sgl = sc->sc_mdts / sc->sc_mps; 405 406 /* reallocate ccbs of admin queue with new max sgl. */ 407 nvme_ccbs_free(sc->sc_admin_q); 408 nvme_ccbs_alloc(sc->sc_admin_q, sc->sc_admin_q->q_entries); 409 410 if (sc->sc_use_mq) { 411 /* Limit the number of queues to the number allocated in HW */ 412 if (nvme_get_number_of_queues(sc, &ioq_allocated) != 0) { 413 aprint_error_dev(sc->sc_dev, 414 "unable to get number of queues\n"); 415 goto disable; 416 } 417 if (sc->sc_nq > ioq_allocated) 418 sc->sc_nq = ioq_allocated; 419 } 420 421 sc->sc_q = kmem_zalloc(sizeof(*sc->sc_q) * sc->sc_nq, KM_SLEEP); 422 for (i = 0; i < sc->sc_nq; i++) { 423 sc->sc_q[i] = nvme_q_alloc(sc, i + 1, ioq_entries, dstrd); 424 if (sc->sc_q[i] == NULL) { 425 aprint_error_dev(sc->sc_dev, 426 "unable to allocate io queue\n"); 427 goto free_q; 428 } 429 if (nvme_q_create(sc, sc->sc_q[i]) != 0) { 430 aprint_error_dev(sc->sc_dev, 431 "unable to create io queue\n"); 432 nvme_q_free(sc, sc->sc_q[i]); 433 goto free_q; 434 } 435 } 436 437 if (!sc->sc_use_mq) 438 nvme_write4(sc, NVME_INTMC, 1); 439 440 /* probe subdevices */ 441 sc->sc_namespaces = kmem_zalloc(sizeof(*sc->sc_namespaces) * sc->sc_nn, 442 KM_SLEEP); 443 nvme_rescan(sc->sc_dev, "nvme", &i); 444 445 return 0; 446 447 free_q: 448 while (--i >= 0) { 449 nvme_q_delete(sc, sc->sc_q[i]); 450 nvme_q_free(sc, sc->sc_q[i]); 451 } 452 disable: 453 nvme_disable(sc); 454 disestablish_admin_q: 455 sc->sc_intr_disestablish(sc, NVME_ADMIN_Q); 456 free_admin_q: 457 nvme_q_free(sc, sc->sc_admin_q); 458 459 return 1; 460 } 461 462 int 463 nvme_rescan(device_t self, const char *attr, const int *flags) 464 { 465 struct nvme_softc *sc = device_private(self); 466 struct nvme_attach_args naa; 467 uint64_t cap; 468 int ioq_entries = nvme_ioq_size; 469 int i; 470 471 cap = nvme_read8(sc, NVME_CAP); 472 if (ioq_entries > NVME_CAP_MQES(cap)) 473 ioq_entries = NVME_CAP_MQES(cap); 474 475 for (i = 0; i < sc->sc_nn; i++) { 476 if (sc->sc_namespaces[i].dev) 477 continue; 478 memset(&naa, 0, sizeof(naa)); 479 naa.naa_nsid = i + 1; 480 naa.naa_qentries = (ioq_entries - 1) * sc->sc_nq; 481 naa.naa_maxphys = sc->sc_mdts; 482 sc->sc_namespaces[i].dev = config_found(sc->sc_dev, &naa, 483 nvme_print); 484 } 485 return 0; 486 } 487 488 static int 489 nvme_print(void *aux, const char *pnp) 490 { 491 struct nvme_attach_args *naa = aux; 492 493 if (pnp) 494 aprint_normal("at %s", pnp); 495 496 if (naa->naa_nsid > 0) 497 aprint_normal(" nsid %d", naa->naa_nsid); 498 499 return UNCONF; 500 } 501 502 int 503 nvme_detach(struct nvme_softc *sc, int flags) 504 { 505 int i, error; 506 507 error = config_detach_children(sc->sc_dev, flags); 508 if (error) 509 return error; 510 511 error = nvme_shutdown(sc); 512 if (error) 513 return error; 514 515 /* from now on we are committed to detach, following will never fail */ 516 for (i = 0; i < sc->sc_nq; i++) 517 nvme_q_free(sc, sc->sc_q[i]); 518 kmem_free(sc->sc_q, sizeof(*sc->sc_q) * sc->sc_nq); 519 nvme_q_free(sc, sc->sc_admin_q); 520 521 return 0; 522 } 523 524 static int 525 nvme_shutdown(struct nvme_softc *sc) 526 { 527 uint32_t cc, csts; 528 bool disabled = false; 529 int i; 530 531 if (!sc->sc_use_mq) 532 nvme_write4(sc, NVME_INTMS, 1); 533 534 for (i = 0; i < sc->sc_nq; i++) { 535 if (nvme_q_delete(sc, sc->sc_q[i]) != 0) { 536 aprint_error_dev(sc->sc_dev, 537 "unable to delete io queue %d, disabling\n", i + 1); 538 disabled = true; 539 } 540 } 541 sc->sc_intr_disestablish(sc, NVME_ADMIN_Q); 542 if (disabled) 543 goto disable; 544 545 cc = nvme_read4(sc, NVME_CC); 546 CLR(cc, NVME_CC_SHN_MASK); 547 SET(cc, NVME_CC_SHN(NVME_CC_SHN_NORMAL)); 548 nvme_write4(sc, NVME_CC, cc); 549 550 for (i = 0; i < 4000; i++) { 551 nvme_barrier(sc, 0, sc->sc_ios, 552 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 553 csts = nvme_read4(sc, NVME_CSTS); 554 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_DONE) 555 return 0; 556 557 delay(1000); 558 } 559 560 aprint_error_dev(sc->sc_dev, "unable to shudown, disabling\n"); 561 562 disable: 563 nvme_disable(sc); 564 return 0; 565 } 566 567 void 568 nvme_childdet(device_t self, device_t child) 569 { 570 struct nvme_softc *sc = device_private(self); 571 int i; 572 573 for (i = 0; i < sc->sc_nn; i++) { 574 if (sc->sc_namespaces[i].dev == child) { 575 /* Already freed ns->ident. */ 576 sc->sc_namespaces[i].dev = NULL; 577 break; 578 } 579 } 580 } 581 582 int 583 nvme_ns_identify(struct nvme_softc *sc, uint16_t nsid) 584 { 585 struct nvme_sqe sqe; 586 struct nvm_identify_namespace *identify; 587 struct nvme_dmamem *mem; 588 struct nvme_ccb *ccb; 589 struct nvme_namespace *ns; 590 int rv; 591 592 KASSERT(nsid > 0); 593 594 ccb = nvme_ccb_get(sc->sc_admin_q, false); 595 KASSERT(ccb != NULL); /* it's a bug if we don't have spare ccb here */ 596 597 mem = nvme_dmamem_alloc(sc, sizeof(*identify)); 598 if (mem == NULL) { 599 nvme_ccb_put(sc->sc_admin_q, ccb); 600 return ENOMEM; 601 } 602 603 memset(&sqe, 0, sizeof(sqe)); 604 sqe.opcode = NVM_ADMIN_IDENTIFY; 605 htolem32(&sqe.nsid, nsid); 606 htolem64(&sqe.entry.prp[0], NVME_DMA_DVA(mem)); 607 htolem32(&sqe.cdw10, 0); 608 609 ccb->ccb_done = nvme_empty_done; 610 ccb->ccb_cookie = &sqe; 611 612 nvme_dmamem_sync(sc, mem, BUS_DMASYNC_PREREAD); 613 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_sqe_fill, NVME_TIMO_IDENT); 614 nvme_dmamem_sync(sc, mem, BUS_DMASYNC_POSTREAD); 615 616 nvme_ccb_put(sc->sc_admin_q, ccb); 617 618 if (rv != 0) { 619 rv = EIO; 620 goto done; 621 } 622 623 /* commit */ 624 625 identify = kmem_zalloc(sizeof(*identify), KM_SLEEP); 626 *identify = *((volatile struct nvm_identify_namespace *)NVME_DMA_KVA(mem)); 627 628 /* Convert data to host endian */ 629 nvme_identify_namespace_swapbytes(identify); 630 631 ns = nvme_ns_get(sc, nsid); 632 KASSERT(ns); 633 KASSERT(ns->ident == NULL); 634 ns->ident = identify; 635 636 done: 637 nvme_dmamem_free(sc, mem); 638 639 return rv; 640 } 641 642 int 643 nvme_ns_dobio(struct nvme_softc *sc, uint16_t nsid, void *cookie, 644 struct buf *bp, void *data, size_t datasize, 645 int secsize, daddr_t blkno, int flags, nvme_nnc_done nnc_done) 646 { 647 struct nvme_queue *q = nvme_get_q(sc); 648 struct nvme_ccb *ccb; 649 bus_dmamap_t dmap; 650 int i, error; 651 652 ccb = nvme_ccb_get(q, false); 653 if (ccb == NULL) 654 return EAGAIN; 655 656 ccb->ccb_done = nvme_ns_io_done; 657 ccb->ccb_cookie = cookie; 658 659 /* namespace context */ 660 ccb->nnc_nsid = nsid; 661 ccb->nnc_flags = flags; 662 ccb->nnc_buf = bp; 663 ccb->nnc_datasize = datasize; 664 ccb->nnc_secsize = secsize; 665 ccb->nnc_blkno = blkno; 666 ccb->nnc_done = nnc_done; 667 668 dmap = ccb->ccb_dmamap; 669 error = bus_dmamap_load(sc->sc_dmat, dmap, data, 670 datasize, NULL, 671 (ISSET(flags, NVME_NS_CTX_F_POLL) ? 672 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 673 (ISSET(flags, NVME_NS_CTX_F_READ) ? 674 BUS_DMA_READ : BUS_DMA_WRITE)); 675 if (error) { 676 nvme_ccb_put(q, ccb); 677 return error; 678 } 679 680 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 681 ISSET(flags, NVME_NS_CTX_F_READ) ? 682 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 683 684 if (dmap->dm_nsegs > 2) { 685 for (i = 1; i < dmap->dm_nsegs; i++) { 686 htolem64(&ccb->ccb_prpl[i - 1], 687 dmap->dm_segs[i].ds_addr); 688 } 689 bus_dmamap_sync(sc->sc_dmat, 690 NVME_DMA_MAP(q->q_ccb_prpls), 691 ccb->ccb_prpl_off, 692 sizeof(*ccb->ccb_prpl) * (dmap->dm_nsegs - 1), 693 BUS_DMASYNC_PREWRITE); 694 } 695 696 if (ISSET(flags, NVME_NS_CTX_F_POLL)) { 697 if (nvme_poll(sc, q, ccb, nvme_ns_io_fill, NVME_TIMO_PT) != 0) 698 return EIO; 699 return 0; 700 } 701 702 nvme_q_submit(sc, q, ccb, nvme_ns_io_fill); 703 return 0; 704 } 705 706 static void 707 nvme_ns_io_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 708 { 709 struct nvme_sqe_io *sqe = slot; 710 bus_dmamap_t dmap = ccb->ccb_dmamap; 711 712 sqe->opcode = ISSET(ccb->nnc_flags, NVME_NS_CTX_F_READ) ? 713 NVM_CMD_READ : NVM_CMD_WRITE; 714 htolem32(&sqe->nsid, ccb->nnc_nsid); 715 716 htolem64(&sqe->entry.prp[0], dmap->dm_segs[0].ds_addr); 717 switch (dmap->dm_nsegs) { 718 case 1: 719 break; 720 case 2: 721 htolem64(&sqe->entry.prp[1], dmap->dm_segs[1].ds_addr); 722 break; 723 default: 724 /* the prp list is already set up and synced */ 725 htolem64(&sqe->entry.prp[1], ccb->ccb_prpl_dva); 726 break; 727 } 728 729 htolem64(&sqe->slba, ccb->nnc_blkno); 730 731 if (ISSET(ccb->nnc_flags, NVME_NS_CTX_F_FUA)) 732 htolem16(&sqe->ioflags, NVM_SQE_IO_FUA); 733 734 /* guaranteed by upper layers, but check just in case */ 735 KASSERT((ccb->nnc_datasize % ccb->nnc_secsize) == 0); 736 htolem16(&sqe->nlb, (ccb->nnc_datasize / ccb->nnc_secsize) - 1); 737 } 738 739 static void 740 nvme_ns_io_done(struct nvme_queue *q, struct nvme_ccb *ccb, 741 struct nvme_cqe *cqe) 742 { 743 struct nvme_softc *sc = q->q_sc; 744 bus_dmamap_t dmap = ccb->ccb_dmamap; 745 void *nnc_cookie = ccb->ccb_cookie; 746 nvme_nnc_done nnc_done = ccb->nnc_done; 747 struct buf *bp = ccb->nnc_buf; 748 749 if (dmap->dm_nsegs > 2) { 750 bus_dmamap_sync(sc->sc_dmat, 751 NVME_DMA_MAP(q->q_ccb_prpls), 752 ccb->ccb_prpl_off, 753 sizeof(*ccb->ccb_prpl) * (dmap->dm_nsegs - 1), 754 BUS_DMASYNC_POSTWRITE); 755 } 756 757 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 758 ISSET(ccb->nnc_flags, NVME_NS_CTX_F_READ) ? 759 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 760 761 bus_dmamap_unload(sc->sc_dmat, dmap); 762 nvme_ccb_put(q, ccb); 763 764 nnc_done(nnc_cookie, bp, lemtoh16(&cqe->flags), lemtoh32(&cqe->cdw0)); 765 } 766 767 /* 768 * If there is no volatile write cache, it makes no sense to issue 769 * flush commands or query for the status. 770 */ 771 static bool 772 nvme_has_volatile_write_cache(struct nvme_softc *sc) 773 { 774 /* sc_identify is filled during attachment */ 775 return ((sc->sc_identify.vwc & NVME_ID_CTRLR_VWC_PRESENT) != 0); 776 } 777 778 static bool 779 nvme_ns_sync_finished(void *cookie) 780 { 781 int *result = cookie; 782 783 return (*result != 0); 784 } 785 786 int 787 nvme_ns_sync(struct nvme_softc *sc, uint16_t nsid, int flags) 788 { 789 struct nvme_queue *q = nvme_get_q(sc); 790 struct nvme_ccb *ccb; 791 int result = 0; 792 793 if (!nvme_has_volatile_write_cache(sc)) { 794 /* cache not present, no value in trying to flush it */ 795 return 0; 796 } 797 798 ccb = nvme_ccb_get(q, true); 799 if (ccb == NULL) 800 return EAGAIN; 801 802 ccb->ccb_done = nvme_ns_sync_done; 803 ccb->ccb_cookie = &result; 804 805 /* namespace context */ 806 ccb->nnc_nsid = nsid; 807 ccb->nnc_flags = flags; 808 ccb->nnc_done = NULL; 809 810 if (ISSET(flags, NVME_NS_CTX_F_POLL)) { 811 if (nvme_poll(sc, q, ccb, nvme_ns_sync_fill, NVME_TIMO_SY) != 0) 812 return EIO; 813 return 0; 814 } 815 816 nvme_q_submit(sc, q, ccb, nvme_ns_sync_fill); 817 818 /* wait for completion */ 819 nvme_q_wait_complete(sc, q, nvme_ns_sync_finished, &result); 820 KASSERT(result != 0); 821 822 return (result > 0) ? 0 : EIO; 823 } 824 825 static void 826 nvme_ns_sync_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 827 { 828 struct nvme_sqe *sqe = slot; 829 830 sqe->opcode = NVM_CMD_FLUSH; 831 htolem32(&sqe->nsid, ccb->nnc_nsid); 832 } 833 834 static void 835 nvme_ns_sync_done(struct nvme_queue *q, struct nvme_ccb *ccb, 836 struct nvme_cqe *cqe) 837 { 838 int *result = ccb->ccb_cookie; 839 uint16_t status = NVME_CQE_SC(lemtoh16(&cqe->flags)); 840 841 if (status == NVME_CQE_SC_SUCCESS) 842 *result = 1; 843 else 844 *result = -1; 845 846 nvme_ccb_put(q, ccb); 847 } 848 849 static bool 850 nvme_getcache_finished(void *xc) 851 { 852 int *addr = xc; 853 854 return (*addr != 0); 855 } 856 857 /* 858 * Get status of volatile write cache. Always asynchronous. 859 */ 860 int 861 nvme_admin_getcache(struct nvme_softc *sc, int *addr) 862 { 863 struct nvme_ccb *ccb; 864 struct nvme_queue *q = sc->sc_admin_q; 865 int result = 0, error; 866 867 if (!nvme_has_volatile_write_cache(sc)) { 868 /* cache simply not present */ 869 *addr = 0; 870 return 0; 871 } 872 873 ccb = nvme_ccb_get(q, true); 874 KASSERT(ccb != NULL); 875 876 ccb->ccb_done = nvme_getcache_done; 877 ccb->ccb_cookie = &result; 878 879 /* namespace context */ 880 ccb->nnc_flags = 0; 881 ccb->nnc_done = NULL; 882 883 nvme_q_submit(sc, q, ccb, nvme_getcache_fill); 884 885 /* wait for completion */ 886 nvme_q_wait_complete(sc, q, nvme_getcache_finished, &result); 887 KASSERT(result != 0); 888 889 if (result > 0) { 890 *addr = result; 891 error = 0; 892 } else 893 error = EINVAL; 894 895 return error; 896 } 897 898 static void 899 nvme_getcache_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 900 { 901 struct nvme_sqe *sqe = slot; 902 903 sqe->opcode = NVM_ADMIN_GET_FEATURES; 904 htolem32(&sqe->cdw10, NVM_FEATURE_VOLATILE_WRITE_CACHE); 905 htolem32(&sqe->cdw11, NVM_VOLATILE_WRITE_CACHE_WCE); 906 } 907 908 static void 909 nvme_getcache_done(struct nvme_queue *q, struct nvme_ccb *ccb, 910 struct nvme_cqe *cqe) 911 { 912 int *addr = ccb->ccb_cookie; 913 uint16_t status = NVME_CQE_SC(lemtoh16(&cqe->flags)); 914 uint32_t cdw0 = lemtoh32(&cqe->cdw0); 915 int result; 916 917 if (status == NVME_CQE_SC_SUCCESS) { 918 result = 0; 919 920 /* 921 * DPO not supported, Dataset Management (DSM) field doesn't 922 * specify the same semantics. FUA is always supported. 923 */ 924 result = DKCACHE_FUA; 925 926 if (cdw0 & NVM_VOLATILE_WRITE_CACHE_WCE) 927 result |= DKCACHE_WRITE; 928 929 /* 930 * If volatile write cache is present, the flag shall also be 931 * settable. 932 */ 933 result |= DKCACHE_WCHANGE; 934 935 /* 936 * ONCS field indicates whether the optional SAVE is also 937 * supported for Set Features. According to spec v1.3, 938 * Volatile Write Cache however doesn't support persistency 939 * across power cycle/reset. 940 */ 941 942 } else { 943 result = -1; 944 } 945 946 *addr = result; 947 948 nvme_ccb_put(q, ccb); 949 } 950 951 struct nvme_setcache_state { 952 int dkcache; 953 int result; 954 }; 955 956 static bool 957 nvme_setcache_finished(void *xc) 958 { 959 struct nvme_setcache_state *st = xc; 960 961 return (st->result != 0); 962 } 963 964 static void 965 nvme_setcache_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 966 { 967 struct nvme_sqe *sqe = slot; 968 struct nvme_setcache_state *st = ccb->ccb_cookie; 969 970 sqe->opcode = NVM_ADMIN_SET_FEATURES; 971 htolem32(&sqe->cdw10, NVM_FEATURE_VOLATILE_WRITE_CACHE); 972 if (st->dkcache & DKCACHE_WRITE) 973 htolem32(&sqe->cdw11, NVM_VOLATILE_WRITE_CACHE_WCE); 974 } 975 976 static void 977 nvme_setcache_done(struct nvme_queue *q, struct nvme_ccb *ccb, 978 struct nvme_cqe *cqe) 979 { 980 struct nvme_setcache_state *st = ccb->ccb_cookie; 981 uint16_t status = NVME_CQE_SC(lemtoh16(&cqe->flags)); 982 983 if (status == NVME_CQE_SC_SUCCESS) { 984 st->result = 1; 985 } else { 986 st->result = -1; 987 } 988 989 nvme_ccb_put(q, ccb); 990 } 991 992 /* 993 * Set status of volatile write cache. Always asynchronous. 994 */ 995 int 996 nvme_admin_setcache(struct nvme_softc *sc, int dkcache) 997 { 998 struct nvme_ccb *ccb; 999 struct nvme_queue *q = sc->sc_admin_q; 1000 int error; 1001 struct nvme_setcache_state st; 1002 1003 if (!nvme_has_volatile_write_cache(sc)) { 1004 /* cache simply not present */ 1005 return EOPNOTSUPP; 1006 } 1007 1008 if (dkcache & ~(DKCACHE_WRITE)) { 1009 /* unsupported parameters */ 1010 return EOPNOTSUPP; 1011 } 1012 1013 ccb = nvme_ccb_get(q, true); 1014 KASSERT(ccb != NULL); 1015 1016 memset(&st, 0, sizeof(st)); 1017 st.dkcache = dkcache; 1018 1019 ccb->ccb_done = nvme_setcache_done; 1020 ccb->ccb_cookie = &st; 1021 1022 /* namespace context */ 1023 ccb->nnc_flags = 0; 1024 ccb->nnc_done = NULL; 1025 1026 nvme_q_submit(sc, q, ccb, nvme_setcache_fill); 1027 1028 /* wait for completion */ 1029 nvme_q_wait_complete(sc, q, nvme_setcache_finished, &st); 1030 KASSERT(st.result != 0); 1031 1032 if (st.result > 0) 1033 error = 0; 1034 else 1035 error = EINVAL; 1036 1037 return error; 1038 } 1039 1040 void 1041 nvme_ns_free(struct nvme_softc *sc, uint16_t nsid) 1042 { 1043 struct nvme_namespace *ns; 1044 struct nvm_identify_namespace *identify; 1045 1046 ns = nvme_ns_get(sc, nsid); 1047 KASSERT(ns); 1048 1049 identify = ns->ident; 1050 ns->ident = NULL; 1051 if (identify != NULL) 1052 kmem_free(identify, sizeof(*identify)); 1053 } 1054 1055 struct nvme_pt_state { 1056 struct nvme_pt_command *pt; 1057 bool finished; 1058 }; 1059 1060 static void 1061 nvme_pt_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 1062 { 1063 struct nvme_softc *sc = q->q_sc; 1064 struct nvme_sqe *sqe = slot; 1065 struct nvme_pt_state *state = ccb->ccb_cookie; 1066 struct nvme_pt_command *pt = state->pt; 1067 bus_dmamap_t dmap = ccb->ccb_dmamap; 1068 int i; 1069 1070 sqe->opcode = pt->cmd.opcode; 1071 htolem32(&sqe->nsid, pt->cmd.nsid); 1072 1073 if (pt->buf != NULL && pt->len > 0) { 1074 htolem64(&sqe->entry.prp[0], dmap->dm_segs[0].ds_addr); 1075 switch (dmap->dm_nsegs) { 1076 case 1: 1077 break; 1078 case 2: 1079 htolem64(&sqe->entry.prp[1], dmap->dm_segs[1].ds_addr); 1080 break; 1081 default: 1082 for (i = 1; i < dmap->dm_nsegs; i++) { 1083 htolem64(&ccb->ccb_prpl[i - 1], 1084 dmap->dm_segs[i].ds_addr); 1085 } 1086 bus_dmamap_sync(sc->sc_dmat, 1087 NVME_DMA_MAP(q->q_ccb_prpls), 1088 ccb->ccb_prpl_off, 1089 sizeof(*ccb->ccb_prpl) * (dmap->dm_nsegs - 1), 1090 BUS_DMASYNC_PREWRITE); 1091 htolem64(&sqe->entry.prp[1], ccb->ccb_prpl_dva); 1092 break; 1093 } 1094 } 1095 1096 htolem32(&sqe->cdw10, pt->cmd.cdw10); 1097 htolem32(&sqe->cdw11, pt->cmd.cdw11); 1098 htolem32(&sqe->cdw12, pt->cmd.cdw12); 1099 htolem32(&sqe->cdw13, pt->cmd.cdw13); 1100 htolem32(&sqe->cdw14, pt->cmd.cdw14); 1101 htolem32(&sqe->cdw15, pt->cmd.cdw15); 1102 } 1103 1104 static void 1105 nvme_pt_done(struct nvme_queue *q, struct nvme_ccb *ccb, struct nvme_cqe *cqe) 1106 { 1107 struct nvme_softc *sc = q->q_sc; 1108 struct nvme_pt_state *state = ccb->ccb_cookie; 1109 struct nvme_pt_command *pt = state->pt; 1110 bus_dmamap_t dmap = ccb->ccb_dmamap; 1111 1112 if (pt->buf != NULL && pt->len > 0) { 1113 if (dmap->dm_nsegs > 2) { 1114 bus_dmamap_sync(sc->sc_dmat, 1115 NVME_DMA_MAP(q->q_ccb_prpls), 1116 ccb->ccb_prpl_off, 1117 sizeof(*ccb->ccb_prpl) * (dmap->dm_nsegs - 1), 1118 BUS_DMASYNC_POSTWRITE); 1119 } 1120 1121 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 1122 pt->is_read ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1123 bus_dmamap_unload(sc->sc_dmat, dmap); 1124 } 1125 1126 pt->cpl.cdw0 = lemtoh32(&cqe->cdw0); 1127 pt->cpl.flags = lemtoh16(&cqe->flags) & ~NVME_CQE_PHASE; 1128 1129 state->finished = true; 1130 1131 nvme_ccb_put(q, ccb); 1132 } 1133 1134 static bool 1135 nvme_pt_finished(void *cookie) 1136 { 1137 struct nvme_pt_state *state = cookie; 1138 1139 return state->finished; 1140 } 1141 1142 static int 1143 nvme_command_passthrough(struct nvme_softc *sc, struct nvme_pt_command *pt, 1144 uint16_t nsid, struct lwp *l, bool is_adminq) 1145 { 1146 struct nvme_queue *q; 1147 struct nvme_ccb *ccb; 1148 void *buf = NULL; 1149 struct nvme_pt_state state; 1150 int error; 1151 1152 /* limit command size to maximum data transfer size */ 1153 if ((pt->buf == NULL && pt->len > 0) || 1154 (pt->buf != NULL && (pt->len == 0 || pt->len > sc->sc_mdts))) 1155 return EINVAL; 1156 1157 q = is_adminq ? sc->sc_admin_q : nvme_get_q(sc); 1158 ccb = nvme_ccb_get(q, true); 1159 KASSERT(ccb != NULL); 1160 1161 if (pt->buf != NULL) { 1162 KASSERT(pt->len > 0); 1163 buf = kmem_alloc(pt->len, KM_SLEEP); 1164 if (!pt->is_read) { 1165 error = copyin(pt->buf, buf, pt->len); 1166 if (error) 1167 goto kmem_free; 1168 } 1169 error = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap, buf, 1170 pt->len, NULL, 1171 BUS_DMA_WAITOK | 1172 (pt->is_read ? BUS_DMA_READ : BUS_DMA_WRITE)); 1173 if (error) 1174 goto kmem_free; 1175 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap, 1176 0, ccb->ccb_dmamap->dm_mapsize, 1177 pt->is_read ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1178 } 1179 1180 memset(&state, 0, sizeof(state)); 1181 state.pt = pt; 1182 state.finished = false; 1183 1184 ccb->ccb_done = nvme_pt_done; 1185 ccb->ccb_cookie = &state; 1186 1187 pt->cmd.nsid = nsid; 1188 1189 nvme_q_submit(sc, q, ccb, nvme_pt_fill); 1190 1191 /* wait for completion */ 1192 nvme_q_wait_complete(sc, q, nvme_pt_finished, &state); 1193 KASSERT(state.finished); 1194 1195 error = 0; 1196 1197 if (buf != NULL) { 1198 if (error == 0 && pt->is_read) 1199 error = copyout(buf, pt->buf, pt->len); 1200 kmem_free: 1201 kmem_free(buf, pt->len); 1202 } 1203 1204 return error; 1205 } 1206 1207 static void 1208 nvme_q_submit(struct nvme_softc *sc, struct nvme_queue *q, struct nvme_ccb *ccb, 1209 void (*fill)(struct nvme_queue *, struct nvme_ccb *, void *)) 1210 { 1211 struct nvme_sqe *sqe = NVME_DMA_KVA(q->q_sq_dmamem); 1212 uint32_t tail; 1213 1214 mutex_enter(&q->q_sq_mtx); 1215 tail = q->q_sq_tail; 1216 if (++q->q_sq_tail >= q->q_entries) 1217 q->q_sq_tail = 0; 1218 1219 sqe += tail; 1220 1221 bus_dmamap_sync(sc->sc_dmat, NVME_DMA_MAP(q->q_sq_dmamem), 1222 sizeof(*sqe) * tail, sizeof(*sqe), BUS_DMASYNC_POSTWRITE); 1223 memset(sqe, 0, sizeof(*sqe)); 1224 (*fill)(q, ccb, sqe); 1225 htolem16(&sqe->cid, ccb->ccb_id); 1226 bus_dmamap_sync(sc->sc_dmat, NVME_DMA_MAP(q->q_sq_dmamem), 1227 sizeof(*sqe) * tail, sizeof(*sqe), BUS_DMASYNC_PREWRITE); 1228 1229 nvme_write4(sc, q->q_sqtdbl, q->q_sq_tail); 1230 mutex_exit(&q->q_sq_mtx); 1231 } 1232 1233 struct nvme_poll_state { 1234 struct nvme_sqe s; 1235 struct nvme_cqe c; 1236 void *cookie; 1237 void (*done)(struct nvme_queue *, struct nvme_ccb *, struct nvme_cqe *); 1238 }; 1239 1240 static int 1241 nvme_poll(struct nvme_softc *sc, struct nvme_queue *q, struct nvme_ccb *ccb, 1242 void (*fill)(struct nvme_queue *, struct nvme_ccb *, void *), int timo_sec) 1243 { 1244 struct nvme_poll_state state; 1245 uint16_t flags; 1246 int step = 10; 1247 int maxloop = timo_sec * 1000000 / step; 1248 int error = 0; 1249 1250 memset(&state, 0, sizeof(state)); 1251 (*fill)(q, ccb, &state.s); 1252 1253 state.done = ccb->ccb_done; 1254 state.cookie = ccb->ccb_cookie; 1255 1256 ccb->ccb_done = nvme_poll_done; 1257 ccb->ccb_cookie = &state; 1258 1259 nvme_q_submit(sc, q, ccb, nvme_poll_fill); 1260 while (!ISSET(state.c.flags, htole16(NVME_CQE_PHASE))) { 1261 if (nvme_q_complete(sc, q) == 0) 1262 delay(step); 1263 1264 if (timo_sec >= 0 && --maxloop <= 0) { 1265 error = ETIMEDOUT; 1266 break; 1267 } 1268 } 1269 1270 if (error == 0) { 1271 flags = lemtoh16(&state.c.flags); 1272 return flags & ~NVME_CQE_PHASE; 1273 } else { 1274 /* 1275 * If it succeds later, it would hit ccb which will have been 1276 * already reused for something else. Not good. Cross 1277 * fingers and hope for best. XXX do controller reset? 1278 */ 1279 aprint_error_dev(sc->sc_dev, "polled command timed out\n"); 1280 1281 /* Invoke the callback to clean state anyway */ 1282 struct nvme_cqe cqe; 1283 memset(&cqe, 0, sizeof(cqe)); 1284 ccb->ccb_done(q, ccb, &cqe); 1285 1286 return 1; 1287 } 1288 } 1289 1290 static void 1291 nvme_poll_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 1292 { 1293 struct nvme_sqe *sqe = slot; 1294 struct nvme_poll_state *state = ccb->ccb_cookie; 1295 1296 *sqe = state->s; 1297 } 1298 1299 static void 1300 nvme_poll_done(struct nvme_queue *q, struct nvme_ccb *ccb, 1301 struct nvme_cqe *cqe) 1302 { 1303 struct nvme_poll_state *state = ccb->ccb_cookie; 1304 1305 SET(cqe->flags, htole16(NVME_CQE_PHASE)); 1306 state->c = *cqe; 1307 1308 ccb->ccb_cookie = state->cookie; 1309 state->done(q, ccb, &state->c); 1310 } 1311 1312 static void 1313 nvme_sqe_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 1314 { 1315 struct nvme_sqe *src = ccb->ccb_cookie; 1316 struct nvme_sqe *dst = slot; 1317 1318 *dst = *src; 1319 } 1320 1321 static void 1322 nvme_empty_done(struct nvme_queue *q, struct nvme_ccb *ccb, 1323 struct nvme_cqe *cqe) 1324 { 1325 } 1326 1327 static int 1328 nvme_q_complete(struct nvme_softc *sc, struct nvme_queue *q) 1329 { 1330 struct nvme_ccb *ccb; 1331 struct nvme_cqe *ring = NVME_DMA_KVA(q->q_cq_dmamem), *cqe; 1332 uint16_t flags; 1333 int rv = 0; 1334 1335 mutex_enter(&q->q_cq_mtx); 1336 1337 nvme_dmamem_sync(sc, q->q_cq_dmamem, BUS_DMASYNC_POSTREAD); 1338 for (;;) { 1339 cqe = &ring[q->q_cq_head]; 1340 flags = lemtoh16(&cqe->flags); 1341 if ((flags & NVME_CQE_PHASE) != q->q_cq_phase) 1342 break; 1343 1344 ccb = &q->q_ccbs[cqe->cid]; 1345 1346 if (++q->q_cq_head >= q->q_entries) { 1347 q->q_cq_head = 0; 1348 q->q_cq_phase ^= NVME_CQE_PHASE; 1349 } 1350 1351 #ifdef DEBUG 1352 /* 1353 * If we get spurious completion notification, something 1354 * is seriously hosed up. Very likely DMA to some random 1355 * memory place happened, so just bail out. 1356 */ 1357 if ((intptr_t)ccb->ccb_cookie == NVME_CCB_FREE) { 1358 panic("%s: invalid ccb detected", 1359 device_xname(sc->sc_dev)); 1360 /* NOTREACHED */ 1361 } 1362 #endif 1363 1364 rv++; 1365 1366 /* 1367 * Unlock the mutex before calling the ccb_done callback 1368 * and re-lock afterwards. The callback triggers lddone() 1369 * which schedules another i/o, and also calls nvme_ccb_put(). 1370 * Unlock/relock avoids possibility of deadlock. 1371 */ 1372 mutex_exit(&q->q_cq_mtx); 1373 ccb->ccb_done(q, ccb, cqe); 1374 mutex_enter(&q->q_cq_mtx); 1375 } 1376 nvme_dmamem_sync(sc, q->q_cq_dmamem, BUS_DMASYNC_PREREAD); 1377 1378 if (rv) 1379 nvme_write4(sc, q->q_cqhdbl, q->q_cq_head); 1380 1381 mutex_exit(&q->q_cq_mtx); 1382 1383 return rv; 1384 } 1385 1386 static void 1387 nvme_q_wait_complete(struct nvme_softc *sc, 1388 struct nvme_queue *q, bool (*finished)(void *), void *cookie) 1389 { 1390 mutex_enter(&q->q_ccb_mtx); 1391 if (finished(cookie)) 1392 goto out; 1393 1394 for(;;) { 1395 q->q_ccb_waiting = true; 1396 cv_wait(&q->q_ccb_wait, &q->q_ccb_mtx); 1397 1398 if (finished(cookie)) 1399 break; 1400 } 1401 1402 out: 1403 mutex_exit(&q->q_ccb_mtx); 1404 } 1405 1406 static int 1407 nvme_identify(struct nvme_softc *sc, u_int mps) 1408 { 1409 char sn[41], mn[81], fr[17]; 1410 struct nvm_identify_controller *identify; 1411 struct nvme_dmamem *mem; 1412 struct nvme_ccb *ccb; 1413 u_int mdts; 1414 int rv = 1; 1415 1416 ccb = nvme_ccb_get(sc->sc_admin_q, false); 1417 KASSERT(ccb != NULL); /* it's a bug if we don't have spare ccb here */ 1418 1419 mem = nvme_dmamem_alloc(sc, sizeof(*identify)); 1420 if (mem == NULL) 1421 return 1; 1422 1423 ccb->ccb_done = nvme_empty_done; 1424 ccb->ccb_cookie = mem; 1425 1426 nvme_dmamem_sync(sc, mem, BUS_DMASYNC_PREREAD); 1427 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_fill_identify, 1428 NVME_TIMO_IDENT); 1429 nvme_dmamem_sync(sc, mem, BUS_DMASYNC_POSTREAD); 1430 1431 nvme_ccb_put(sc->sc_admin_q, ccb); 1432 1433 if (rv != 0) 1434 goto done; 1435 1436 identify = NVME_DMA_KVA(mem); 1437 sc->sc_identify = *identify; 1438 identify = NULL; 1439 1440 /* Convert data to host endian */ 1441 nvme_identify_controller_swapbytes(&sc->sc_identify); 1442 1443 strnvisx(sn, sizeof(sn), (const char *)sc->sc_identify.sn, 1444 sizeof(sc->sc_identify.sn), VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1445 strnvisx(mn, sizeof(mn), (const char *)sc->sc_identify.mn, 1446 sizeof(sc->sc_identify.mn), VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1447 strnvisx(fr, sizeof(fr), (const char *)sc->sc_identify.fr, 1448 sizeof(sc->sc_identify.fr), VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1449 aprint_normal_dev(sc->sc_dev, "%s, firmware %s, serial %s\n", mn, fr, 1450 sn); 1451 1452 if (sc->sc_identify.mdts > 0) { 1453 mdts = (1 << sc->sc_identify.mdts) * (1 << mps); 1454 if (mdts < sc->sc_mdts) 1455 sc->sc_mdts = mdts; 1456 } 1457 1458 sc->sc_nn = sc->sc_identify.nn; 1459 1460 done: 1461 nvme_dmamem_free(sc, mem); 1462 1463 return rv; 1464 } 1465 1466 static int 1467 nvme_q_create(struct nvme_softc *sc, struct nvme_queue *q) 1468 { 1469 struct nvme_sqe_q sqe; 1470 struct nvme_ccb *ccb; 1471 int rv; 1472 1473 if (sc->sc_use_mq && sc->sc_intr_establish(sc, q->q_id, q) != 0) 1474 return 1; 1475 1476 ccb = nvme_ccb_get(sc->sc_admin_q, false); 1477 KASSERT(ccb != NULL); 1478 1479 ccb->ccb_done = nvme_empty_done; 1480 ccb->ccb_cookie = &sqe; 1481 1482 memset(&sqe, 0, sizeof(sqe)); 1483 sqe.opcode = NVM_ADMIN_ADD_IOCQ; 1484 htolem64(&sqe.prp1, NVME_DMA_DVA(q->q_cq_dmamem)); 1485 htolem16(&sqe.qsize, q->q_entries - 1); 1486 htolem16(&sqe.qid, q->q_id); 1487 sqe.qflags = NVM_SQE_CQ_IEN | NVM_SQE_Q_PC; 1488 if (sc->sc_use_mq) 1489 htolem16(&sqe.cqid, q->q_id); /* qid == vector */ 1490 1491 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_sqe_fill, NVME_TIMO_QOP); 1492 if (rv != 0) 1493 goto fail; 1494 1495 ccb->ccb_done = nvme_empty_done; 1496 ccb->ccb_cookie = &sqe; 1497 1498 memset(&sqe, 0, sizeof(sqe)); 1499 sqe.opcode = NVM_ADMIN_ADD_IOSQ; 1500 htolem64(&sqe.prp1, NVME_DMA_DVA(q->q_sq_dmamem)); 1501 htolem16(&sqe.qsize, q->q_entries - 1); 1502 htolem16(&sqe.qid, q->q_id); 1503 htolem16(&sqe.cqid, q->q_id); 1504 sqe.qflags = NVM_SQE_Q_PC; 1505 1506 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_sqe_fill, NVME_TIMO_QOP); 1507 if (rv != 0) 1508 goto fail; 1509 1510 nvme_ccb_put(sc->sc_admin_q, ccb); 1511 return 0; 1512 1513 fail: 1514 if (sc->sc_use_mq) 1515 sc->sc_intr_disestablish(sc, q->q_id); 1516 1517 nvme_ccb_put(sc->sc_admin_q, ccb); 1518 return rv; 1519 } 1520 1521 static int 1522 nvme_q_delete(struct nvme_softc *sc, struct nvme_queue *q) 1523 { 1524 struct nvme_sqe_q sqe; 1525 struct nvme_ccb *ccb; 1526 int rv; 1527 1528 ccb = nvme_ccb_get(sc->sc_admin_q, false); 1529 KASSERT(ccb != NULL); 1530 1531 ccb->ccb_done = nvme_empty_done; 1532 ccb->ccb_cookie = &sqe; 1533 1534 memset(&sqe, 0, sizeof(sqe)); 1535 sqe.opcode = NVM_ADMIN_DEL_IOSQ; 1536 htolem16(&sqe.qid, q->q_id); 1537 1538 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_sqe_fill, NVME_TIMO_QOP); 1539 if (rv != 0) 1540 goto fail; 1541 1542 ccb->ccb_done = nvme_empty_done; 1543 ccb->ccb_cookie = &sqe; 1544 1545 memset(&sqe, 0, sizeof(sqe)); 1546 sqe.opcode = NVM_ADMIN_DEL_IOCQ; 1547 htolem16(&sqe.qid, q->q_id); 1548 1549 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_sqe_fill, NVME_TIMO_QOP); 1550 if (rv != 0) 1551 goto fail; 1552 1553 fail: 1554 nvme_ccb_put(sc->sc_admin_q, ccb); 1555 1556 if (rv == 0 && sc->sc_use_mq) { 1557 if (sc->sc_intr_disestablish(sc, q->q_id)) 1558 rv = 1; 1559 } 1560 1561 return rv; 1562 } 1563 1564 static void 1565 nvme_fill_identify(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 1566 { 1567 struct nvme_sqe *sqe = slot; 1568 struct nvme_dmamem *mem = ccb->ccb_cookie; 1569 1570 sqe->opcode = NVM_ADMIN_IDENTIFY; 1571 htolem64(&sqe->entry.prp[0], NVME_DMA_DVA(mem)); 1572 htolem32(&sqe->cdw10, 1); 1573 } 1574 1575 static int 1576 nvme_get_number_of_queues(struct nvme_softc *sc, u_int *nqap) 1577 { 1578 struct nvme_pt_state state; 1579 struct nvme_pt_command pt; 1580 struct nvme_ccb *ccb; 1581 uint16_t ncqa, nsqa; 1582 int rv; 1583 1584 ccb = nvme_ccb_get(sc->sc_admin_q, false); 1585 KASSERT(ccb != NULL); /* it's a bug if we don't have spare ccb here */ 1586 1587 memset(&pt, 0, sizeof(pt)); 1588 pt.cmd.opcode = NVM_ADMIN_GET_FEATURES; 1589 pt.cmd.cdw10 = NVM_FEATURE_NUMBER_OF_QUEUES; 1590 1591 memset(&state, 0, sizeof(state)); 1592 state.pt = &pt; 1593 state.finished = false; 1594 1595 ccb->ccb_done = nvme_pt_done; 1596 ccb->ccb_cookie = &state; 1597 1598 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_pt_fill, NVME_TIMO_QOP); 1599 1600 if (rv != 0) { 1601 *nqap = 0; 1602 return EIO; 1603 } 1604 1605 ncqa = pt.cpl.cdw0 >> 16; 1606 nsqa = pt.cpl.cdw0 & 0xffff; 1607 *nqap = MIN(ncqa, nsqa) + 1; 1608 1609 return 0; 1610 } 1611 1612 static int 1613 nvme_ccbs_alloc(struct nvme_queue *q, uint16_t nccbs) 1614 { 1615 struct nvme_softc *sc = q->q_sc; 1616 struct nvme_ccb *ccb; 1617 bus_addr_t off; 1618 uint64_t *prpl; 1619 u_int i; 1620 1621 mutex_init(&q->q_ccb_mtx, MUTEX_DEFAULT, IPL_BIO); 1622 cv_init(&q->q_ccb_wait, "nvmeqw"); 1623 q->q_ccb_waiting = false; 1624 SIMPLEQ_INIT(&q->q_ccb_list); 1625 1626 q->q_ccbs = kmem_alloc(sizeof(*ccb) * nccbs, KM_SLEEP); 1627 1628 q->q_nccbs = nccbs; 1629 q->q_ccb_prpls = nvme_dmamem_alloc(sc, 1630 sizeof(*prpl) * sc->sc_max_sgl * nccbs); 1631 1632 prpl = NVME_DMA_KVA(q->q_ccb_prpls); 1633 off = 0; 1634 1635 for (i = 0; i < nccbs; i++) { 1636 ccb = &q->q_ccbs[i]; 1637 1638 if (bus_dmamap_create(sc->sc_dmat, sc->sc_mdts, 1639 sc->sc_max_sgl + 1 /* we get a free prp in the sqe */, 1640 sc->sc_mps, sc->sc_mps, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1641 &ccb->ccb_dmamap) != 0) 1642 goto free_maps; 1643 1644 ccb->ccb_id = i; 1645 ccb->ccb_prpl = prpl; 1646 ccb->ccb_prpl_off = off; 1647 ccb->ccb_prpl_dva = NVME_DMA_DVA(q->q_ccb_prpls) + off; 1648 1649 SIMPLEQ_INSERT_TAIL(&q->q_ccb_list, ccb, ccb_entry); 1650 1651 prpl += sc->sc_max_sgl; 1652 off += sizeof(*prpl) * sc->sc_max_sgl; 1653 } 1654 1655 return 0; 1656 1657 free_maps: 1658 nvme_ccbs_free(q); 1659 return 1; 1660 } 1661 1662 static struct nvme_ccb * 1663 nvme_ccb_get(struct nvme_queue *q, bool wait) 1664 { 1665 struct nvme_ccb *ccb = NULL; 1666 1667 mutex_enter(&q->q_ccb_mtx); 1668 again: 1669 ccb = SIMPLEQ_FIRST(&q->q_ccb_list); 1670 if (ccb != NULL) { 1671 SIMPLEQ_REMOVE_HEAD(&q->q_ccb_list, ccb_entry); 1672 #ifdef DEBUG 1673 ccb->ccb_cookie = NULL; 1674 #endif 1675 } else { 1676 if (__predict_false(wait)) { 1677 q->q_ccb_waiting = true; 1678 cv_wait(&q->q_ccb_wait, &q->q_ccb_mtx); 1679 goto again; 1680 } 1681 } 1682 mutex_exit(&q->q_ccb_mtx); 1683 1684 return ccb; 1685 } 1686 1687 static void 1688 nvme_ccb_put(struct nvme_queue *q, struct nvme_ccb *ccb) 1689 { 1690 1691 mutex_enter(&q->q_ccb_mtx); 1692 #ifdef DEBUG 1693 ccb->ccb_cookie = (void *)NVME_CCB_FREE; 1694 #endif 1695 SIMPLEQ_INSERT_HEAD(&q->q_ccb_list, ccb, ccb_entry); 1696 1697 /* It's unlikely there are any waiters, it's not used for regular I/O */ 1698 if (__predict_false(q->q_ccb_waiting)) { 1699 q->q_ccb_waiting = false; 1700 cv_broadcast(&q->q_ccb_wait); 1701 } 1702 1703 mutex_exit(&q->q_ccb_mtx); 1704 } 1705 1706 static void 1707 nvme_ccbs_free(struct nvme_queue *q) 1708 { 1709 struct nvme_softc *sc = q->q_sc; 1710 struct nvme_ccb *ccb; 1711 1712 mutex_enter(&q->q_ccb_mtx); 1713 while ((ccb = SIMPLEQ_FIRST(&q->q_ccb_list)) != NULL) { 1714 SIMPLEQ_REMOVE_HEAD(&q->q_ccb_list, ccb_entry); 1715 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 1716 } 1717 mutex_exit(&q->q_ccb_mtx); 1718 1719 nvme_dmamem_free(sc, q->q_ccb_prpls); 1720 kmem_free(q->q_ccbs, sizeof(*ccb) * q->q_nccbs); 1721 q->q_ccbs = NULL; 1722 cv_destroy(&q->q_ccb_wait); 1723 mutex_destroy(&q->q_ccb_mtx); 1724 } 1725 1726 static struct nvme_queue * 1727 nvme_q_alloc(struct nvme_softc *sc, uint16_t id, u_int entries, u_int dstrd) 1728 { 1729 struct nvme_queue *q; 1730 1731 q = kmem_alloc(sizeof(*q), KM_SLEEP); 1732 q->q_sc = sc; 1733 q->q_sq_dmamem = nvme_dmamem_alloc(sc, 1734 sizeof(struct nvme_sqe) * entries); 1735 if (q->q_sq_dmamem == NULL) 1736 goto free; 1737 1738 q->q_cq_dmamem = nvme_dmamem_alloc(sc, 1739 sizeof(struct nvme_cqe) * entries); 1740 if (q->q_cq_dmamem == NULL) 1741 goto free_sq; 1742 1743 memset(NVME_DMA_KVA(q->q_sq_dmamem), 0, NVME_DMA_LEN(q->q_sq_dmamem)); 1744 memset(NVME_DMA_KVA(q->q_cq_dmamem), 0, NVME_DMA_LEN(q->q_cq_dmamem)); 1745 1746 mutex_init(&q->q_sq_mtx, MUTEX_DEFAULT, IPL_BIO); 1747 mutex_init(&q->q_cq_mtx, MUTEX_DEFAULT, IPL_BIO); 1748 q->q_sqtdbl = NVME_SQTDBL(id, dstrd); 1749 q->q_cqhdbl = NVME_CQHDBL(id, dstrd); 1750 q->q_id = id; 1751 q->q_entries = entries; 1752 q->q_sq_tail = 0; 1753 q->q_cq_head = 0; 1754 q->q_cq_phase = NVME_CQE_PHASE; 1755 1756 nvme_dmamem_sync(sc, q->q_sq_dmamem, BUS_DMASYNC_PREWRITE); 1757 nvme_dmamem_sync(sc, q->q_cq_dmamem, BUS_DMASYNC_PREREAD); 1758 1759 /* 1760 * Due to definition of full and empty queue (queue is empty 1761 * when head == tail, full when tail is one less then head), 1762 * we can actually only have (entries - 1) in-flight commands. 1763 */ 1764 if (nvme_ccbs_alloc(q, entries - 1) != 0) { 1765 aprint_error_dev(sc->sc_dev, "unable to allocate ccbs\n"); 1766 goto free_cq; 1767 } 1768 1769 return q; 1770 1771 free_cq: 1772 nvme_dmamem_free(sc, q->q_cq_dmamem); 1773 free_sq: 1774 nvme_dmamem_free(sc, q->q_sq_dmamem); 1775 free: 1776 kmem_free(q, sizeof(*q)); 1777 1778 return NULL; 1779 } 1780 1781 static void 1782 nvme_q_free(struct nvme_softc *sc, struct nvme_queue *q) 1783 { 1784 nvme_ccbs_free(q); 1785 mutex_destroy(&q->q_sq_mtx); 1786 mutex_destroy(&q->q_cq_mtx); 1787 nvme_dmamem_sync(sc, q->q_cq_dmamem, BUS_DMASYNC_POSTREAD); 1788 nvme_dmamem_sync(sc, q->q_sq_dmamem, BUS_DMASYNC_POSTWRITE); 1789 nvme_dmamem_free(sc, q->q_cq_dmamem); 1790 nvme_dmamem_free(sc, q->q_sq_dmamem); 1791 kmem_free(q, sizeof(*q)); 1792 } 1793 1794 int 1795 nvme_intr(void *xsc) 1796 { 1797 struct nvme_softc *sc = xsc; 1798 1799 /* 1800 * INTx is level triggered, controller deasserts the interrupt only 1801 * when we advance command queue head via write to the doorbell. 1802 * Tell the controller to block the interrupts while we process 1803 * the queue(s). 1804 */ 1805 nvme_write4(sc, NVME_INTMS, 1); 1806 1807 softint_schedule(sc->sc_softih[0]); 1808 1809 /* don't know, might not have been for us */ 1810 return 1; 1811 } 1812 1813 void 1814 nvme_softintr_intx(void *xq) 1815 { 1816 struct nvme_queue *q = xq; 1817 struct nvme_softc *sc = q->q_sc; 1818 1819 nvme_q_complete(sc, sc->sc_admin_q); 1820 if (sc->sc_q != NULL) 1821 nvme_q_complete(sc, sc->sc_q[0]); 1822 1823 /* 1824 * Processing done, tell controller to issue interrupts again. There 1825 * is no race, as NVMe spec requires the controller to maintain state, 1826 * and assert the interrupt whenever there are unacknowledged 1827 * completion queue entries. 1828 */ 1829 nvme_write4(sc, NVME_INTMC, 1); 1830 } 1831 1832 int 1833 nvme_intr_msi(void *xq) 1834 { 1835 struct nvme_queue *q = xq; 1836 1837 KASSERT(q && q->q_sc && q->q_sc->sc_softih 1838 && q->q_sc->sc_softih[q->q_id]); 1839 1840 /* 1841 * MSI/MSI-X are edge triggered, so can handover processing to softint 1842 * without masking the interrupt. 1843 */ 1844 softint_schedule(q->q_sc->sc_softih[q->q_id]); 1845 1846 return 1; 1847 } 1848 1849 void 1850 nvme_softintr_msi(void *xq) 1851 { 1852 struct nvme_queue *q = xq; 1853 struct nvme_softc *sc = q->q_sc; 1854 1855 nvme_q_complete(sc, q); 1856 } 1857 1858 static struct nvme_dmamem * 1859 nvme_dmamem_alloc(struct nvme_softc *sc, size_t size) 1860 { 1861 struct nvme_dmamem *ndm; 1862 int nsegs; 1863 1864 ndm = kmem_zalloc(sizeof(*ndm), KM_SLEEP); 1865 if (ndm == NULL) 1866 return NULL; 1867 1868 ndm->ndm_size = size; 1869 1870 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1871 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &ndm->ndm_map) != 0) 1872 goto ndmfree; 1873 1874 if (bus_dmamem_alloc(sc->sc_dmat, size, sc->sc_mps, 0, &ndm->ndm_seg, 1875 1, &nsegs, BUS_DMA_WAITOK) != 0) 1876 goto destroy; 1877 1878 if (bus_dmamem_map(sc->sc_dmat, &ndm->ndm_seg, nsegs, size, 1879 &ndm->ndm_kva, BUS_DMA_WAITOK) != 0) 1880 goto free; 1881 memset(ndm->ndm_kva, 0, size); 1882 1883 if (bus_dmamap_load(sc->sc_dmat, ndm->ndm_map, ndm->ndm_kva, size, 1884 NULL, BUS_DMA_WAITOK) != 0) 1885 goto unmap; 1886 1887 return ndm; 1888 1889 unmap: 1890 bus_dmamem_unmap(sc->sc_dmat, ndm->ndm_kva, size); 1891 free: 1892 bus_dmamem_free(sc->sc_dmat, &ndm->ndm_seg, 1); 1893 destroy: 1894 bus_dmamap_destroy(sc->sc_dmat, ndm->ndm_map); 1895 ndmfree: 1896 kmem_free(ndm, sizeof(*ndm)); 1897 return NULL; 1898 } 1899 1900 static void 1901 nvme_dmamem_sync(struct nvme_softc *sc, struct nvme_dmamem *mem, int ops) 1902 { 1903 bus_dmamap_sync(sc->sc_dmat, NVME_DMA_MAP(mem), 1904 0, NVME_DMA_LEN(mem), ops); 1905 } 1906 1907 void 1908 nvme_dmamem_free(struct nvme_softc *sc, struct nvme_dmamem *ndm) 1909 { 1910 bus_dmamap_unload(sc->sc_dmat, ndm->ndm_map); 1911 bus_dmamem_unmap(sc->sc_dmat, ndm->ndm_kva, ndm->ndm_size); 1912 bus_dmamem_free(sc->sc_dmat, &ndm->ndm_seg, 1); 1913 bus_dmamap_destroy(sc->sc_dmat, ndm->ndm_map); 1914 kmem_free(ndm, sizeof(*ndm)); 1915 } 1916 1917 /* 1918 * ioctl 1919 */ 1920 1921 dev_type_open(nvmeopen); 1922 dev_type_close(nvmeclose); 1923 dev_type_ioctl(nvmeioctl); 1924 1925 const struct cdevsw nvme_cdevsw = { 1926 .d_open = nvmeopen, 1927 .d_close = nvmeclose, 1928 .d_read = noread, 1929 .d_write = nowrite, 1930 .d_ioctl = nvmeioctl, 1931 .d_stop = nostop, 1932 .d_tty = notty, 1933 .d_poll = nopoll, 1934 .d_mmap = nommap, 1935 .d_kqfilter = nokqfilter, 1936 .d_discard = nodiscard, 1937 .d_flag = D_OTHER, 1938 }; 1939 1940 /* 1941 * Accept an open operation on the control device. 1942 */ 1943 int 1944 nvmeopen(dev_t dev, int flag, int mode, struct lwp *l) 1945 { 1946 struct nvme_softc *sc; 1947 int unit = minor(dev) / 0x10000; 1948 int nsid = minor(dev) & 0xffff; 1949 int nsidx; 1950 1951 if ((sc = device_lookup_private(&nvme_cd, unit)) == NULL) 1952 return ENXIO; 1953 if ((sc->sc_flags & NVME_F_ATTACHED) == 0) 1954 return ENXIO; 1955 1956 if (nsid == 0) { 1957 /* controller */ 1958 if (ISSET(sc->sc_flags, NVME_F_OPEN)) 1959 return EBUSY; 1960 SET(sc->sc_flags, NVME_F_OPEN); 1961 } else { 1962 /* namespace */ 1963 nsidx = nsid - 1; 1964 if (nsidx >= sc->sc_nn || sc->sc_namespaces[nsidx].dev == NULL) 1965 return ENXIO; 1966 if (ISSET(sc->sc_namespaces[nsidx].flags, NVME_NS_F_OPEN)) 1967 return EBUSY; 1968 SET(sc->sc_namespaces[nsidx].flags, NVME_NS_F_OPEN); 1969 } 1970 return 0; 1971 } 1972 1973 /* 1974 * Accept the last close on the control device. 1975 */ 1976 int 1977 nvmeclose(dev_t dev, int flag, int mode, struct lwp *l) 1978 { 1979 struct nvme_softc *sc; 1980 int unit = minor(dev) / 0x10000; 1981 int nsid = minor(dev) & 0xffff; 1982 int nsidx; 1983 1984 sc = device_lookup_private(&nvme_cd, unit); 1985 if (sc == NULL) 1986 return ENXIO; 1987 1988 if (nsid == 0) { 1989 /* controller */ 1990 CLR(sc->sc_flags, NVME_F_OPEN); 1991 } else { 1992 /* namespace */ 1993 nsidx = nsid - 1; 1994 if (nsidx >= sc->sc_nn) 1995 return ENXIO; 1996 CLR(sc->sc_namespaces[nsidx].flags, NVME_NS_F_OPEN); 1997 } 1998 1999 return 0; 2000 } 2001 2002 /* 2003 * Handle control operations. 2004 */ 2005 int 2006 nvmeioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 2007 { 2008 struct nvme_softc *sc; 2009 int unit = minor(dev) / 0x10000; 2010 int nsid = minor(dev) & 0xffff; 2011 struct nvme_pt_command *pt; 2012 2013 sc = device_lookup_private(&nvme_cd, unit); 2014 if (sc == NULL) 2015 return ENXIO; 2016 2017 switch (cmd) { 2018 case NVME_PASSTHROUGH_CMD: 2019 pt = data; 2020 return nvme_command_passthrough(sc, data, 2021 nsid == 0 ? pt->cmd.nsid : nsid, l, nsid == 0); 2022 } 2023 2024 return ENOTTY; 2025 } 2026
Indexes created Sun Sep 28 07:09:56 GMT 2025