nvme.c revision 1.68
1 /* $NetBSD: nvme.c,v 1.68 2024/03/10 04:49:22 mrg Exp $ */ 2 /* $OpenBSD: nvme.c,v 1.49 2016/04/18 05:59:50 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2014 David Gwynne <dlg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __KERNEL_RCSID(0, "$NetBSD: nvme.c,v 1.68 2024/03/10 04:49:22 mrg Exp $"); 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/kernel.h> 26 #include <sys/atomic.h> 27 #include <sys/bus.h> 28 #include <sys/buf.h> 29 #include <sys/conf.h> 30 #include <sys/device.h> 31 #include <sys/kmem.h> 32 #include <sys/once.h> 33 #include <sys/proc.h> 34 #include <sys/queue.h> 35 #include <sys/mutex.h> 36 37 #include <uvm/uvm_extern.h> 38 39 #include <dev/ic/nvmereg.h> 40 #include <dev/ic/nvmevar.h> 41 #include <dev/ic/nvmeio.h> 42 43 #include "ioconf.h" 44 #include "locators.h" 45 46 #define B4_CHK_RDY_DELAY_MS 2300 /* workaround controller bug */ 47 48 int nvme_adminq_size = 32; 49 int nvme_ioq_size = 1024; 50 51 static int nvme_print(void *, const char *); 52 53 static int nvme_ready(struct nvme_softc *, uint32_t); 54 static int nvme_enable(struct nvme_softc *, u_int); 55 static int nvme_disable(struct nvme_softc *); 56 static int nvme_shutdown(struct nvme_softc *); 57 58 uint32_t nvme_op_sq_enter(struct nvme_softc *, 59 struct nvme_queue *, struct nvme_ccb *); 60 void nvme_op_sq_leave(struct nvme_softc *, 61 struct nvme_queue *, struct nvme_ccb *); 62 uint32_t nvme_op_sq_enter_locked(struct nvme_softc *, 63 struct nvme_queue *, struct nvme_ccb *); 64 void nvme_op_sq_leave_locked(struct nvme_softc *, 65 struct nvme_queue *, struct nvme_ccb *); 66 67 void nvme_op_cq_done(struct nvme_softc *, 68 struct nvme_queue *, struct nvme_ccb *); 69 70 static const struct nvme_ops nvme_ops = { 71 .op_sq_enter = nvme_op_sq_enter, 72 .op_sq_leave = nvme_op_sq_leave, 73 .op_sq_enter_locked = nvme_op_sq_enter_locked, 74 .op_sq_leave_locked = nvme_op_sq_leave_locked, 75 76 .op_cq_done = nvme_op_cq_done, 77 }; 78 79 #ifdef NVME_DEBUG 80 static void nvme_dumpregs(struct nvme_softc *); 81 #endif 82 static int nvme_identify(struct nvme_softc *, u_int); 83 static void nvme_fill_identify(struct nvme_queue *, struct nvme_ccb *, 84 void *); 85 86 static int nvme_ccbs_alloc(struct nvme_queue *, uint16_t); 87 static void nvme_ccbs_free(struct nvme_queue *); 88 89 static struct nvme_ccb * 90 nvme_ccb_get(struct nvme_queue *, bool); 91 static struct nvme_ccb * 92 nvme_ccb_get_bio(struct nvme_softc *, struct buf *, 93 struct nvme_queue **); 94 static void nvme_ccb_put(struct nvme_queue *, struct nvme_ccb *); 95 96 static int nvme_poll(struct nvme_softc *, struct nvme_queue *, 97 struct nvme_ccb *, void (*)(struct nvme_queue *, 98 struct nvme_ccb *, void *), int); 99 static void nvme_poll_fill(struct nvme_queue *, struct nvme_ccb *, void *); 100 static void nvme_poll_done(struct nvme_queue *, struct nvme_ccb *, 101 struct nvme_cqe *); 102 static void nvme_sqe_fill(struct nvme_queue *, struct nvme_ccb *, void *); 103 static void nvme_empty_done(struct nvme_queue *, struct nvme_ccb *, 104 struct nvme_cqe *); 105 106 static struct nvme_queue * 107 nvme_q_alloc(struct nvme_softc *, uint16_t, u_int, u_int); 108 static int nvme_q_create(struct nvme_softc *, struct nvme_queue *); 109 static void nvme_q_reset(struct nvme_softc *, struct nvme_queue *); 110 static int nvme_q_delete(struct nvme_softc *, struct nvme_queue *); 111 static void nvme_q_submit(struct nvme_softc *, struct nvme_queue *, 112 struct nvme_ccb *, void (*)(struct nvme_queue *, 113 struct nvme_ccb *, void *)); 114 static int nvme_q_complete(struct nvme_softc *, struct nvme_queue *q); 115 static void nvme_q_free(struct nvme_softc *, struct nvme_queue *); 116 static void nvme_q_wait_complete(struct nvme_softc *, struct nvme_queue *, 117 bool (*)(void *), void *); 118 119 static void nvme_ns_io_fill(struct nvme_queue *, struct nvme_ccb *, 120 void *); 121 static void nvme_ns_io_done(struct nvme_queue *, struct nvme_ccb *, 122 struct nvme_cqe *); 123 static void nvme_ns_sync_fill(struct nvme_queue *, struct nvme_ccb *, 124 void *); 125 static void nvme_ns_sync_done(struct nvme_queue *, struct nvme_ccb *, 126 struct nvme_cqe *); 127 static void nvme_getcache_fill(struct nvme_queue *, struct nvme_ccb *, 128 void *); 129 static void nvme_getcache_done(struct nvme_queue *, struct nvme_ccb *, 130 struct nvme_cqe *); 131 132 static void nvme_pt_fill(struct nvme_queue *, struct nvme_ccb *, 133 void *); 134 static void nvme_pt_done(struct nvme_queue *, struct nvme_ccb *, 135 struct nvme_cqe *); 136 static int nvme_command_passthrough(struct nvme_softc *, 137 struct nvme_pt_command *, uint32_t, struct lwp *, bool); 138 139 static int nvme_set_number_of_queues(struct nvme_softc *, u_int, u_int *, 140 u_int *); 141 142 #define NVME_TIMO_QOP 5 /* queue create and delete timeout */ 143 #define NVME_TIMO_IDENT 10 /* probe identify timeout */ 144 #define NVME_TIMO_PT -1 /* passthrough cmd timeout */ 145 #define NVME_TIMO_SY 60 /* sync cache timeout */ 146 147 /* 148 * Some controllers, at least Apple NVMe, always require split 149 * transfers, so don't use bus_space_{read,write}_8() on LP64. 150 */ 151 uint64_t 152 nvme_read8(struct nvme_softc *sc, bus_size_t r) 153 { 154 uint64_t v; 155 uint32_t *a = (uint32_t *)&v; 156 157 #if _BYTE_ORDER == _LITTLE_ENDIAN 158 a[0] = nvme_read4(sc, r); 159 a[1] = nvme_read4(sc, r + 4); 160 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 161 a[1] = nvme_read4(sc, r); 162 a[0] = nvme_read4(sc, r + 4); 163 #endif 164 165 return v; 166 } 167 168 void 169 nvme_write8(struct nvme_softc *sc, bus_size_t r, uint64_t v) 170 { 171 uint32_t *a = (uint32_t *)&v; 172 173 #if _BYTE_ORDER == _LITTLE_ENDIAN 174 nvme_write4(sc, r, a[0]); 175 nvme_write4(sc, r + 4, a[1]); 176 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 177 nvme_write4(sc, r, a[1]); 178 nvme_write4(sc, r + 4, a[0]); 179 #endif 180 } 181 182 #ifdef NVME_DEBUG 183 static __used void 184 nvme_dumpregs(struct nvme_softc *sc) 185 { 186 uint64_t r8; 187 uint32_t r4; 188 189 #define DEVNAME(_sc) device_xname((_sc)->sc_dev) 190 r8 = nvme_read8(sc, NVME_CAP); 191 printf("%s: cap 0x%016"PRIx64"\n", DEVNAME(sc), nvme_read8(sc, NVME_CAP)); 192 printf("%s: mpsmax %u (%u)\n", DEVNAME(sc), 193 (u_int)NVME_CAP_MPSMAX(r8), (1 << NVME_CAP_MPSMAX(r8))); 194 printf("%s: mpsmin %u (%u)\n", DEVNAME(sc), 195 (u_int)NVME_CAP_MPSMIN(r8), (1 << NVME_CAP_MPSMIN(r8))); 196 printf("%s: css %"PRIu64"\n", DEVNAME(sc), NVME_CAP_CSS(r8)); 197 printf("%s: nssrs %"PRIu64"\n", DEVNAME(sc), NVME_CAP_NSSRS(r8)); 198 printf("%s: dstrd %"PRIu64"\n", DEVNAME(sc), NVME_CAP_DSTRD(r8)); 199 printf("%s: to %"PRIu64" msec\n", DEVNAME(sc), NVME_CAP_TO(r8)); 200 printf("%s: ams %"PRIu64"\n", DEVNAME(sc), NVME_CAP_AMS(r8)); 201 printf("%s: cqr %"PRIu64"\n", DEVNAME(sc), NVME_CAP_CQR(r8)); 202 printf("%s: mqes %"PRIu64"\n", DEVNAME(sc), NVME_CAP_MQES(r8)); 203 204 printf("%s: vs 0x%04x\n", DEVNAME(sc), nvme_read4(sc, NVME_VS)); 205 206 r4 = nvme_read4(sc, NVME_CC); 207 printf("%s: cc 0x%04x\n", DEVNAME(sc), r4); 208 printf("%s: iocqes %u (%u)\n", DEVNAME(sc), NVME_CC_IOCQES_R(r4), 209 (1 << NVME_CC_IOCQES_R(r4))); 210 printf("%s: iosqes %u (%u)\n", DEVNAME(sc), NVME_CC_IOSQES_R(r4), 211 (1 << NVME_CC_IOSQES_R(r4))); 212 printf("%s: shn %u\n", DEVNAME(sc), NVME_CC_SHN_R(r4)); 213 printf("%s: ams %u\n", DEVNAME(sc), NVME_CC_AMS_R(r4)); 214 printf("%s: mps %u (%u)\n", DEVNAME(sc), NVME_CC_MPS_R(r4), 215 (1 << NVME_CC_MPS_R(r4))); 216 printf("%s: css %u\n", DEVNAME(sc), NVME_CC_CSS_R(r4)); 217 printf("%s: en %u\n", DEVNAME(sc), ISSET(r4, NVME_CC_EN) ? 1 : 0); 218 219 r4 = nvme_read4(sc, NVME_CSTS); 220 printf("%s: csts 0x%08x\n", DEVNAME(sc), r4); 221 printf("%s: rdy %u\n", DEVNAME(sc), r4 & NVME_CSTS_RDY); 222 printf("%s: cfs %u\n", DEVNAME(sc), r4 & NVME_CSTS_CFS); 223 printf("%s: shst %x\n", DEVNAME(sc), r4 & NVME_CSTS_SHST_MASK); 224 225 r4 = nvme_read4(sc, NVME_AQA); 226 printf("%s: aqa 0x%08x\n", DEVNAME(sc), r4); 227 printf("%s: acqs %u\n", DEVNAME(sc), NVME_AQA_ACQS_R(r4)); 228 printf("%s: asqs %u\n", DEVNAME(sc), NVME_AQA_ASQS_R(r4)); 229 230 printf("%s: asq 0x%016"PRIx64"\n", DEVNAME(sc), nvme_read8(sc, NVME_ASQ)); 231 printf("%s: acq 0x%016"PRIx64"\n", DEVNAME(sc), nvme_read8(sc, NVME_ACQ)); 232 #undef DEVNAME 233 } 234 #endif /* NVME_DEBUG */ 235 236 static int 237 nvme_ready(struct nvme_softc *sc, uint32_t rdy) 238 { 239 u_int i = 0; 240 241 while ((nvme_read4(sc, NVME_CSTS) & NVME_CSTS_RDY) != rdy) { 242 if (i++ > sc->sc_rdy_to) 243 return ENXIO; 244 245 delay(1000); 246 nvme_barrier(sc, NVME_CSTS, 4, BUS_SPACE_BARRIER_READ); 247 } 248 249 return 0; 250 } 251 252 static int 253 nvme_enable(struct nvme_softc *sc, u_int mps) 254 { 255 uint32_t cc, csts; 256 int error; 257 258 cc = nvme_read4(sc, NVME_CC); 259 csts = nvme_read4(sc, NVME_CSTS); 260 261 /* 262 * See note in nvme_disable. Short circuit if we're already enabled. 263 */ 264 if (ISSET(cc, NVME_CC_EN)) { 265 if (ISSET(csts, NVME_CSTS_RDY)) 266 return 0; 267 268 goto waitready; 269 } else { 270 /* EN == 0 already wait for RDY == 0 or fail */ 271 error = nvme_ready(sc, 0); 272 if (error) 273 return error; 274 } 275 276 if (sc->sc_ops->op_enable != NULL) 277 sc->sc_ops->op_enable(sc); 278 279 nvme_write8(sc, NVME_ASQ, NVME_DMA_DVA(sc->sc_admin_q->q_sq_dmamem)); 280 nvme_barrier(sc, 0, sc->sc_ios, BUS_SPACE_BARRIER_WRITE); 281 delay(5000); 282 nvme_write8(sc, NVME_ACQ, NVME_DMA_DVA(sc->sc_admin_q->q_cq_dmamem)); 283 nvme_barrier(sc, 0, sc->sc_ios, BUS_SPACE_BARRIER_WRITE); 284 delay(5000); 285 286 nvme_write4(sc, NVME_AQA, NVME_AQA_ACQS(sc->sc_admin_q->q_entries) | 287 NVME_AQA_ASQS(sc->sc_admin_q->q_entries)); 288 nvme_barrier(sc, 0, sc->sc_ios, BUS_SPACE_BARRIER_WRITE); 289 delay(5000); 290 291 CLR(cc, NVME_CC_IOCQES_MASK | NVME_CC_IOSQES_MASK | NVME_CC_SHN_MASK | 292 NVME_CC_AMS_MASK | NVME_CC_MPS_MASK | NVME_CC_CSS_MASK); 293 SET(cc, NVME_CC_IOSQES(ffs(64) - 1) | NVME_CC_IOCQES(ffs(16) - 1)); 294 SET(cc, NVME_CC_SHN(NVME_CC_SHN_NONE)); 295 SET(cc, NVME_CC_CSS(NVME_CC_CSS_NVM)); 296 SET(cc, NVME_CC_AMS(NVME_CC_AMS_RR)); 297 SET(cc, NVME_CC_MPS(mps)); 298 SET(cc, NVME_CC_EN); 299 300 nvme_write4(sc, NVME_CC, cc); 301 nvme_barrier(sc, 0, sc->sc_ios, 302 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 303 304 waitready: 305 return nvme_ready(sc, NVME_CSTS_RDY); 306 } 307 308 static int 309 nvme_disable(struct nvme_softc *sc) 310 { 311 uint32_t cc, csts; 312 int error; 313 314 cc = nvme_read4(sc, NVME_CC); 315 csts = nvme_read4(sc, NVME_CSTS); 316 317 /* 318 * Per 3.1.5 in NVME 1.3 spec, transitioning CC.EN from 0 to 1 319 * when CSTS.RDY is 1 or transitioning CC.EN from 1 to 0 when 320 * CSTS.RDY is 0 "has undefined results" So make sure that CSTS.RDY 321 * isn't the desired value. Short circuit if we're already disabled. 322 */ 323 if (ISSET(cc, NVME_CC_EN)) { 324 if (!ISSET(csts, NVME_CSTS_RDY)) { 325 /* EN == 1, wait for RDY == 1 or fail */ 326 error = nvme_ready(sc, NVME_CSTS_RDY); 327 if (error) 328 return error; 329 } 330 } else { 331 /* EN == 0 already wait for RDY == 0 */ 332 if (!ISSET(csts, NVME_CSTS_RDY)) 333 return 0; 334 335 goto waitready; 336 } 337 338 CLR(cc, NVME_CC_EN); 339 nvme_write4(sc, NVME_CC, cc); 340 nvme_barrier(sc, 0, sc->sc_ios, BUS_SPACE_BARRIER_READ); 341 342 /* 343 * Some drives have issues with accessing the mmio after we disable, 344 * so delay for a bit after we write the bit to cope with these issues. 345 */ 346 if (ISSET(sc->sc_quirks, NVME_QUIRK_DELAY_B4_CHK_RDY)) 347 delay(B4_CHK_RDY_DELAY_MS); 348 349 waitready: 350 return nvme_ready(sc, 0); 351 } 352 353 int 354 nvme_attach(struct nvme_softc *sc) 355 { 356 uint64_t cap; 357 uint32_t reg; 358 u_int mps = PAGE_SHIFT; 359 u_int ncq, nsq; 360 uint16_t adminq_entries = nvme_adminq_size; 361 uint16_t ioq_entries = nvme_ioq_size; 362 int i; 363 364 if (sc->sc_ops == NULL) 365 sc->sc_ops = &nvme_ops; 366 367 reg = nvme_read4(sc, NVME_VS); 368 if (reg == 0xffffffff) { 369 aprint_error_dev(sc->sc_dev, "invalid mapping\n"); 370 return 1; 371 } 372 373 if (NVME_VS_TER(reg) == 0) 374 aprint_normal_dev(sc->sc_dev, "NVMe %d.%d\n", NVME_VS_MJR(reg), 375 NVME_VS_MNR(reg)); 376 else 377 aprint_normal_dev(sc->sc_dev, "NVMe %d.%d.%d\n", NVME_VS_MJR(reg), 378 NVME_VS_MNR(reg), NVME_VS_TER(reg)); 379 380 cap = nvme_read8(sc, NVME_CAP); 381 sc->sc_dstrd = NVME_CAP_DSTRD(cap); 382 if (NVME_CAP_MPSMIN(cap) > PAGE_SHIFT) { 383 aprint_error_dev(sc->sc_dev, "NVMe minimum page size %u " 384 "is greater than CPU page size %u\n", 385 1 << NVME_CAP_MPSMIN(cap), 1 << PAGE_SHIFT); 386 return 1; 387 } 388 if (NVME_CAP_MPSMAX(cap) < mps) 389 mps = NVME_CAP_MPSMAX(cap); 390 if (ioq_entries > NVME_CAP_MQES(cap)) 391 ioq_entries = NVME_CAP_MQES(cap); 392 393 /* set initial values to be used for admin queue during probe */ 394 sc->sc_rdy_to = NVME_CAP_TO(cap); 395 sc->sc_mps = 1 << mps; 396 sc->sc_mdts = MAXPHYS; 397 sc->sc_max_sgl = btoc(round_page(sc->sc_mdts)); 398 399 if (nvme_disable(sc) != 0) { 400 aprint_error_dev(sc->sc_dev, "unable to disable controller\n"); 401 return 1; 402 } 403 404 sc->sc_admin_q = nvme_q_alloc(sc, NVME_ADMIN_Q, adminq_entries, 405 sc->sc_dstrd); 406 if (sc->sc_admin_q == NULL) { 407 aprint_error_dev(sc->sc_dev, 408 "unable to allocate admin queue\n"); 409 return 1; 410 } 411 if (sc->sc_intr_establish(sc, NVME_ADMIN_Q, sc->sc_admin_q)) 412 goto free_admin_q; 413 414 if (nvme_enable(sc, mps) != 0) { 415 aprint_error_dev(sc->sc_dev, "unable to enable controller\n"); 416 goto disestablish_admin_q; 417 } 418 419 if (nvme_identify(sc, NVME_CAP_MPSMIN(cap)) != 0) { 420 aprint_error_dev(sc->sc_dev, "unable to identify controller\n"); 421 goto disable; 422 } 423 if (sc->sc_nn == 0) { 424 aprint_error_dev(sc->sc_dev, "namespace not found\n"); 425 goto disable; 426 } 427 428 /* we know how big things are now */ 429 sc->sc_max_sgl = sc->sc_mdts / sc->sc_mps; 430 431 /* reallocate ccbs of admin queue with new max sgl. */ 432 nvme_ccbs_free(sc->sc_admin_q); 433 nvme_ccbs_alloc(sc->sc_admin_q, sc->sc_admin_q->q_entries); 434 435 if (sc->sc_use_mq) { 436 /* Limit the number of queues to the number allocated in HW */ 437 if (nvme_set_number_of_queues(sc, sc->sc_nq, &ncq, &nsq) != 0) { 438 aprint_error_dev(sc->sc_dev, 439 "unable to get number of queues\n"); 440 goto disable; 441 } 442 if (sc->sc_nq > ncq) 443 sc->sc_nq = ncq; 444 if (sc->sc_nq > nsq) 445 sc->sc_nq = nsq; 446 } 447 448 sc->sc_q = kmem_zalloc(sizeof(*sc->sc_q) * sc->sc_nq, KM_SLEEP); 449 for (i = 0; i < sc->sc_nq; i++) { 450 sc->sc_q[i] = nvme_q_alloc(sc, i + 1, ioq_entries, 451 sc->sc_dstrd); 452 if (sc->sc_q[i] == NULL) { 453 aprint_error_dev(sc->sc_dev, 454 "unable to allocate io queue\n"); 455 goto free_q; 456 } 457 if (nvme_q_create(sc, sc->sc_q[i]) != 0) { 458 aprint_error_dev(sc->sc_dev, 459 "unable to create io queue\n"); 460 nvme_q_free(sc, sc->sc_q[i]); 461 goto free_q; 462 } 463 } 464 465 if (!sc->sc_use_mq) 466 nvme_write4(sc, NVME_INTMC, 1); 467 468 /* probe subdevices */ 469 sc->sc_namespaces = kmem_zalloc(sizeof(*sc->sc_namespaces) * sc->sc_nn, 470 KM_SLEEP); 471 nvme_rescan(sc->sc_dev, NULL, NULL); 472 473 return 0; 474 475 free_q: 476 while (--i >= 0) { 477 nvme_q_delete(sc, sc->sc_q[i]); 478 nvme_q_free(sc, sc->sc_q[i]); 479 } 480 disable: 481 nvme_disable(sc); 482 disestablish_admin_q: 483 sc->sc_intr_disestablish(sc, NVME_ADMIN_Q); 484 free_admin_q: 485 nvme_q_free(sc, sc->sc_admin_q); 486 487 return 1; 488 } 489 490 int 491 nvme_rescan(device_t self, const char *ifattr, const int *locs) 492 { 493 struct nvme_softc *sc = device_private(self); 494 struct nvme_attach_args naa; 495 struct nvm_namespace_format *f; 496 struct nvme_namespace *ns; 497 uint64_t cap; 498 int ioq_entries = nvme_ioq_size; 499 int i, mlocs[NVMECF_NLOCS]; 500 int error; 501 502 cap = nvme_read8(sc, NVME_CAP); 503 if (ioq_entries > NVME_CAP_MQES(cap)) 504 ioq_entries = NVME_CAP_MQES(cap); 505 506 for (i = 1; i <= sc->sc_nn; i++) { 507 if (sc->sc_namespaces[i - 1].dev) 508 continue; 509 510 /* identify to check for availability */ 511 error = nvme_ns_identify(sc, i); 512 if (error) { 513 aprint_error_dev(self, "couldn't identify namespace #%d\n", i); 514 continue; 515 } 516 517 ns = nvme_ns_get(sc, i); 518 KASSERT(ns); 519 520 f = &ns->ident->lbaf[NVME_ID_NS_FLBAS(ns->ident->flbas)]; 521 522 /* 523 * NVME1.0e 6.11 Identify command 524 * 525 * LBADS values smaller than 9 are not supported, a value 526 * of zero means that the format is not used. 527 */ 528 if (f->lbads < 9) { 529 if (f->lbads > 0) 530 aprint_error_dev(self, 531 "unsupported logical data size %u\n", f->lbads); 532 continue; 533 } 534 535 mlocs[NVMECF_NSID] = i; 536 537 memset(&naa, 0, sizeof(naa)); 538 naa.naa_nsid = i; 539 naa.naa_qentries = (ioq_entries - 1) * sc->sc_nq; 540 naa.naa_maxphys = sc->sc_mdts; 541 naa.naa_typename = sc->sc_modelname; 542 sc->sc_namespaces[i - 1].dev = 543 config_found(sc->sc_dev, &naa, nvme_print, 544 CFARGS(.submatch = config_stdsubmatch, 545 .locators = mlocs)); 546 } 547 return 0; 548 } 549 550 static int 551 nvme_print(void *aux, const char *pnp) 552 { 553 struct nvme_attach_args *naa = aux; 554 555 if (pnp) 556 aprint_normal("ld at %s", pnp); 557 558 if (naa->naa_nsid > 0) 559 aprint_normal(" nsid %d", naa->naa_nsid); 560 561 return UNCONF; 562 } 563 564 int 565 nvme_detach(struct nvme_softc *sc, int flags) 566 { 567 int i, error; 568 569 error = config_detach_children(sc->sc_dev, flags); 570 if (error) 571 return error; 572 573 error = nvme_shutdown(sc); 574 if (error) 575 return error; 576 577 /* from now on we are committed to detach, following will never fail */ 578 sc->sc_intr_disestablish(sc, NVME_ADMIN_Q); 579 for (i = 0; i < sc->sc_nq; i++) 580 nvme_q_free(sc, sc->sc_q[i]); 581 kmem_free(sc->sc_q, sizeof(*sc->sc_q) * sc->sc_nq); 582 nvme_q_free(sc, sc->sc_admin_q); 583 584 return 0; 585 } 586 587 int 588 nvme_suspend(struct nvme_softc *sc) 589 { 590 591 return nvme_shutdown(sc); 592 } 593 594 int 595 nvme_resume(struct nvme_softc *sc) 596 { 597 int i, error; 598 599 error = nvme_disable(sc); 600 if (error) { 601 device_printf(sc->sc_dev, "unable to disable controller\n"); 602 return error; 603 } 604 605 nvme_q_reset(sc, sc->sc_admin_q); 606 607 error = nvme_enable(sc, ffs(sc->sc_mps) - 1); 608 if (error) { 609 device_printf(sc->sc_dev, "unable to enable controller\n"); 610 return error; 611 } 612 613 for (i = 0; i < sc->sc_nq; i++) { 614 nvme_q_reset(sc, sc->sc_q[i]); 615 if (nvme_q_create(sc, sc->sc_q[i]) != 0) { 616 error = EIO; 617 device_printf(sc->sc_dev, "unable to create io q %d" 618 "\n", i); 619 goto disable; 620 } 621 } 622 623 if (!sc->sc_use_mq) 624 nvme_write4(sc, NVME_INTMC, 1); 625 626 return 0; 627 628 disable: 629 (void)nvme_disable(sc); 630 631 return error; 632 } 633 634 static int 635 nvme_shutdown(struct nvme_softc *sc) 636 { 637 uint32_t cc, csts; 638 bool disabled = false; 639 int i; 640 641 if (!sc->sc_use_mq) 642 nvme_write4(sc, NVME_INTMS, 1); 643 644 for (i = 0; i < sc->sc_nq; i++) { 645 if (nvme_q_delete(sc, sc->sc_q[i]) != 0) { 646 aprint_error_dev(sc->sc_dev, 647 "unable to delete io queue %d, disabling\n", i + 1); 648 disabled = true; 649 } 650 } 651 if (disabled) 652 goto disable; 653 654 cc = nvme_read4(sc, NVME_CC); 655 CLR(cc, NVME_CC_SHN_MASK); 656 SET(cc, NVME_CC_SHN(NVME_CC_SHN_NORMAL)); 657 nvme_write4(sc, NVME_CC, cc); 658 659 for (i = 0; i < 4000; i++) { 660 nvme_barrier(sc, 0, sc->sc_ios, 661 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 662 csts = nvme_read4(sc, NVME_CSTS); 663 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_DONE) 664 return 0; 665 666 delay(1000); 667 } 668 669 aprint_error_dev(sc->sc_dev, "unable to shudown, disabling\n"); 670 671 disable: 672 nvme_disable(sc); 673 return 0; 674 } 675 676 void 677 nvme_childdet(device_t self, device_t child) 678 { 679 struct nvme_softc *sc = device_private(self); 680 int i; 681 682 for (i = 0; i < sc->sc_nn; i++) { 683 if (sc->sc_namespaces[i].dev == child) { 684 /* Already freed ns->ident. */ 685 sc->sc_namespaces[i].dev = NULL; 686 break; 687 } 688 } 689 } 690 691 int 692 nvme_ns_identify(struct nvme_softc *sc, uint16_t nsid) 693 { 694 struct nvme_sqe sqe; 695 struct nvm_identify_namespace *identify; 696 struct nvme_dmamem *mem; 697 struct nvme_ccb *ccb; 698 struct nvme_namespace *ns; 699 int rv; 700 701 KASSERT(nsid > 0); 702 703 ns = nvme_ns_get(sc, nsid); 704 KASSERT(ns); 705 706 if (ns->ident != NULL) 707 return 0; 708 709 ccb = nvme_ccb_get(sc->sc_admin_q, false); 710 KASSERT(ccb != NULL); /* it's a bug if we don't have spare ccb here */ 711 712 mem = nvme_dmamem_alloc(sc, sizeof(*identify)); 713 if (mem == NULL) { 714 nvme_ccb_put(sc->sc_admin_q, ccb); 715 return ENOMEM; 716 } 717 718 memset(&sqe, 0, sizeof(sqe)); 719 sqe.opcode = NVM_ADMIN_IDENTIFY; 720 htolem32(&sqe.nsid, nsid); 721 htolem64(&sqe.entry.prp[0], NVME_DMA_DVA(mem)); 722 htolem32(&sqe.cdw10, 0); 723 724 ccb->ccb_done = nvme_empty_done; 725 ccb->ccb_cookie = &sqe; 726 727 nvme_dmamem_sync(sc, mem, BUS_DMASYNC_PREREAD); 728 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_sqe_fill, NVME_TIMO_IDENT); 729 nvme_dmamem_sync(sc, mem, BUS_DMASYNC_POSTREAD); 730 731 nvme_ccb_put(sc->sc_admin_q, ccb); 732 733 if (rv != 0) { 734 rv = EIO; 735 goto done; 736 } 737 738 /* commit */ 739 740 identify = kmem_zalloc(sizeof(*identify), KM_SLEEP); 741 *identify = *((volatile struct nvm_identify_namespace *)NVME_DMA_KVA(mem)); 742 743 /* Convert data to host endian */ 744 nvme_identify_namespace_swapbytes(identify); 745 746 ns->ident = identify; 747 748 done: 749 nvme_dmamem_free(sc, mem); 750 751 return rv; 752 } 753 754 int 755 nvme_ns_dobio(struct nvme_softc *sc, uint16_t nsid, void *cookie, 756 struct buf *bp, void *data, size_t datasize, 757 int secsize, daddr_t blkno, int flags, nvme_nnc_done nnc_done) 758 { 759 struct nvme_queue *q; 760 struct nvme_ccb *ccb; 761 bus_dmamap_t dmap; 762 int i, error; 763 764 ccb = nvme_ccb_get_bio(sc, bp, &q); 765 if (ccb == NULL) 766 return EAGAIN; 767 768 ccb->ccb_done = nvme_ns_io_done; 769 ccb->ccb_cookie = cookie; 770 771 /* namespace context */ 772 ccb->nnc_nsid = nsid; 773 ccb->nnc_flags = flags; 774 ccb->nnc_buf = bp; 775 ccb->nnc_datasize = datasize; 776 ccb->nnc_secsize = secsize; 777 ccb->nnc_blkno = blkno; 778 ccb->nnc_done = nnc_done; 779 780 dmap = ccb->ccb_dmamap; 781 error = bus_dmamap_load(sc->sc_dmat, dmap, data, 782 datasize, NULL, 783 (ISSET(flags, NVME_NS_CTX_F_POLL) ? 784 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 785 (ISSET(flags, NVME_NS_CTX_F_READ) ? 786 BUS_DMA_READ : BUS_DMA_WRITE)); 787 if (error) { 788 nvme_ccb_put(q, ccb); 789 return error; 790 } 791 792 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 793 ISSET(flags, NVME_NS_CTX_F_READ) ? 794 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 795 796 if (dmap->dm_nsegs > 2) { 797 for (i = 1; i < dmap->dm_nsegs; i++) { 798 htolem64(&ccb->ccb_prpl[i - 1], 799 dmap->dm_segs[i].ds_addr); 800 } 801 bus_dmamap_sync(sc->sc_dmat, 802 NVME_DMA_MAP(q->q_ccb_prpls), 803 ccb->ccb_prpl_off, 804 sizeof(*ccb->ccb_prpl) * (dmap->dm_nsegs - 1), 805 BUS_DMASYNC_PREWRITE); 806 } 807 808 if (ISSET(flags, NVME_NS_CTX_F_POLL)) { 809 if (nvme_poll(sc, q, ccb, nvme_ns_io_fill, NVME_TIMO_PT) != 0) 810 return EIO; 811 return 0; 812 } 813 814 nvme_q_submit(sc, q, ccb, nvme_ns_io_fill); 815 return 0; 816 } 817 818 static void 819 nvme_ns_io_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 820 { 821 struct nvme_sqe_io *sqe = slot; 822 bus_dmamap_t dmap = ccb->ccb_dmamap; 823 824 sqe->opcode = ISSET(ccb->nnc_flags, NVME_NS_CTX_F_READ) ? 825 NVM_CMD_READ : NVM_CMD_WRITE; 826 htolem32(&sqe->nsid, ccb->nnc_nsid); 827 828 htolem64(&sqe->entry.prp[0], dmap->dm_segs[0].ds_addr); 829 switch (dmap->dm_nsegs) { 830 case 1: 831 break; 832 case 2: 833 htolem64(&sqe->entry.prp[1], dmap->dm_segs[1].ds_addr); 834 break; 835 default: 836 /* the prp list is already set up and synced */ 837 htolem64(&sqe->entry.prp[1], ccb->ccb_prpl_dva); 838 break; 839 } 840 841 htolem64(&sqe->slba, ccb->nnc_blkno); 842 843 if (ISSET(ccb->nnc_flags, NVME_NS_CTX_F_FUA)) 844 htolem16(&sqe->ioflags, NVM_SQE_IO_FUA); 845 846 /* guaranteed by upper layers, but check just in case */ 847 KASSERT((ccb->nnc_datasize % ccb->nnc_secsize) == 0); 848 htolem16(&sqe->nlb, (ccb->nnc_datasize / ccb->nnc_secsize) - 1); 849 } 850 851 static void 852 nvme_ns_io_done(struct nvme_queue *q, struct nvme_ccb *ccb, 853 struct nvme_cqe *cqe) 854 { 855 struct nvme_softc *sc = q->q_sc; 856 bus_dmamap_t dmap = ccb->ccb_dmamap; 857 void *nnc_cookie = ccb->ccb_cookie; 858 nvme_nnc_done nnc_done = ccb->nnc_done; 859 struct buf *bp = ccb->nnc_buf; 860 861 if (dmap->dm_nsegs > 2) { 862 bus_dmamap_sync(sc->sc_dmat, 863 NVME_DMA_MAP(q->q_ccb_prpls), 864 ccb->ccb_prpl_off, 865 sizeof(*ccb->ccb_prpl) * (dmap->dm_nsegs - 1), 866 BUS_DMASYNC_POSTWRITE); 867 } 868 869 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 870 ISSET(ccb->nnc_flags, NVME_NS_CTX_F_READ) ? 871 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 872 873 bus_dmamap_unload(sc->sc_dmat, dmap); 874 nvme_ccb_put(q, ccb); 875 876 nnc_done(nnc_cookie, bp, lemtoh16(&cqe->flags), lemtoh32(&cqe->cdw0)); 877 } 878 879 /* 880 * If there is no volatile write cache, it makes no sense to issue 881 * flush commands or query for the status. 882 */ 883 static bool 884 nvme_has_volatile_write_cache(struct nvme_softc *sc) 885 { 886 /* sc_identify is filled during attachment */ 887 return ((sc->sc_identify.vwc & NVME_ID_CTRLR_VWC_PRESENT) != 0); 888 } 889 890 static bool 891 nvme_ns_sync_finished(void *cookie) 892 { 893 int *result = cookie; 894 895 return (*result != 0); 896 } 897 898 int 899 nvme_ns_sync(struct nvme_softc *sc, uint16_t nsid, int flags) 900 { 901 struct nvme_queue *q = nvme_get_q(sc); 902 struct nvme_ccb *ccb; 903 int result = 0; 904 905 if (!nvme_has_volatile_write_cache(sc)) { 906 /* cache not present, no value in trying to flush it */ 907 return 0; 908 } 909 910 ccb = nvme_ccb_get(q, true); 911 KASSERT(ccb != NULL); 912 913 ccb->ccb_done = nvme_ns_sync_done; 914 ccb->ccb_cookie = &result; 915 916 /* namespace context */ 917 ccb->nnc_nsid = nsid; 918 ccb->nnc_flags = flags; 919 ccb->nnc_done = NULL; 920 921 if (ISSET(flags, NVME_NS_CTX_F_POLL)) { 922 if (nvme_poll(sc, q, ccb, nvme_ns_sync_fill, NVME_TIMO_SY) != 0) 923 return EIO; 924 return 0; 925 } 926 927 nvme_q_submit(sc, q, ccb, nvme_ns_sync_fill); 928 929 /* wait for completion */ 930 nvme_q_wait_complete(sc, q, nvme_ns_sync_finished, &result); 931 KASSERT(result != 0); 932 933 return (result > 0) ? 0 : EIO; 934 } 935 936 static void 937 nvme_ns_sync_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 938 { 939 struct nvme_sqe *sqe = slot; 940 941 sqe->opcode = NVM_CMD_FLUSH; 942 htolem32(&sqe->nsid, ccb->nnc_nsid); 943 } 944 945 static void 946 nvme_ns_sync_done(struct nvme_queue *q, struct nvme_ccb *ccb, 947 struct nvme_cqe *cqe) 948 { 949 int *result = ccb->ccb_cookie; 950 uint16_t status = NVME_CQE_SC(lemtoh16(&cqe->flags)); 951 952 if (status == NVME_CQE_SC_SUCCESS) 953 *result = 1; 954 else 955 *result = -1; 956 957 nvme_ccb_put(q, ccb); 958 } 959 960 static bool 961 nvme_getcache_finished(void *xc) 962 { 963 int *addr = xc; 964 965 return (*addr != 0); 966 } 967 968 /* 969 * Get status of volatile write cache. Always asynchronous. 970 */ 971 int 972 nvme_admin_getcache(struct nvme_softc *sc, int *addr) 973 { 974 struct nvme_ccb *ccb; 975 struct nvme_queue *q = sc->sc_admin_q; 976 int result = 0, error; 977 978 if (!nvme_has_volatile_write_cache(sc)) { 979 /* cache simply not present */ 980 *addr = 0; 981 return 0; 982 } 983 984 ccb = nvme_ccb_get(q, true); 985 KASSERT(ccb != NULL); 986 987 ccb->ccb_done = nvme_getcache_done; 988 ccb->ccb_cookie = &result; 989 990 /* namespace context */ 991 ccb->nnc_flags = 0; 992 ccb->nnc_done = NULL; 993 994 nvme_q_submit(sc, q, ccb, nvme_getcache_fill); 995 996 /* wait for completion */ 997 nvme_q_wait_complete(sc, q, nvme_getcache_finished, &result); 998 KASSERT(result != 0); 999 1000 if (result > 0) { 1001 *addr = result; 1002 error = 0; 1003 } else 1004 error = EINVAL; 1005 1006 return error; 1007 } 1008 1009 static void 1010 nvme_getcache_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 1011 { 1012 struct nvme_sqe *sqe = slot; 1013 1014 sqe->opcode = NVM_ADMIN_GET_FEATURES; 1015 htolem32(&sqe->cdw10, NVM_FEATURE_VOLATILE_WRITE_CACHE); 1016 htolem32(&sqe->cdw11, NVM_VOLATILE_WRITE_CACHE_WCE); 1017 } 1018 1019 static void 1020 nvme_getcache_done(struct nvme_queue *q, struct nvme_ccb *ccb, 1021 struct nvme_cqe *cqe) 1022 { 1023 int *addr = ccb->ccb_cookie; 1024 uint16_t status = NVME_CQE_SC(lemtoh16(&cqe->flags)); 1025 uint32_t cdw0 = lemtoh32(&cqe->cdw0); 1026 int result; 1027 1028 if (status == NVME_CQE_SC_SUCCESS) { 1029 result = 0; 1030 1031 /* 1032 * DPO not supported, Dataset Management (DSM) field doesn't 1033 * specify the same semantics. FUA is always supported. 1034 */ 1035 result = DKCACHE_FUA; 1036 1037 if (cdw0 & NVM_VOLATILE_WRITE_CACHE_WCE) 1038 result |= DKCACHE_WRITE; 1039 1040 /* 1041 * If volatile write cache is present, the flag shall also be 1042 * settable. 1043 */ 1044 result |= DKCACHE_WCHANGE; 1045 1046 /* 1047 * ONCS field indicates whether the optional SAVE is also 1048 * supported for Set Features. According to spec v1.3, 1049 * Volatile Write Cache however doesn't support persistency 1050 * across power cycle/reset. 1051 */ 1052 1053 } else { 1054 result = -1; 1055 } 1056 1057 *addr = result; 1058 1059 nvme_ccb_put(q, ccb); 1060 } 1061 1062 struct nvme_setcache_state { 1063 int dkcache; 1064 int result; 1065 }; 1066 1067 static bool 1068 nvme_setcache_finished(void *xc) 1069 { 1070 struct nvme_setcache_state *st = xc; 1071 1072 return (st->result != 0); 1073 } 1074 1075 static void 1076 nvme_setcache_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 1077 { 1078 struct nvme_sqe *sqe = slot; 1079 struct nvme_setcache_state *st = ccb->ccb_cookie; 1080 1081 sqe->opcode = NVM_ADMIN_SET_FEATURES; 1082 htolem32(&sqe->cdw10, NVM_FEATURE_VOLATILE_WRITE_CACHE); 1083 if (st->dkcache & DKCACHE_WRITE) 1084 htolem32(&sqe->cdw11, NVM_VOLATILE_WRITE_CACHE_WCE); 1085 } 1086 1087 static void 1088 nvme_setcache_done(struct nvme_queue *q, struct nvme_ccb *ccb, 1089 struct nvme_cqe *cqe) 1090 { 1091 struct nvme_setcache_state *st = ccb->ccb_cookie; 1092 uint16_t status = NVME_CQE_SC(lemtoh16(&cqe->flags)); 1093 1094 if (status == NVME_CQE_SC_SUCCESS) { 1095 st->result = 1; 1096 } else { 1097 st->result = -1; 1098 } 1099 1100 nvme_ccb_put(q, ccb); 1101 } 1102 1103 /* 1104 * Set status of volatile write cache. Always asynchronous. 1105 */ 1106 int 1107 nvme_admin_setcache(struct nvme_softc *sc, int dkcache) 1108 { 1109 struct nvme_ccb *ccb; 1110 struct nvme_queue *q = sc->sc_admin_q; 1111 int error; 1112 struct nvme_setcache_state st; 1113 1114 if (!nvme_has_volatile_write_cache(sc)) { 1115 /* cache simply not present */ 1116 return EOPNOTSUPP; 1117 } 1118 1119 if (dkcache & ~(DKCACHE_WRITE)) { 1120 /* unsupported parameters */ 1121 return EOPNOTSUPP; 1122 } 1123 1124 ccb = nvme_ccb_get(q, true); 1125 KASSERT(ccb != NULL); 1126 1127 memset(&st, 0, sizeof(st)); 1128 st.dkcache = dkcache; 1129 1130 ccb->ccb_done = nvme_setcache_done; 1131 ccb->ccb_cookie = &st; 1132 1133 /* namespace context */ 1134 ccb->nnc_flags = 0; 1135 ccb->nnc_done = NULL; 1136 1137 nvme_q_submit(sc, q, ccb, nvme_setcache_fill); 1138 1139 /* wait for completion */ 1140 nvme_q_wait_complete(sc, q, nvme_setcache_finished, &st); 1141 KASSERT(st.result != 0); 1142 1143 if (st.result > 0) 1144 error = 0; 1145 else 1146 error = EINVAL; 1147 1148 return error; 1149 } 1150 1151 void 1152 nvme_ns_free(struct nvme_softc *sc, uint16_t nsid) 1153 { 1154 struct nvme_namespace *ns; 1155 struct nvm_identify_namespace *identify; 1156 1157 ns = nvme_ns_get(sc, nsid); 1158 KASSERT(ns); 1159 1160 identify = ns->ident; 1161 ns->ident = NULL; 1162 if (identify != NULL) 1163 kmem_free(identify, sizeof(*identify)); 1164 } 1165 1166 struct nvme_pt_state { 1167 struct nvme_pt_command *pt; 1168 bool finished; 1169 }; 1170 1171 static void 1172 nvme_pt_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 1173 { 1174 struct nvme_softc *sc = q->q_sc; 1175 struct nvme_sqe *sqe = slot; 1176 struct nvme_pt_state *state = ccb->ccb_cookie; 1177 struct nvme_pt_command *pt = state->pt; 1178 bus_dmamap_t dmap = ccb->ccb_dmamap; 1179 int i; 1180 1181 sqe->opcode = pt->cmd.opcode; 1182 htolem32(&sqe->nsid, pt->cmd.nsid); 1183 1184 if (pt->buf != NULL && pt->len > 0) { 1185 htolem64(&sqe->entry.prp[0], dmap->dm_segs[0].ds_addr); 1186 switch (dmap->dm_nsegs) { 1187 case 1: 1188 break; 1189 case 2: 1190 htolem64(&sqe->entry.prp[1], dmap->dm_segs[1].ds_addr); 1191 break; 1192 default: 1193 for (i = 1; i < dmap->dm_nsegs; i++) { 1194 htolem64(&ccb->ccb_prpl[i - 1], 1195 dmap->dm_segs[i].ds_addr); 1196 } 1197 bus_dmamap_sync(sc->sc_dmat, 1198 NVME_DMA_MAP(q->q_ccb_prpls), 1199 ccb->ccb_prpl_off, 1200 sizeof(*ccb->ccb_prpl) * (dmap->dm_nsegs - 1), 1201 BUS_DMASYNC_PREWRITE); 1202 htolem64(&sqe->entry.prp[1], ccb->ccb_prpl_dva); 1203 break; 1204 } 1205 } 1206 1207 htolem32(&sqe->cdw10, pt->cmd.cdw10); 1208 htolem32(&sqe->cdw11, pt->cmd.cdw11); 1209 htolem32(&sqe->cdw12, pt->cmd.cdw12); 1210 htolem32(&sqe->cdw13, pt->cmd.cdw13); 1211 htolem32(&sqe->cdw14, pt->cmd.cdw14); 1212 htolem32(&sqe->cdw15, pt->cmd.cdw15); 1213 } 1214 1215 static void 1216 nvme_pt_done(struct nvme_queue *q, struct nvme_ccb *ccb, struct nvme_cqe *cqe) 1217 { 1218 struct nvme_softc *sc = q->q_sc; 1219 struct nvme_pt_state *state = ccb->ccb_cookie; 1220 struct nvme_pt_command *pt = state->pt; 1221 bus_dmamap_t dmap = ccb->ccb_dmamap; 1222 1223 if (pt->buf != NULL && pt->len > 0) { 1224 if (dmap->dm_nsegs > 2) { 1225 bus_dmamap_sync(sc->sc_dmat, 1226 NVME_DMA_MAP(q->q_ccb_prpls), 1227 ccb->ccb_prpl_off, 1228 sizeof(*ccb->ccb_prpl) * (dmap->dm_nsegs - 1), 1229 BUS_DMASYNC_POSTWRITE); 1230 } 1231 1232 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 1233 pt->is_read ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1234 bus_dmamap_unload(sc->sc_dmat, dmap); 1235 } 1236 1237 pt->cpl.cdw0 = lemtoh32(&cqe->cdw0); 1238 pt->cpl.flags = lemtoh16(&cqe->flags) & ~NVME_CQE_PHASE; 1239 1240 state->finished = true; 1241 1242 nvme_ccb_put(q, ccb); 1243 } 1244 1245 static bool 1246 nvme_pt_finished(void *cookie) 1247 { 1248 struct nvme_pt_state *state = cookie; 1249 1250 return state->finished; 1251 } 1252 1253 static int 1254 nvme_command_passthrough(struct nvme_softc *sc, struct nvme_pt_command *pt, 1255 uint32_t nsid, struct lwp *l, bool is_adminq) 1256 { 1257 struct nvme_queue *q; 1258 struct nvme_ccb *ccb; 1259 void *buf = NULL; 1260 struct nvme_pt_state state; 1261 int error; 1262 1263 /* limit command size to maximum data transfer size */ 1264 if ((pt->buf == NULL && pt->len > 0) || 1265 (pt->buf != NULL && (pt->len == 0 || pt->len > sc->sc_mdts))) 1266 return EINVAL; 1267 1268 q = is_adminq ? sc->sc_admin_q : nvme_get_q(sc); 1269 ccb = nvme_ccb_get(q, true); 1270 KASSERT(ccb != NULL); 1271 1272 if (pt->buf != NULL) { 1273 KASSERT(pt->len > 0); 1274 buf = kmem_alloc(pt->len, KM_SLEEP); 1275 if (!pt->is_read) { 1276 error = copyin(pt->buf, buf, pt->len); 1277 if (error) 1278 goto kmem_free; 1279 } 1280 error = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap, buf, 1281 pt->len, NULL, 1282 BUS_DMA_WAITOK | 1283 (pt->is_read ? BUS_DMA_READ : BUS_DMA_WRITE)); 1284 if (error) 1285 goto kmem_free; 1286 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap, 1287 0, ccb->ccb_dmamap->dm_mapsize, 1288 pt->is_read ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1289 } 1290 1291 memset(&state, 0, sizeof(state)); 1292 state.pt = pt; 1293 state.finished = false; 1294 1295 ccb->ccb_done = nvme_pt_done; 1296 ccb->ccb_cookie = &state; 1297 1298 pt->cmd.nsid = nsid; 1299 1300 nvme_q_submit(sc, q, ccb, nvme_pt_fill); 1301 1302 /* wait for completion */ 1303 nvme_q_wait_complete(sc, q, nvme_pt_finished, &state); 1304 KASSERT(state.finished); 1305 1306 error = 0; 1307 1308 if (buf != NULL) { 1309 if (error == 0 && pt->is_read) 1310 error = copyout(buf, pt->buf, pt->len); 1311 kmem_free: 1312 kmem_free(buf, pt->len); 1313 } 1314 1315 return error; 1316 } 1317 1318 uint32_t 1319 nvme_op_sq_enter(struct nvme_softc *sc, 1320 struct nvme_queue *q, struct nvme_ccb *ccb) 1321 { 1322 mutex_enter(&q->q_sq_mtx); 1323 1324 return nvme_op_sq_enter_locked(sc, q, ccb); 1325 } 1326 1327 uint32_t 1328 nvme_op_sq_enter_locked(struct nvme_softc *sc, 1329 struct nvme_queue *q, struct nvme_ccb *ccb) 1330 { 1331 return q->q_sq_tail; 1332 } 1333 1334 void 1335 nvme_op_sq_leave_locked(struct nvme_softc *sc, 1336 struct nvme_queue *q, struct nvme_ccb *ccb) 1337 { 1338 uint32_t tail; 1339 1340 tail = ++q->q_sq_tail; 1341 if (tail >= q->q_entries) 1342 tail = 0; 1343 q->q_sq_tail = tail; 1344 nvme_write4(sc, q->q_sqtdbl, tail); 1345 } 1346 1347 void 1348 nvme_op_sq_leave(struct nvme_softc *sc, 1349 struct nvme_queue *q, struct nvme_ccb *ccb) 1350 { 1351 nvme_op_sq_leave_locked(sc, q, ccb); 1352 1353 mutex_exit(&q->q_sq_mtx); 1354 } 1355 1356 static void 1357 nvme_q_submit(struct nvme_softc *sc, struct nvme_queue *q, struct nvme_ccb *ccb, 1358 void (*fill)(struct nvme_queue *, struct nvme_ccb *, void *)) 1359 { 1360 struct nvme_sqe *sqe = NVME_DMA_KVA(q->q_sq_dmamem); 1361 uint32_t tail; 1362 1363 tail = sc->sc_ops->op_sq_enter(sc, q, ccb); 1364 1365 sqe += tail; 1366 1367 bus_dmamap_sync(sc->sc_dmat, NVME_DMA_MAP(q->q_sq_dmamem), 1368 sizeof(*sqe) * tail, sizeof(*sqe), BUS_DMASYNC_POSTWRITE); 1369 memset(sqe, 0, sizeof(*sqe)); 1370 (*fill)(q, ccb, sqe); 1371 htolem16(&sqe->cid, ccb->ccb_id); 1372 bus_dmamap_sync(sc->sc_dmat, NVME_DMA_MAP(q->q_sq_dmamem), 1373 sizeof(*sqe) * tail, sizeof(*sqe), BUS_DMASYNC_PREWRITE); 1374 1375 sc->sc_ops->op_sq_leave(sc, q, ccb); 1376 } 1377 1378 struct nvme_poll_state { 1379 struct nvme_sqe s; 1380 struct nvme_cqe c; 1381 void *cookie; 1382 void (*done)(struct nvme_queue *, struct nvme_ccb *, struct nvme_cqe *); 1383 }; 1384 1385 static int 1386 nvme_poll(struct nvme_softc *sc, struct nvme_queue *q, struct nvme_ccb *ccb, 1387 void (*fill)(struct nvme_queue *, struct nvme_ccb *, void *), int timo_sec) 1388 { 1389 struct nvme_poll_state state; 1390 uint16_t flags; 1391 int step = 10; 1392 int maxloop = timo_sec * 1000000 / step; 1393 int error = 0; 1394 1395 memset(&state, 0, sizeof(state)); 1396 (*fill)(q, ccb, &state.s); 1397 1398 state.done = ccb->ccb_done; 1399 state.cookie = ccb->ccb_cookie; 1400 1401 ccb->ccb_done = nvme_poll_done; 1402 ccb->ccb_cookie = &state; 1403 1404 nvme_q_submit(sc, q, ccb, nvme_poll_fill); 1405 while (!ISSET(state.c.flags, htole16(NVME_CQE_PHASE))) { 1406 if (nvme_q_complete(sc, q) == 0) 1407 delay(step); 1408 1409 if (timo_sec >= 0 && --maxloop <= 0) { 1410 error = ETIMEDOUT; 1411 break; 1412 } 1413 } 1414 1415 if (error == 0) { 1416 flags = lemtoh16(&state.c.flags); 1417 return flags & ~NVME_CQE_PHASE; 1418 } else { 1419 /* 1420 * If it succeds later, it would hit ccb which will have been 1421 * already reused for something else. Not good. Cross 1422 * fingers and hope for best. XXX do controller reset? 1423 */ 1424 aprint_error_dev(sc->sc_dev, "polled command timed out\n"); 1425 1426 /* Invoke the callback to clean state anyway */ 1427 struct nvme_cqe cqe; 1428 memset(&cqe, 0, sizeof(cqe)); 1429 ccb->ccb_done(q, ccb, &cqe); 1430 1431 return 1; 1432 } 1433 } 1434 1435 static void 1436 nvme_poll_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 1437 { 1438 struct nvme_sqe *sqe = slot; 1439 struct nvme_poll_state *state = ccb->ccb_cookie; 1440 1441 *sqe = state->s; 1442 } 1443 1444 static void 1445 nvme_poll_done(struct nvme_queue *q, struct nvme_ccb *ccb, 1446 struct nvme_cqe *cqe) 1447 { 1448 struct nvme_poll_state *state = ccb->ccb_cookie; 1449 1450 state->c = *cqe; 1451 SET(state->c.flags, htole16(NVME_CQE_PHASE)); 1452 1453 ccb->ccb_cookie = state->cookie; 1454 state->done(q, ccb, &state->c); 1455 } 1456 1457 static void 1458 nvme_sqe_fill(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 1459 { 1460 struct nvme_sqe *src = ccb->ccb_cookie; 1461 struct nvme_sqe *dst = slot; 1462 1463 *dst = *src; 1464 } 1465 1466 static void 1467 nvme_empty_done(struct nvme_queue *q, struct nvme_ccb *ccb, 1468 struct nvme_cqe *cqe) 1469 { 1470 } 1471 1472 void 1473 nvme_op_cq_done(struct nvme_softc *sc, 1474 struct nvme_queue *q, struct nvme_ccb *ccb) 1475 { 1476 /* nop */ 1477 } 1478 1479 static int 1480 nvme_q_complete(struct nvme_softc *sc, struct nvme_queue *q) 1481 { 1482 struct nvme_ccb *ccb; 1483 struct nvme_cqe *ring = NVME_DMA_KVA(q->q_cq_dmamem), *cqe; 1484 uint16_t flags; 1485 int rv = 0; 1486 1487 mutex_enter(&q->q_cq_mtx); 1488 1489 nvme_dmamem_sync(sc, q->q_cq_dmamem, BUS_DMASYNC_POSTREAD); 1490 for (;;) { 1491 cqe = &ring[q->q_cq_head]; 1492 flags = lemtoh16(&cqe->flags); 1493 if ((flags & NVME_CQE_PHASE) != q->q_cq_phase) 1494 break; 1495 1496 /* 1497 * Make sure we have read the flags _before_ we read 1498 * the cid. Otherwise the CPU might speculatively read 1499 * the cid before the entry has been assigned to our 1500 * phase. 1501 */ 1502 nvme_dmamem_sync(sc, q->q_cq_dmamem, BUS_DMASYNC_POSTREAD); 1503 1504 ccb = &q->q_ccbs[lemtoh16(&cqe->cid)]; 1505 1506 if (++q->q_cq_head >= q->q_entries) { 1507 q->q_cq_head = 0; 1508 q->q_cq_phase ^= NVME_CQE_PHASE; 1509 } 1510 1511 #ifdef DEBUG 1512 /* 1513 * If we get spurious completion notification, something 1514 * is seriously hosed up. Very likely DMA to some random 1515 * memory place happened, so just bail out. 1516 */ 1517 if ((intptr_t)ccb->ccb_cookie == NVME_CCB_FREE) { 1518 panic("%s: invalid ccb detected", 1519 device_xname(sc->sc_dev)); 1520 /* NOTREACHED */ 1521 } 1522 #endif 1523 1524 rv++; 1525 1526 sc->sc_ops->op_cq_done(sc, q, ccb); 1527 1528 /* 1529 * Unlock the mutex before calling the ccb_done callback 1530 * and re-lock afterwards. The callback triggers lddone() 1531 * which schedules another i/o, and also calls nvme_ccb_put(). 1532 * Unlock/relock avoids possibility of deadlock. 1533 */ 1534 mutex_exit(&q->q_cq_mtx); 1535 ccb->ccb_done(q, ccb, cqe); 1536 mutex_enter(&q->q_cq_mtx); 1537 } 1538 nvme_dmamem_sync(sc, q->q_cq_dmamem, BUS_DMASYNC_PREREAD); 1539 1540 if (rv) 1541 nvme_write4(sc, q->q_cqhdbl, q->q_cq_head); 1542 1543 mutex_exit(&q->q_cq_mtx); 1544 1545 return rv; 1546 } 1547 1548 static void 1549 nvme_q_wait_complete(struct nvme_softc *sc, 1550 struct nvme_queue *q, bool (*finished)(void *), void *cookie) 1551 { 1552 mutex_enter(&q->q_ccb_mtx); 1553 if (finished(cookie)) 1554 goto out; 1555 1556 for(;;) { 1557 q->q_ccb_waiting = true; 1558 cv_wait(&q->q_ccb_wait, &q->q_ccb_mtx); 1559 1560 if (finished(cookie)) 1561 break; 1562 } 1563 1564 out: 1565 mutex_exit(&q->q_ccb_mtx); 1566 } 1567 1568 static int 1569 nvme_identify(struct nvme_softc *sc, u_int mps) 1570 { 1571 char sn[41], mn[81], fr[17]; 1572 struct nvm_identify_controller *identify; 1573 struct nvme_dmamem *mem; 1574 struct nvme_ccb *ccb; 1575 u_int mdts; 1576 int rv = 1; 1577 1578 ccb = nvme_ccb_get(sc->sc_admin_q, false); 1579 KASSERT(ccb != NULL); /* it's a bug if we don't have spare ccb here */ 1580 1581 mem = nvme_dmamem_alloc(sc, sizeof(*identify)); 1582 if (mem == NULL) 1583 return 1; 1584 1585 ccb->ccb_done = nvme_empty_done; 1586 ccb->ccb_cookie = mem; 1587 1588 nvme_dmamem_sync(sc, mem, BUS_DMASYNC_PREREAD); 1589 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_fill_identify, 1590 NVME_TIMO_IDENT); 1591 nvme_dmamem_sync(sc, mem, BUS_DMASYNC_POSTREAD); 1592 1593 nvme_ccb_put(sc->sc_admin_q, ccb); 1594 1595 if (rv != 0) 1596 goto done; 1597 1598 identify = NVME_DMA_KVA(mem); 1599 sc->sc_identify = *identify; 1600 identify = NULL; 1601 1602 /* Convert data to host endian */ 1603 nvme_identify_controller_swapbytes(&sc->sc_identify); 1604 1605 strnvisx(sn, sizeof(sn), (const char *)sc->sc_identify.sn, 1606 sizeof(sc->sc_identify.sn), VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1607 strnvisx(mn, sizeof(mn), (const char *)sc->sc_identify.mn, 1608 sizeof(sc->sc_identify.mn), VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1609 strnvisx(fr, sizeof(fr), (const char *)sc->sc_identify.fr, 1610 sizeof(sc->sc_identify.fr), VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1611 aprint_normal_dev(sc->sc_dev, "%s, firmware %s, serial %s\n", mn, fr, 1612 sn); 1613 1614 strlcpy(sc->sc_modelname, mn, sizeof(sc->sc_modelname)); 1615 1616 if (sc->sc_identify.mdts > 0) { 1617 mdts = (1 << sc->sc_identify.mdts) * (1 << mps); 1618 if (mdts < sc->sc_mdts) 1619 sc->sc_mdts = mdts; 1620 } 1621 1622 sc->sc_nn = sc->sc_identify.nn; 1623 1624 done: 1625 nvme_dmamem_free(sc, mem); 1626 1627 return rv; 1628 } 1629 1630 static int 1631 nvme_q_create(struct nvme_softc *sc, struct nvme_queue *q) 1632 { 1633 struct nvme_sqe_q sqe; 1634 struct nvme_ccb *ccb; 1635 int rv; 1636 1637 if (sc->sc_use_mq && sc->sc_intr_establish(sc, q->q_id, q) != 0) 1638 return 1; 1639 1640 ccb = nvme_ccb_get(sc->sc_admin_q, false); 1641 KASSERT(ccb != NULL); 1642 1643 ccb->ccb_done = nvme_empty_done; 1644 ccb->ccb_cookie = &sqe; 1645 1646 memset(&sqe, 0, sizeof(sqe)); 1647 sqe.opcode = NVM_ADMIN_ADD_IOCQ; 1648 htolem64(&sqe.prp1, NVME_DMA_DVA(q->q_cq_dmamem)); 1649 htolem16(&sqe.qsize, q->q_entries - 1); 1650 htolem16(&sqe.qid, q->q_id); 1651 sqe.qflags = NVM_SQE_CQ_IEN | NVM_SQE_Q_PC; 1652 if (sc->sc_use_mq) 1653 htolem16(&sqe.cqid, q->q_id); /* qid == vector */ 1654 1655 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_sqe_fill, NVME_TIMO_QOP); 1656 if (rv != 0) 1657 goto fail; 1658 1659 ccb->ccb_done = nvme_empty_done; 1660 ccb->ccb_cookie = &sqe; 1661 1662 memset(&sqe, 0, sizeof(sqe)); 1663 sqe.opcode = NVM_ADMIN_ADD_IOSQ; 1664 htolem64(&sqe.prp1, NVME_DMA_DVA(q->q_sq_dmamem)); 1665 htolem16(&sqe.qsize, q->q_entries - 1); 1666 htolem16(&sqe.qid, q->q_id); 1667 htolem16(&sqe.cqid, q->q_id); 1668 sqe.qflags = NVM_SQE_Q_PC; 1669 1670 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_sqe_fill, NVME_TIMO_QOP); 1671 if (rv != 0) 1672 goto fail; 1673 1674 nvme_ccb_put(sc->sc_admin_q, ccb); 1675 return 0; 1676 1677 fail: 1678 if (sc->sc_use_mq) 1679 sc->sc_intr_disestablish(sc, q->q_id); 1680 1681 nvme_ccb_put(sc->sc_admin_q, ccb); 1682 return rv; 1683 } 1684 1685 static int 1686 nvme_q_delete(struct nvme_softc *sc, struct nvme_queue *q) 1687 { 1688 struct nvme_sqe_q sqe; 1689 struct nvme_ccb *ccb; 1690 int rv; 1691 1692 ccb = nvme_ccb_get(sc->sc_admin_q, false); 1693 KASSERT(ccb != NULL); 1694 1695 ccb->ccb_done = nvme_empty_done; 1696 ccb->ccb_cookie = &sqe; 1697 1698 memset(&sqe, 0, sizeof(sqe)); 1699 sqe.opcode = NVM_ADMIN_DEL_IOSQ; 1700 htolem16(&sqe.qid, q->q_id); 1701 1702 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_sqe_fill, NVME_TIMO_QOP); 1703 if (rv != 0) 1704 goto fail; 1705 1706 ccb->ccb_done = nvme_empty_done; 1707 ccb->ccb_cookie = &sqe; 1708 1709 memset(&sqe, 0, sizeof(sqe)); 1710 sqe.opcode = NVM_ADMIN_DEL_IOCQ; 1711 htolem16(&sqe.qid, q->q_id); 1712 1713 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_sqe_fill, NVME_TIMO_QOP); 1714 if (rv != 0) 1715 goto fail; 1716 1717 fail: 1718 nvme_ccb_put(sc->sc_admin_q, ccb); 1719 1720 if (rv == 0 && sc->sc_use_mq) { 1721 if (sc->sc_intr_disestablish(sc, q->q_id)) 1722 rv = 1; 1723 } 1724 1725 return rv; 1726 } 1727 1728 static void 1729 nvme_fill_identify(struct nvme_queue *q, struct nvme_ccb *ccb, void *slot) 1730 { 1731 struct nvme_sqe *sqe = slot; 1732 struct nvme_dmamem *mem = ccb->ccb_cookie; 1733 1734 sqe->opcode = NVM_ADMIN_IDENTIFY; 1735 htolem64(&sqe->entry.prp[0], NVME_DMA_DVA(mem)); 1736 htolem32(&sqe->cdw10, 1); 1737 } 1738 1739 static int 1740 nvme_set_number_of_queues(struct nvme_softc *sc, u_int nq, u_int *ncqa, 1741 u_int *nsqa) 1742 { 1743 struct nvme_pt_state state; 1744 struct nvme_pt_command pt; 1745 struct nvme_ccb *ccb; 1746 int rv; 1747 1748 ccb = nvme_ccb_get(sc->sc_admin_q, false); 1749 KASSERT(ccb != NULL); /* it's a bug if we don't have spare ccb here */ 1750 1751 memset(&pt, 0, sizeof(pt)); 1752 pt.cmd.opcode = NVM_ADMIN_SET_FEATURES; 1753 pt.cmd.cdw10 = NVM_FEATURE_NUMBER_OF_QUEUES; 1754 pt.cmd.cdw11 = ((nq - 1) << 16) | (nq - 1); 1755 1756 memset(&state, 0, sizeof(state)); 1757 state.pt = &pt; 1758 state.finished = false; 1759 1760 ccb->ccb_done = nvme_pt_done; 1761 ccb->ccb_cookie = &state; 1762 1763 rv = nvme_poll(sc, sc->sc_admin_q, ccb, nvme_pt_fill, NVME_TIMO_QOP); 1764 1765 if (rv != 0) { 1766 *ncqa = *nsqa = 0; 1767 return EIO; 1768 } 1769 1770 *ncqa = (pt.cpl.cdw0 >> 16) + 1; 1771 *nsqa = (pt.cpl.cdw0 & 0xffff) + 1; 1772 1773 return 0; 1774 } 1775 1776 static int 1777 nvme_ccbs_alloc(struct nvme_queue *q, uint16_t nccbs) 1778 { 1779 struct nvme_softc *sc = q->q_sc; 1780 struct nvme_ccb *ccb; 1781 bus_addr_t off; 1782 uint64_t *prpl; 1783 u_int i; 1784 1785 mutex_init(&q->q_ccb_mtx, MUTEX_DEFAULT, IPL_BIO); 1786 cv_init(&q->q_ccb_wait, "nvmeqw"); 1787 q->q_ccb_waiting = false; 1788 SIMPLEQ_INIT(&q->q_ccb_list); 1789 1790 q->q_ccbs = kmem_alloc(sizeof(*ccb) * nccbs, KM_SLEEP); 1791 1792 q->q_nccbs = nccbs; 1793 q->q_ccb_prpls = nvme_dmamem_alloc(sc, 1794 sizeof(*prpl) * sc->sc_max_sgl * nccbs); 1795 1796 prpl = NVME_DMA_KVA(q->q_ccb_prpls); 1797 off = 0; 1798 1799 for (i = 0; i < nccbs; i++) { 1800 ccb = &q->q_ccbs[i]; 1801 1802 if (bus_dmamap_create(sc->sc_dmat, sc->sc_mdts, 1803 sc->sc_max_sgl + 1 /* we get a free prp in the sqe */, 1804 sc->sc_mps, sc->sc_mps, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1805 &ccb->ccb_dmamap) != 0) 1806 goto free_maps; 1807 1808 ccb->ccb_id = i; 1809 ccb->ccb_prpl = prpl; 1810 ccb->ccb_prpl_off = off; 1811 ccb->ccb_prpl_dva = NVME_DMA_DVA(q->q_ccb_prpls) + off; 1812 1813 SIMPLEQ_INSERT_TAIL(&q->q_ccb_list, ccb, ccb_entry); 1814 1815 prpl += sc->sc_max_sgl; 1816 off += sizeof(*prpl) * sc->sc_max_sgl; 1817 } 1818 1819 return 0; 1820 1821 free_maps: 1822 nvme_ccbs_free(q); 1823 return 1; 1824 } 1825 1826 static struct nvme_ccb * 1827 nvme_ccb_get(struct nvme_queue *q, bool wait) 1828 { 1829 struct nvme_ccb *ccb = NULL; 1830 1831 mutex_enter(&q->q_ccb_mtx); 1832 again: 1833 ccb = SIMPLEQ_FIRST(&q->q_ccb_list); 1834 if (ccb != NULL) { 1835 SIMPLEQ_REMOVE_HEAD(&q->q_ccb_list, ccb_entry); 1836 #ifdef DEBUG 1837 ccb->ccb_cookie = NULL; 1838 #endif 1839 } else { 1840 if (__predict_false(wait)) { 1841 q->q_ccb_waiting = true; 1842 cv_wait(&q->q_ccb_wait, &q->q_ccb_mtx); 1843 goto again; 1844 } 1845 } 1846 mutex_exit(&q->q_ccb_mtx); 1847 1848 return ccb; 1849 } 1850 1851 static struct nvme_ccb * 1852 nvme_ccb_get_bio(struct nvme_softc *sc, struct buf *bp, 1853 struct nvme_queue **selq) 1854 { 1855 u_int cpuindex = cpu_index((bp && bp->b_ci) ? bp->b_ci : curcpu()); 1856 1857 /* 1858 * Find a queue with available ccbs, preferring the originating 1859 * CPU's queue. 1860 */ 1861 1862 for (u_int qoff = 0; qoff < sc->sc_nq; qoff++) { 1863 struct nvme_queue *q = sc->sc_q[(cpuindex + qoff) % sc->sc_nq]; 1864 struct nvme_ccb *ccb; 1865 1866 mutex_enter(&q->q_ccb_mtx); 1867 ccb = SIMPLEQ_FIRST(&q->q_ccb_list); 1868 if (ccb != NULL) { 1869 SIMPLEQ_REMOVE_HEAD(&q->q_ccb_list, ccb_entry); 1870 #ifdef DEBUG 1871 ccb->ccb_cookie = NULL; 1872 #endif 1873 } 1874 mutex_exit(&q->q_ccb_mtx); 1875 1876 if (ccb != NULL) { 1877 *selq = q; 1878 return ccb; 1879 } 1880 } 1881 1882 return NULL; 1883 } 1884 1885 static void 1886 nvme_ccb_put(struct nvme_queue *q, struct nvme_ccb *ccb) 1887 { 1888 1889 mutex_enter(&q->q_ccb_mtx); 1890 #ifdef DEBUG 1891 ccb->ccb_cookie = (void *)NVME_CCB_FREE; 1892 #endif 1893 SIMPLEQ_INSERT_HEAD(&q->q_ccb_list, ccb, ccb_entry); 1894 1895 /* It's unlikely there are any waiters, it's not used for regular I/O */ 1896 if (__predict_false(q->q_ccb_waiting)) { 1897 q->q_ccb_waiting = false; 1898 cv_broadcast(&q->q_ccb_wait); 1899 } 1900 1901 mutex_exit(&q->q_ccb_mtx); 1902 } 1903 1904 static void 1905 nvme_ccbs_free(struct nvme_queue *q) 1906 { 1907 struct nvme_softc *sc = q->q_sc; 1908 struct nvme_ccb *ccb; 1909 1910 mutex_enter(&q->q_ccb_mtx); 1911 while ((ccb = SIMPLEQ_FIRST(&q->q_ccb_list)) != NULL) { 1912 SIMPLEQ_REMOVE_HEAD(&q->q_ccb_list, ccb_entry); 1913 /* 1914 * bus_dmamap_destroy() may call vm_map_lock() and rw_enter() 1915 * internally. don't hold spin mutex 1916 */ 1917 mutex_exit(&q->q_ccb_mtx); 1918 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 1919 mutex_enter(&q->q_ccb_mtx); 1920 } 1921 mutex_exit(&q->q_ccb_mtx); 1922 1923 nvme_dmamem_free(sc, q->q_ccb_prpls); 1924 kmem_free(q->q_ccbs, sizeof(*ccb) * q->q_nccbs); 1925 q->q_ccbs = NULL; 1926 cv_destroy(&q->q_ccb_wait); 1927 mutex_destroy(&q->q_ccb_mtx); 1928 } 1929 1930 static struct nvme_queue * 1931 nvme_q_alloc(struct nvme_softc *sc, uint16_t id, u_int entries, u_int dstrd) 1932 { 1933 struct nvme_queue *q; 1934 1935 q = kmem_alloc(sizeof(*q), KM_SLEEP); 1936 q->q_sc = sc; 1937 q->q_sq_dmamem = nvme_dmamem_alloc(sc, 1938 sizeof(struct nvme_sqe) * entries); 1939 if (q->q_sq_dmamem == NULL) 1940 goto free; 1941 1942 q->q_cq_dmamem = nvme_dmamem_alloc(sc, 1943 sizeof(struct nvme_cqe) * entries); 1944 if (q->q_cq_dmamem == NULL) 1945 goto free_sq; 1946 1947 memset(NVME_DMA_KVA(q->q_sq_dmamem), 0, NVME_DMA_LEN(q->q_sq_dmamem)); 1948 memset(NVME_DMA_KVA(q->q_cq_dmamem), 0, NVME_DMA_LEN(q->q_cq_dmamem)); 1949 1950 mutex_init(&q->q_sq_mtx, MUTEX_DEFAULT, IPL_BIO); 1951 mutex_init(&q->q_cq_mtx, MUTEX_DEFAULT, IPL_BIO); 1952 q->q_sqtdbl = NVME_SQTDBL(id, dstrd); 1953 q->q_cqhdbl = NVME_CQHDBL(id, dstrd); 1954 q->q_id = id; 1955 q->q_entries = entries; 1956 q->q_sq_tail = 0; 1957 q->q_cq_head = 0; 1958 q->q_cq_phase = NVME_CQE_PHASE; 1959 1960 if (sc->sc_ops->op_q_alloc != NULL) { 1961 if (sc->sc_ops->op_q_alloc(sc, q) != 0) 1962 goto free_cq; 1963 } 1964 1965 nvme_dmamem_sync(sc, q->q_sq_dmamem, BUS_DMASYNC_PREWRITE); 1966 nvme_dmamem_sync(sc, q->q_cq_dmamem, BUS_DMASYNC_PREREAD); 1967 1968 /* 1969 * Due to definition of full and empty queue (queue is empty 1970 * when head == tail, full when tail is one less then head), 1971 * we can actually only have (entries - 1) in-flight commands. 1972 */ 1973 if (nvme_ccbs_alloc(q, entries - 1) != 0) { 1974 aprint_error_dev(sc->sc_dev, "unable to allocate ccbs\n"); 1975 goto free_cq; 1976 } 1977 1978 return q; 1979 1980 free_cq: 1981 nvme_dmamem_free(sc, q->q_cq_dmamem); 1982 free_sq: 1983 nvme_dmamem_free(sc, q->q_sq_dmamem); 1984 free: 1985 kmem_free(q, sizeof(*q)); 1986 1987 return NULL; 1988 } 1989 1990 static void 1991 nvme_q_reset(struct nvme_softc *sc, struct nvme_queue *q) 1992 { 1993 1994 memset(NVME_DMA_KVA(q->q_sq_dmamem), 0, NVME_DMA_LEN(q->q_sq_dmamem)); 1995 memset(NVME_DMA_KVA(q->q_cq_dmamem), 0, NVME_DMA_LEN(q->q_cq_dmamem)); 1996 1997 q->q_sq_tail = 0; 1998 q->q_cq_head = 0; 1999 q->q_cq_phase = NVME_CQE_PHASE; 2000 2001 nvme_dmamem_sync(sc, q->q_sq_dmamem, BUS_DMASYNC_PREWRITE); 2002 nvme_dmamem_sync(sc, q->q_cq_dmamem, BUS_DMASYNC_PREREAD); 2003 } 2004 2005 static void 2006 nvme_q_free(struct nvme_softc *sc, struct nvme_queue *q) 2007 { 2008 nvme_ccbs_free(q); 2009 mutex_destroy(&q->q_sq_mtx); 2010 mutex_destroy(&q->q_cq_mtx); 2011 nvme_dmamem_sync(sc, q->q_cq_dmamem, BUS_DMASYNC_POSTREAD); 2012 nvme_dmamem_sync(sc, q->q_sq_dmamem, BUS_DMASYNC_POSTWRITE); 2013 2014 if (sc->sc_ops->op_q_alloc != NULL) 2015 sc->sc_ops->op_q_free(sc, q); 2016 2017 nvme_dmamem_free(sc, q->q_cq_dmamem); 2018 nvme_dmamem_free(sc, q->q_sq_dmamem); 2019 kmem_free(q, sizeof(*q)); 2020 } 2021 2022 int 2023 nvme_intr(void *xsc) 2024 { 2025 struct nvme_softc *sc = xsc; 2026 2027 KASSERT(!sc->sc_use_mq); 2028 2029 /* 2030 * INTx is level triggered, controller deasserts the interrupt only 2031 * when we advance command queue head via write to the doorbell. 2032 * Tell the controller to block the interrupts while we process 2033 * the queue(s). 2034 */ 2035 nvme_write4(sc, NVME_INTMS, 1); 2036 2037 softint_schedule(sc->sc_softih[0]); 2038 2039 /* don't know, might not have been for us */ 2040 return 1; 2041 } 2042 2043 void 2044 nvme_softintr_intx(void *xq) 2045 { 2046 struct nvme_queue *q = xq; 2047 struct nvme_softc *sc = q->q_sc; 2048 2049 KASSERT(!sc->sc_use_mq); 2050 2051 nvme_q_complete(sc, sc->sc_admin_q); 2052 if (sc->sc_q != NULL) 2053 nvme_q_complete(sc, sc->sc_q[0]); 2054 2055 /* 2056 * Processing done, tell controller to issue interrupts again. There 2057 * is no race, as NVMe spec requires the controller to maintain state, 2058 * and assert the interrupt whenever there are unacknowledged 2059 * completion queue entries. 2060 */ 2061 nvme_write4(sc, NVME_INTMC, 1); 2062 } 2063 2064 int 2065 nvme_intr_msi(void *xq) 2066 { 2067 struct nvme_queue *q = xq; 2068 2069 KASSERT(q); 2070 KASSERT(q->q_sc); 2071 KASSERT(q->q_sc->sc_softih); 2072 KASSERT(q->q_sc->sc_softih[q->q_id]); 2073 2074 /* 2075 * MSI/MSI-X are edge triggered, so can handover processing to softint 2076 * without masking the interrupt. 2077 */ 2078 softint_schedule(q->q_sc->sc_softih[q->q_id]); 2079 2080 return 1; 2081 } 2082 2083 void 2084 nvme_softintr_msi(void *xq) 2085 { 2086 struct nvme_queue *q = xq; 2087 struct nvme_softc *sc = q->q_sc; 2088 2089 nvme_q_complete(sc, q); 2090 } 2091 2092 struct nvme_dmamem * 2093 nvme_dmamem_alloc(struct nvme_softc *sc, size_t size) 2094 { 2095 struct nvme_dmamem *ndm; 2096 int nsegs; 2097 2098 ndm = kmem_zalloc(sizeof(*ndm), KM_SLEEP); 2099 if (ndm == NULL) 2100 return NULL; 2101 2102 ndm->ndm_size = size; 2103 2104 if (bus_dmamap_create(sc->sc_dmat, size, btoc(round_page(size)), size, 0, 2105 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &ndm->ndm_map) != 0) 2106 goto ndmfree; 2107 2108 if (bus_dmamem_alloc(sc->sc_dmat, size, sc->sc_mps, 0, &ndm->ndm_seg, 2109 1, &nsegs, BUS_DMA_WAITOK) != 0) 2110 goto destroy; 2111 2112 if (bus_dmamem_map(sc->sc_dmat, &ndm->ndm_seg, nsegs, size, 2113 &ndm->ndm_kva, BUS_DMA_WAITOK) != 0) 2114 goto free; 2115 2116 if (bus_dmamap_load(sc->sc_dmat, ndm->ndm_map, ndm->ndm_kva, size, 2117 NULL, BUS_DMA_WAITOK) != 0) 2118 goto unmap; 2119 2120 memset(ndm->ndm_kva, 0, size); 2121 bus_dmamap_sync(sc->sc_dmat, ndm->ndm_map, 0, size, BUS_DMASYNC_PREREAD); 2122 2123 return ndm; 2124 2125 unmap: 2126 bus_dmamem_unmap(sc->sc_dmat, ndm->ndm_kva, size); 2127 free: 2128 bus_dmamem_free(sc->sc_dmat, &ndm->ndm_seg, 1); 2129 destroy: 2130 bus_dmamap_destroy(sc->sc_dmat, ndm->ndm_map); 2131 ndmfree: 2132 kmem_free(ndm, sizeof(*ndm)); 2133 return NULL; 2134 } 2135 2136 void 2137 nvme_dmamem_sync(struct nvme_softc *sc, struct nvme_dmamem *mem, int ops) 2138 { 2139 bus_dmamap_sync(sc->sc_dmat, NVME_DMA_MAP(mem), 2140 0, NVME_DMA_LEN(mem), ops); 2141 } 2142 2143 void 2144 nvme_dmamem_free(struct nvme_softc *sc, struct nvme_dmamem *ndm) 2145 { 2146 bus_dmamap_unload(sc->sc_dmat, ndm->ndm_map); 2147 bus_dmamem_unmap(sc->sc_dmat, ndm->ndm_kva, ndm->ndm_size); 2148 bus_dmamem_free(sc->sc_dmat, &ndm->ndm_seg, 1); 2149 bus_dmamap_destroy(sc->sc_dmat, ndm->ndm_map); 2150 kmem_free(ndm, sizeof(*ndm)); 2151 } 2152 2153 /* 2154 * ioctl 2155 */ 2156 2157 dev_type_open(nvmeopen); 2158 dev_type_close(nvmeclose); 2159 dev_type_ioctl(nvmeioctl); 2160 2161 const struct cdevsw nvme_cdevsw = { 2162 .d_open = nvmeopen, 2163 .d_close = nvmeclose, 2164 .d_read = noread, 2165 .d_write = nowrite, 2166 .d_ioctl = nvmeioctl, 2167 .d_stop = nostop, 2168 .d_tty = notty, 2169 .d_poll = nopoll, 2170 .d_mmap = nommap, 2171 .d_kqfilter = nokqfilter, 2172 .d_discard = nodiscard, 2173 .d_flag = D_OTHER, 2174 }; 2175 2176 /* 2177 * Accept an open operation on the control device. 2178 */ 2179 int 2180 nvmeopen(dev_t dev, int flag, int mode, struct lwp *l) 2181 { 2182 struct nvme_softc *sc; 2183 int unit = minor(dev) / 0x10000; 2184 int nsid = minor(dev) & 0xffff; 2185 int nsidx; 2186 2187 if ((sc = device_lookup_private(&nvme_cd, unit)) == NULL) 2188 return ENXIO; 2189 if ((sc->sc_flags & NVME_F_ATTACHED) == 0) 2190 return ENXIO; 2191 2192 if (nsid == 0) { 2193 /* controller */ 2194 if (ISSET(sc->sc_flags, NVME_F_OPEN)) 2195 return EBUSY; 2196 SET(sc->sc_flags, NVME_F_OPEN); 2197 } else { 2198 /* namespace */ 2199 nsidx = nsid - 1; 2200 if (nsidx >= sc->sc_nn || sc->sc_namespaces[nsidx].dev == NULL) 2201 return ENXIO; 2202 if (ISSET(sc->sc_namespaces[nsidx].flags, NVME_NS_F_OPEN)) 2203 return EBUSY; 2204 SET(sc->sc_namespaces[nsidx].flags, NVME_NS_F_OPEN); 2205 } 2206 return 0; 2207 } 2208 2209 /* 2210 * Accept the last close on the control device. 2211 */ 2212 int 2213 nvmeclose(dev_t dev, int flag, int mode, struct lwp *l) 2214 { 2215 struct nvme_softc *sc; 2216 int unit = minor(dev) / 0x10000; 2217 int nsid = minor(dev) & 0xffff; 2218 int nsidx; 2219 2220 sc = device_lookup_private(&nvme_cd, unit); 2221 if (sc == NULL) 2222 return ENXIO; 2223 2224 if (nsid == 0) { 2225 /* controller */ 2226 CLR(sc->sc_flags, NVME_F_OPEN); 2227 } else { 2228 /* namespace */ 2229 nsidx = nsid - 1; 2230 if (nsidx >= sc->sc_nn) 2231 return ENXIO; 2232 CLR(sc->sc_namespaces[nsidx].flags, NVME_NS_F_OPEN); 2233 } 2234 2235 return 0; 2236 } 2237 2238 /* 2239 * Handle control operations. 2240 */ 2241 int 2242 nvmeioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 2243 { 2244 struct nvme_softc *sc; 2245 int unit = minor(dev) / 0x10000; 2246 int nsid = minor(dev) & 0xffff; 2247 struct nvme_pt_command *pt; 2248 2249 sc = device_lookup_private(&nvme_cd, unit); 2250 if (sc == NULL) 2251 return ENXIO; 2252 2253 switch (cmd) { 2254 case NVME_PASSTHROUGH_CMD: 2255 pt = data; 2256 return nvme_command_passthrough(sc, data, 2257 nsid == 0 ? pt->cmd.nsid : (uint32_t)nsid, l, nsid == 0); 2258 } 2259 2260 return ENOTTY; 2261 } 2262
Indexes created Sat Sep 27 22:09:54 GMT 2025