nvmereg.h revision 1.8
1 /* $NetBSD: nvmereg.h,v 1.8 2017/02/28 20:53:50 jdolecek Exp $ */ 2 /* $OpenBSD: nvmereg.h,v 1.10 2016/04/14 11:18:32 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2014 David Gwynne <dlg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef __NVMEREG_H__ 21 #define __NVMEREG_H__ 22 23 #define NVME_CAP 0x0000 /* Controller Capabilities */ 24 #define NVME_CAP_MPSMAX(_r) (12 + (((_r) >> 52) & 0xf)) /* shift */ 25 #define NVME_CAP_MPSMIN(_r) (12 + (((_r) >> 48) & 0xf)) /* shift */ 26 #define NVME_CAP_CSS(_r) (((_r) >> 37) & 0x7f) 27 #define NVME_CAP_CSS_NVM __BIT(0) 28 #define NVME_CAP_NSSRS(_r) ISSET((_r), __BIT(36)) 29 #define NVME_CAP_DSTRD(_r) __BIT(2 + (((_r) >> 32) & 0xf)) /* bytes */ 30 #define NVME_CAP_TO(_r) (500 * (((_r) >> 24) & 0xff)) /* ms */ 31 #define NVME_CAP_AMS(_r) (((_r) >> 17) & 0x3) 32 #define NVME_CAP_AMS_WRR __BIT(0) 33 #define NVME_CAP_AMS_VENDOR __BIT(1) 34 #define NVME_CAP_CQR(_r) ISSET((_r), __BIT(16)) 35 #define NVME_CAP_MQES(_r) (((_r) & 0xffff) + 1) 36 #define NVME_CAP_LO 0x0000 37 #define NVME_CAP_HI 0x0004 38 #define NVME_VS 0x0008 /* Version */ 39 #define NVME_VS_MJR(_r) (((_r) >> 16) & 0xffff) 40 #define NVME_VS_MNR(_r) ((_r) & 0xffff) 41 #define NVME_VS_1_0 0x00010000 42 #define NVME_VS_1_1 0x00010100 43 #define NVME_VS_1_2 0x00010200 44 #define NVME_VS_1_2_1 0x00010201 45 #define NVME_INTMS 0x000c /* Interrupt Mask Set */ 46 #define NVME_INTMC 0x0010 /* Interrupt Mask Clear */ 47 #define NVME_CC 0x0014 /* Controller Configuration */ 48 #define NVME_CC_IOCQES(_v) (((_v) & 0xf) << 20) 49 #define NVME_CC_IOCQES_MASK NVME_CC_IOCQES(0xf) 50 #define NVME_CC_IOCQES_R(_v) (((_v) >> 20) & 0xf) 51 #define NVME_CC_IOSQES(_v) (((_v) & 0xf) << 16) 52 #define NVME_CC_IOSQES_MASK NVME_CC_IOSQES(0xf) 53 #define NVME_CC_IOSQES_R(_v) (((_v) >> 16) & 0xf) 54 #define NVME_CC_SHN(_v) (((_v) & 0x3) << 14) 55 #define NVME_CC_SHN_MASK NVME_CC_SHN(0x3) 56 #define NVME_CC_SHN_R(_v) (((_v) >> 15) & 0x3) 57 #define NVME_CC_SHN_NONE 0 58 #define NVME_CC_SHN_NORMAL 1 59 #define NVME_CC_SHN_ABRUPT 2 60 #define NVME_CC_AMS(_v) (((_v) & 0x7) << 11) 61 #define NVME_CC_AMS_MASK NVME_CC_AMS(0x7) 62 #define NVME_CC_AMS_R(_v) (((_v) >> 11) & 0xf) 63 #define NVME_CC_AMS_RR 0 /* round-robin */ 64 #define NVME_CC_AMS_WRR_U 1 /* weighted round-robin w/ urgent */ 65 #define NVME_CC_AMS_VENDOR 7 /* vendor */ 66 #define NVME_CC_MPS(_v) ((((_v) - 12) & 0xf) << 7) 67 #define NVME_CC_MPS_MASK (0xf << 7) 68 #define NVME_CC_MPS_R(_v) (12 + (((_v) >> 7) & 0xf)) 69 #define NVME_CC_CSS(_v) (((_v) & 0x7) << 4) 70 #define NVME_CC_CSS_MASK NVME_CC_CSS(0x7) 71 #define NVME_CC_CSS_R(_v) (((_v) >> 4) & 0x7) 72 #define NVME_CC_CSS_NVM 0 73 #define NVME_CC_EN __BIT(0) 74 #define NVME_CSTS 0x001c /* Controller Status */ 75 #define NVME_CSTS_SHST_MASK (0x3 << 2) 76 #define NVME_CSTS_SHST_NONE (0x0 << 2) /* normal operation */ 77 #define NVME_CSTS_SHST_WAIT (0x1 << 2) /* shutdown processing occurring */ 78 #define NVME_CSTS_SHST_DONE (0x2 << 2) /* shutdown processing complete */ 79 #define NVME_CSTS_CFS (1 << 1) 80 #define NVME_CSTS_RDY (1 << 0) 81 #define NVME_NSSR 0x0020 /* NVM Subsystem Reset (Optional) */ 82 #define NVME_AQA 0x0024 /* Admin Queue Attributes */ 83 /* Admin Completion Queue Size */ 84 #define NVME_AQA_ACQS(_v) (((_v) - 1) << 16) 85 #define NVME_AQA_ACQS_R(_v) ((_v >> 16) & ((1 << 12) - 1)) 86 /* Admin Submission Queue Size */ 87 #define NVME_AQA_ASQS(_v) (((_v) - 1) << 0) 88 #define NVME_AQA_ASQS_R(_v) (_v & ((1 << 12) - 1)) 89 #define NVME_ASQ 0x0028 /* Admin Submission Queue Base Address */ 90 #define NVME_ACQ 0x0030 /* Admin Completion Queue Base Address */ 91 92 #define NVME_ADMIN_Q 0 93 /* Submission Queue Tail Doorbell */ 94 #define NVME_SQTDBL(_q, _s) (0x1000 + (2 * (_q) + 0) * (_s)) 95 /* Completion Queue Head Doorbell */ 96 #define NVME_CQHDBL(_q, _s) (0x1000 + (2 * (_q) + 1) * (_s)) 97 98 struct nvme_sge { 99 uint8_t id; 100 uint8_t _reserved[15]; 101 } __packed __aligned(8); 102 103 struct nvme_sge_data { 104 uint8_t id; 105 uint8_t _reserved[3]; 106 107 uint32_t length; 108 109 uint64_t address; 110 } __packed __aligned(8); 111 112 struct nvme_sge_bit_bucket { 113 uint8_t id; 114 uint8_t _reserved[3]; 115 116 uint32_t length; 117 118 uint64_t address; 119 } __packed __aligned(8); 120 121 struct nvme_sqe { 122 uint8_t opcode; 123 uint8_t flags; 124 uint16_t cid; 125 126 uint32_t nsid; 127 128 uint8_t _reserved[8]; 129 130 uint64_t mptr; 131 132 union { 133 uint64_t prp[2]; 134 struct nvme_sge sge; 135 } __packed entry; 136 137 uint32_t cdw10; 138 uint32_t cdw11; 139 uint32_t cdw12; 140 uint32_t cdw13; 141 uint32_t cdw14; 142 uint32_t cdw15; 143 } __packed __aligned(8); 144 145 struct nvme_sqe_q { 146 uint8_t opcode; 147 uint8_t flags; 148 uint16_t cid; 149 150 uint8_t _reserved1[20]; 151 152 uint64_t prp1; 153 154 uint8_t _reserved2[8]; 155 156 uint16_t qid; 157 uint16_t qsize; 158 159 uint8_t qflags; 160 #define NVM_SQE_SQ_QPRIO_URG (0x0 << 1) 161 #define NVM_SQE_SQ_QPRIO_HI (0x1 << 1) 162 #define NVM_SQE_SQ_QPRIO_MED (0x2 << 1) 163 #define NVM_SQE_SQ_QPRIO_LOW (0x3 << 1) 164 #define NVM_SQE_CQ_IEN (1 << 1) 165 #define NVM_SQE_Q_PC (1 << 0) 166 uint8_t _reserved3; 167 uint16_t cqid; /* XXX interrupt vector for cq */ 168 169 uint8_t _reserved4[16]; 170 } __packed __aligned(8); 171 172 struct nvme_sqe_io { 173 uint8_t opcode; 174 uint8_t flags; 175 uint16_t cid; 176 177 uint32_t nsid; 178 179 uint8_t _reserved[8]; 180 181 uint64_t mptr; 182 183 union { 184 uint64_t prp[2]; 185 struct nvme_sge sge; 186 } __packed entry; 187 188 uint64_t slba; /* Starting LBA */ 189 190 uint16_t nlb; /* Number of Logical Blocks */ 191 uint16_t ioflags; 192 #define NVM_SQE_IO_LR __BIT(15) /* Limited Retry */ 193 #define NVM_SQE_IO_FUA __BIT(14) /* Force Unit Access (bypass cache) */ 194 195 uint8_t dsm; /* Dataset Management */ 196 #define NVM_SQE_IO_INCOMP __BIT(7) /* Incompressible */ 197 #define NVM_SQE_IO_SEQ __BIT(6) /* Sequential request */ 198 #define NVM_SQE_IO_LAT_MASK __BITS(4, 5) /* Access Latency */ 199 #define NVM_SQE_IO_LAT_NONE 0 /* Latency: none */ 200 #define NVM_SQE_IO_LAT_IDLE __BIT(4) /* Latency: idle */ 201 #define NVM_SQE_IO_LAT_NORMAL __BIT(5) /* Latency: normal */ 202 #define NVM_SQE_IO_LAT_LOW __BITS(4, 5) /* Latency: low */ 203 #define NVM_SQE_IO_FREQ_MASK __BITS(0, 3) /* Access Frequency */ 204 #define NVM_SQE_IO_FREQ_TYPICAL 0x1 /* Typical */ 205 #define NVM_SQE_IO_FREQ_INFR_INFW 0x2 /* Infrequent read and writes */ 206 #define NVM_SQE_IO_FREQ_FRR_INFW 0x3 /* Frequent read, inf. writes */ 207 #define NVM_SQE_IO_FREQ_INFR_FRW 0x4 /* Inf. read, freq. writes */ 208 #define NVM_SQE_IO_FREQ_FRR_FRW 0x5 /* Freq. read and writes */ 209 #define NVM_SQE_IO_FREQ_ONCE 0x6 /* One time i/o operation */ 210 /* Extra Access Frequency bits for read operations */ 211 #define NVM_SQE_IO_FREQ_SPEC 0x7 /* Speculative read - prefech */ 212 #define NVM_SQE_IO_FREQ_OVERWRITE 0x8 /* Will be overwritten soon */ 213 uint8_t _reserved2[3]; 214 215 uint32_t eilbrt; /* Expected Initial Logical Block 216 Reference Tag */ 217 218 uint16_t elbat; /* Expected Logical Block 219 Application Tag */ 220 uint16_t elbatm; /* Expected Logical Block 221 Application Tag Mask */ 222 } __packed __aligned(8); 223 224 struct nvme_cqe { 225 uint32_t cdw0; 226 #define NVME_CQE_CDW0_VWC_WCE __BIT(1) /* Volatile Write Cache Enable */ 227 228 uint32_t _reserved; 229 230 uint16_t sqhd; /* SQ Head Pointer */ 231 uint16_t sqid; /* SQ Identifier */ 232 233 uint16_t cid; /* Command Identifier */ 234 uint16_t flags; 235 #define NVME_CQE_DNR __BIT(15) 236 #define NVME_CQE_M __BIT(14) 237 #define NVME_CQE_SCT_MASK __BITS(8, 10) 238 #define NVME_CQE_SCT(_f) ((_f) & (0x07 << 8)) 239 #define NVME_CQE_SCT_GENERIC (0x00 << 8) 240 #define NVME_CQE_SCT_COMMAND (0x01 << 8) 241 #define NVME_CQE_SCT_MEDIAERR (0x02 << 8) 242 #define NVME_CQE_SCT_VENDOR (0x07 << 8) 243 #define NVME_CQE_SC_MASK __BITS(1, 7) 244 #define NVME_CQE_SC(_f) ((_f) & (0x7f << 1)) 245 /* generic command status codes */ 246 #define NVME_CQE_SC_SUCCESS (0x00 << 1) 247 #define NVME_CQE_SC_INVALID_OPCODE (0x01 << 1) 248 #define NVME_CQE_SC_INVALID_FIELD (0x02 << 1) 249 #define NVME_CQE_SC_CID_CONFLICT (0x03 << 1) 250 #define NVME_CQE_SC_DATA_XFER_ERR (0x04 << 1) 251 #define NVME_CQE_SC_ABRT_BY_NO_PWR (0x05 << 1) 252 #define NVME_CQE_SC_INTERNAL_DEV_ERR (0x06 << 1) 253 #define NVME_CQE_SC_CMD_ABRT_REQD (0x07 << 1) 254 #define NVME_CQE_SC_CMD_ABDR_SQ_DEL (0x08 << 1) 255 #define NVME_CQE_SC_CMD_ABDR_FUSE_ERR (0x09 << 1) 256 #define NVME_CQE_SC_CMD_ABDR_FUSE_MISS (0x0a << 1) 257 #define NVME_CQE_SC_INVALID_NS (0x0b << 1) 258 #define NVME_CQE_SC_CMD_SEQ_ERR (0x0c << 1) 259 #define NVME_CQE_SC_INVALID_LAST_SGL (0x0d << 1) 260 #define NVME_CQE_SC_INVALID_NUM_SGL (0x0e << 1) 261 #define NVME_CQE_SC_DATA_SGL_LEN (0x0f << 1) 262 #define NVME_CQE_SC_MDATA_SGL_LEN (0x10 << 1) 263 #define NVME_CQE_SC_SGL_TYPE_INVALID (0x11 << 1) 264 #define NVME_CQE_SC_LBA_RANGE (0x80 << 1) 265 #define NVME_CQE_SC_CAP_EXCEEDED (0x81 << 1) 266 #define NVME_CQE_SC_NS_NOT_RDY (0x82 << 1) 267 #define NVME_CQE_SC_RSV_CONFLICT (0x83 << 1) 268 /* command specific status codes */ 269 #define NVME_CQE_SC_CQE_INVALID (0x00 << 1) 270 #define NVME_CQE_SC_INVALID_QID (0x01 << 1) 271 #define NVME_CQE_SC_MAX_Q_SIZE (0x02 << 1) 272 #define NVME_CQE_SC_ABORT_LIMIT (0x03 << 1) 273 #define NVME_CQE_SC_ASYNC_EV_REQ_LIMIT (0x05 << 1) 274 #define NVME_CQE_SC_INVALID_FW_SLOT (0x06 << 1) 275 #define NVME_CQE_SC_INVALID_FW_IMAGE (0x07 << 1) 276 #define NVME_CQE_SC_INVALID_INT_VEC (0x08 << 1) 277 #define NVME_CQE_SC_INVALID_LOG_PAGE (0x09 << 1) 278 #define NVME_CQE_SC_INVALID_FORMAT (0x0a << 1) 279 #define NVME_CQE_SC_FW_REQ_CNV_RESET (0x0b << 1) 280 #define NVME_CQE_SC_FW_REQ_NVM_RESET (0x10 << 1) 281 #define NVME_CQE_SC_FW_REQ_RESET (0x11 << 1) 282 #define NVME_CQE_SC_FW_MAX_TIME_VIO (0x12 << 1) 283 #define NVME_CQE_SC_FW_PROHIBIT (0x13 << 1) 284 #define NVME_CQE_SC_OVERLAP_RANGE (0x14 << 1) 285 #define NVME_CQE_SC_CONFLICT_ATTRS (0x80 << 1) 286 #define NVME_CQE_SC_INVALID_PROT_INFO (0x81 << 1) 287 #define NVME_CQE_SC_ATT_WR_TO_RO_PAGE (0x82 << 1) 288 /* media error status codes */ 289 #define NVME_CQE_SC_WRITE_FAULTS (0x80 << 1) 290 #define NVME_CQE_SC_UNRECV_READ_ERR (0x81 << 1) 291 #define NVME_CQE_SC_GUARD_CHECK_ERR (0x82 << 1) 292 #define NVME_CQE_SC_APPL_TAG_CHECK_ERR (0x83 << 1) 293 #define NVME_CQE_SC_REF_TAG_CHECK_ERR (0x84 << 1) 294 #define NVME_CQE_SC_CMP_FAIL (0x85 << 1) 295 #define NVME_CQE_SC_ACCESS_DENIED (0x86 << 1) 296 #define NVME_CQE_PHASE __BIT(0) 297 } __packed __aligned(8); 298 299 #define NVM_ADMIN_DEL_IOSQ 0x00 /* Delete I/O Submission Queue */ 300 #define NVM_ADMIN_ADD_IOSQ 0x01 /* Create I/O Submission Queue */ 301 #define NVM_ADMIN_GET_LOG_PG 0x02 /* Get Log Page */ 302 #define NVM_ADMIN_DEL_IOCQ 0x04 /* Delete I/O Completion Queue */ 303 #define NVM_ADMIN_ADD_IOCQ 0x05 /* Create I/O Completion Queue */ 304 #define NVM_ADMIN_IDENTIFY 0x06 /* Identify */ 305 #define NVM_ADMIN_ABORT 0x08 /* Abort */ 306 #define NVM_ADMIN_SET_FEATURES 0x09 /* Set Features */ 307 #define NVM_ADMIN_GET_FEATURES 0x0a /* Get Features */ 308 #define NVM_ADMIN_ASYNC_EV_REQ 0x0c /* Asynchronous Event Request */ 309 #define NVM_ADMIN_FW_COMMIT 0x10 /* Firmware Commit */ 310 #define NVM_ADMIN_FW_DOWNLOAD 0x11 /* Firmware Image Download */ 311 312 #define NVM_CMD_FLUSH 0x00 /* Flush */ 313 #define NVM_CMD_WRITE 0x01 /* Write */ 314 #define NVM_CMD_READ 0x02 /* Read */ 315 #define NVM_CMD_WR_UNCOR 0x04 /* Write Uncorrectable */ 316 #define NVM_CMD_COMPARE 0x05 /* Compare */ 317 #define NVM_CMD_DSM 0x09 /* Dataset Management */ 318 319 /* Features for GET/SET FEATURES */ 320 #define NVM_FEATURE_VOLATILE_WRITE_CACHE 0x06 /* optional */ 321 #define NVM_FEATURE_NUMBER_OF_QUEUES 0x07 /* mandatory */ 322 323 /* Power State Descriptor Data */ 324 struct nvm_identify_psd { 325 uint16_t mp; /* Max Power */ 326 uint8_t _reserved1; 327 uint8_t flags; 328 #define NVME_PSD_NOPS __BIT(1) 329 #define NVME_PSD_MPS __BIT(0) 330 331 uint32_t enlat; /* Entry Latency */ 332 333 uint32_t exlat; /* Exit Latency */ 334 335 uint8_t rrt; /* Relative Read Throughput */ 336 #define NVME_PSD_RRT_MASK __BITS(0, 4) 337 uint8_t rrl; /* Relative Read Latency */ 338 #define NVME_PSD_RRL_MASK __BITS(0, 4) 339 uint8_t rwt; /* Relative Write Throughput */ 340 #define NVME_PSD_RWT_MASK __BITS(0, 4) 341 uint8_t rwl; /* Relative Write Latency */ 342 #define NVME_PSD_RWL_MASK __BITS(0, 4) 343 344 uint16_t idlp; /* Idle Power */ 345 uint8_t ips; /* Idle Power Scale */ 346 #define NVME_PSD_IPS_MASK __BITS(0, 1) 347 uint8_t _reserved2; 348 uint16_t actp; /* Active Power */ 349 uint16_t ap; /* Active Power Workload/Scale */ 350 #define NVME_PSD_APW_MASK __BITS(0, 2) 351 #define NVME_PSD_APS_MASK __BITS(6, 7) 352 353 uint8_t _reserved[8]; 354 } __packed __aligned(8); 355 356 struct nvm_identify_controller { 357 /* Controller Capabilities and Features */ 358 359 uint16_t vid; /* PCI Vendor ID */ 360 uint16_t ssvid; /* PCI Subsystem Vendor ID */ 361 362 uint8_t sn[20]; /* Serial Number */ 363 uint8_t mn[40]; /* Model Number */ 364 uint8_t fr[8]; /* Firmware Revision */ 365 366 uint8_t rab; /* Recommended Arbitration Burst */ 367 uint8_t ieee[3]; /* IEEE OUI Identifier */ 368 369 uint8_t cmic; /* Controller Multi-Path I/O and 370 Namespace Sharing Capabilities */ 371 uint8_t mdts; /* Maximum Data Transfer Size */ 372 uint16_t cntlid; /* Controller ID */ 373 374 uint8_t _reserved1[176]; 375 376 /* Admin Command Set Attributes & Optional Controller Capabilities */ 377 378 uint16_t oacs; /* Optional Admin Command Support */ 379 #define NVME_ID_CTRLR_OACS_NS __BIT(3) 380 #define NVME_ID_CTRLR_OACS_FW __BIT(2) 381 #define NVME_ID_CTRLR_OACS_FORMAT __BIT(1) 382 #define NVME_ID_CTRLR_OACS_SECURITY __BIT(0) 383 uint8_t acl; /* Abort Command Limit */ 384 uint8_t aerl; /* Asynchronous Event Request Limit */ 385 386 uint8_t frmw; /* Firmware Updates */ 387 #define NVME_ID_CTRLR_FRMW_NOREQ_RESET __BIT(4) 388 #define NVME_ID_CTRLR_FRMW_NSLOT __BITS(1, 3) 389 #define NVME_ID_CTRLR_FRMW_SLOT1_RO __BIT(0) 390 uint8_t lpa; /* Log Page Attributes */ 391 #define NVME_ID_CTRLR_LPA_CMD_EFFECT __BIT(1) 392 #define NVME_ID_CTRLR_LPA_NS_SMART __BIT(0) 393 uint8_t elpe; /* Error Log Page Entries */ 394 uint8_t npss; /* Number of Power States Support */ 395 396 uint8_t avscc; /* Admin Vendor Specific Command 397 Configuration */ 398 uint8_t apsta; /* Autonomous Power State Transition 399 Attributes */ 400 401 uint8_t _reserved2[246]; 402 403 /* NVM Command Set Attributes */ 404 405 uint8_t sqes; /* Submission Queue Entry Size */ 406 #define NVME_ID_CTRLR_SQES_MAX __BITS(4, 7) 407 #define NVME_ID_CTRLR_SQES_MIN __BITS(0, 3) 408 uint8_t cqes; /* Completion Queue Entry Size */ 409 #define NVME_ID_CTRLR_CQES_MAX __BITS(4, 7) 410 #define NVME_ID_CTRLR_CQES_MIN __BITS(0, 3) 411 uint8_t _reserved3[2]; 412 413 uint32_t nn; /* Number of Namespaces */ 414 415 uint16_t oncs; /* Optional NVM Command Support */ 416 #define NVME_ID_CTRLR_ONCS_RESERVATION __BIT(5) 417 #define NVME_ID_CTRLR_ONCS_SET_FEATURES __BIT(4) 418 #define NVME_ID_CTRLR_ONCS_WRITE_ZERO __BIT(3) 419 #define NVME_ID_CTRLR_ONCS_DSM __BIT(2) 420 #define NVME_ID_CTRLR_ONCS_WRITE_UNC __BIT(1) 421 #define NVME_ID_CTRLR_ONCS_COMPARE __BIT(0) 422 uint16_t fuses; /* Fused Operation Support */ 423 424 uint8_t fna; /* Format NVM Attributes */ 425 uint8_t vwc; /* Volatile Write Cache */ 426 #define NVME_ID_CTRLR_VWC_PRESENT __BIT(0) 427 uint16_t awun; /* Atomic Write Unit Normal */ 428 429 uint16_t awupf; /* Atomic Write Unit Power Fail */ 430 uint8_t nvscc; /* NVM Vendor Specific Command */ 431 uint8_t _reserved4[1]; 432 433 uint16_t acwu; /* Atomic Compare & Write Unit */ 434 uint8_t _reserved5[2]; 435 436 uint32_t sgls; /* SGL Support */ 437 438 uint8_t _reserved6[164]; 439 440 /* I/O Command Set Attributes */ 441 442 uint8_t _reserved7[1344]; 443 444 /* Power State Descriptors */ 445 446 struct nvm_identify_psd psd[32]; /* Power State Descriptors */ 447 448 /* Vendor Specific */ 449 450 uint8_t _reserved8[1024]; 451 } __packed __aligned(8); 452 453 struct nvm_namespace_format { 454 uint16_t ms; /* Metadata Size */ 455 uint8_t lbads; /* LBA Data Size */ 456 uint8_t rp; /* Relative Performance */ 457 } __packed __aligned(4); 458 459 struct nvm_identify_namespace { 460 uint64_t nsze; /* Namespace Size */ 461 462 uint64_t ncap; /* Namespace Capacity */ 463 464 uint64_t nuse; /* Namespace Utilization */ 465 466 uint8_t nsfeat; /* Namespace Features */ 467 #define NVME_ID_NS_NSFEAT_LOGICAL_BLK_ERR __BIT(2) 468 #define NVME_ID_NS_NSFEAT_NS __BIT(1) 469 #define NVME_ID_NS_NSFEAT_THIN_PROV __BIT(0) 470 uint8_t nlbaf; /* Number of LBA Formats */ 471 uint8_t flbas; /* Formatted LBA Size */ 472 #define NVME_ID_NS_FLBAS(_f) ((_f) & 0x0f) 473 #define NVME_ID_NS_FLBAS_MD 0x10 474 uint8_t mc; /* Metadata Capabilities */ 475 uint8_t dpc; /* End-to-end Data Protection 476 Capabilities */ 477 uint8_t dps; /* End-to-end Data Protection Type Settings */ 478 479 uint8_t _reserved1[98]; 480 481 struct nvm_namespace_format 482 lbaf[16]; /* LBA Format Support */ 483 484 uint8_t _reserved2[192]; 485 486 uint8_t vs[3712]; 487 } __packed __aligned(8); 488 489 #endif /* __NVMEREG_H__ */ 490
Indexes created Sat Sep 27 22:09:54 GMT 2025