oosiop.c revision 1.12.26.1
1 /* $NetBSD: oosiop.c,v 1.12.26.1 2011/03/05 20:53:19 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Shuichiro URATA. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * NCR53C700 SCSI I/O processor (OOSIOP) driver 31 * 32 * TODO: 33 * - More better error handling. 34 * - Implement tagged queuing. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: oosiop.c,v 1.12.26.1 2011/03/05 20:53:19 rmind Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/buf.h> 46 #include <sys/malloc.h> 47 #include <sys/queue.h> 48 49 #include <dev/scsipi/scsi_all.h> 50 #include <dev/scsipi/scsipi_all.h> 51 #include <dev/scsipi/scsiconf.h> 52 #include <dev/scsipi/scsi_message.h> 53 54 #include <sys/cpu.h> 55 #include <sys/bus.h> 56 57 #include <dev/ic/oosiopreg.h> 58 #include <dev/ic/oosiopvar.h> 59 #include <dev/microcode/siop/oosiop.out> 60 61 static int oosiop_alloc_cb(struct oosiop_softc *, int); 62 63 static inline void oosiop_relocate_io(struct oosiop_softc *, bus_addr_t); 64 static inline void oosiop_relocate_tc(struct oosiop_softc *, bus_addr_t); 65 static inline void oosiop_fixup_select(struct oosiop_softc *, bus_addr_t, 66 int); 67 static inline void oosiop_fixup_jump(struct oosiop_softc *, bus_addr_t, 68 bus_addr_t); 69 static inline void oosiop_fixup_move(struct oosiop_softc *, bus_addr_t, 70 bus_size_t, bus_addr_t); 71 72 static void oosiop_load_script(struct oosiop_softc *); 73 static void oosiop_setup_sgdma(struct oosiop_softc *, struct oosiop_cb *); 74 static void oosiop_setup_dma(struct oosiop_softc *); 75 static void oosiop_flush_fifo(struct oosiop_softc *); 76 static void oosiop_clear_fifo(struct oosiop_softc *); 77 static void oosiop_phasemismatch(struct oosiop_softc *); 78 static void oosiop_setup_syncxfer(struct oosiop_softc *); 79 static void oosiop_set_syncparam(struct oosiop_softc *, int, int, int); 80 static void oosiop_minphys(struct buf *); 81 static void oosiop_scsipi_request(struct scsipi_channel *, 82 scsipi_adapter_req_t, void *); 83 static void oosiop_done(struct oosiop_softc *, struct oosiop_cb *); 84 static void oosiop_timeout(void *); 85 static void oosiop_reset(struct oosiop_softc *); 86 static void oosiop_reset_bus(struct oosiop_softc *); 87 static void oosiop_scriptintr(struct oosiop_softc *); 88 static void oosiop_msgin(struct oosiop_softc *, struct oosiop_cb *); 89 90 /* Trap interrupt code for unexpected data I/O */ 91 #define DATAIN_TRAP 0xdead0001 92 #define DATAOUT_TRAP 0xdead0002 93 94 /* Possible TP and SCF conbination */ 95 static const struct { 96 uint8_t tp; 97 uint8_t scf; 98 } synctbl[] = { 99 {0, 1}, /* SCLK / 4.0 */ 100 {1, 1}, /* SCLK / 5.0 */ 101 {2, 1}, /* SCLK / 6.0 */ 102 {3, 1}, /* SCLK / 7.0 */ 103 {1, 2}, /* SCLK / 7.5 */ 104 {4, 1}, /* SCLK / 8.0 */ 105 {5, 1}, /* SCLK / 9.0 */ 106 {6, 1}, /* SCLK / 10.0 */ 107 {3, 2}, /* SCLK / 10.5 */ 108 {7, 1}, /* SCLK / 11.0 */ 109 {4, 2}, /* SCLK / 12.0 */ 110 {5, 2}, /* SCLK / 13.5 */ 111 {3, 3}, /* SCLK / 14.0 */ 112 {6, 2}, /* SCLK / 15.0 */ 113 {4, 3}, /* SCLK / 16.0 */ 114 {7, 2}, /* SCLK / 16.5 */ 115 {5, 3}, /* SCLK / 18.0 */ 116 {6, 3}, /* SCLK / 20.0 */ 117 {7, 3} /* SCLK / 22.0 */ 118 }; 119 #define NSYNCTBL (sizeof(synctbl) / sizeof(synctbl[0])) 120 121 #define oosiop_period(sc, tp, scf) \ 122 (((1000000000 / (sc)->sc_freq) * (tp) * (scf)) / 40) 123 124 void 125 oosiop_attach(struct oosiop_softc *sc) 126 { 127 bus_size_t scrsize; 128 bus_dma_segment_t seg; 129 struct oosiop_cb *cb; 130 int err, i, nseg; 131 132 /* 133 * Allocate DMA-safe memory for the script and map it. 134 */ 135 scrsize = sizeof(oosiop_script); 136 err = bus_dmamem_alloc(sc->sc_dmat, scrsize, PAGE_SIZE, 0, &seg, 1, 137 &nseg, BUS_DMA_NOWAIT); 138 if (err) { 139 aprint_error(": failed to allocate script memory, err=%d\n", 140 err); 141 return; 142 } 143 err = bus_dmamem_map(sc->sc_dmat, &seg, nseg, scrsize, 144 (void **)&sc->sc_scr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 145 if (err) { 146 aprint_error(": failed to map script memory, err=%d\n", err); 147 return; 148 } 149 err = bus_dmamap_create(sc->sc_dmat, scrsize, 1, scrsize, 0, 150 BUS_DMA_NOWAIT, &sc->sc_scrdma); 151 if (err) { 152 aprint_error(": failed to create script map, err=%d\n", err); 153 return; 154 } 155 err = bus_dmamap_load(sc->sc_dmat, sc->sc_scrdma, sc->sc_scr, scrsize, 156 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 157 if (err) { 158 aprint_error(": failed to load script map, err=%d\n", err); 159 return; 160 } 161 sc->sc_scrbase = sc->sc_scrdma->dm_segs[0].ds_addr; 162 163 /* Initialize command block array */ 164 TAILQ_INIT(&sc->sc_free_cb); 165 TAILQ_INIT(&sc->sc_cbq); 166 if (oosiop_alloc_cb(sc, OOSIOP_NCB) != 0) 167 return; 168 169 /* Use first cb to reselection msgin buffer */ 170 cb = TAILQ_FIRST(&sc->sc_free_cb); 171 sc->sc_reselbuf = cb->xferdma->dm_segs[0].ds_addr + 172 offsetof(struct oosiop_xfer, msgin[0]); 173 174 for (i = 0; i < OOSIOP_NTGT; i++) { 175 sc->sc_tgt[i].nexus = NULL; 176 sc->sc_tgt[i].flags = 0; 177 } 178 179 /* Setup asynchronous clock divisor parameters */ 180 if (sc->sc_freq <= 25000000) { 181 sc->sc_ccf = 10; 182 sc->sc_dcntl = OOSIOP_DCNTL_CF_1; 183 } else if (sc->sc_freq <= 37500000) { 184 sc->sc_ccf = 15; 185 sc->sc_dcntl = OOSIOP_DCNTL_CF_1_5; 186 } else if (sc->sc_freq <= 50000000) { 187 sc->sc_ccf = 20; 188 sc->sc_dcntl = OOSIOP_DCNTL_CF_2; 189 } else { 190 sc->sc_ccf = 30; 191 sc->sc_dcntl = OOSIOP_DCNTL_CF_3; 192 } 193 194 if (sc->sc_chip == OOSIOP_700) 195 sc->sc_minperiod = oosiop_period(sc, 4, sc->sc_ccf); 196 else 197 sc->sc_minperiod = oosiop_period(sc, 4, 10); 198 199 if (sc->sc_minperiod < 25) 200 sc->sc_minperiod = 25; /* limit to 10MB/s */ 201 202 aprint_normal(": NCR53C700%s rev %d, %dMHz, SCSI ID %d\n", 203 sc->sc_chip == OOSIOP_700_66 ? "-66" : "", 204 oosiop_read_1(sc, OOSIOP_CTEST7) >> 4, 205 sc->sc_freq / 1000000, sc->sc_id); 206 /* 207 * Reset all 208 */ 209 oosiop_reset(sc); 210 oosiop_reset_bus(sc); 211 212 /* 213 * Start SCRIPTS processor 214 */ 215 oosiop_load_script(sc); 216 sc->sc_active = 0; 217 oosiop_write_4(sc, OOSIOP_DSP, sc->sc_scrbase + Ent_wait_reselect); 218 219 /* 220 * Fill in the scsipi_adapter. 221 */ 222 sc->sc_adapter.adapt_dev = sc->sc_dev; 223 sc->sc_adapter.adapt_nchannels = 1; 224 sc->sc_adapter.adapt_openings = OOSIOP_NCB; 225 sc->sc_adapter.adapt_max_periph = 1; 226 sc->sc_adapter.adapt_ioctl = NULL; 227 sc->sc_adapter.adapt_minphys = oosiop_minphys; 228 sc->sc_adapter.adapt_request = oosiop_scsipi_request; 229 230 /* 231 * Fill in the scsipi_channel. 232 */ 233 sc->sc_channel.chan_adapter = &sc->sc_adapter; 234 sc->sc_channel.chan_bustype = &scsi_bustype; 235 sc->sc_channel.chan_channel = 0; 236 sc->sc_channel.chan_ntargets = OOSIOP_NTGT; 237 sc->sc_channel.chan_nluns = 8; 238 sc->sc_channel.chan_id = sc->sc_id; 239 240 /* 241 * Now try to attach all the sub devices. 242 */ 243 config_found(sc->sc_dev, &sc->sc_channel, scsiprint); 244 } 245 246 static int 247 oosiop_alloc_cb(struct oosiop_softc *sc, int ncb) 248 { 249 struct oosiop_cb *cb; 250 struct oosiop_xfer *xfer; 251 bus_size_t xfersize; 252 bus_dma_segment_t seg; 253 int i, s, err, nseg; 254 255 /* 256 * Allocate oosiop_cb. 257 */ 258 cb = malloc(sizeof(struct oosiop_cb) * ncb, M_DEVBUF, M_NOWAIT|M_ZERO); 259 if (cb == NULL) { 260 printf(": failed to allocate cb memory\n"); 261 return (ENOMEM); 262 } 263 264 /* 265 * Allocate DMA-safe memory for the oosiop_xfer and map it. 266 */ 267 xfersize = sizeof(struct oosiop_xfer) * ncb; 268 err = bus_dmamem_alloc(sc->sc_dmat, xfersize, PAGE_SIZE, 0, &seg, 1, 269 &nseg, BUS_DMA_NOWAIT); 270 if (err) { 271 printf(": failed to allocate xfer block memory, err=%d\n", err); 272 return (err); 273 } 274 err = bus_dmamem_map(sc->sc_dmat, &seg, nseg, xfersize, 275 (void **)(void *)&xfer, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 276 if (err) { 277 printf(": failed to map xfer block memory, err=%d\n", err); 278 return (err); 279 } 280 281 /* Initialize each command block */ 282 for (i = 0; i < ncb; i++) { 283 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 284 0, BUS_DMA_NOWAIT, &cb->cmddma); 285 if (err) { 286 printf(": failed to create cmddma map, err=%d\n", err); 287 return (err); 288 } 289 err = bus_dmamap_create(sc->sc_dmat, OOSIOP_MAX_XFER, 290 OOSIOP_NSG, OOSIOP_DBC_MAX, 0, BUS_DMA_NOWAIT, 291 &cb->datadma); 292 if (err) { 293 printf(": failed to create datadma map, err=%d\n", err); 294 return (err); 295 } 296 297 err = bus_dmamap_create(sc->sc_dmat, 298 sizeof(struct oosiop_xfer), 1, sizeof(struct oosiop_xfer), 299 0, BUS_DMA_NOWAIT, &cb->xferdma); 300 if (err) { 301 printf(": failed to create xfer block map, err=%d\n", 302 err); 303 return (err); 304 } 305 err = bus_dmamap_load(sc->sc_dmat, cb->xferdma, xfer, 306 sizeof(struct oosiop_xfer), NULL, BUS_DMA_NOWAIT); 307 if (err) { 308 printf(": failed to load xfer block, err=%d\n", err); 309 return (err); 310 } 311 312 cb->xfer = xfer; 313 314 s = splbio(); 315 TAILQ_INSERT_TAIL(&sc->sc_free_cb, cb, chain); 316 splx(s); 317 318 cb++; 319 xfer++; 320 } 321 322 return (0); 323 } 324 325 static inline void 326 oosiop_relocate_io(struct oosiop_softc *sc, bus_addr_t addr) 327 { 328 uint32_t dcmd; 329 int32_t dsps; 330 331 dcmd = le32toh(sc->sc_scr[addr / 4 + 0]); 332 dsps = le32toh(sc->sc_scr[addr / 4 + 1]); 333 334 /* convert relative to absolute */ 335 if (dcmd & 0x04000000) { 336 dcmd &= ~0x04000000; 337 #if 0 338 /* 339 * sign extension isn't needed here because 340 * ncr53cxxx.c generates 32 bit dsps. 341 */ 342 dsps <<= 8; 343 dsps >>= 8; 344 #endif 345 sc->sc_scr[addr / 4 + 0] = htole32(dcmd); 346 dsps += addr + 8; 347 } 348 349 sc->sc_scr[addr / 4 + 1] = htole32(dsps + sc->sc_scrbase); 350 } 351 352 static inline void 353 oosiop_relocate_tc(struct oosiop_softc *sc, bus_addr_t addr) 354 { 355 uint32_t dcmd; 356 int32_t dsps; 357 358 dcmd = le32toh(sc->sc_scr[addr / 4 + 0]); 359 dsps = le32toh(sc->sc_scr[addr / 4 + 1]); 360 361 /* convert relative to absolute */ 362 if (dcmd & 0x00800000) { 363 dcmd &= ~0x00800000; 364 sc->sc_scr[addr / 4] = htole32(dcmd); 365 #if 0 366 /* 367 * sign extension isn't needed here because 368 * ncr53cxxx.c generates 32 bit dsps. 369 */ 370 dsps <<= 8; 371 dsps >>= 8; 372 #endif 373 dsps += addr + 8; 374 } 375 376 sc->sc_scr[addr / 4 + 1] = htole32(dsps + sc->sc_scrbase); 377 } 378 379 static inline void 380 oosiop_fixup_select(struct oosiop_softc *sc, bus_addr_t addr, int id) 381 { 382 uint32_t dcmd; 383 384 dcmd = le32toh(sc->sc_scr[addr / 4]); 385 dcmd &= 0xff00ffff; 386 dcmd |= 0x00010000 << id; 387 sc->sc_scr[addr / 4] = htole32(dcmd); 388 } 389 390 static inline void 391 oosiop_fixup_jump(struct oosiop_softc *sc, bus_addr_t addr, bus_addr_t dst) 392 { 393 394 sc->sc_scr[addr / 4 + 1] = htole32(dst); 395 } 396 397 static inline void 398 oosiop_fixup_move(struct oosiop_softc *sc, bus_addr_t addr, bus_size_t dbc, 399 bus_addr_t dsps) 400 { 401 uint32_t dcmd; 402 403 dcmd = le32toh(sc->sc_scr[addr / 4]); 404 dcmd &= 0xff000000; 405 dcmd |= dbc & 0x00ffffff; 406 sc->sc_scr[addr / 4 + 0] = htole32(dcmd); 407 sc->sc_scr[addr / 4 + 1] = htole32(dsps); 408 } 409 410 static void 411 oosiop_load_script(struct oosiop_softc *sc) 412 { 413 int i; 414 415 /* load script */ 416 for (i = 0; i < sizeof(oosiop_script) / sizeof(oosiop_script[0]); i++) 417 sc->sc_scr[i] = htole32(oosiop_script[i]); 418 419 /* relocate script */ 420 for (i = 0; i < (sizeof(oosiop_script) / 8); i++) { 421 switch (oosiop_script[i * 2] >> 27) { 422 case 0x08: /* select */ 423 case 0x0a: /* wait reselect */ 424 oosiop_relocate_io(sc, i * 8); 425 break; 426 case 0x10: /* jump */ 427 case 0x11: /* call */ 428 oosiop_relocate_tc(sc, i * 8); 429 break; 430 } 431 } 432 433 oosiop_fixup_move(sc, Ent_p_resel_msgin_move, 1, sc->sc_reselbuf); 434 OOSIOP_SCRIPT_SYNC(sc, BUS_DMASYNC_PREWRITE); 435 } 436 437 static void 438 oosiop_setup_sgdma(struct oosiop_softc *sc, struct oosiop_cb *cb) 439 { 440 int i, n, off, control; 441 struct oosiop_xfer *xfer; 442 443 OOSIOP_XFERSCR_SYNC(sc, cb, 444 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 445 446 off = cb->curdp; 447 xfer = cb->xfer; 448 control = cb->xs->xs_control; 449 450 if (control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 451 /* Find start segment */ 452 for (i = 0; i < cb->datadma->dm_nsegs; i++) { 453 if (off < cb->datadma->dm_segs[i].ds_len) 454 break; 455 off -= cb->datadma->dm_segs[i].ds_len; 456 } 457 458 /* build MOVE block */ 459 if (control & XS_CTL_DATA_IN) { 460 n = 0; 461 while (i < cb->datadma->dm_nsegs) { 462 xfer->datain_scr[n * 2 + 0] = 463 htole32(0x09000000 | 464 (cb->datadma->dm_segs[i].ds_len - off)); 465 xfer->datain_scr[n * 2 + 1] = 466 htole32(cb->datadma->dm_segs[i].ds_addr + 467 off); 468 n++; 469 i++; 470 off = 0; 471 } 472 xfer->datain_scr[n * 2 + 0] = htole32(0x80080000); 473 xfer->datain_scr[n * 2 + 1] = 474 htole32(sc->sc_scrbase + Ent_phasedispatch); 475 } 476 if (control & XS_CTL_DATA_OUT) { 477 n = 0; 478 while (i < cb->datadma->dm_nsegs) { 479 xfer->dataout_scr[n * 2 + 0] = 480 htole32(0x08000000 | 481 (cb->datadma->dm_segs[i].ds_len - off)); 482 xfer->dataout_scr[n * 2 + 1] = 483 htole32(cb->datadma->dm_segs[i].ds_addr + 484 off); 485 n++; 486 i++; 487 off = 0; 488 } 489 xfer->dataout_scr[n * 2 + 0] = htole32(0x80080000); 490 xfer->dataout_scr[n * 2 + 1] = 491 htole32(sc->sc_scrbase + Ent_phasedispatch); 492 } 493 } 494 if ((control & XS_CTL_DATA_IN) == 0) { 495 xfer->datain_scr[0] = htole32(0x98080000); 496 xfer->datain_scr[1] = htole32(DATAIN_TRAP); 497 } 498 if ((control & XS_CTL_DATA_OUT) == 0) { 499 xfer->dataout_scr[0] = htole32(0x98080000); 500 xfer->dataout_scr[1] = htole32(DATAOUT_TRAP); 501 } 502 OOSIOP_XFERSCR_SYNC(sc, cb, 503 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 504 } 505 506 /* 507 * Setup DMA pointer into script. 508 */ 509 static void 510 oosiop_setup_dma(struct oosiop_softc *sc) 511 { 512 struct oosiop_cb *cb; 513 bus_addr_t xferbase; 514 515 cb = sc->sc_curcb; 516 xferbase = cb->xferdma->dm_segs[0].ds_addr; 517 518 OOSIOP_SCRIPT_SYNC(sc, BUS_DMASYNC_POSTWRITE); 519 520 oosiop_fixup_select(sc, Ent_p_select, cb->id); 521 oosiop_fixup_jump(sc, Ent_p_datain_jump, xferbase + 522 offsetof(struct oosiop_xfer, datain_scr[0])); 523 oosiop_fixup_jump(sc, Ent_p_dataout_jump, xferbase + 524 offsetof(struct oosiop_xfer, dataout_scr[0])); 525 oosiop_fixup_move(sc, Ent_p_msgin_move, 1, xferbase + 526 offsetof(struct oosiop_xfer, msgin[0])); 527 oosiop_fixup_move(sc, Ent_p_extmsglen_move, 1, xferbase + 528 offsetof(struct oosiop_xfer, msgin[1])); 529 oosiop_fixup_move(sc, Ent_p_msgout_move, cb->msgoutlen, xferbase + 530 offsetof(struct oosiop_xfer, msgout[0])); 531 oosiop_fixup_move(sc, Ent_p_status_move, 1, xferbase + 532 offsetof(struct oosiop_xfer, status)); 533 oosiop_fixup_move(sc, Ent_p_cmdout_move, cb->xs->cmdlen, 534 cb->cmddma->dm_segs[0].ds_addr); 535 536 OOSIOP_SCRIPT_SYNC(sc, BUS_DMASYNC_PREWRITE); 537 } 538 539 static void 540 oosiop_flush_fifo(struct oosiop_softc *sc) 541 { 542 543 oosiop_write_1(sc, OOSIOP_DFIFO, oosiop_read_1(sc, OOSIOP_DFIFO) | 544 OOSIOP_DFIFO_FLF); 545 while ((oosiop_read_1(sc, OOSIOP_CTEST1) & OOSIOP_CTEST1_FMT) != 546 OOSIOP_CTEST1_FMT) 547 ; 548 oosiop_write_1(sc, OOSIOP_DFIFO, oosiop_read_1(sc, OOSIOP_DFIFO) & 549 ~OOSIOP_DFIFO_FLF); 550 } 551 552 static void 553 oosiop_clear_fifo(struct oosiop_softc *sc) 554 { 555 556 oosiop_write_1(sc, OOSIOP_DFIFO, oosiop_read_1(sc, OOSIOP_DFIFO) | 557 OOSIOP_DFIFO_CLF); 558 while ((oosiop_read_1(sc, OOSIOP_CTEST1) & OOSIOP_CTEST1_FMT) != 559 OOSIOP_CTEST1_FMT) 560 ; 561 oosiop_write_1(sc, OOSIOP_DFIFO, oosiop_read_1(sc, OOSIOP_DFIFO) & 562 ~OOSIOP_DFIFO_CLF); 563 } 564 565 static void 566 oosiop_phasemismatch(struct oosiop_softc *sc) 567 { 568 struct oosiop_cb *cb; 569 uint32_t dsp, dbc, n, i, len; 570 uint8_t dfifo, sstat1; 571 572 cb = sc->sc_curcb; 573 if (cb == NULL) 574 return; 575 576 dsp = oosiop_read_4(sc, OOSIOP_DSP); 577 dbc = oosiop_read_4(sc, OOSIOP_DBC) & OOSIOP_DBC_MAX; 578 len = 0; 579 580 n = dsp - cb->xferdma->dm_segs[0].ds_addr - 8; 581 if (n >= offsetof(struct oosiop_xfer, datain_scr[0]) && 582 n < offsetof(struct oosiop_xfer, datain_scr[OOSIOP_NSG * 2])) { 583 n -= offsetof(struct oosiop_xfer, datain_scr[0]); 584 n >>= 3; 585 OOSIOP_DINSCR_SYNC(sc, cb, 586 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 587 for (i = 0; i <= n; i++) 588 len += le32toh(cb->xfer->datain_scr[i * 2]) & 589 0x00ffffff; 590 OOSIOP_DINSCR_SYNC(sc, cb, 591 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 592 /* All data in the chip are already flushed */ 593 } else if (n >= offsetof(struct oosiop_xfer, dataout_scr[0]) && 594 n < offsetof(struct oosiop_xfer, dataout_scr[OOSIOP_NSG * 2])) { 595 n -= offsetof(struct oosiop_xfer, dataout_scr[0]); 596 n >>= 3; 597 OOSIOP_DOUTSCR_SYNC(sc, cb, 598 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 599 for (i = 0; i <= n; i++) 600 len += le32toh(cb->xfer->dataout_scr[i * 2]) & 601 0x00ffffff; 602 OOSIOP_DOUTSCR_SYNC(sc, cb, 603 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 604 605 dfifo = oosiop_read_1(sc, OOSIOP_DFIFO); 606 dbc += ((dfifo & OOSIOP_DFIFO_BO) - (dbc & OOSIOP_DFIFO_BO)) & 607 OOSIOP_DFIFO_BO; 608 609 sstat1 = oosiop_read_1(sc, OOSIOP_SSTAT1); 610 if (sstat1 & OOSIOP_SSTAT1_OLF) 611 dbc++; 612 if ((sc->sc_tgt[cb->id].sxfer != 0) && 613 (sstat1 & OOSIOP_SSTAT1_ORF) != 0) 614 dbc++; 615 616 oosiop_clear_fifo(sc); 617 } else { 618 printf("%s: phase mismatch addr=%08x\n", 619 device_xname(sc->sc_dev), 620 oosiop_read_4(sc, OOSIOP_DSP) - 8); 621 oosiop_clear_fifo(sc); 622 return; 623 } 624 625 len -= dbc; 626 if (len) { 627 cb->curdp += len; 628 oosiop_setup_sgdma(sc, cb); 629 } 630 } 631 632 static void 633 oosiop_setup_syncxfer(struct oosiop_softc *sc) 634 { 635 int id; 636 637 id = sc->sc_curcb->id; 638 if (sc->sc_chip != OOSIOP_700) 639 oosiop_write_1(sc, OOSIOP_SBCL, sc->sc_tgt[id].scf); 640 641 oosiop_write_1(sc, OOSIOP_SXFER, sc->sc_tgt[id].sxfer); 642 } 643 644 static void 645 oosiop_set_syncparam(struct oosiop_softc *sc, int id, int period, int offset) 646 { 647 int i, p; 648 struct scsipi_xfer_mode xm; 649 650 xm.xm_target = id; 651 xm.xm_mode = 0; 652 xm.xm_period = 0; 653 xm.xm_offset = 0; 654 655 if (offset == 0) { 656 /* Asynchronous */ 657 sc->sc_tgt[id].scf = 0; 658 sc->sc_tgt[id].sxfer = 0; 659 } else { 660 /* Synchronous */ 661 if (sc->sc_chip == OOSIOP_700) { 662 for (i = 4; i < 12; i++) { 663 p = oosiop_period(sc, i, sc->sc_ccf); 664 if (p >= period) 665 break; 666 } 667 if (i == 12) { 668 printf("%s: target %d period too large\n", 669 device_xname(sc->sc_dev), id); 670 i = 11; /* XXX */ 671 } 672 sc->sc_tgt[id].scf = 0; 673 sc->sc_tgt[id].sxfer = ((i - 4) << 4) | offset; 674 } else { 675 for (i = 0; i < NSYNCTBL; i++) { 676 p = oosiop_period(sc, synctbl[i].tp + 4, 677 (synctbl[i].scf + 1) * 5); 678 if (p >= period) 679 break; 680 } 681 if (i == NSYNCTBL) { 682 printf("%s: target %d period too large\n", 683 device_xname(sc->sc_dev), id); 684 i = NSYNCTBL - 1; /* XXX */ 685 } 686 sc->sc_tgt[id].scf = synctbl[i].scf; 687 sc->sc_tgt[id].sxfer = (synctbl[i].tp << 4) | offset; 688 } 689 690 xm.xm_mode |= PERIPH_CAP_SYNC; 691 xm.xm_period = period; 692 xm.xm_offset = offset; 693 } 694 695 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 696 } 697 698 static void 699 oosiop_minphys(struct buf *bp) 700 { 701 702 if (bp->b_bcount > OOSIOP_MAX_XFER) 703 bp->b_bcount = OOSIOP_MAX_XFER; 704 minphys(bp); 705 } 706 707 static void 708 oosiop_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 709 void *arg) 710 { 711 struct scsipi_xfer *xs; 712 struct oosiop_softc *sc; 713 struct oosiop_cb *cb; 714 struct oosiop_xfer *xfer; 715 struct scsipi_xfer_mode *xm; 716 int s, err; 717 718 sc = device_private(chan->chan_adapter->adapt_dev); 719 720 switch (req) { 721 case ADAPTER_REQ_RUN_XFER: 722 xs = arg; 723 724 s = splbio(); 725 cb = TAILQ_FIRST(&sc->sc_free_cb); 726 TAILQ_REMOVE(&sc->sc_free_cb, cb, chain); 727 splx(s); 728 729 cb->xs = xs; 730 cb->flags = 0; 731 cb->id = xs->xs_periph->periph_target; 732 cb->lun = xs->xs_periph->periph_lun; 733 cb->curdp = 0; 734 cb->savedp = 0; 735 xfer = cb->xfer; 736 737 /* Setup SCSI command buffer DMA */ 738 err = bus_dmamap_load(sc->sc_dmat, cb->cmddma, xs->cmd, 739 xs->cmdlen, NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 740 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_WRITE); 741 if (err) { 742 printf("%s: unable to load cmd DMA map: %d", 743 device_xname(sc->sc_dev), err); 744 xs->error = XS_RESOURCE_SHORTAGE; 745 TAILQ_INSERT_TAIL(&sc->sc_free_cb, cb, chain); 746 scsipi_done(xs); 747 return; 748 } 749 bus_dmamap_sync(sc->sc_dmat, cb->cmddma, 0, xs->cmdlen, 750 BUS_DMASYNC_PREWRITE); 751 752 /* Setup data buffer DMA */ 753 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 754 err = bus_dmamap_load(sc->sc_dmat, cb->datadma, 755 xs->data, xs->datalen, NULL, 756 ((xs->xs_control & XS_CTL_NOSLEEP) ? 757 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 758 BUS_DMA_STREAMING | 759 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : 760 BUS_DMA_WRITE)); 761 if (err) { 762 printf("%s: unable to load data DMA map: %d", 763 device_xname(sc->sc_dev), err); 764 xs->error = XS_RESOURCE_SHORTAGE; 765 bus_dmamap_unload(sc->sc_dmat, cb->cmddma); 766 TAILQ_INSERT_TAIL(&sc->sc_free_cb, cb, chain); 767 scsipi_done(xs); 768 return; 769 } 770 bus_dmamap_sync(sc->sc_dmat, cb->datadma, 771 0, xs->datalen, 772 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 773 } 774 775 oosiop_setup_sgdma(sc, cb); 776 777 /* Setup msgout buffer */ 778 OOSIOP_XFERMSG_SYNC(sc, cb, 779 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 780 xfer->msgout[0] = MSG_IDENTIFY(cb->lun, 781 (xs->xs_control & XS_CTL_REQSENSE) == 0); 782 cb->msgoutlen = 1; 783 784 if (sc->sc_tgt[cb->id].flags & TGTF_SYNCNEG) { 785 /* Send SDTR */ 786 xfer->msgout[1] = MSG_EXTENDED; 787 xfer->msgout[2] = MSG_EXT_SDTR_LEN; 788 xfer->msgout[3] = MSG_EXT_SDTR; 789 xfer->msgout[4] = sc->sc_minperiod; 790 xfer->msgout[5] = OOSIOP_MAX_OFFSET; 791 cb->msgoutlen = 6; 792 sc->sc_tgt[cb->id].flags &= ~TGTF_SYNCNEG; 793 sc->sc_tgt[cb->id].flags |= TGTF_WAITSDTR; 794 } 795 796 xfer->status = SCSI_OOSIOP_NOSTATUS; 797 798 OOSIOP_XFERMSG_SYNC(sc, cb, 799 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 800 801 s = splbio(); 802 803 TAILQ_INSERT_TAIL(&sc->sc_cbq, cb, chain); 804 805 if (!sc->sc_active) { 806 /* Abort script to start selection */ 807 oosiop_write_1(sc, OOSIOP_ISTAT, OOSIOP_ISTAT_ABRT); 808 } 809 if (xs->xs_control & XS_CTL_POLL) { 810 /* Poll for command completion */ 811 while ((xs->xs_status & XS_STS_DONE) == 0) { 812 delay(1000); 813 oosiop_intr(sc); 814 } 815 } 816 817 splx(s); 818 819 return; 820 821 case ADAPTER_REQ_GROW_RESOURCES: 822 return; 823 824 case ADAPTER_REQ_SET_XFER_MODE: 825 xm = arg; 826 if (xm->xm_mode & PERIPH_CAP_SYNC) 827 sc->sc_tgt[xm->xm_target].flags |= TGTF_SYNCNEG; 828 else 829 oosiop_set_syncparam(sc, xm->xm_target, 0, 0); 830 831 return; 832 } 833 } 834 835 static void 836 oosiop_done(struct oosiop_softc *sc, struct oosiop_cb *cb) 837 { 838 struct scsipi_xfer *xs; 839 840 xs = cb->xs; 841 if (cb == sc->sc_curcb) 842 sc->sc_curcb = NULL; 843 if (cb == sc->sc_lastcb) 844 sc->sc_lastcb = NULL; 845 sc->sc_tgt[cb->id].nexus = NULL; 846 847 callout_stop(&xs->xs_callout); 848 849 bus_dmamap_sync(sc->sc_dmat, cb->cmddma, 0, xs->cmdlen, 850 BUS_DMASYNC_POSTWRITE); 851 bus_dmamap_unload(sc->sc_dmat, cb->cmddma); 852 853 if (xs->datalen > 0) { 854 bus_dmamap_sync(sc->sc_dmat, cb->datadma, 0, xs->datalen, 855 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 856 bus_dmamap_unload(sc->sc_dmat, cb->datadma); 857 } 858 859 xs->status = cb->xfer->status; 860 xs->resid = 0; /* XXX */ 861 862 if (cb->flags & CBF_SELTOUT) 863 xs->error = XS_SELTIMEOUT; 864 else if (cb->flags & CBF_TIMEOUT) 865 xs->error = XS_TIMEOUT; 866 else switch (xs->status) { 867 case SCSI_OK: 868 xs->error = XS_NOERROR; 869 break; 870 871 case SCSI_BUSY: 872 case SCSI_CHECK: 873 xs->error = XS_BUSY; 874 break; 875 case SCSI_OOSIOP_NOSTATUS: 876 /* the status byte was not updated, cmd was aborted. */ 877 xs->error = XS_SELTIMEOUT; 878 break; 879 880 default: 881 xs->error = XS_RESET; 882 break; 883 } 884 885 scsipi_done(xs); 886 887 /* Put it on the free list. */ 888 TAILQ_INSERT_TAIL(&sc->sc_free_cb, cb, chain); 889 } 890 891 static void 892 oosiop_timeout(void *arg) 893 { 894 struct oosiop_cb *cb; 895 struct scsipi_periph *periph; 896 struct oosiop_softc *sc; 897 int s; 898 899 cb = arg; 900 periph = cb->xs->xs_periph; 901 sc = device_private(periph->periph_channel->chan_adapter->adapt_dev); 902 scsipi_printaddr(periph); 903 printf("timed out\n"); 904 905 s = splbio(); 906 907 cb->flags |= CBF_TIMEOUT; 908 oosiop_done(sc, cb); 909 910 splx(s); 911 } 912 913 static void 914 oosiop_reset(struct oosiop_softc *sc) 915 { 916 int i, s; 917 918 s = splbio(); 919 920 /* Stop SCRIPTS processor */ 921 oosiop_write_1(sc, OOSIOP_ISTAT, OOSIOP_ISTAT_ABRT); 922 delay(100); 923 oosiop_write_1(sc, OOSIOP_ISTAT, 0); 924 925 /* Reset the chip */ 926 oosiop_write_1(sc, OOSIOP_DCNTL, sc->sc_dcntl | OOSIOP_DCNTL_RST); 927 delay(100); 928 oosiop_write_1(sc, OOSIOP_DCNTL, sc->sc_dcntl); 929 delay(10000); 930 931 /* Set up various chip parameters */ 932 oosiop_write_1(sc, OOSIOP_SCNTL0, OOSIOP_ARB_FULL | OOSIOP_SCNTL0_EPG); 933 oosiop_write_1(sc, OOSIOP_SCNTL1, OOSIOP_SCNTL1_ESR); 934 oosiop_write_1(sc, OOSIOP_DCNTL, sc->sc_dcntl); 935 oosiop_write_1(sc, OOSIOP_DMODE, OOSIOP_DMODE_BL_8); 936 oosiop_write_1(sc, OOSIOP_SCID, OOSIOP_SCID_VALUE(sc->sc_id)); 937 oosiop_write_1(sc, OOSIOP_DWT, 0xff); /* Enable DMA timeout */ 938 oosiop_write_1(sc, OOSIOP_CTEST7, 0); 939 oosiop_write_1(sc, OOSIOP_SXFER, 0); 940 941 /* Clear all interrupts */ 942 (void)oosiop_read_1(sc, OOSIOP_SSTAT0); 943 (void)oosiop_read_1(sc, OOSIOP_SSTAT1); 944 (void)oosiop_read_1(sc, OOSIOP_DSTAT); 945 946 /* Enable interrupts */ 947 oosiop_write_1(sc, OOSIOP_SIEN, 948 OOSIOP_SIEN_M_A | OOSIOP_SIEN_STO | OOSIOP_SIEN_SGE | 949 OOSIOP_SIEN_UDC | OOSIOP_SIEN_RST | OOSIOP_SIEN_PAR); 950 oosiop_write_1(sc, OOSIOP_DIEN, 951 OOSIOP_DIEN_ABRT | OOSIOP_DIEN_SSI | OOSIOP_DIEN_SIR | 952 OOSIOP_DIEN_WTD | OOSIOP_DIEN_IID); 953 954 /* Set target state to asynchronous */ 955 for (i = 0; i < OOSIOP_NTGT; i++) { 956 sc->sc_tgt[i].flags = 0; 957 sc->sc_tgt[i].scf = 0; 958 sc->sc_tgt[i].sxfer = 0; 959 } 960 961 splx(s); 962 } 963 964 static void 965 oosiop_reset_bus(struct oosiop_softc *sc) 966 { 967 int s, i; 968 969 s = splbio(); 970 971 /* Assert SCSI RST */ 972 oosiop_write_1(sc, OOSIOP_SCNTL1, OOSIOP_SCNTL1_RST); 973 delay(25); /* Reset hold time (25us) */ 974 oosiop_write_1(sc, OOSIOP_SCNTL1, 0); 975 976 /* Remove all nexuses */ 977 for (i = 0; i < OOSIOP_NTGT; i++) { 978 if (sc->sc_tgt[i].nexus) { 979 sc->sc_tgt[i].nexus->xfer->status = 980 SCSI_OOSIOP_NOSTATUS; /* XXX */ 981 oosiop_done(sc, sc->sc_tgt[i].nexus); 982 } 983 } 984 985 sc->sc_curcb = NULL; 986 987 delay(250000); /* Reset to selection (250ms) */ 988 989 splx(s); 990 } 991 992 /* 993 * interrupt handler 994 */ 995 int 996 oosiop_intr(struct oosiop_softc *sc) 997 { 998 struct oosiop_cb *cb; 999 uint32_t dcmd; 1000 int timeout; 1001 uint8_t istat, dstat, sstat0; 1002 1003 istat = oosiop_read_1(sc, OOSIOP_ISTAT); 1004 1005 if ((istat & (OOSIOP_ISTAT_SIP | OOSIOP_ISTAT_DIP)) == 0) 1006 return (0); 1007 1008 sc->sc_nextdsp = Ent_wait_reselect; 1009 1010 /* DMA interrupts */ 1011 if (istat & OOSIOP_ISTAT_DIP) { 1012 oosiop_write_1(sc, OOSIOP_ISTAT, 0); 1013 1014 dstat = oosiop_read_1(sc, OOSIOP_DSTAT); 1015 1016 if (dstat & OOSIOP_DSTAT_ABRT) { 1017 sc->sc_nextdsp = oosiop_read_4(sc, OOSIOP_DSP) - 1018 sc->sc_scrbase - 8; 1019 1020 if (sc->sc_nextdsp == Ent_p_resel_msgin_move && 1021 (oosiop_read_1(sc, OOSIOP_SBCL) & OOSIOP_ACK)) { 1022 if ((dstat & OOSIOP_DSTAT_DFE) == 0) 1023 oosiop_flush_fifo(sc); 1024 sc->sc_nextdsp += 8; 1025 } 1026 } 1027 1028 if (dstat & OOSIOP_DSTAT_SSI) { 1029 sc->sc_nextdsp = oosiop_read_4(sc, OOSIOP_DSP) - 1030 sc->sc_scrbase; 1031 printf("%s: single step %08x\n", 1032 device_xname(sc->sc_dev), sc->sc_nextdsp); 1033 } 1034 1035 if (dstat & OOSIOP_DSTAT_SIR) { 1036 if ((dstat & OOSIOP_DSTAT_DFE) == 0) 1037 oosiop_flush_fifo(sc); 1038 oosiop_scriptintr(sc); 1039 } 1040 1041 if (dstat & OOSIOP_DSTAT_WTD) { 1042 printf("%s: DMA time out\n", device_xname(sc->sc_dev)); 1043 oosiop_reset(sc); 1044 } 1045 1046 if (dstat & OOSIOP_DSTAT_IID) { 1047 dcmd = oosiop_read_4(sc, OOSIOP_DBC); 1048 if ((dcmd & 0xf8000000) == 0x48000000) { 1049 printf("%s: REQ asserted on WAIT DISCONNECT\n", 1050 device_xname(sc->sc_dev)); 1051 sc->sc_nextdsp = Ent_phasedispatch; /* XXX */ 1052 } else { 1053 printf("%s: invalid SCRIPTS instruction " 1054 "addr=%08x dcmd=%08x dsps=%08x\n", 1055 device_xname(sc->sc_dev), 1056 oosiop_read_4(sc, OOSIOP_DSP) - 8, dcmd, 1057 oosiop_read_4(sc, OOSIOP_DSPS)); 1058 oosiop_reset(sc); 1059 OOSIOP_SCRIPT_SYNC(sc, BUS_DMASYNC_POSTWRITE); 1060 oosiop_load_script(sc); 1061 } 1062 } 1063 1064 if ((dstat & OOSIOP_DSTAT_DFE) == 0) 1065 oosiop_clear_fifo(sc); 1066 } 1067 1068 /* SCSI interrupts */ 1069 if (istat & OOSIOP_ISTAT_SIP) { 1070 if (istat & OOSIOP_ISTAT_DIP) 1071 delay(1); 1072 sstat0 = oosiop_read_1(sc, OOSIOP_SSTAT0); 1073 1074 if (sstat0 & OOSIOP_SSTAT0_M_A) { 1075 /* SCSI phase mismatch during MOVE operation */ 1076 oosiop_phasemismatch(sc); 1077 sc->sc_nextdsp = Ent_phasedispatch; 1078 } 1079 1080 if (sstat0 & OOSIOP_SSTAT0_STO) { 1081 if (sc->sc_curcb) { 1082 sc->sc_curcb->flags |= CBF_SELTOUT; 1083 oosiop_done(sc, sc->sc_curcb); 1084 } 1085 } 1086 1087 if (sstat0 & OOSIOP_SSTAT0_SGE) { 1088 printf("%s: SCSI gross error\n", 1089 device_xname(sc->sc_dev)); 1090 oosiop_reset(sc); 1091 } 1092 1093 if (sstat0 & OOSIOP_SSTAT0_UDC) { 1094 /* XXX */ 1095 if (sc->sc_curcb) { 1096 printf("%s: unexpected disconnect\n", 1097 device_xname(sc->sc_dev)); 1098 oosiop_done(sc, sc->sc_curcb); 1099 } 1100 } 1101 1102 if (sstat0 & OOSIOP_SSTAT0_RST) 1103 oosiop_reset(sc); 1104 1105 if (sstat0 & OOSIOP_SSTAT0_PAR) 1106 printf("%s: parity error\n", device_xname(sc->sc_dev)); 1107 } 1108 1109 /* Start next command if available */ 1110 if (sc->sc_nextdsp == Ent_wait_reselect && TAILQ_FIRST(&sc->sc_cbq)) { 1111 cb = sc->sc_curcb = TAILQ_FIRST(&sc->sc_cbq); 1112 TAILQ_REMOVE(&sc->sc_cbq, cb, chain); 1113 sc->sc_tgt[cb->id].nexus = cb; 1114 1115 oosiop_setup_dma(sc); 1116 oosiop_setup_syncxfer(sc); 1117 sc->sc_lastcb = cb; 1118 sc->sc_nextdsp = Ent_start_select; 1119 1120 /* Schedule timeout */ 1121 if ((cb->xs->xs_control & XS_CTL_POLL) == 0) { 1122 timeout = mstohz(cb->xs->timeout) + 1; 1123 callout_reset(&cb->xs->xs_callout, timeout, 1124 oosiop_timeout, cb); 1125 } 1126 } 1127 1128 sc->sc_active = (sc->sc_nextdsp != Ent_wait_reselect); 1129 1130 /* Restart script */ 1131 oosiop_write_4(sc, OOSIOP_DSP, sc->sc_nextdsp + sc->sc_scrbase); 1132 1133 return (1); 1134 } 1135 1136 static void 1137 oosiop_scriptintr(struct oosiop_softc *sc) 1138 { 1139 struct oosiop_cb *cb; 1140 uint32_t icode; 1141 uint32_t dsp; 1142 int i; 1143 uint8_t sfbr, resid, resmsg; 1144 1145 cb = sc->sc_curcb; 1146 icode = oosiop_read_4(sc, OOSIOP_DSPS); 1147 1148 switch (icode) { 1149 case A_int_done: 1150 if (cb) 1151 oosiop_done(sc, cb); 1152 break; 1153 1154 case A_int_msgin: 1155 if (cb) 1156 oosiop_msgin(sc, cb); 1157 break; 1158 1159 case A_int_extmsg: 1160 /* extended message in DMA setup request */ 1161 sfbr = oosiop_read_1(sc, OOSIOP_SFBR); 1162 OOSIOP_SCRIPT_SYNC(sc, BUS_DMASYNC_POSTWRITE); 1163 oosiop_fixup_move(sc, Ent_p_extmsgin_move, sfbr, 1164 cb->xferdma->dm_segs[0].ds_addr + 1165 offsetof(struct oosiop_xfer, msgin[2])); 1166 OOSIOP_SCRIPT_SYNC(sc, BUS_DMASYNC_PREWRITE); 1167 sc->sc_nextdsp = Ent_rcv_extmsg; 1168 break; 1169 1170 case A_int_resel: 1171 /* reselected */ 1172 resid = oosiop_read_1(sc, OOSIOP_SFBR); 1173 for (i = 0; i < OOSIOP_NTGT; i++) 1174 if (resid & (1 << i)) 1175 break; 1176 if (i == OOSIOP_NTGT) { 1177 printf("%s: missing reselection target id\n", 1178 device_xname(sc->sc_dev)); 1179 break; 1180 } 1181 sc->sc_resid = i; 1182 sc->sc_nextdsp = Ent_wait_resel_identify; 1183 1184 if (cb) { 1185 /* Current command was lost arbitration */ 1186 sc->sc_tgt[cb->id].nexus = NULL; 1187 TAILQ_INSERT_HEAD(&sc->sc_cbq, cb, chain); 1188 sc->sc_curcb = NULL; 1189 } 1190 1191 break; 1192 1193 case A_int_res_id: 1194 cb = sc->sc_tgt[sc->sc_resid].nexus; 1195 resmsg = oosiop_read_1(sc, OOSIOP_SFBR); 1196 if (MSG_ISIDENTIFY(resmsg) && cb && 1197 (resmsg & MSG_IDENTIFY_LUNMASK) == cb->lun) { 1198 sc->sc_curcb = cb; 1199 if (cb != sc->sc_lastcb) { 1200 oosiop_setup_dma(sc); 1201 oosiop_setup_syncxfer(sc); 1202 sc->sc_lastcb = cb; 1203 } 1204 if (cb->curdp != cb->savedp) { 1205 cb->curdp = cb->savedp; 1206 oosiop_setup_sgdma(sc, cb); 1207 } 1208 sc->sc_nextdsp = Ent_ack_msgin; 1209 } else { 1210 /* Reselection from invalid target */ 1211 oosiop_reset_bus(sc); 1212 } 1213 break; 1214 1215 case A_int_resfail: 1216 /* reselect failed */ 1217 break; 1218 1219 case A_int_disc: 1220 /* disconnected */ 1221 sc->sc_curcb = NULL; 1222 break; 1223 1224 case A_int_err: 1225 /* generic error */ 1226 dsp = oosiop_read_4(sc, OOSIOP_DSP); 1227 printf("%s: script error at 0x%08x\n", 1228 device_xname(sc->sc_dev), dsp - 8); 1229 sc->sc_curcb = NULL; 1230 break; 1231 1232 case DATAIN_TRAP: 1233 printf("%s: unexpected datain\n", device_xname(sc->sc_dev)); 1234 /* XXX: need to reset? */ 1235 break; 1236 1237 case DATAOUT_TRAP: 1238 printf("%s: unexpected dataout\n", device_xname(sc->sc_dev)); 1239 /* XXX: need to reset? */ 1240 break; 1241 1242 default: 1243 printf("%s: unknown intr code %08x\n", 1244 device_xname(sc->sc_dev), icode); 1245 break; 1246 } 1247 } 1248 1249 static void 1250 oosiop_msgin(struct oosiop_softc *sc, struct oosiop_cb *cb) 1251 { 1252 struct oosiop_xfer *xfer; 1253 int msgout; 1254 1255 xfer = cb->xfer; 1256 sc->sc_nextdsp = Ent_ack_msgin; 1257 msgout = 0; 1258 1259 OOSIOP_XFERMSG_SYNC(sc, cb, 1260 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1261 1262 switch (xfer->msgin[0]) { 1263 case MSG_EXTENDED: 1264 switch (xfer->msgin[2]) { 1265 case MSG_EXT_SDTR: 1266 if (sc->sc_tgt[cb->id].flags & TGTF_WAITSDTR) { 1267 /* Host initiated SDTR */ 1268 sc->sc_tgt[cb->id].flags &= ~TGTF_WAITSDTR; 1269 } else { 1270 /* Target initiated SDTR */ 1271 if (xfer->msgin[3] < sc->sc_minperiod) 1272 xfer->msgin[3] = sc->sc_minperiod; 1273 if (xfer->msgin[4] > OOSIOP_MAX_OFFSET) 1274 xfer->msgin[4] = OOSIOP_MAX_OFFSET; 1275 xfer->msgout[0] = MSG_EXTENDED; 1276 xfer->msgout[1] = MSG_EXT_SDTR_LEN; 1277 xfer->msgout[2] = MSG_EXT_SDTR; 1278 xfer->msgout[3] = xfer->msgin[3]; 1279 xfer->msgout[4] = xfer->msgin[4]; 1280 cb->msgoutlen = 5; 1281 msgout = 1; 1282 } 1283 oosiop_set_syncparam(sc, cb->id, (int)xfer->msgin[3], 1284 (int)xfer->msgin[4]); 1285 oosiop_setup_syncxfer(sc); 1286 break; 1287 1288 default: 1289 /* Reject message */ 1290 xfer->msgout[0] = MSG_MESSAGE_REJECT; 1291 cb->msgoutlen = 1; 1292 msgout = 1; 1293 break; 1294 } 1295 break; 1296 1297 case MSG_SAVEDATAPOINTER: 1298 cb->savedp = cb->curdp; 1299 break; 1300 1301 case MSG_RESTOREPOINTERS: 1302 if (cb->curdp != cb->savedp) { 1303 cb->curdp = cb->savedp; 1304 oosiop_setup_sgdma(sc, cb); 1305 } 1306 break; 1307 1308 case MSG_MESSAGE_REJECT: 1309 if (sc->sc_tgt[cb->id].flags & TGTF_WAITSDTR) { 1310 /* SDTR rejected */ 1311 sc->sc_tgt[cb->id].flags &= ~TGTF_WAITSDTR; 1312 oosiop_set_syncparam(sc, cb->id, 0, 0); 1313 oosiop_setup_syncxfer(sc); 1314 } 1315 break; 1316 1317 default: 1318 /* Reject message */ 1319 xfer->msgout[0] = MSG_MESSAGE_REJECT; 1320 cb->msgoutlen = 1; 1321 msgout = 1; 1322 } 1323 1324 OOSIOP_XFERMSG_SYNC(sc, cb, 1325 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1326 1327 if (msgout) { 1328 OOSIOP_SCRIPT_SYNC(sc, BUS_DMASYNC_POSTWRITE); 1329 oosiop_fixup_move(sc, Ent_p_msgout_move, cb->msgoutlen, 1330 cb->xferdma->dm_segs[0].ds_addr + 1331 offsetof(struct oosiop_xfer, msgout[0])); 1332 OOSIOP_SCRIPT_SYNC(sc, BUS_DMASYNC_PREWRITE); 1333 sc->sc_nextdsp = Ent_sendmsg; 1334 } 1335 } 1336
Indexes created Tue Oct 21 12:09:54 GMT 2025