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rs5c313.c revision 1.1.40.1
      1  1.1.40.1  mjf /*	$NetBSD: rs5c313.c,v 1.1.40.1 2007/11/19 00:47:55 mjf Exp $	*/
      2       1.1  uwe 
      3       1.1  uwe /*-
      4       1.1  uwe  * Copyright (c) 2006 The NetBSD Foundation, Inc.
      5       1.1  uwe  * All rights reserved.
      6       1.1  uwe  *
      7       1.1  uwe  * Redistribution and use in source and binary forms, with or without
      8       1.1  uwe  * modification, are permitted provided that the following conditions
      9       1.1  uwe  * are met:
     10       1.1  uwe  * 1. Redistributions of source code must retain the above copyright
     11       1.1  uwe  *    notice, this list of conditions and the following disclaimer.
     12       1.1  uwe  * 2. Redistributions in binary form must reproduce the above copyright
     13       1.1  uwe  *    notice, this list of conditions and the following disclaimer in the
     14       1.1  uwe  *    documentation and/or other materials provided with the distribution.
     15       1.1  uwe  * 3. All advertising materials mentioning features or use of this software
     16       1.1  uwe  *    must display the following acknowledgement:
     17       1.1  uwe  *        This product includes software developed by the NetBSD
     18       1.1  uwe  *        Foundation, Inc. and its contributors.
     19       1.1  uwe  *
     20       1.1  uwe  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21       1.1  uwe  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22       1.1  uwe  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23       1.1  uwe  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24       1.1  uwe  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25       1.1  uwe  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26       1.1  uwe  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27       1.1  uwe  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28       1.1  uwe  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29       1.1  uwe  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30       1.1  uwe  * POSSIBILITY OF SUCH DAMAGE.
     31       1.1  uwe  */
     32       1.1  uwe 
     33       1.1  uwe #include <sys/cdefs.h>
     34  1.1.40.1  mjf __KERNEL_RCSID(0, "$NetBSD: rs5c313.c,v 1.1.40.1 2007/11/19 00:47:55 mjf Exp $");
     35       1.1  uwe 
     36       1.1  uwe #include <sys/param.h>
     37       1.1  uwe #include <sys/systm.h>
     38       1.1  uwe #include <sys/device.h>
     39       1.1  uwe #include <sys/kernel.h>
     40       1.1  uwe 
     41       1.1  uwe #include <dev/clock_subr.h>
     42       1.1  uwe 
     43       1.1  uwe #include <dev/ic/rs5c313reg.h>
     44       1.1  uwe #include <dev/ic/rs5c313var.h>
     45       1.1  uwe 
     46       1.1  uwe 
     47       1.1  uwe /* todr(9) methods */
     48       1.1  uwe static int rs5c313_todr_gettime(todr_chip_handle_t, volatile struct timeval *);
     49       1.1  uwe static int rs5c313_todr_settime(todr_chip_handle_t, volatile struct timeval *);
     50       1.1  uwe 
     51       1.1  uwe /* sugar for chip access */
     52       1.1  uwe #define rtc_begin(sc)		((*sc->sc_ops->rs5c313_op_begin)(sc))
     53       1.1  uwe #define rtc_ce(sc, onoff)	((*sc->sc_ops->rs5c313_op_ce)(sc, onoff))
     54       1.1  uwe #define rtc_clk(sc, onoff)	((*sc->sc_ops->rs5c313_op_clk)(sc, onoff))
     55       1.1  uwe #define rtc_dir(sc, output)	((*sc->sc_ops->rs5c313_op_dir)(sc, output))
     56       1.1  uwe #define rtc_di(sc)		((*sc->sc_ops->rs5c313_op_read)(sc))
     57       1.1  uwe #define rtc_do(sc, bit)		((*sc->sc_ops->rs5c313_op_write)(sc, bit))
     58       1.1  uwe 
     59       1.1  uwe static int rs5c313_init(struct rs5c313_softc *);
     60       1.1  uwe static int rs5c313_read_reg(struct rs5c313_softc *, int);
     61       1.1  uwe static void rs5c313_write_reg(struct rs5c313_softc *, int, int);
     62       1.1  uwe 
     63       1.1  uwe 
     64       1.1  uwe void
     65       1.1  uwe rs5c313_attach(struct rs5c313_softc *sc)
     66       1.1  uwe {
     67       1.1  uwe 
     68  1.1.40.1  mjf 	aprint_naive("\n");
     69  1.1.40.1  mjf 	aprint_normal(": real time clock\n");
     70       1.1  uwe 
     71       1.1  uwe 	sc->sc_todr.cookie = sc;
     72       1.1  uwe 	sc->sc_todr.todr_gettime = rs5c313_todr_gettime;
     73       1.1  uwe 	sc->sc_todr.todr_settime = rs5c313_todr_settime;
     74       1.1  uwe 	sc->sc_todr.todr_setwen = NULL;
     75       1.1  uwe 
     76       1.1  uwe 	if (rs5c313_init(sc) != 0) {
     77  1.1.40.1  mjf 		aprint_error_dev(&sc->sc_dev, "init failed\n");
     78       1.1  uwe 		return;
     79       1.1  uwe 	}
     80       1.1  uwe 
     81       1.1  uwe 	todr_attach(&sc->sc_todr);
     82       1.1  uwe }
     83       1.1  uwe 
     84       1.1  uwe 
     85       1.1  uwe static int
     86       1.1  uwe rs5c313_init(struct rs5c313_softc *sc)
     87       1.1  uwe {
     88       1.1  uwe 	int status = 0;
     89       1.1  uwe 	int retry;
     90       1.1  uwe 
     91       1.1  uwe 	rtc_ce(sc, 0);
     92       1.1  uwe 
     93       1.1  uwe 	rtc_begin(sc);
     94       1.1  uwe 	rtc_ce(sc, 1);
     95       1.1  uwe 
     96       1.1  uwe 	if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_XSTP) == 0) {
     97       1.1  uwe 		sc->sc_valid = 1;
     98       1.1  uwe 		goto done;
     99       1.1  uwe 	}
    100       1.1  uwe 
    101       1.1  uwe 	sc->sc_valid = 0;
    102  1.1.40.1  mjf 	aprint_error_dev(&sc->sc_dev, "time not valid\n");
    103       1.1  uwe 
    104       1.1  uwe 	rs5c313_write_reg(sc, RS5C313_TINT, 0);
    105       1.1  uwe 	rs5c313_write_reg(sc, RS5C313_CTRL, (CTRL_BASE | CTRL_ADJ));
    106       1.1  uwe 
    107       1.1  uwe 	for (retry = 1000; retry > 0; --retry) {
    108       1.1  uwe 		if (rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY)
    109       1.1  uwe 			delay(1);
    110       1.1  uwe 		else
    111       1.1  uwe 			break;
    112       1.1  uwe 	}
    113       1.1  uwe 
    114       1.1  uwe 	if (retry == 0) {
    115       1.1  uwe 		status = EIO;
    116       1.1  uwe 		goto done;
    117       1.1  uwe 	}
    118       1.1  uwe 
    119       1.1  uwe 	rs5c313_write_reg(sc, RS5C313_CTRL, CTRL_BASE);
    120       1.1  uwe 
    121       1.1  uwe   done:
    122       1.1  uwe 	rtc_ce(sc, 0);
    123       1.1  uwe 	return status;
    124       1.1  uwe }
    125       1.1  uwe 
    126       1.1  uwe 
    127       1.1  uwe static int
    128       1.1  uwe rs5c313_todr_gettime(todr_chip_handle_t todr, volatile struct timeval *tv)
    129       1.1  uwe {
    130       1.1  uwe 	struct rs5c313_softc *sc = todr->cookie;
    131       1.1  uwe 	struct clock_ymdhms dt;
    132       1.1  uwe 	int retry;
    133       1.1  uwe 	int s;
    134       1.1  uwe 
    135       1.1  uwe 	/*
    136       1.1  uwe 	 * If chip had invalid data on init, don't bother reading
    137       1.1  uwe 	 * bogus values, let todr(9) cope.
    138       1.1  uwe 	 */
    139       1.1  uwe 	if (sc->sc_valid == 0)
    140       1.1  uwe 		return EIO;
    141       1.1  uwe 
    142       1.1  uwe 	s = splhigh();
    143       1.1  uwe 
    144       1.1  uwe 	rtc_begin(sc);
    145       1.1  uwe 	for (retry = 10; retry > 0; --retry) {
    146       1.1  uwe 		rtc_ce(sc, 1);
    147       1.1  uwe 
    148       1.1  uwe 		rs5c313_write_reg(sc, RS5C313_CTRL, CTRL_BASE);
    149       1.1  uwe 		if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY) == 0)
    150       1.1  uwe 			break;
    151       1.1  uwe 
    152       1.1  uwe 		rtc_ce(sc, 0);
    153       1.1  uwe 		delay(1);
    154       1.1  uwe 	}
    155       1.1  uwe 
    156       1.1  uwe 	if (retry == 0) {
    157       1.1  uwe 		splx(s);
    158       1.1  uwe 		return EIO;
    159       1.1  uwe 	}
    160       1.1  uwe 
    161       1.1  uwe #define RTCGET(x, y)							\
    162       1.1  uwe 	do {								\
    163       1.1  uwe 		int ones = rs5c313_read_reg(sc, RS5C313_ ## y ## 1);	\
    164       1.1  uwe 		int tens = rs5c313_read_reg(sc, RS5C313_ ## y ## 10);	\
    165       1.1  uwe 		dt.dt_ ## x = tens * 10 + ones;				\
    166       1.1  uwe 	} while (/* CONSTCOND */0)
    167       1.1  uwe 
    168       1.1  uwe 	RTCGET(sec, SEC);
    169       1.1  uwe 	RTCGET(min, MIN);
    170       1.1  uwe 	RTCGET(hour, HOUR);
    171       1.1  uwe 	RTCGET(day, DAY);
    172       1.1  uwe 	RTCGET(mon, MON);
    173       1.1  uwe 	RTCGET(year, YEAR);
    174       1.1  uwe #undef	RTCGET
    175       1.1  uwe 	dt.dt_wday = rs5c313_read_reg(sc, RS5C313_WDAY);
    176       1.1  uwe 
    177       1.1  uwe 	rtc_ce(sc, 0);
    178       1.1  uwe 	splx(s);
    179       1.1  uwe 
    180       1.1  uwe 	dt.dt_year = (dt.dt_year % 100) + 1900;
    181       1.1  uwe 	if (dt.dt_year < 1970) {
    182       1.1  uwe 		dt.dt_year += 100;
    183       1.1  uwe 	}
    184       1.1  uwe 
    185       1.1  uwe 	/*
    186       1.1  uwe 	 * If time_t is 32 bits, then the "End of Time" is
    187       1.1  uwe 	 * Mon Jan 18 22:14:07 2038 (US/Eastern)
    188       1.1  uwe 	 * This code copes with RTC's past the end of time if time_t
    189       1.1  uwe 	 * is an int32 or less. Needed because sometimes RTCs screw
    190       1.1  uwe 	 * up or are badly set, and that would cause the time to go
    191       1.1  uwe 	 * negative in the calculation below, which causes Very Bad
    192       1.1  uwe 	 * Mojo. This at least lets the user boot and fix the problem.
    193       1.1  uwe 	 * Note the code is self eliminating once time_t goes to 64 bits.
    194       1.1  uwe 	 */
    195       1.1  uwe 	if (/* CONSTCOND */ sizeof(time_t) <= sizeof(int32_t)) {
    196       1.1  uwe 		if (dt.dt_year >= 2038) {
    197       1.1  uwe 			return -1;
    198       1.1  uwe 		}
    199       1.1  uwe 	}
    200       1.1  uwe 
    201       1.1  uwe 	tv->tv_sec = clock_ymdhms_to_secs(&dt) + rtc_offset * 60;
    202       1.1  uwe 	tv->tv_usec = 0;
    203       1.1  uwe 
    204       1.1  uwe 	return 0;
    205       1.1  uwe }
    206       1.1  uwe 
    207       1.1  uwe 
    208       1.1  uwe static int
    209       1.1  uwe rs5c313_todr_settime(todr_chip_handle_t todr, volatile struct timeval *tv)
    210       1.1  uwe {
    211       1.1  uwe 	struct rs5c313_softc *sc = todr->cookie;
    212       1.1  uwe 	struct clock_ymdhms dt;
    213       1.1  uwe 	int retry;
    214       1.1  uwe 	int t;
    215       1.1  uwe 	int s;
    216       1.1  uwe 
    217       1.1  uwe 	clock_secs_to_ymdhms(tv->tv_sec - rtc_offset * 60, &dt);
    218       1.1  uwe 
    219       1.1  uwe 	s = splhigh();
    220       1.1  uwe 
    221       1.1  uwe 	rtc_begin(sc);
    222       1.1  uwe 	for (retry = 10; retry > 0; --retry) {
    223       1.1  uwe 		rtc_ce(sc, 1);
    224       1.1  uwe 
    225       1.1  uwe 		rs5c313_write_reg(sc, RS5C313_CTRL, CTRL_BASE);
    226       1.1  uwe 		if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY) == 0)
    227       1.1  uwe 			break;
    228       1.1  uwe 
    229       1.1  uwe 		rtc_ce(sc, 0);
    230       1.1  uwe 		delay(1);
    231       1.1  uwe 	}
    232       1.1  uwe 
    233       1.1  uwe 	if (retry == 0) {
    234       1.1  uwe 		splx(s);
    235       1.1  uwe 		return EIO;
    236       1.1  uwe 	}
    237       1.1  uwe 
    238       1.1  uwe #define	RTCSET(x, y)							     \
    239       1.1  uwe 	do {								     \
    240       1.1  uwe 		t = TOBCD(dt.dt_ ## y) & 0xff;				     \
    241       1.1  uwe 		rs5c313_write_reg(sc, RS5C313_ ## x ## 1, t & 0x0f);	     \
    242       1.1  uwe 		rs5c313_write_reg(sc, RS5C313_ ## x ## 10, (t >> 4) & 0x0f); \
    243       1.1  uwe 	} while (/* CONSTCOND */0)
    244       1.1  uwe 
    245       1.1  uwe 	RTCSET(SEC, sec);
    246       1.1  uwe 	RTCSET(MIN, min);
    247       1.1  uwe 	RTCSET(HOUR, hour);
    248       1.1  uwe 	RTCSET(DAY, day);
    249       1.1  uwe 	RTCSET(MON, mon);
    250       1.1  uwe 
    251       1.1  uwe #undef	RTCSET
    252       1.1  uwe 
    253       1.1  uwe 	t = dt.dt_year % 100;
    254       1.1  uwe 	t = TOBCD(t);
    255       1.1  uwe 	rs5c313_write_reg(sc, RS5C313_YEAR1, t & 0x0f);
    256       1.1  uwe 	rs5c313_write_reg(sc, RS5C313_YEAR10, (t >> 4) & 0x0f);
    257       1.1  uwe 
    258       1.1  uwe 	rs5c313_write_reg(sc, RS5C313_WDAY, dt.dt_wday);
    259       1.1  uwe 
    260       1.1  uwe 	rtc_ce(sc, 0);
    261       1.1  uwe 	splx(s);
    262       1.1  uwe 
    263       1.1  uwe 	sc->sc_valid = 1;
    264       1.1  uwe 	return 0;
    265       1.1  uwe }
    266       1.1  uwe 
    267       1.1  uwe 
    268       1.1  uwe static int
    269       1.1  uwe rs5c313_read_reg(struct rs5c313_softc *sc, int addr)
    270       1.1  uwe {
    271       1.1  uwe 	int data;
    272       1.1  uwe 
    273       1.1  uwe 	/* output */
    274       1.1  uwe 	rtc_dir(sc, 1);
    275       1.1  uwe 
    276       1.1  uwe 	/* control */
    277       1.1  uwe 	rtc_do(sc, 1);		/* ignored */
    278       1.1  uwe 	rtc_do(sc, 1);		/* R/#W = 1(READ) */
    279       1.1  uwe 	rtc_do(sc, 1);		/* AD = 1 */
    280       1.1  uwe 	rtc_do(sc, 0);		/* DT = 0 */
    281       1.1  uwe 
    282       1.1  uwe 	/* address */
    283       1.1  uwe 	rtc_do(sc, addr & 0x8);	/* A3 */
    284       1.1  uwe 	rtc_do(sc, addr & 0x4);	/* A2 */
    285       1.1  uwe 	rtc_do(sc, addr & 0x2);	/* A1 */
    286       1.1  uwe 	rtc_do(sc, addr & 0x1);	/* A0 */
    287       1.1  uwe 
    288       1.1  uwe 	/* input */
    289       1.1  uwe 	rtc_dir(sc, 0);
    290       1.1  uwe 
    291       1.1  uwe 	/* ignore */
    292       1.1  uwe 	(void)rtc_di(sc);
    293       1.1  uwe 	(void)rtc_di(sc);
    294       1.1  uwe 	(void)rtc_di(sc);
    295       1.1  uwe 	(void)rtc_di(sc);
    296       1.1  uwe 
    297       1.1  uwe 	/* data */
    298       1.1  uwe 	data = rtc_di(sc);	/* D3 */
    299       1.1  uwe 	data <<= 1;
    300       1.1  uwe 	data |= rtc_di(sc);	/* D2 */
    301       1.1  uwe 	data <<= 1;
    302       1.1  uwe 	data |= rtc_di(sc);	/* D1 */
    303       1.1  uwe 	data <<= 1;
    304       1.1  uwe 	data |= rtc_di(sc);	/* D0 */
    305       1.1  uwe 
    306       1.1  uwe 	return data;
    307       1.1  uwe }
    308       1.1  uwe 
    309       1.1  uwe 
    310       1.1  uwe static void
    311       1.1  uwe rs5c313_write_reg(struct rs5c313_softc *sc, int addr, int data)
    312       1.1  uwe {
    313       1.1  uwe 
    314       1.1  uwe 	/* output */
    315       1.1  uwe 	rtc_dir(sc, 1);
    316       1.1  uwe 
    317       1.1  uwe 	/* control */
    318       1.1  uwe 	rtc_do(sc, 1);		/* ignored */
    319       1.1  uwe 	rtc_do(sc, 0);		/* R/#W = 0 (WRITE) */
    320       1.1  uwe 	rtc_do(sc, 1);		/* AD = 1 */
    321       1.1  uwe 	rtc_do(sc, 0);		/* DT = 0 */
    322       1.1  uwe 
    323       1.1  uwe 	/* address */
    324       1.1  uwe 	rtc_do(sc, addr & 0x8);	/* A3 */
    325       1.1  uwe 	rtc_do(sc, addr & 0x4);	/* A2 */
    326       1.1  uwe 	rtc_do(sc, addr & 0x2);	/* A1 */
    327       1.1  uwe 	rtc_do(sc, addr & 0x1);	/* A0 */
    328       1.1  uwe 
    329       1.1  uwe 	/* control */
    330       1.1  uwe 	rtc_do(sc, 1);		/* ignored */
    331       1.1  uwe 	rtc_do(sc, 0);		/* R/#W = 0(WRITE) */
    332       1.1  uwe 	rtc_do(sc, 0);		/* AD = 0 */
    333       1.1  uwe 	rtc_do(sc, 1);		/* DT = 1 */
    334       1.1  uwe 
    335       1.1  uwe 	/* data */
    336       1.1  uwe 	rtc_do(sc, data & 0x8);	/* D3 */
    337       1.1  uwe 	rtc_do(sc, data & 0x4);	/* D2 */
    338       1.1  uwe 	rtc_do(sc, data & 0x2);	/* D1 */
    339       1.1  uwe 	rtc_do(sc, data & 0x1);	/* D0 */
    340       1.1  uwe }
    341