rs5c313.c revision 1.6 1 1.6 uwe /* $NetBSD: rs5c313.c,v 1.6 2008/01/09 22:29:20 uwe Exp $ */
2 1.1 uwe
3 1.1 uwe /*-
4 1.1 uwe * Copyright (c) 2006 The NetBSD Foundation, Inc.
5 1.1 uwe * All rights reserved.
6 1.1 uwe *
7 1.1 uwe * Redistribution and use in source and binary forms, with or without
8 1.1 uwe * modification, are permitted provided that the following conditions
9 1.1 uwe * are met:
10 1.1 uwe * 1. Redistributions of source code must retain the above copyright
11 1.1 uwe * notice, this list of conditions and the following disclaimer.
12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uwe * notice, this list of conditions and the following disclaimer in the
14 1.1 uwe * documentation and/or other materials provided with the distribution.
15 1.1 uwe * 3. All advertising materials mentioning features or use of this software
16 1.1 uwe * must display the following acknowledgement:
17 1.1 uwe * This product includes software developed by the NetBSD
18 1.1 uwe * Foundation, Inc. and its contributors.
19 1.1 uwe *
20 1.1 uwe * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 1.1 uwe * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 1.1 uwe * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 1.1 uwe * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 1.1 uwe * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 1.1 uwe * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 1.1 uwe * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 1.1 uwe * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 1.1 uwe * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 1.1 uwe * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 1.1 uwe * POSSIBILITY OF SUCH DAMAGE.
31 1.1 uwe */
32 1.1 uwe
33 1.1 uwe #include <sys/cdefs.h>
34 1.6 uwe __KERNEL_RCSID(0, "$NetBSD: rs5c313.c,v 1.6 2008/01/09 22:29:20 uwe Exp $");
35 1.1 uwe
36 1.1 uwe #include <sys/param.h>
37 1.1 uwe #include <sys/systm.h>
38 1.1 uwe #include <sys/device.h>
39 1.1 uwe #include <sys/kernel.h>
40 1.1 uwe
41 1.1 uwe #include <dev/clock_subr.h>
42 1.1 uwe
43 1.1 uwe #include <dev/ic/rs5c313reg.h>
44 1.1 uwe #include <dev/ic/rs5c313var.h>
45 1.1 uwe
46 1.1 uwe
47 1.1 uwe /* todr(9) methods */
48 1.4 uwe static int rs5c313_todr_gettime_ymdhms(todr_chip_handle_t, struct clock_ymdhms *);
49 1.4 uwe static int rs5c313_todr_settime_ymdhms(todr_chip_handle_t, struct clock_ymdhms *);
50 1.1 uwe
51 1.1 uwe /* sugar for chip access */
52 1.1 uwe #define rtc_begin(sc) ((*sc->sc_ops->rs5c313_op_begin)(sc))
53 1.1 uwe #define rtc_ce(sc, onoff) ((*sc->sc_ops->rs5c313_op_ce)(sc, onoff))
54 1.1 uwe #define rtc_clk(sc, onoff) ((*sc->sc_ops->rs5c313_op_clk)(sc, onoff))
55 1.1 uwe #define rtc_dir(sc, output) ((*sc->sc_ops->rs5c313_op_dir)(sc, output))
56 1.1 uwe #define rtc_di(sc) ((*sc->sc_ops->rs5c313_op_read)(sc))
57 1.1 uwe #define rtc_do(sc, bit) ((*sc->sc_ops->rs5c313_op_write)(sc, bit))
58 1.1 uwe
59 1.1 uwe static int rs5c313_init(struct rs5c313_softc *);
60 1.1 uwe static int rs5c313_read_reg(struct rs5c313_softc *, int);
61 1.1 uwe static void rs5c313_write_reg(struct rs5c313_softc *, int, int);
62 1.1 uwe
63 1.1 uwe
64 1.1 uwe void
65 1.1 uwe rs5c313_attach(struct rs5c313_softc *sc)
66 1.1 uwe {
67 1.6 uwe device_t self = &sc->sc_dev;
68 1.1 uwe
69 1.2 uwe aprint_naive("\n");
70 1.2 uwe aprint_normal(": real time clock\n");
71 1.1 uwe
72 1.1 uwe sc->sc_todr.cookie = sc;
73 1.4 uwe sc->sc_todr.todr_gettime_ymdhms = rs5c313_todr_gettime_ymdhms;
74 1.4 uwe sc->sc_todr.todr_settime_ymdhms = rs5c313_todr_settime_ymdhms;
75 1.4 uwe
76 1.1 uwe if (rs5c313_init(sc) != 0) {
77 1.6 uwe aprint_error_dev(self, "init failed\n");
78 1.1 uwe return;
79 1.1 uwe }
80 1.1 uwe
81 1.1 uwe todr_attach(&sc->sc_todr);
82 1.1 uwe }
83 1.1 uwe
84 1.1 uwe
85 1.1 uwe static int
86 1.1 uwe rs5c313_init(struct rs5c313_softc *sc)
87 1.1 uwe {
88 1.6 uwe device_t self = &sc->sc_dev;
89 1.1 uwe int status = 0;
90 1.1 uwe int retry;
91 1.1 uwe
92 1.1 uwe rtc_ce(sc, 0);
93 1.1 uwe
94 1.1 uwe rtc_begin(sc);
95 1.1 uwe rtc_ce(sc, 1);
96 1.1 uwe
97 1.1 uwe if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_XSTP) == 0) {
98 1.1 uwe sc->sc_valid = 1;
99 1.1 uwe goto done;
100 1.1 uwe }
101 1.1 uwe
102 1.1 uwe sc->sc_valid = 0;
103 1.6 uwe aprint_error_dev(self, "time not valid\n");
104 1.1 uwe
105 1.1 uwe rs5c313_write_reg(sc, RS5C313_TINT, 0);
106 1.1 uwe rs5c313_write_reg(sc, RS5C313_CTRL, (CTRL_BASE | CTRL_ADJ));
107 1.1 uwe
108 1.1 uwe for (retry = 1000; retry > 0; --retry) {
109 1.1 uwe if (rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY)
110 1.1 uwe delay(1);
111 1.1 uwe else
112 1.1 uwe break;
113 1.1 uwe }
114 1.1 uwe
115 1.1 uwe if (retry == 0) {
116 1.1 uwe status = EIO;
117 1.1 uwe goto done;
118 1.1 uwe }
119 1.1 uwe
120 1.1 uwe rs5c313_write_reg(sc, RS5C313_CTRL, CTRL_BASE);
121 1.1 uwe
122 1.1 uwe done:
123 1.1 uwe rtc_ce(sc, 0);
124 1.1 uwe return status;
125 1.1 uwe }
126 1.1 uwe
127 1.1 uwe
128 1.1 uwe static int
129 1.4 uwe rs5c313_todr_gettime_ymdhms(todr_chip_handle_t todr, struct clock_ymdhms *dt)
130 1.1 uwe {
131 1.1 uwe struct rs5c313_softc *sc = todr->cookie;
132 1.1 uwe int retry;
133 1.1 uwe int s;
134 1.1 uwe
135 1.1 uwe /*
136 1.1 uwe * If chip had invalid data on init, don't bother reading
137 1.1 uwe * bogus values, let todr(9) cope.
138 1.1 uwe */
139 1.1 uwe if (sc->sc_valid == 0)
140 1.1 uwe return EIO;
141 1.1 uwe
142 1.1 uwe s = splhigh();
143 1.1 uwe
144 1.1 uwe rtc_begin(sc);
145 1.1 uwe for (retry = 10; retry > 0; --retry) {
146 1.1 uwe rtc_ce(sc, 1);
147 1.1 uwe
148 1.1 uwe rs5c313_write_reg(sc, RS5C313_CTRL, CTRL_BASE);
149 1.1 uwe if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY) == 0)
150 1.1 uwe break;
151 1.1 uwe
152 1.1 uwe rtc_ce(sc, 0);
153 1.1 uwe delay(1);
154 1.1 uwe }
155 1.1 uwe
156 1.1 uwe if (retry == 0) {
157 1.1 uwe splx(s);
158 1.1 uwe return EIO;
159 1.1 uwe }
160 1.1 uwe
161 1.1 uwe #define RTCGET(x, y) \
162 1.1 uwe do { \
163 1.1 uwe int ones = rs5c313_read_reg(sc, RS5C313_ ## y ## 1); \
164 1.1 uwe int tens = rs5c313_read_reg(sc, RS5C313_ ## y ## 10); \
165 1.4 uwe dt->dt_ ## x = tens * 10 + ones; \
166 1.1 uwe } while (/* CONSTCOND */0)
167 1.1 uwe
168 1.1 uwe RTCGET(sec, SEC);
169 1.1 uwe RTCGET(min, MIN);
170 1.1 uwe RTCGET(hour, HOUR);
171 1.1 uwe RTCGET(day, DAY);
172 1.1 uwe RTCGET(mon, MON);
173 1.1 uwe RTCGET(year, YEAR);
174 1.1 uwe #undef RTCGET
175 1.4 uwe dt->dt_wday = rs5c313_read_reg(sc, RS5C313_WDAY);
176 1.1 uwe
177 1.1 uwe rtc_ce(sc, 0);
178 1.1 uwe splx(s);
179 1.1 uwe
180 1.1 uwe
181 1.4 uwe dt->dt_year = (dt->dt_year % 100) + 1900;
182 1.4 uwe if (dt->dt_year < POSIX_BASE_YEAR) {
183 1.4 uwe dt->dt_year += 100;
184 1.1 uwe }
185 1.1 uwe
186 1.1 uwe return 0;
187 1.1 uwe }
188 1.1 uwe
189 1.1 uwe
190 1.1 uwe static int
191 1.4 uwe rs5c313_todr_settime_ymdhms(todr_chip_handle_t todr, struct clock_ymdhms *dt)
192 1.1 uwe {
193 1.1 uwe struct rs5c313_softc *sc = todr->cookie;
194 1.1 uwe int retry;
195 1.1 uwe int t;
196 1.1 uwe int s;
197 1.1 uwe
198 1.1 uwe s = splhigh();
199 1.1 uwe
200 1.1 uwe rtc_begin(sc);
201 1.1 uwe for (retry = 10; retry > 0; --retry) {
202 1.1 uwe rtc_ce(sc, 1);
203 1.1 uwe
204 1.1 uwe rs5c313_write_reg(sc, RS5C313_CTRL, CTRL_BASE);
205 1.1 uwe if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY) == 0)
206 1.1 uwe break;
207 1.1 uwe
208 1.1 uwe rtc_ce(sc, 0);
209 1.1 uwe delay(1);
210 1.1 uwe }
211 1.1 uwe
212 1.1 uwe if (retry == 0) {
213 1.1 uwe splx(s);
214 1.1 uwe return EIO;
215 1.1 uwe }
216 1.1 uwe
217 1.1 uwe #define RTCSET(x, y) \
218 1.1 uwe do { \
219 1.4 uwe t = TOBCD(dt->dt_ ## y) & 0xff; \
220 1.1 uwe rs5c313_write_reg(sc, RS5C313_ ## x ## 1, t & 0x0f); \
221 1.1 uwe rs5c313_write_reg(sc, RS5C313_ ## x ## 10, (t >> 4) & 0x0f); \
222 1.1 uwe } while (/* CONSTCOND */0)
223 1.1 uwe
224 1.1 uwe RTCSET(SEC, sec);
225 1.1 uwe RTCSET(MIN, min);
226 1.1 uwe RTCSET(HOUR, hour);
227 1.1 uwe RTCSET(DAY, day);
228 1.1 uwe RTCSET(MON, mon);
229 1.1 uwe
230 1.1 uwe #undef RTCSET
231 1.1 uwe
232 1.4 uwe t = dt->dt_year % 100;
233 1.1 uwe t = TOBCD(t);
234 1.1 uwe rs5c313_write_reg(sc, RS5C313_YEAR1, t & 0x0f);
235 1.1 uwe rs5c313_write_reg(sc, RS5C313_YEAR10, (t >> 4) & 0x0f);
236 1.1 uwe
237 1.4 uwe rs5c313_write_reg(sc, RS5C313_WDAY, dt->dt_wday);
238 1.1 uwe
239 1.1 uwe rtc_ce(sc, 0);
240 1.1 uwe splx(s);
241 1.1 uwe
242 1.1 uwe sc->sc_valid = 1;
243 1.1 uwe return 0;
244 1.1 uwe }
245 1.1 uwe
246 1.1 uwe
247 1.1 uwe static int
248 1.1 uwe rs5c313_read_reg(struct rs5c313_softc *sc, int addr)
249 1.1 uwe {
250 1.1 uwe int data;
251 1.1 uwe
252 1.1 uwe /* output */
253 1.1 uwe rtc_dir(sc, 1);
254 1.1 uwe
255 1.1 uwe /* control */
256 1.1 uwe rtc_do(sc, 1); /* ignored */
257 1.1 uwe rtc_do(sc, 1); /* R/#W = 1(READ) */
258 1.1 uwe rtc_do(sc, 1); /* AD = 1 */
259 1.1 uwe rtc_do(sc, 0); /* DT = 0 */
260 1.1 uwe
261 1.1 uwe /* address */
262 1.1 uwe rtc_do(sc, addr & 0x8); /* A3 */
263 1.1 uwe rtc_do(sc, addr & 0x4); /* A2 */
264 1.1 uwe rtc_do(sc, addr & 0x2); /* A1 */
265 1.1 uwe rtc_do(sc, addr & 0x1); /* A0 */
266 1.1 uwe
267 1.1 uwe /* input */
268 1.1 uwe rtc_dir(sc, 0);
269 1.1 uwe
270 1.1 uwe /* ignore */
271 1.1 uwe (void)rtc_di(sc);
272 1.1 uwe (void)rtc_di(sc);
273 1.1 uwe (void)rtc_di(sc);
274 1.1 uwe (void)rtc_di(sc);
275 1.1 uwe
276 1.1 uwe /* data */
277 1.1 uwe data = rtc_di(sc); /* D3 */
278 1.1 uwe data <<= 1;
279 1.1 uwe data |= rtc_di(sc); /* D2 */
280 1.1 uwe data <<= 1;
281 1.1 uwe data |= rtc_di(sc); /* D1 */
282 1.1 uwe data <<= 1;
283 1.1 uwe data |= rtc_di(sc); /* D0 */
284 1.1 uwe
285 1.1 uwe return data;
286 1.1 uwe }
287 1.1 uwe
288 1.1 uwe
289 1.1 uwe static void
290 1.1 uwe rs5c313_write_reg(struct rs5c313_softc *sc, int addr, int data)
291 1.1 uwe {
292 1.1 uwe
293 1.1 uwe /* output */
294 1.1 uwe rtc_dir(sc, 1);
295 1.1 uwe
296 1.1 uwe /* control */
297 1.1 uwe rtc_do(sc, 1); /* ignored */
298 1.1 uwe rtc_do(sc, 0); /* R/#W = 0 (WRITE) */
299 1.1 uwe rtc_do(sc, 1); /* AD = 1 */
300 1.1 uwe rtc_do(sc, 0); /* DT = 0 */
301 1.1 uwe
302 1.1 uwe /* address */
303 1.1 uwe rtc_do(sc, addr & 0x8); /* A3 */
304 1.1 uwe rtc_do(sc, addr & 0x4); /* A2 */
305 1.1 uwe rtc_do(sc, addr & 0x2); /* A1 */
306 1.1 uwe rtc_do(sc, addr & 0x1); /* A0 */
307 1.1 uwe
308 1.1 uwe /* control */
309 1.1 uwe rtc_do(sc, 1); /* ignored */
310 1.1 uwe rtc_do(sc, 0); /* R/#W = 0(WRITE) */
311 1.1 uwe rtc_do(sc, 0); /* AD = 0 */
312 1.1 uwe rtc_do(sc, 1); /* DT = 1 */
313 1.1 uwe
314 1.1 uwe /* data */
315 1.1 uwe rtc_do(sc, data & 0x8); /* D3 */
316 1.1 uwe rtc_do(sc, data & 0x4); /* D2 */
317 1.1 uwe rtc_do(sc, data & 0x2); /* D1 */
318 1.1 uwe rtc_do(sc, data & 0x1); /* D0 */
319 1.1 uwe }
320