1 1.3 nonaka /* $NetBSD: rs5c313reg.h,v 1.3 2010/04/06 15:29:19 nonaka Exp $ */ 2 1.1 uwe 3 1.1 uwe /*- 4 1.1 uwe * Copyright (c) 2005 The NetBSD Foundation, Inc. 5 1.1 uwe * All rights reserved. 6 1.1 uwe * 7 1.1 uwe * Redistribution and use in source and binary forms, with or without 8 1.1 uwe * modification, are permitted provided that the following conditions 9 1.1 uwe * are met: 10 1.1 uwe * 1. Redistributions of source code must retain the above copyright 11 1.1 uwe * notice, this list of conditions and the following disclaimer. 12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 uwe * notice, this list of conditions and the following disclaimer in the 14 1.1 uwe * documentation and/or other materials provided with the distribution. 15 1.1 uwe * 16 1.1 uwe * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 1.1 uwe * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.1 uwe * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.1 uwe * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 1.1 uwe * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.1 uwe * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.1 uwe * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.1 uwe * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.1 uwe * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.1 uwe * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.1 uwe * POSSIBILITY OF SUCH DAMAGE. 27 1.1 uwe */ 28 1.1 uwe 29 1.1 uwe #ifndef _DEV_IC_RS5C313REG_H_ 30 1.1 uwe #define _DEV_IC_RS5C313REG_H_ 31 1.1 uwe 32 1.1 uwe /* 33 1.3 nonaka * RICOH RS5C3[12]x Real Time Clock 34 1.1 uwe */ 35 1.3 nonaka /* 5c313/5c314 don't have bank1 */ 36 1.3 nonaka #define RS5C313_SEC1 0 /* bank0 */ 37 1.3 nonaka #define RS5C313_SEC10 1 /* bank0 */ 38 1.3 nonaka #define RS5C313_MIN1 2 /* bank0 */ 39 1.3 nonaka #define RS5C313_MIN10 3 /* bank0 */ 40 1.3 nonaka #define RS5C313_HOUR1 4 /* bank0 */ 41 1.3 nonaka #define RS5C313_HOUR10 5 /* bank0 */ 42 1.3 nonaka #define RS5C313_WDAY 6 /* bank0 */ 43 1.3 nonaka #define RS5C313_TINT 7 /* bank0/1 (5c313/5c314/5c316/5c317) */ 44 1.3 nonaka #define RS5C313_SCRATCH 7 /* bank0/1 (5c321) */ 45 1.3 nonaka #define RS5C313_DAY1 8 /* bank0 */ 46 1.3 nonaka #define RS5C313_DAY10 9 /* bank0 */ 47 1.3 nonaka #define RS5C313_MON1 10 /* bank0 */ 48 1.3 nonaka #define RS5C313_MON10 11 /* bank0 */ 49 1.3 nonaka #define RS5C313_YEAR1 12 /* bank0 */ 50 1.3 nonaka #define RS5C313_YEAR10 13 /* bank0 */ 51 1.3 nonaka #define RS5C313_CTRL 14 /* bank0/1 */ 52 1.3 nonaka #define RS5C313_CTRL2 15 /* bank0/1 */ 53 1.3 nonaka 54 1.3 nonaka /* Alarm register (5c316/5c317) */ 55 1.3 nonaka #define RS5C313_AWOD1 0 /* bank1 */ 56 1.3 nonaka #define RS5C313_AWOD2 1 /* bank1 */ 57 1.3 nonaka #define RS5C313_AMIN1 2 /* bank1 */ 58 1.3 nonaka #define RS5C313_AMIN10 3 /* bank1 */ 59 1.3 nonaka #define RS5C313_AHOUR1 4 /* bank1 */ 60 1.3 nonaka #define RS5C313_AHOUR10 5 /* bank1 */ 61 1.3 nonaka 62 1.3 nonaka /* Timer register (5c317) */ 63 1.3 nonaka #define RS5C313_TMR 9 /* bank1 */ 64 1.3 nonaka 65 1.3 nonaka /* 32kHz control register (5c317/5c321) */ 66 1.3 nonaka #define RS5C313_32KHZ 10 /* bank1 */ 67 1.1 uwe 68 1.1 uwe /* TINT register */ 69 1.1 uwe #define TINT_CT0 0x01 70 1.1 uwe #define TINT_CT1 0x02 71 1.1 uwe #define TINT_CT2 0x04 72 1.1 uwe #define TINT_CT3 0x08 73 1.1 uwe 74 1.1 uwe /* CTRL register */ 75 1.1 uwe #define CTRL_BSY 0x01 /* read */ 76 1.1 uwe #define CTRL_ADJ 0x01 /* write */ 77 1.1 uwe #define CTRL_XSTP 0x02 /* read */ 78 1.1 uwe #define CTRL_WTEN 0x02 /* write */ 79 1.3 nonaka #define CTRL_24H 0x04 /* read/write (5c313/5c314) */ 80 1.3 nonaka #define CTRL_ALFG 0x04 /* read/write (5c316/5c317) */ 81 1.1 uwe #define CTRL_CTFG 0x08 /* read/write */ 82 1.1 uwe 83 1.3 nonaka /* CTRL2 register */ 84 1.3 nonaka #define CTRL2_NTEST 0x01 85 1.3 nonaka #define CTRL2_BANK 0x02 /* (5c316/5c317/5c321) */ 86 1.3 nonaka #define CTRL2_TMR 0x04 /* (5c317) */ 87 1.3 nonaka #define CTRL2_24H 0x08 /* (5c316/5c317/5c321) */ 88 1.1 uwe 89 1.1 uwe #endif /* _DEV_IC_RS5C313REG_H_ */ 90
Indexes created Wed Sep 24 05:09:52 GMT 2025