rt2661.c revision 1.17
1 /* $NetBSD: rt2661.c,v 1.17 2007/09/01 07:32:27 dyoung Exp $ */ 2 /* $OpenBSD: rt2661.c,v 1.17 2006/05/01 08:41:11 damien Exp $ */ 3 /* $FreeBSD: rt2560.c,v 1.5 2006/06/02 19:59:31 csjp Exp $ */ 4 5 /*- 6 * Copyright (c) 2006 7 * Damien Bergamini <damien.bergamini (at) free.fr> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2661.c,v 1.17 2007/09/01 07:32:27 dyoung Exp $"); 29 30 #include "bpfilter.h" 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/device.h> 43 44 #include <machine/bus.h> 45 #include <machine/endian.h> 46 #include <machine/intr.h> 47 48 #if NBPFILTER > 0 49 #include <net/bpf.h> 50 #endif 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_ether.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 63 #include <net80211/ieee80211_var.h> 64 #include <net80211/ieee80211_rssadapt.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #include <dev/ic/rt2661reg.h> 68 #include <dev/ic/rt2661var.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <dev/firmload.h> 75 76 #ifdef RAL_DEBUG 77 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 78 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 79 int rt2661_debug = 0; 80 #else 81 #define DPRINTF(x) 82 #define DPRINTFN(n, x) 83 #endif 84 85 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 86 struct rt2661_tx_ring *, int); 87 static void rt2661_reset_tx_ring(struct rt2661_softc *, 88 struct rt2661_tx_ring *); 89 static void rt2661_free_tx_ring(struct rt2661_softc *, 90 struct rt2661_tx_ring *); 91 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 92 struct rt2661_rx_ring *, int); 93 static void rt2661_reset_rx_ring(struct rt2661_softc *, 94 struct rt2661_rx_ring *); 95 static void rt2661_free_rx_ring(struct rt2661_softc *, 96 struct rt2661_rx_ring *); 97 static struct ieee80211_node * 98 rt2661_node_alloc(struct ieee80211_node_table *); 99 static int rt2661_media_change(struct ifnet *); 100 static void rt2661_next_scan(void *); 101 static void rt2661_iter_func(void *, struct ieee80211_node *); 102 static void rt2661_rssadapt_updatestats(void *); 103 static int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 104 int); 105 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 106 static void rt2661_tx_intr(struct rt2661_softc *); 107 static void rt2661_tx_dma_intr(struct rt2661_softc *, 108 struct rt2661_tx_ring *); 109 static void rt2661_rx_intr(struct rt2661_softc *); 110 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 111 static void rt2661_mcu_wakeup(struct rt2661_softc *); 112 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 113 int rt2661_intr(void *); 114 #if NBPFILTER > 0 115 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 116 #endif 117 static int rt2661_ack_rate(struct ieee80211com *, int); 118 static uint16_t rt2661_txtime(int, int, uint32_t); 119 static uint8_t rt2661_plcp_signal(int); 120 static void rt2661_setup_tx_desc(struct rt2661_softc *, 121 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 122 const bus_dma_segment_t *, int, int); 123 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 124 struct ieee80211_node *); 125 static struct mbuf * 126 rt2661_get_rts(struct rt2661_softc *, 127 struct ieee80211_frame *, uint16_t); 128 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 129 struct ieee80211_node *, int); 130 static void rt2661_start(struct ifnet *); 131 static void rt2661_watchdog(struct ifnet *); 132 static int rt2661_reset(struct ifnet *); 133 static int rt2661_ioctl(struct ifnet *, u_long, void *); 134 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 135 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 136 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 137 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 138 static void rt2661_select_antenna(struct rt2661_softc *); 139 static void rt2661_enable_mrr(struct rt2661_softc *); 140 static void rt2661_set_txpreamble(struct rt2661_softc *); 141 static void rt2661_set_basicrates(struct rt2661_softc *, 142 const struct ieee80211_rateset *); 143 static void rt2661_select_band(struct rt2661_softc *, 144 struct ieee80211_channel *); 145 static void rt2661_set_chan(struct rt2661_softc *, 146 struct ieee80211_channel *); 147 static void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 148 static void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 149 static void rt2661_update_promisc(struct rt2661_softc *); 150 #if 0 151 static int rt2661_wme_update(struct ieee80211com *); 152 #endif 153 154 static void rt2661_update_slot(struct ifnet *); 155 static const char * 156 rt2661_get_rf(int); 157 static void rt2661_read_eeprom(struct rt2661_softc *); 158 static int rt2661_bbp_init(struct rt2661_softc *); 159 static int rt2661_init(struct ifnet *); 160 static void rt2661_stop(struct ifnet *, int); 161 static int rt2661_load_microcode(struct rt2661_softc *, const uint8_t *, 162 int); 163 #ifdef notyet 164 static void rt2661_rx_tune(struct rt2661_softc *); 165 static void rt2661_radar_start(struct rt2661_softc *); 166 static int rt2661_radar_stop(struct rt2661_softc *); 167 #endif 168 static int rt2661_prepare_beacon(struct rt2661_softc *); 169 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 170 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 171 172 /* 173 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 174 */ 175 static const struct ieee80211_rateset rt2661_rateset_11a = 176 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 177 178 static const struct ieee80211_rateset rt2661_rateset_11b = 179 { 4, { 2, 4, 11, 22 } }; 180 181 static const struct ieee80211_rateset rt2661_rateset_11g = 182 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 183 184 /* 185 * Default values for MAC registers; values taken from the reference driver. 186 */ 187 static const struct { 188 uint32_t reg; 189 uint32_t val; 190 } rt2661_def_mac[] = { 191 { RT2661_TXRX_CSR0, 0x0000b032 }, 192 { RT2661_TXRX_CSR1, 0x9eb39eb3 }, 193 { RT2661_TXRX_CSR2, 0x8a8b8c8d }, 194 { RT2661_TXRX_CSR3, 0x00858687 }, 195 { RT2661_TXRX_CSR7, 0x2e31353b }, 196 { RT2661_TXRX_CSR8, 0x2a2a2a2c }, 197 { RT2661_TXRX_CSR15, 0x0000000f }, 198 { RT2661_MAC_CSR6, 0x00000fff }, 199 { RT2661_MAC_CSR8, 0x016c030a }, 200 { RT2661_MAC_CSR10, 0x00000718 }, 201 { RT2661_MAC_CSR12, 0x00000004 }, 202 { RT2661_MAC_CSR13, 0x0000e000 }, 203 { RT2661_SEC_CSR0, 0x00000000 }, 204 { RT2661_SEC_CSR1, 0x00000000 }, 205 { RT2661_SEC_CSR5, 0x00000000 }, 206 { RT2661_PHY_CSR1, 0x000023b0 }, 207 { RT2661_PHY_CSR5, 0x060a100c }, 208 { RT2661_PHY_CSR6, 0x00080606 }, 209 { RT2661_PHY_CSR7, 0x00000a08 }, 210 { RT2661_PCI_CFG_CSR, 0x3cca4808 }, 211 { RT2661_AIFSN_CSR, 0x00002273 }, 212 { RT2661_CWMIN_CSR, 0x00002344 }, 213 { RT2661_CWMAX_CSR, 0x000034aa }, 214 { RT2661_TEST_MODE_CSR, 0x00000200 }, 215 { RT2661_M2H_CMD_DONE_CSR, 0xffffffff } 216 }; 217 218 /* 219 * Default values for BBP registers; values taken from the reference driver. 220 */ 221 static const struct { 222 uint8_t reg; 223 uint8_t val; 224 } rt2661_def_bbp[] = { 225 { 3, 0x00 }, 226 { 15, 0x30 }, 227 { 17, 0x20 }, 228 { 21, 0xc8 }, 229 { 22, 0x38 }, 230 { 23, 0x06 }, 231 { 24, 0xfe }, 232 { 25, 0x0a }, 233 { 26, 0x0d }, 234 { 34, 0x12 }, 235 { 37, 0x07 }, 236 { 39, 0xf8 }, 237 { 41, 0x60 }, 238 { 53, 0x10 }, 239 { 54, 0x18 }, 240 { 60, 0x10 }, 241 { 61, 0x04 }, 242 { 62, 0x04 }, 243 { 75, 0xfe }, 244 { 86, 0xfe }, 245 { 88, 0xfe }, 246 { 90, 0x0f }, 247 { 99, 0x00 }, 248 { 102, 0x16 }, 249 { 107, 0x04 } 250 }; 251 252 /* 253 * Default settings for RF registers; values taken from the reference driver. 254 */ 255 static const struct rfprog { 256 uint8_t chan; 257 uint32_t r1; 258 uint32_t r2; 259 uint32_t r3; 260 uint32_t r4; 261 } rt2661_rf5225_1[] = { 262 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, 263 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, 264 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, 265 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, 266 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, 267 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, 268 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, 269 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, 270 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, 271 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, 272 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, 273 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, 274 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, 275 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, 276 277 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, 278 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, 279 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, 280 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, 281 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, 282 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, 283 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, 284 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, 285 286 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, 287 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, 288 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, 289 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, 290 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, 291 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, 292 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, 293 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, 294 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, 295 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, 296 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, 297 298 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, 299 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, 300 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, 301 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, 302 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } 303 304 }, rt2661_rf5225_2[] = { 305 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, 306 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, 307 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, 308 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, 309 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, 310 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, 311 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, 312 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, 313 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, 314 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, 315 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, 316 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, 317 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, 318 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, 319 320 { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, 321 { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, 322 { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, 323 { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, 324 { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, 325 { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, 326 { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, 327 { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, 328 329 { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, 330 { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, 331 { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, 332 { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, 333 { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, 334 { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, 335 { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, 336 { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, 337 { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, 338 { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, 339 { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, 340 341 { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, 342 { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, 343 { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, 344 { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, 345 { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 } 346 }; 347 348 int 349 rt2661_attach(void *xsc, int id) 350 { 351 struct rt2661_softc *sc = xsc; 352 struct ieee80211com *ic = &sc->sc_ic; 353 struct ifnet *ifp = &sc->sc_if; 354 uint32_t val; 355 int error, i, ntries; 356 357 sc->sc_id = id; 358 359 callout_init(&sc->scan_ch, 0); 360 callout_init(&sc->rssadapt_ch, 0); 361 362 /* wait for NIC to initialize */ 363 for (ntries = 0; ntries < 1000; ntries++) { 364 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 365 break; 366 DELAY(1000); 367 } 368 if (ntries == 1000) { 369 aprint_error("%s: timeout waiting for NIC to initialize\n", 370 sc->sc_dev.dv_xname); 371 return EIO; 372 } 373 374 /* retrieve RF rev. no and various other things from EEPROM */ 375 rt2661_read_eeprom(sc); 376 aprint_normal("%s: 802.11 address %s\n", sc->sc_dev.dv_xname, 377 ether_sprintf(ic->ic_myaddr)); 378 379 aprint_normal("%s: MAC/BBP RT%X, RF %s\n", sc->sc_dev.dv_xname, val, 380 rt2661_get_rf(sc->rf_rev)); 381 382 /* 383 * Allocate Tx and Rx rings. 384 */ 385 error = rt2661_alloc_tx_ring(sc, &sc->txq[0], RT2661_TX_RING_COUNT); 386 if (error != 0) { 387 aprint_error("%s: could not allocate Tx ring 0\n", 388 sc->sc_dev.dv_xname); 389 goto fail1; 390 } 391 392 error = rt2661_alloc_tx_ring(sc, &sc->txq[1], RT2661_TX_RING_COUNT); 393 if (error != 0) { 394 aprint_error("%s: could not allocate Tx ring 1\n", 395 sc->sc_dev.dv_xname); 396 goto fail2; 397 } 398 399 error = rt2661_alloc_tx_ring(sc, &sc->txq[2], RT2661_TX_RING_COUNT); 400 if (error != 0) { 401 aprint_error("%s: could not allocate Tx ring 2\n", 402 sc->sc_dev.dv_xname); 403 goto fail3; 404 } 405 406 error = rt2661_alloc_tx_ring(sc, &sc->txq[3], RT2661_TX_RING_COUNT); 407 if (error != 0) { 408 aprint_error("%s: could not allocate Tx ring 3\n", 409 sc->sc_dev.dv_xname); 410 goto fail4; 411 } 412 413 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 414 if (error != 0) { 415 aprint_error("%s: could not allocate Mgt ring\n", 416 sc->sc_dev.dv_xname); 417 goto fail5; 418 } 419 420 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 421 if (error != 0) { 422 aprint_error("%s: could not allocate Rx ring\n", 423 sc->sc_dev.dv_xname); 424 goto fail6; 425 } 426 427 ifp->if_softc = sc; 428 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 429 ifp->if_init = rt2661_init; 430 ifp->if_ioctl = rt2661_ioctl; 431 ifp->if_start = rt2661_start; 432 ifp->if_watchdog = rt2661_watchdog; 433 IFQ_SET_READY(&ifp->if_snd); 434 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 435 436 ic->ic_ifp = ifp; 437 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 438 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 439 ic->ic_state = IEEE80211_S_INIT; 440 441 /* set device capabilities */ 442 ic->ic_caps = 443 IEEE80211_C_IBSS | /* IBSS mode supported */ 444 IEEE80211_C_MONITOR | /* monitor mode supported */ 445 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 446 IEEE80211_C_TXPMGT | /* tx power management */ 447 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 448 IEEE80211_C_SHSLOT | /* short slot time supported */ 449 IEEE80211_C_WPA; /* 802.11i */ 450 451 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 452 /* set supported .11a rates */ 453 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 454 455 /* set supported .11a channels */ 456 for (i = 36; i <= 64; i += 4) { 457 ic->ic_channels[i].ic_freq = 458 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 459 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 460 } 461 for (i = 100; i <= 140; i += 4) { 462 ic->ic_channels[i].ic_freq = 463 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 464 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 465 } 466 for (i = 149; i <= 165; i += 4) { 467 ic->ic_channels[i].ic_freq = 468 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 469 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 470 } 471 } 472 473 /* set supported .11b and .11g rates */ 474 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 475 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 476 477 /* set supported .11b and .11g channels (1 through 14) */ 478 for (i = 1; i <= 14; i++) { 479 ic->ic_channels[i].ic_freq = 480 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 481 ic->ic_channels[i].ic_flags = 482 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 483 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 484 } 485 486 if_attach(ifp); 487 ieee80211_ifattach(ic); 488 ic->ic_node_alloc = rt2661_node_alloc; 489 ic->ic_updateslot = rt2661_update_slot; 490 ic->ic_reset = rt2661_reset; 491 492 /* override state transition machine */ 493 sc->sc_newstate = ic->ic_newstate; 494 ic->ic_newstate = rt2661_newstate; 495 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 496 497 #if NPBFILTER > 0 498 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 499 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 500 501 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 502 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 503 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 504 505 sc->sc_txtap_len = sizeof sc->sc_txtapu; 506 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 507 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 508 #endif 509 510 ieee80211_announce(ic); 511 512 return 0; 513 514 fail6: rt2661_free_tx_ring(sc, &sc->mgtq); 515 fail5: rt2661_free_tx_ring(sc, &sc->txq[3]); 516 fail4: rt2661_free_tx_ring(sc, &sc->txq[2]); 517 fail3: rt2661_free_tx_ring(sc, &sc->txq[1]); 518 fail2: rt2661_free_tx_ring(sc, &sc->txq[0]); 519 fail1: return ENXIO; 520 } 521 522 int 523 rt2661_detach(void *xsc) 524 { 525 struct rt2661_softc *sc = xsc; 526 struct ifnet *ifp = &sc->sc_if; 527 528 callout_stop(&sc->scan_ch); 529 callout_stop(&sc->rssadapt_ch); 530 531 ieee80211_ifdetach(&sc->sc_ic); 532 if_detach(ifp); 533 534 rt2661_free_tx_ring(sc, &sc->txq[0]); 535 rt2661_free_tx_ring(sc, &sc->txq[1]); 536 rt2661_free_tx_ring(sc, &sc->txq[2]); 537 rt2661_free_tx_ring(sc, &sc->txq[3]); 538 rt2661_free_tx_ring(sc, &sc->mgtq); 539 rt2661_free_rx_ring(sc, &sc->rxq); 540 541 return 0; 542 } 543 544 static int 545 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 546 int count) 547 { 548 int i, nsegs, error; 549 550 ring->count = count; 551 ring->queued = 0; 552 ring->cur = ring->next = ring->stat = 0; 553 554 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 555 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 556 if (error != 0) { 557 aprint_error("%s: could not create desc DMA map\n", 558 sc->sc_dev.dv_xname); 559 goto fail; 560 } 561 562 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 563 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 564 if (error != 0) { 565 aprint_error("%s: could not allocate DMA memory\n", 566 sc->sc_dev.dv_xname); 567 goto fail; 568 } 569 570 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 571 count * RT2661_TX_DESC_SIZE, (void **)&ring->desc, 572 BUS_DMA_NOWAIT); 573 if (error != 0) { 574 aprint_error("%s: could not map desc DMA memory\n", 575 sc->sc_dev.dv_xname); 576 goto fail; 577 } 578 579 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 580 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 581 if (error != 0) { 582 aprint_error("%s: could not load desc DMA map\n", 583 sc->sc_dev.dv_xname); 584 goto fail; 585 } 586 587 memset(ring->desc, 0, count * RT2661_TX_DESC_SIZE); 588 ring->physaddr = ring->map->dm_segs->ds_addr; 589 590 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 591 M_NOWAIT); 592 if (ring->data == NULL) { 593 aprint_error("%s: could not allocate soft data\n", 594 sc->sc_dev.dv_xname); 595 error = ENOMEM; 596 goto fail; 597 } 598 599 memset(ring->data, 0, count * sizeof (struct rt2661_tx_data)); 600 for (i = 0; i < count; i++) { 601 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 602 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 603 &ring->data[i].map); 604 if (error != 0) { 605 aprint_error("%s: could not create DMA map\n", 606 sc->sc_dev.dv_xname); 607 goto fail; 608 } 609 } 610 611 return 0; 612 613 fail: rt2661_free_tx_ring(sc, ring); 614 return error; 615 } 616 617 static void 618 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 619 { 620 struct rt2661_tx_desc *desc; 621 struct rt2661_tx_data *data; 622 int i; 623 624 for (i = 0; i < ring->count; i++) { 625 desc = &ring->desc[i]; 626 data = &ring->data[i]; 627 628 if (data->m != NULL) { 629 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 630 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 631 bus_dmamap_unload(sc->sc_dmat, data->map); 632 m_freem(data->m); 633 data->m = NULL; 634 } 635 636 if (data->ni != NULL) { 637 ieee80211_free_node(data->ni); 638 data->ni = NULL; 639 } 640 641 desc->flags = 0; 642 } 643 644 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 645 BUS_DMASYNC_PREWRITE); 646 647 ring->queued = 0; 648 ring->cur = ring->next = ring->stat = 0; 649 } 650 651 652 static void 653 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 654 { 655 struct rt2661_tx_data *data; 656 int i; 657 658 if (ring->desc != NULL) { 659 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 660 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 661 bus_dmamap_unload(sc->sc_dmat, ring->map); 662 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 663 ring->count * RT2661_TX_DESC_SIZE); 664 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 665 } 666 667 if (ring->data != NULL) { 668 for (i = 0; i < ring->count; i++) { 669 data = &ring->data[i]; 670 671 if (data->m != NULL) { 672 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 673 data->map->dm_mapsize, 674 BUS_DMASYNC_POSTWRITE); 675 bus_dmamap_unload(sc->sc_dmat, data->map); 676 m_freem(data->m); 677 } 678 679 if (data->ni != NULL) 680 ieee80211_free_node(data->ni); 681 682 if (data->map != NULL) 683 bus_dmamap_destroy(sc->sc_dmat, data->map); 684 } 685 free(ring->data, M_DEVBUF); 686 } 687 } 688 689 static int 690 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 691 int count) 692 { 693 struct rt2661_rx_desc *desc; 694 struct rt2661_rx_data *data; 695 int i, nsegs, error; 696 697 ring->count = count; 698 ring->cur = ring->next = 0; 699 700 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 701 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 702 if (error != 0) { 703 aprint_error("%s: could not create desc DMA map\n", 704 sc->sc_dev.dv_xname); 705 goto fail; 706 } 707 708 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 709 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 710 if (error != 0) { 711 aprint_error("%s: could not allocate DMA memory\n", 712 sc->sc_dev.dv_xname); 713 goto fail; 714 } 715 716 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 717 count * RT2661_RX_DESC_SIZE, (void **)&ring->desc, 718 BUS_DMA_NOWAIT); 719 if (error != 0) { 720 aprint_error("%s: could not map desc DMA memory\n", 721 sc->sc_dev.dv_xname); 722 goto fail; 723 } 724 725 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 726 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 727 if (error != 0) { 728 aprint_error("%s: could not load desc DMA map\n", 729 sc->sc_dev.dv_xname); 730 goto fail; 731 } 732 733 memset(ring->desc, 0, count * RT2661_RX_DESC_SIZE); 734 ring->physaddr = ring->map->dm_segs->ds_addr; 735 736 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 737 M_NOWAIT); 738 if (ring->data == NULL) { 739 aprint_error("%s: could not allocate soft data\n", 740 sc->sc_dev.dv_xname); 741 error = ENOMEM; 742 goto fail; 743 } 744 745 /* 746 * Pre-allocate Rx buffers and populate Rx ring. 747 */ 748 memset(ring->data, 0, count * sizeof (struct rt2661_rx_data)); 749 for (i = 0; i < count; i++) { 750 desc = &sc->rxq.desc[i]; 751 data = &sc->rxq.data[i]; 752 753 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 754 0, BUS_DMA_NOWAIT, &data->map); 755 if (error != 0) { 756 printf("%s: could not create DMA map\n", 757 sc->sc_dev.dv_xname); 758 goto fail; 759 } 760 761 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 762 if (data->m == NULL) { 763 printf("%s: could not allocate rx mbuf\n", 764 sc->sc_dev.dv_xname); 765 error = ENOMEM; 766 goto fail; 767 } 768 769 MCLGET(data->m, M_DONTWAIT); 770 if (!(data->m->m_flags & M_EXT)) { 771 printf("%s: could not allocate rx mbuf cluster\n", 772 sc->sc_dev.dv_xname); 773 error = ENOMEM; 774 goto fail; 775 } 776 777 error = bus_dmamap_load(sc->sc_dmat, data->map, 778 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 779 if (error != 0) { 780 printf("%s: could not load rx buf DMA map", 781 sc->sc_dev.dv_xname); 782 goto fail; 783 } 784 785 desc->flags = htole32(RT2661_RX_BUSY); 786 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 787 } 788 789 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 790 BUS_DMASYNC_PREWRITE); 791 792 return 0; 793 794 fail: rt2661_free_rx_ring(sc, ring); 795 return error; 796 } 797 798 static void 799 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 800 { 801 int i; 802 803 for (i = 0; i < ring->count; i++) 804 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 805 806 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 807 BUS_DMASYNC_PREWRITE); 808 809 ring->cur = ring->next = 0; 810 } 811 812 static void 813 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 814 { 815 struct rt2661_rx_data *data; 816 int i; 817 818 if (ring->desc != NULL) { 819 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 820 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 821 bus_dmamap_unload(sc->sc_dmat, ring->map); 822 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 823 ring->count * RT2661_RX_DESC_SIZE); 824 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 825 } 826 827 if (ring->data != NULL) { 828 for (i = 0; i < ring->count; i++) { 829 data = &ring->data[i]; 830 831 if (data->m != NULL) { 832 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 833 data->map->dm_mapsize, 834 BUS_DMASYNC_POSTREAD); 835 bus_dmamap_unload(sc->sc_dmat, data->map); 836 m_freem(data->m); 837 } 838 839 if (data->map != NULL) 840 bus_dmamap_destroy(sc->sc_dmat, data->map); 841 } 842 free(ring->data, M_DEVBUF); 843 } 844 } 845 846 static struct ieee80211_node * 847 rt2661_node_alloc(struct ieee80211_node_table *nt) 848 { 849 struct rt2661_node *rn; 850 851 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 852 M_NOWAIT | M_ZERO); 853 854 return (rn != NULL) ? &rn->ni : NULL; 855 } 856 857 static int 858 rt2661_media_change(struct ifnet *ifp) 859 { 860 int error; 861 862 error = ieee80211_media_change(ifp); 863 if (error != ENETRESET) 864 return error; 865 866 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 867 rt2661_init(ifp); 868 869 return 0; 870 } 871 872 /* 873 * This function is called periodically (every 200ms) during scanning to 874 * switch from one channel to another. 875 */ 876 static void 877 rt2661_next_scan(void *arg) 878 { 879 struct rt2661_softc *sc = arg; 880 struct ieee80211com *ic = &sc->sc_ic; 881 882 if (ic->ic_state == IEEE80211_S_SCAN) 883 ieee80211_next_scan(ic); 884 } 885 886 /* 887 * This function is called for each neighbor node. 888 */ 889 static void 890 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 891 { 892 struct rt2661_node *rn = (struct rt2661_node *)ni; 893 894 ieee80211_rssadapt_updatestats(&rn->rssadapt); 895 } 896 897 /* 898 * This function is called periodically (every 100ms) in RUN state to update 899 * the rate adaptation statistics. 900 */ 901 static void 902 rt2661_rssadapt_updatestats(void *arg) 903 { 904 struct rt2661_softc *sc = arg; 905 struct ieee80211com *ic = &sc->sc_ic; 906 907 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 908 909 callout_reset(&sc->rssadapt_ch, hz / 10, rt2661_rssadapt_updatestats, 910 sc); 911 } 912 913 static int 914 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 915 { 916 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 917 enum ieee80211_state ostate; 918 struct ieee80211_node *ni; 919 uint32_t tmp; 920 int error = 0; 921 922 ostate = ic->ic_state; 923 callout_stop(&sc->scan_ch); 924 925 switch (nstate) { 926 case IEEE80211_S_INIT: 927 callout_stop(&sc->rssadapt_ch); 928 929 if (ostate == IEEE80211_S_RUN) { 930 /* abort TSF synchronization */ 931 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 932 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 933 } 934 break; 935 936 case IEEE80211_S_SCAN: 937 rt2661_set_chan(sc, ic->ic_curchan); 938 callout_reset(&sc->scan_ch, hz / 5, rt2661_next_scan, sc); 939 break; 940 941 case IEEE80211_S_AUTH: 942 case IEEE80211_S_ASSOC: 943 rt2661_set_chan(sc, ic->ic_curchan); 944 break; 945 946 case IEEE80211_S_RUN: 947 rt2661_set_chan(sc, ic->ic_curchan); 948 949 ni = ic->ic_bss; 950 951 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 952 rt2661_enable_mrr(sc); 953 rt2661_set_txpreamble(sc); 954 rt2661_set_basicrates(sc, &ni->ni_rates); 955 rt2661_set_bssid(sc, ni->ni_bssid); 956 } 957 958 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 959 ic->ic_opmode == IEEE80211_M_IBSS) { 960 if ((error = rt2661_prepare_beacon(sc)) != 0) 961 break; 962 } 963 964 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 965 callout_reset(&sc->rssadapt_ch, hz / 10, 966 rt2661_rssadapt_updatestats, sc); 967 rt2661_enable_tsf_sync(sc); 968 } 969 break; 970 } 971 972 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 973 } 974 975 /* 976 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 977 * 93C66). 978 */ 979 static uint16_t 980 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 981 { 982 uint32_t tmp; 983 uint16_t val; 984 int n; 985 986 /* clock C once before the first command */ 987 RT2661_EEPROM_CTL(sc, 0); 988 989 RT2661_EEPROM_CTL(sc, RT2661_S); 990 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 991 RT2661_EEPROM_CTL(sc, RT2661_S); 992 993 /* write start bit (1) */ 994 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 995 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 996 997 /* write READ opcode (10) */ 998 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 999 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 1000 RT2661_EEPROM_CTL(sc, RT2661_S); 1001 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1002 1003 /* write address (A5-A0 or A7-A0) */ 1004 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 1005 for (; n >= 0; n--) { 1006 RT2661_EEPROM_CTL(sc, RT2661_S | 1007 (((addr >> n) & 1) << RT2661_SHIFT_D)); 1008 RT2661_EEPROM_CTL(sc, RT2661_S | 1009 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 1010 } 1011 1012 RT2661_EEPROM_CTL(sc, RT2661_S); 1013 1014 /* read data Q15-Q0 */ 1015 val = 0; 1016 for (n = 15; n >= 0; n--) { 1017 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1018 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 1019 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 1020 RT2661_EEPROM_CTL(sc, RT2661_S); 1021 } 1022 1023 RT2661_EEPROM_CTL(sc, 0); 1024 1025 /* clear Chip Select and clock C */ 1026 RT2661_EEPROM_CTL(sc, RT2661_S); 1027 RT2661_EEPROM_CTL(sc, 0); 1028 RT2661_EEPROM_CTL(sc, RT2661_C); 1029 1030 return val; 1031 } 1032 1033 static void 1034 rt2661_tx_intr(struct rt2661_softc *sc) 1035 { 1036 struct ieee80211com *ic = &sc->sc_ic; 1037 struct ifnet *ifp = &sc->sc_if; 1038 struct rt2661_tx_ring *txq; 1039 struct rt2661_tx_data *data; 1040 struct rt2661_node *rn; 1041 uint32_t val; 1042 int qid, retrycnt; 1043 1044 for (;;) { 1045 val = RAL_READ(sc, RT2661_STA_CSR4); 1046 if (!(val & RT2661_TX_STAT_VALID)) 1047 break; 1048 1049 /* retrieve the queue in which this frame was sent */ 1050 qid = RT2661_TX_QID(val); 1051 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 1052 1053 /* retrieve rate control algorithm context */ 1054 data = &txq->data[txq->stat]; 1055 rn = (struct rt2661_node *)data->ni; 1056 1057 /* if no frame has been sent, ignore */ 1058 if (rn == NULL) 1059 continue; 1060 1061 switch (RT2661_TX_RESULT(val)) { 1062 case RT2661_TX_SUCCESS: 1063 retrycnt = RT2661_TX_RETRYCNT(val); 1064 1065 DPRINTFN(10, ("data frame sent successfully after " 1066 "%d retries\n", retrycnt)); 1067 if (retrycnt == 0 && data->id.id_node != NULL) { 1068 ieee80211_rssadapt_raise_rate(ic, 1069 &rn->rssadapt, &data->id); 1070 } 1071 ifp->if_opackets++; 1072 break; 1073 1074 case RT2661_TX_RETRY_FAIL: 1075 DPRINTFN(9, ("sending data frame failed (too much " 1076 "retries)\n")); 1077 if (data->id.id_node != NULL) { 1078 ieee80211_rssadapt_lower_rate(ic, data->ni, 1079 &rn->rssadapt, &data->id); 1080 } 1081 ifp->if_oerrors++; 1082 break; 1083 1084 default: 1085 /* other failure */ 1086 printf("%s: sending data frame failed 0x%08x\n", 1087 sc->sc_dev.dv_xname, val); 1088 ifp->if_oerrors++; 1089 } 1090 1091 ieee80211_free_node(data->ni); 1092 data->ni = NULL; 1093 1094 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 1095 1096 txq->queued--; 1097 if (++txq->stat >= txq->count) /* faster than % count */ 1098 txq->stat = 0; 1099 } 1100 1101 sc->sc_tx_timer = 0; 1102 ifp->if_flags &= ~IFF_OACTIVE; 1103 rt2661_start(ifp); 1104 } 1105 1106 static void 1107 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1108 { 1109 struct rt2661_tx_desc *desc; 1110 struct rt2661_tx_data *data; 1111 1112 for (;;) { 1113 desc = &txq->desc[txq->next]; 1114 data = &txq->data[txq->next]; 1115 1116 bus_dmamap_sync(sc->sc_dmat, txq->map, 1117 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1118 BUS_DMASYNC_POSTREAD); 1119 1120 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1121 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1122 break; 1123 1124 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1125 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1126 bus_dmamap_unload(sc->sc_dmat, data->map); 1127 m_freem(data->m); 1128 data->m = NULL; 1129 /* node reference is released in rt2661_tx_intr() */ 1130 1131 /* descriptor is no longer valid */ 1132 desc->flags &= ~htole32(RT2661_TX_VALID); 1133 1134 bus_dmamap_sync(sc->sc_dmat, txq->map, 1135 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1136 BUS_DMASYNC_PREWRITE); 1137 1138 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1139 1140 if (++txq->next >= txq->count) /* faster than % count */ 1141 txq->next = 0; 1142 } 1143 } 1144 1145 static void 1146 rt2661_rx_intr(struct rt2661_softc *sc) 1147 { 1148 struct ieee80211com *ic = &sc->sc_ic; 1149 struct ifnet *ifp = &sc->sc_if; 1150 struct rt2661_rx_desc *desc; 1151 struct rt2661_rx_data *data; 1152 struct rt2661_node *rn; 1153 struct ieee80211_frame *wh; 1154 struct ieee80211_node *ni; 1155 struct mbuf *mnew, *m; 1156 int error; 1157 1158 for (;;) { 1159 desc = &sc->rxq.desc[sc->rxq.cur]; 1160 data = &sc->rxq.data[sc->rxq.cur]; 1161 1162 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1163 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1164 BUS_DMASYNC_POSTREAD); 1165 1166 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1167 break; 1168 1169 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1170 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1171 /* 1172 * This should not happen since we did not request 1173 * to receive those frames when we filled TXRX_CSR0. 1174 */ 1175 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1176 le32toh(desc->flags))); 1177 ifp->if_ierrors++; 1178 goto skip; 1179 } 1180 1181 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1182 ifp->if_ierrors++; 1183 goto skip; 1184 } 1185 1186 /* 1187 * Try to allocate a new mbuf for this ring element and load it 1188 * before processing the current mbuf. If the ring element 1189 * cannot be loaded, drop the received packet and reuse the old 1190 * mbuf. In the unlikely case that the old mbuf can't be 1191 * reloaded either, explicitly panic. 1192 */ 1193 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1194 if (mnew == NULL) { 1195 ifp->if_ierrors++; 1196 goto skip; 1197 } 1198 1199 MCLGET(mnew, M_DONTWAIT); 1200 if (!(mnew->m_flags & M_EXT)) { 1201 m_freem(mnew); 1202 ifp->if_ierrors++; 1203 goto skip; 1204 } 1205 1206 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1207 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1208 bus_dmamap_unload(sc->sc_dmat, data->map); 1209 1210 error = bus_dmamap_load(sc->sc_dmat, data->map, 1211 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1212 if (error != 0) { 1213 m_freem(mnew); 1214 1215 /* try to reload the old mbuf */ 1216 error = bus_dmamap_load(sc->sc_dmat, data->map, 1217 mtod(data->m, void *), MCLBYTES, NULL, 1218 BUS_DMA_NOWAIT); 1219 if (error != 0) { 1220 /* very unlikely that it will fail... */ 1221 panic("%s: could not load old rx mbuf", 1222 sc->sc_dev.dv_xname); 1223 } 1224 ifp->if_ierrors++; 1225 goto skip; 1226 } 1227 1228 /* 1229 * New mbuf successfully loaded, update Rx ring and continue 1230 * processing. 1231 */ 1232 m = data->m; 1233 data->m = mnew; 1234 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1235 1236 /* finalize mbuf */ 1237 m->m_pkthdr.rcvif = ifp; 1238 m->m_pkthdr.len = m->m_len = 1239 (le32toh(desc->flags) >> 16) & 0xfff; 1240 1241 #if NBPFILTER > 0 1242 if (sc->sc_drvbpf != NULL) { 1243 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1244 uint32_t tsf_lo, tsf_hi; 1245 1246 /* get timestamp (low and high 32 bits) */ 1247 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1248 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1249 1250 tap->wr_tsf = 1251 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1252 tap->wr_flags = 0; 1253 tap->wr_rate = rt2661_rxrate(desc); 1254 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1255 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1256 tap->wr_antsignal = desc->rssi; 1257 1258 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1259 } 1260 #endif 1261 1262 wh = mtod(m, struct ieee80211_frame *); 1263 ni = ieee80211_find_rxnode(ic, 1264 (struct ieee80211_frame_min *)wh); 1265 1266 /* send the frame to the 802.11 layer */ 1267 ieee80211_input(ic, m, ni, desc->rssi, 0); 1268 1269 1270 /* give rssi to the rate adatation algorithm */ 1271 rn = (struct rt2661_node *)ni; 1272 ieee80211_rssadapt_input(ic, ni, &rn->rssadapt, 1273 rt2661_get_rssi(sc, desc->rssi)); 1274 1275 /* node is no longer needed */ 1276 ieee80211_free_node(ni); 1277 1278 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1279 1280 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1281 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1282 BUS_DMASYNC_PREWRITE); 1283 1284 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1285 1286 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1287 } 1288 1289 /* 1290 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 1291 * without calling if_start(). 1292 */ 1293 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 1294 rt2661_start(ifp); 1295 } 1296 1297 /* ARGSUSED */ 1298 static void 1299 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1300 { 1301 /* do nothing */ 1302 } 1303 1304 static void 1305 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1306 { 1307 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1308 1309 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1310 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1311 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1312 1313 /* send wakeup command to MCU */ 1314 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1315 } 1316 1317 static void 1318 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1319 { 1320 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1321 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1322 } 1323 1324 int 1325 rt2661_intr(void *arg) 1326 { 1327 struct rt2661_softc *sc = arg; 1328 struct ifnet *ifp = &sc->sc_if; 1329 uint32_t r1, r2; 1330 1331 /* disable MAC and MCU interrupts */ 1332 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1333 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1334 1335 /* don't re-enable interrupts if we're shutting down */ 1336 if (!(ifp->if_flags & IFF_RUNNING)) 1337 return 0; 1338 1339 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1340 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1341 1342 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1343 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1344 1345 if (r1 & RT2661_MGT_DONE) 1346 rt2661_tx_dma_intr(sc, &sc->mgtq); 1347 1348 if (r1 & RT2661_RX_DONE) 1349 rt2661_rx_intr(sc); 1350 1351 if (r1 & RT2661_TX0_DMA_DONE) 1352 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1353 1354 if (r1 & RT2661_TX1_DMA_DONE) 1355 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1356 1357 if (r1 & RT2661_TX2_DMA_DONE) 1358 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1359 1360 if (r1 & RT2661_TX3_DMA_DONE) 1361 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1362 1363 if (r1 & RT2661_TX_DONE) 1364 rt2661_tx_intr(sc); 1365 1366 if (r2 & RT2661_MCU_CMD_DONE) 1367 rt2661_mcu_cmd_intr(sc); 1368 1369 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1370 rt2661_mcu_beacon_expire(sc); 1371 1372 if (r2 & RT2661_MCU_WAKEUP) 1373 rt2661_mcu_wakeup(sc); 1374 1375 /* re-enable MAC and MCU interrupts */ 1376 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1377 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1378 1379 return 1; 1380 } 1381 1382 /* quickly determine if a given rate is CCK or OFDM */ 1383 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1384 1385 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1386 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1387 1388 #define RAL_SIFS 10 /* us */ 1389 1390 /* 1391 * This function is only used by the Rx radiotap code. It returns the rate at 1392 * which a given frame was received. 1393 */ 1394 #if NBPFILTER > 0 1395 static uint8_t 1396 rt2661_rxrate(struct rt2661_rx_desc *desc) 1397 { 1398 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1399 /* reverse function of rt2661_plcp_signal */ 1400 switch (desc->rate & 0xf) { 1401 case 0xb: return 12; 1402 case 0xf: return 18; 1403 case 0xa: return 24; 1404 case 0xe: return 36; 1405 case 0x9: return 48; 1406 case 0xd: return 72; 1407 case 0x8: return 96; 1408 case 0xc: return 108; 1409 } 1410 } else { 1411 if (desc->rate == 10) 1412 return 2; 1413 if (desc->rate == 20) 1414 return 4; 1415 if (desc->rate == 55) 1416 return 11; 1417 if (desc->rate == 110) 1418 return 22; 1419 } 1420 return 2; /* should not get there */ 1421 } 1422 #endif 1423 1424 /* 1425 * Return the expected ack rate for a frame transmitted at rate `rate'. 1426 * XXX: this should depend on the destination node basic rate set. 1427 */ 1428 static int 1429 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1430 { 1431 switch (rate) { 1432 /* CCK rates */ 1433 case 2: 1434 return 2; 1435 case 4: 1436 case 11: 1437 case 22: 1438 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1439 1440 /* OFDM rates */ 1441 case 12: 1442 case 18: 1443 return 12; 1444 case 24: 1445 case 36: 1446 return 24; 1447 case 48: 1448 case 72: 1449 case 96: 1450 case 108: 1451 return 48; 1452 } 1453 1454 /* default to 1Mbps */ 1455 return 2; 1456 } 1457 1458 /* 1459 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1460 * The function automatically determines the operating mode depending on the 1461 * given rate. `flags' indicates whether short preamble is in use or not. 1462 */ 1463 static uint16_t 1464 rt2661_txtime(int len, int rate, uint32_t flags) 1465 { 1466 uint16_t txtime; 1467 1468 if (RAL_RATE_IS_OFDM(rate)) { 1469 /* IEEE Std 802.11a-1999, pp. 37 */ 1470 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1471 txtime = 16 + 4 + 4 * txtime + 6; 1472 } else { 1473 /* IEEE Std 802.11b-1999, pp. 28 */ 1474 txtime = (16 * len + rate - 1) / rate; 1475 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1476 txtime += 72 + 24; 1477 else 1478 txtime += 144 + 48; 1479 } 1480 return txtime; 1481 } 1482 1483 static uint8_t 1484 rt2661_plcp_signal(int rate) 1485 { 1486 switch (rate) { 1487 /* CCK rates (returned values are device-dependent) */ 1488 case 2: return 0x0; 1489 case 4: return 0x1; 1490 case 11: return 0x2; 1491 case 22: return 0x3; 1492 1493 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1494 case 12: return 0xb; 1495 case 18: return 0xf; 1496 case 24: return 0xa; 1497 case 36: return 0xe; 1498 case 48: return 0x9; 1499 case 72: return 0xd; 1500 case 96: return 0x8; 1501 case 108: return 0xc; 1502 1503 /* unsupported rates (should not get there) */ 1504 default: return 0xff; 1505 } 1506 } 1507 1508 static void 1509 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1510 uint32_t flags, uint16_t xflags, int len, int rate, 1511 const bus_dma_segment_t *segs, int nsegs, int ac) 1512 { 1513 struct ieee80211com *ic = &sc->sc_ic; 1514 uint16_t plcp_length; 1515 int i, remainder; 1516 1517 desc->flags = htole32(flags); 1518 desc->flags |= htole32(len << 16); 1519 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1520 1521 desc->xflags = htole16(xflags); 1522 desc->xflags |= htole16(nsegs << 13); 1523 1524 desc->wme = htole16( 1525 RT2661_QID(ac) | 1526 RT2661_AIFSN(2) | 1527 RT2661_LOGCWMIN(4) | 1528 RT2661_LOGCWMAX(10)); 1529 1530 /* 1531 * Remember in which queue this frame was sent. This field is driver 1532 * private data only. It will be made available by the NIC in STA_CSR4 1533 * on Tx interrupts. 1534 */ 1535 desc->qid = ac; 1536 1537 /* setup PLCP fields */ 1538 desc->plcp_signal = rt2661_plcp_signal(rate); 1539 desc->plcp_service = 4; 1540 1541 len += IEEE80211_CRC_LEN; 1542 if (RAL_RATE_IS_OFDM(rate)) { 1543 desc->flags |= htole32(RT2661_TX_OFDM); 1544 1545 plcp_length = len & 0xfff; 1546 desc->plcp_length_hi = plcp_length >> 6; 1547 desc->plcp_length_lo = plcp_length & 0x3f; 1548 } else { 1549 plcp_length = (16 * len + rate - 1) / rate; 1550 if (rate == 22) { 1551 remainder = (16 * len) % 22; 1552 if (remainder != 0 && remainder < 7) 1553 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1554 } 1555 desc->plcp_length_hi = plcp_length >> 8; 1556 desc->plcp_length_lo = plcp_length & 0xff; 1557 1558 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1559 desc->plcp_signal |= 0x08; 1560 } 1561 1562 /* RT2x61 supports scatter with up to 5 segments */ 1563 for (i = 0; i < nsegs; i++) { 1564 desc->addr[i] = htole32(segs[i].ds_addr); 1565 desc->len [i] = htole16(segs[i].ds_len); 1566 } 1567 } 1568 1569 static int 1570 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1571 struct ieee80211_node *ni) 1572 { 1573 struct ieee80211com *ic = &sc->sc_ic; 1574 struct rt2661_tx_desc *desc; 1575 struct rt2661_tx_data *data; 1576 struct ieee80211_frame *wh; 1577 uint16_t dur; 1578 uint32_t flags = 0; 1579 int rate, error; 1580 1581 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1582 data = &sc->mgtq.data[sc->mgtq.cur]; 1583 1584 /* send mgt frames at the lowest available rate */ 1585 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1586 1587 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1588 BUS_DMA_NOWAIT); 1589 if (error != 0) { 1590 printf("%s: could not map mbuf (error %d)\n", 1591 sc->sc_dev.dv_xname, error); 1592 m_freem(m0); 1593 return error; 1594 } 1595 1596 #if NBPFILTER > 0 1597 if (sc->sc_drvbpf != NULL) { 1598 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1599 1600 tap->wt_flags = 0; 1601 tap->wt_rate = rate; 1602 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1603 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1604 1605 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1606 } 1607 #endif 1608 1609 data->m = m0; 1610 data->ni = ni; 1611 1612 wh = mtod(m0, struct ieee80211_frame *); 1613 1614 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1615 flags |= RT2661_TX_NEED_ACK; 1616 1617 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1618 RAL_SIFS; 1619 *(uint16_t *)wh->i_dur = htole16(dur); 1620 1621 /* tell hardware to add timestamp in probe responses */ 1622 if ((wh->i_fc[0] & 1623 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1624 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1625 flags |= RT2661_TX_TIMESTAMP; 1626 } 1627 1628 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1629 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1630 RT2661_QID_MGT); 1631 1632 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1633 BUS_DMASYNC_PREWRITE); 1634 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1635 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1636 BUS_DMASYNC_PREWRITE); 1637 1638 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1639 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1640 1641 /* kick mgt */ 1642 sc->mgtq.queued++; 1643 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1644 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1645 1646 return 0; 1647 } 1648 1649 /* 1650 * Build a RTS control frame. 1651 */ 1652 static struct mbuf * 1653 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1654 uint16_t dur) 1655 { 1656 struct ieee80211_frame_rts *rts; 1657 struct mbuf *m; 1658 1659 MGETHDR(m, M_DONTWAIT, MT_DATA); 1660 if (m == NULL) { 1661 sc->sc_ic.ic_stats.is_tx_nobuf++; 1662 printf("%s: could not allocate RTS frame\n", 1663 sc->sc_dev.dv_xname); 1664 return NULL; 1665 } 1666 1667 rts = mtod(m, struct ieee80211_frame_rts *); 1668 1669 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1670 IEEE80211_FC0_SUBTYPE_RTS; 1671 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1672 *(uint16_t *)rts->i_dur = htole16(dur); 1673 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1674 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1675 1676 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1677 1678 return m; 1679 } 1680 1681 static int 1682 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1683 struct ieee80211_node *ni, int ac) 1684 { 1685 struct ieee80211com *ic = &sc->sc_ic; 1686 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1687 struct rt2661_tx_desc *desc; 1688 struct rt2661_tx_data *data; 1689 struct rt2661_node *rn; 1690 struct ieee80211_rateset *rs; 1691 struct ieee80211_frame *wh; 1692 struct ieee80211_key *k; 1693 struct mbuf *mnew; 1694 uint16_t dur; 1695 uint32_t flags = 0; 1696 int rate, error; 1697 1698 wh = mtod(m0, struct ieee80211_frame *); 1699 1700 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1701 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1702 rate = rs->rs_rates[ic->ic_fixed_rate]; 1703 } else { 1704 rs = &ni->ni_rates; 1705 rn = (struct rt2661_node *)ni; 1706 ni->ni_txrate = ieee80211_rssadapt_choose(&rn->rssadapt, rs, 1707 wh, m0->m_pkthdr.len, -1, NULL, 0); 1708 rate = rs->rs_rates[ni->ni_txrate]; 1709 } 1710 rate &= IEEE80211_RATE_VAL; 1711 1712 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1713 k = ieee80211_crypto_encap(ic, ni, m0); 1714 if (k == NULL) { 1715 m_freem(m0); 1716 return ENOBUFS; 1717 } 1718 1719 /* packet header may have moved, reset our local pointer */ 1720 wh = mtod(m0, struct ieee80211_frame *); 1721 } 1722 1723 /* 1724 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1725 * for directed frames only when the length of the MPDU is greater 1726 * than the length threshold indicated by [...]" ic_rtsthreshold. 1727 */ 1728 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1729 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1730 struct mbuf *m; 1731 int rtsrate, ackrate; 1732 1733 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1734 ackrate = rt2661_ack_rate(ic, rate); 1735 1736 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1737 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1738 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1739 3 * RAL_SIFS; 1740 1741 m = rt2661_get_rts(sc, wh, dur); 1742 1743 desc = &txq->desc[txq->cur]; 1744 data = &txq->data[txq->cur]; 1745 1746 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1747 BUS_DMA_NOWAIT); 1748 if (error != 0) { 1749 printf("%s: could not map mbuf (error %d)\n", 1750 sc->sc_dev.dv_xname, error); 1751 m_freem(m); 1752 m_freem(m0); 1753 return error; 1754 } 1755 1756 /* avoid multiple free() of the same node for each fragment */ 1757 ieee80211_ref_node(ni); 1758 1759 data->m = m; 1760 data->ni = ni; 1761 1762 /* RTS frames are not taken into account for rssadapt */ 1763 data->id.id_node = NULL; 1764 1765 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1766 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, 1767 data->map->dm_segs, data->map->dm_nsegs, ac); 1768 1769 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1770 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1771 bus_dmamap_sync(sc->sc_dmat, txq->map, 1772 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1773 BUS_DMASYNC_PREWRITE); 1774 1775 txq->queued++; 1776 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1777 1778 /* 1779 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1780 * asynchronous data frame shall be transmitted after the CTS 1781 * frame and a SIFS period. 1782 */ 1783 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1784 } 1785 1786 data = &txq->data[txq->cur]; 1787 desc = &txq->desc[txq->cur]; 1788 1789 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1790 BUS_DMA_NOWAIT); 1791 if (error != 0 && error != EFBIG) { 1792 printf("%s: could not map mbuf (error %d)\n", 1793 sc->sc_dev.dv_xname, error); 1794 m_freem(m0); 1795 return error; 1796 } 1797 if (error != 0) { 1798 /* too many fragments, linearize */ 1799 1800 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1801 if (mnew == NULL) { 1802 m_freem(m0); 1803 return ENOMEM; 1804 } 1805 1806 M_COPY_PKTHDR(mnew, m0); 1807 if (m0->m_pkthdr.len > MHLEN) { 1808 MCLGET(mnew, M_DONTWAIT); 1809 if (!(mnew->m_flags & M_EXT)) { 1810 m_freem(m0); 1811 m_freem(mnew); 1812 return ENOMEM; 1813 } 1814 } 1815 1816 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1817 m_freem(m0); 1818 mnew->m_len = mnew->m_pkthdr.len; 1819 m0 = mnew; 1820 1821 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1822 BUS_DMA_NOWAIT); 1823 if (error != 0) { 1824 printf("%s: could not map mbuf (error %d)\n", 1825 sc->sc_dev.dv_xname, error); 1826 m_freem(m0); 1827 return error; 1828 } 1829 1830 /* packet header have moved, reset our local pointer */ 1831 wh = mtod(m0, struct ieee80211_frame *); 1832 } 1833 1834 #if NBPFILTER > 0 1835 if (sc->sc_drvbpf != NULL) { 1836 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1837 1838 tap->wt_flags = 0; 1839 tap->wt_rate = rate; 1840 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1841 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1842 1843 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1844 } 1845 #endif 1846 1847 data->m = m0; 1848 data->ni = ni; 1849 1850 /* remember link conditions for rate adaptation algorithm */ 1851 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1852 data->id.id_len = m0->m_pkthdr.len; 1853 data->id.id_rateidx = ni->ni_txrate; 1854 data->id.id_node = ni; 1855 data->id.id_rssi = ni->ni_rssi; 1856 } else 1857 data->id.id_node = NULL; 1858 1859 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1860 flags |= RT2661_TX_NEED_ACK; 1861 1862 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1863 ic->ic_flags) + RAL_SIFS; 1864 *(uint16_t *)wh->i_dur = htole16(dur); 1865 } 1866 1867 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1868 data->map->dm_segs, data->map->dm_nsegs, ac); 1869 1870 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1871 BUS_DMASYNC_PREWRITE); 1872 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1873 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1874 1875 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1876 m0->m_pkthdr.len, txq->cur, rate)); 1877 1878 /* kick Tx */ 1879 txq->queued++; 1880 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1881 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1882 1883 return 0; 1884 } 1885 1886 static void 1887 rt2661_start(struct ifnet *ifp) 1888 { 1889 struct rt2661_softc *sc = ifp->if_softc; 1890 struct ieee80211com *ic = &sc->sc_ic; 1891 struct mbuf *m0; 1892 struct ether_header *eh; 1893 struct ieee80211_node *ni = NULL; 1894 int ac; 1895 1896 /* 1897 * net80211 may still try to send management frames even if the 1898 * IFF_RUNNING flag is not set... 1899 */ 1900 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1901 return; 1902 1903 for (;;) { 1904 IF_POLL(&ic->ic_mgtq, m0); 1905 if (m0 != NULL) { 1906 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1907 ifp->if_flags |= IFF_OACTIVE; 1908 break; 1909 } 1910 IF_DEQUEUE(&ic->ic_mgtq, m0); 1911 if (m0 == NULL) 1912 break; 1913 1914 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1915 m0->m_pkthdr.rcvif = NULL; 1916 #if NBPFILTER > 0 1917 if (ic->ic_rawbpf != NULL) 1918 bpf_mtap(ic->ic_rawbpf, m0); 1919 #endif 1920 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1921 break; 1922 1923 } else { 1924 if (ic->ic_state != IEEE80211_S_RUN) 1925 break; 1926 IFQ_DEQUEUE(&ifp->if_snd, m0); 1927 if (m0 == NULL) 1928 break; 1929 1930 if (m0->m_len < sizeof (struct ether_header) && 1931 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1932 continue; 1933 1934 eh = mtod(m0, struct ether_header *); 1935 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1936 if (ni == NULL) { 1937 m_freem(m0); 1938 ifp->if_oerrors++; 1939 continue; 1940 } 1941 1942 1943 /* classify mbuf so we can find which tx ring to use */ 1944 if (ieee80211_classify(ic, m0, ni) != 0) { 1945 m_freem(m0); 1946 ieee80211_free_node(ni); 1947 ifp->if_oerrors++; 1948 continue; 1949 } 1950 1951 /* no QoS encapsulation for EAPOL frames */ 1952 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 1953 M_WME_GETAC(m0) : WME_AC_BE; 1954 1955 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1956 /* there is no place left in this ring */ 1957 ifp->if_flags |= IFF_OACTIVE; 1958 break; 1959 } 1960 #if NBPFILTER > 0 1961 if (ifp->if_bpf != NULL) 1962 bpf_mtap(ifp->if_bpf, m0); 1963 #endif 1964 m0 = ieee80211_encap(ic, m0, ni); 1965 if (m0 == NULL) { 1966 ieee80211_free_node(ni); 1967 ifp->if_oerrors++; 1968 continue; 1969 } 1970 #if NBPFILTER > 0 1971 if (ic->ic_rawbpf != NULL) 1972 bpf_mtap(ic->ic_rawbpf, m0); 1973 #endif 1974 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1975 if (ni != NULL) 1976 ieee80211_free_node(ni); 1977 ifp->if_oerrors++; 1978 break; 1979 } 1980 } 1981 1982 sc->sc_tx_timer = 5; 1983 ifp->if_timer = 1; 1984 } 1985 } 1986 1987 static void 1988 rt2661_watchdog(struct ifnet *ifp) 1989 { 1990 struct rt2661_softc *sc = ifp->if_softc; 1991 1992 ifp->if_timer = 0; 1993 1994 if (sc->sc_tx_timer > 0) { 1995 if (--sc->sc_tx_timer == 0) { 1996 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1997 rt2661_init(ifp); 1998 ifp->if_oerrors++; 1999 return; 2000 } 2001 ifp->if_timer = 1; 2002 } 2003 2004 ieee80211_watchdog(&sc->sc_ic); 2005 } 2006 2007 /* 2008 * This function allows for fast channel switching in monitor mode (used by 2009 * kismet). In IBSS mode, we must explicitly reset the interface to 2010 * generate a new beacon frame. 2011 */ 2012 static int 2013 rt2661_reset(struct ifnet *ifp) 2014 { 2015 struct rt2661_softc *sc = ifp->if_softc; 2016 struct ieee80211com *ic = &sc->sc_ic; 2017 2018 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2019 return ENETRESET; 2020 2021 rt2661_set_chan(sc, ic->ic_curchan); 2022 2023 return 0; 2024 } 2025 2026 static int 2027 rt2661_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2028 { 2029 struct rt2661_softc *sc = ifp->if_softc; 2030 struct ieee80211com *ic = &sc->sc_ic; 2031 int s, error = 0; 2032 2033 s = splnet(); 2034 2035 switch (cmd) { 2036 case SIOCSIFFLAGS: 2037 if (ifp->if_flags & IFF_UP) { 2038 if (ifp->if_flags & IFF_RUNNING) 2039 rt2661_update_promisc(sc); 2040 else 2041 rt2661_init(ifp); 2042 } else { 2043 if (ifp->if_flags & IFF_RUNNING) 2044 rt2661_stop(ifp, 1); 2045 } 2046 break; 2047 2048 case SIOCADDMULTI: 2049 case SIOCDELMULTI: 2050 /* XXX no h/w multicast filter? --dyoung */ 2051 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2052 error = 0; 2053 break; 2054 2055 case SIOCS80211CHANNEL: 2056 /* 2057 * This allows for fast channel switching in monitor mode 2058 * (used by kismet). In IBSS mode, we must explicitly reset 2059 * the interface to generate a new beacon frame. 2060 */ 2061 error = ieee80211_ioctl(ic, cmd, data); 2062 if (error == ENETRESET && 2063 ic->ic_opmode == IEEE80211_M_MONITOR) { 2064 rt2661_set_chan(sc, ic->ic_ibss_chan); 2065 error = 0; 2066 } 2067 break; 2068 2069 default: 2070 error = ieee80211_ioctl(ic, cmd, data); 2071 2072 } 2073 2074 if (error == ENETRESET) { 2075 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2076 (IFF_UP | IFF_RUNNING)) 2077 rt2661_init(ifp); 2078 error = 0; 2079 } 2080 2081 splx(s); 2082 2083 return error; 2084 } 2085 2086 static void 2087 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 2088 { 2089 uint32_t tmp; 2090 int ntries; 2091 2092 for (ntries = 0; ntries < 100; ntries++) { 2093 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2094 break; 2095 DELAY(1); 2096 } 2097 if (ntries == 100) { 2098 printf("%s: could not write to BBP\n", sc->sc_dev.dv_xname); 2099 return; 2100 } 2101 2102 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 2103 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 2104 2105 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 2106 } 2107 2108 static uint8_t 2109 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2110 { 2111 uint32_t val; 2112 int ntries; 2113 2114 for (ntries = 0; ntries < 100; ntries++) { 2115 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2116 break; 2117 DELAY(1); 2118 } 2119 if (ntries == 100) { 2120 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 2121 return 0; 2122 } 2123 2124 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2125 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2126 2127 for (ntries = 0; ntries < 100; ntries++) { 2128 val = RAL_READ(sc, RT2661_PHY_CSR3); 2129 if (!(val & RT2661_BBP_BUSY)) 2130 return val & 0xff; 2131 DELAY(1); 2132 } 2133 2134 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 2135 return 0; 2136 } 2137 2138 static void 2139 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2140 { 2141 uint32_t tmp; 2142 int ntries; 2143 2144 for (ntries = 0; ntries < 100; ntries++) { 2145 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2146 break; 2147 DELAY(1); 2148 } 2149 if (ntries == 100) { 2150 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 2151 return; 2152 } 2153 2154 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2155 (reg & 3); 2156 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2157 2158 /* remember last written value in sc */ 2159 sc->rf_regs[reg] = val; 2160 2161 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2162 } 2163 2164 static int 2165 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2166 { 2167 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2168 return EIO; /* there is already a command pending */ 2169 2170 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2171 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2172 2173 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2174 2175 return 0; 2176 } 2177 2178 static void 2179 rt2661_select_antenna(struct rt2661_softc *sc) 2180 { 2181 uint8_t bbp4, bbp77; 2182 uint32_t tmp; 2183 2184 bbp4 = rt2661_bbp_read(sc, 4); 2185 bbp77 = rt2661_bbp_read(sc, 77); 2186 2187 /* TBD */ 2188 2189 /* make sure Rx is disabled before switching antenna */ 2190 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2191 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2192 2193 rt2661_bbp_write(sc, 4, bbp4); 2194 rt2661_bbp_write(sc, 77, bbp77); 2195 2196 /* restore Rx filter */ 2197 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2198 } 2199 2200 /* 2201 * Enable multi-rate retries for frames sent at OFDM rates. 2202 * In 802.11b/g mode, allow fallback to CCK rates. 2203 */ 2204 static void 2205 rt2661_enable_mrr(struct rt2661_softc *sc) 2206 { 2207 struct ieee80211com *ic = &sc->sc_ic; 2208 uint32_t tmp; 2209 2210 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2211 2212 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2213 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2214 tmp |= RT2661_MRR_CCK_FALLBACK; 2215 tmp |= RT2661_MRR_ENABLED; 2216 2217 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2218 } 2219 2220 static void 2221 rt2661_set_txpreamble(struct rt2661_softc *sc) 2222 { 2223 uint32_t tmp; 2224 2225 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2226 2227 tmp &= ~RT2661_SHORT_PREAMBLE; 2228 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2229 tmp |= RT2661_SHORT_PREAMBLE; 2230 2231 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2232 } 2233 2234 static void 2235 rt2661_set_basicrates(struct rt2661_softc *sc, 2236 const struct ieee80211_rateset *rs) 2237 { 2238 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2239 uint32_t mask = 0; 2240 uint8_t rate; 2241 int i, j; 2242 2243 for (i = 0; i < rs->rs_nrates; i++) { 2244 rate = rs->rs_rates[i]; 2245 2246 if (!(rate & IEEE80211_RATE_BASIC)) 2247 continue; 2248 2249 /* 2250 * Find h/w rate index. We know it exists because the rate 2251 * set has already been negotiated. 2252 */ 2253 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++); 2254 2255 mask |= 1 << j; 2256 } 2257 2258 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2259 2260 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2261 #undef RV 2262 } 2263 2264 /* 2265 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2266 * driver. 2267 */ 2268 static void 2269 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2270 { 2271 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2272 uint32_t tmp; 2273 2274 /* update all BBP registers that depend on the band */ 2275 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2276 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2277 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2278 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2279 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2280 } 2281 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2282 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2283 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2284 } 2285 2286 rt2661_bbp_write(sc, 17, bbp17); 2287 rt2661_bbp_write(sc, 96, bbp96); 2288 rt2661_bbp_write(sc, 104, bbp104); 2289 2290 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2291 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2292 rt2661_bbp_write(sc, 75, 0x80); 2293 rt2661_bbp_write(sc, 86, 0x80); 2294 rt2661_bbp_write(sc, 88, 0x80); 2295 } 2296 2297 rt2661_bbp_write(sc, 35, bbp35); 2298 rt2661_bbp_write(sc, 97, bbp97); 2299 rt2661_bbp_write(sc, 98, bbp98); 2300 2301 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2302 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2303 if (IEEE80211_IS_CHAN_2GHZ(c)) 2304 tmp |= RT2661_PA_PE_2GHZ; 2305 else 2306 tmp |= RT2661_PA_PE_5GHZ; 2307 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2308 } 2309 2310 static void 2311 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2312 { 2313 struct ieee80211com *ic = &sc->sc_ic; 2314 const struct rfprog *rfprog; 2315 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2316 int8_t power; 2317 u_int i, chan; 2318 2319 chan = ieee80211_chan2ieee(ic, c); 2320 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2321 return; 2322 2323 /* select the appropriate RF settings based on what EEPROM says */ 2324 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2325 2326 /* find the settings for this channel (we know it exists) */ 2327 for (i = 0; rfprog[i].chan != chan; i++); 2328 2329 power = sc->txpow[i]; 2330 if (power < 0) { 2331 bbp94 += power; 2332 power = 0; 2333 } else if (power > 31) { 2334 bbp94 += power - 31; 2335 power = 31; 2336 } 2337 2338 /* 2339 * If we are switching from the 2GHz band to the 5GHz band or 2340 * vice-versa, BBP registers need to be reprogrammed. 2341 */ 2342 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2343 rt2661_select_band(sc, c); 2344 rt2661_select_antenna(sc); 2345 } 2346 sc->sc_curchan = c; 2347 2348 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2349 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2350 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2351 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2352 2353 DELAY(200); 2354 2355 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2356 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2357 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2358 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2359 2360 DELAY(200); 2361 2362 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2363 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2364 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2365 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2366 2367 /* enable smart mode for MIMO-capable RFs */ 2368 bbp3 = rt2661_bbp_read(sc, 3); 2369 2370 bbp3 &= ~RT2661_SMART_MODE; 2371 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2372 bbp3 |= RT2661_SMART_MODE; 2373 2374 rt2661_bbp_write(sc, 3, bbp3); 2375 2376 if (bbp94 != RT2661_BBPR94_DEFAULT) 2377 rt2661_bbp_write(sc, 94, bbp94); 2378 2379 /* 5GHz radio needs a 1ms delay here */ 2380 if (IEEE80211_IS_CHAN_5GHZ(c)) 2381 DELAY(1000); 2382 } 2383 2384 static void 2385 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2386 { 2387 uint32_t tmp; 2388 2389 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2390 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2391 2392 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2393 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2394 } 2395 2396 static void 2397 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2398 { 2399 uint32_t tmp; 2400 2401 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2402 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2403 2404 tmp = addr[4] | addr[5] << 8; 2405 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2406 } 2407 2408 static void 2409 rt2661_update_promisc(struct rt2661_softc *sc) 2410 { 2411 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2412 uint32_t tmp; 2413 2414 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2415 2416 tmp &= ~RT2661_DROP_NOT_TO_ME; 2417 if (!(ifp->if_flags & IFF_PROMISC)) 2418 tmp |= RT2661_DROP_NOT_TO_ME; 2419 2420 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2421 2422 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2423 "entering" : "leaving")); 2424 } 2425 2426 #if 0 2427 /* 2428 * Update QoS (802.11e) settings for each h/w Tx ring. 2429 */ 2430 static int 2431 rt2661_wme_update(struct ieee80211com *ic) 2432 { 2433 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2434 const struct wmeParams *wmep; 2435 2436 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2437 2438 /* XXX: not sure about shifts. */ 2439 /* XXX: the reference driver plays with AC_VI settings too. */ 2440 2441 /* update TxOp */ 2442 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2443 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2444 wmep[WME_AC_BK].wmep_txopLimit); 2445 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2446 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2447 wmep[WME_AC_VO].wmep_txopLimit); 2448 2449 /* update CWmin */ 2450 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2451 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2452 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2453 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2454 wmep[WME_AC_VO].wmep_logcwmin); 2455 2456 /* update CWmax */ 2457 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2458 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2459 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2460 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2461 wmep[WME_AC_VO].wmep_logcwmax); 2462 2463 /* update Aifsn */ 2464 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2465 wmep[WME_AC_BE].wmep_aifsn << 12 | 2466 wmep[WME_AC_BK].wmep_aifsn << 8 | 2467 wmep[WME_AC_VI].wmep_aifsn << 4 | 2468 wmep[WME_AC_VO].wmep_aifsn); 2469 2470 return 0; 2471 } 2472 #endif 2473 2474 static void 2475 rt2661_update_slot(struct ifnet *ifp) 2476 { 2477 struct rt2661_softc *sc = ifp->if_softc; 2478 struct ieee80211com *ic = &sc->sc_ic; 2479 uint8_t slottime; 2480 uint32_t tmp; 2481 2482 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2483 2484 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2485 tmp = (tmp & ~0xff) | slottime; 2486 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2487 } 2488 2489 static const char * 2490 rt2661_get_rf(int rev) 2491 { 2492 switch (rev) { 2493 case RT2661_RF_5225: return "RT5225"; 2494 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2495 case RT2661_RF_2527: return "RT2527"; 2496 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2497 default: return "unknown"; 2498 } 2499 } 2500 2501 static void 2502 rt2661_read_eeprom(struct rt2661_softc *sc) 2503 { 2504 struct ieee80211com *ic = &sc->sc_ic; 2505 uint16_t val; 2506 int i; 2507 2508 /* read MAC address */ 2509 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2510 ic->ic_myaddr[0] = val & 0xff; 2511 ic->ic_myaddr[1] = val >> 8; 2512 2513 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2514 ic->ic_myaddr[2] = val & 0xff; 2515 ic->ic_myaddr[3] = val >> 8; 2516 2517 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2518 ic->ic_myaddr[4] = val & 0xff; 2519 ic->ic_myaddr[5] = val >> 8; 2520 2521 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2522 /* XXX: test if different from 0xffff? */ 2523 sc->rf_rev = (val >> 11) & 0x1f; 2524 sc->hw_radio = (val >> 10) & 0x1; 2525 sc->rx_ant = (val >> 4) & 0x3; 2526 sc->tx_ant = (val >> 2) & 0x3; 2527 sc->nb_ant = val & 0x3; 2528 2529 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2530 2531 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2532 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2533 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2534 2535 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2536 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2537 2538 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2539 if ((val & 0xff) != 0xff) 2540 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2541 2542 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2543 if ((val & 0xff) != 0xff) 2544 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2545 2546 /* adjust RSSI correction for external low-noise amplifier */ 2547 if (sc->ext_2ghz_lna) 2548 sc->rssi_2ghz_corr -= 14; 2549 if (sc->ext_5ghz_lna) 2550 sc->rssi_5ghz_corr -= 14; 2551 2552 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2553 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2554 2555 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2556 if ((val >> 8) != 0xff) 2557 sc->rfprog = (val >> 8) & 0x3; 2558 if ((val & 0xff) != 0xff) 2559 sc->rffreq = val & 0xff; 2560 2561 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2562 2563 /* read Tx power for all a/b/g channels */ 2564 for (i = 0; i < 19; i++) { 2565 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2566 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2567 DPRINTF(("Channel=%d Tx power=%d\n", 2568 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2569 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2570 DPRINTF(("Channel=%d Tx power=%d\n", 2571 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2572 } 2573 2574 /* read vendor-specific BBP values */ 2575 for (i = 0; i < 16; i++) { 2576 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2577 if (val == 0 || val == 0xffff) 2578 continue; /* skip invalid entries */ 2579 sc->bbp_prom[i].reg = val >> 8; 2580 sc->bbp_prom[i].val = val & 0xff; 2581 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2582 sc->bbp_prom[i].val)); 2583 } 2584 } 2585 2586 static int 2587 rt2661_bbp_init(struct rt2661_softc *sc) 2588 { 2589 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2590 int i, ntries; 2591 uint8_t val; 2592 2593 /* wait for BBP to be ready */ 2594 for (ntries = 0; ntries < 100; ntries++) { 2595 val = rt2661_bbp_read(sc, 0); 2596 if (val != 0 && val != 0xff) 2597 break; 2598 DELAY(100); 2599 } 2600 if (ntries == 100) { 2601 printf("%s: timeout waiting for BBP\n", sc->sc_dev.dv_xname); 2602 return EIO; 2603 } 2604 2605 /* initialize BBP registers to default values */ 2606 for (i = 0; i < N(rt2661_def_bbp); i++) { 2607 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2608 rt2661_def_bbp[i].val); 2609 } 2610 2611 /* write vendor-specific BBP values (from EEPROM) */ 2612 for (i = 0; i < 16; i++) { 2613 if (sc->bbp_prom[i].reg == 0) 2614 continue; 2615 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2616 } 2617 2618 return 0; 2619 #undef N 2620 } 2621 2622 static int 2623 rt2661_init(struct ifnet *ifp) 2624 { 2625 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2626 struct rt2661_softc *sc = ifp->if_softc; 2627 struct ieee80211com *ic = &sc->sc_ic; 2628 const char *name = NULL; /* make lint happy */ 2629 uint8_t *ucode; 2630 size_t size; 2631 uint32_t tmp, star[3]; 2632 int i, ntries; 2633 firmware_handle_t fh; 2634 2635 /* for CardBus, power on the socket */ 2636 if (!(sc->sc_flags & RT2661_ENABLED)) { 2637 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2638 printf("%s: could not enable device\n", 2639 sc->sc_dev.dv_xname); 2640 return EIO; 2641 } 2642 sc->sc_flags |= RT2661_ENABLED; 2643 } 2644 2645 rt2661_stop(ifp, 0); 2646 2647 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2648 switch (sc->sc_id) { 2649 case PCI_PRODUCT_RALINK_RT2561: 2650 name = "ral-rt2561"; 2651 break; 2652 case PCI_PRODUCT_RALINK_RT2561S: 2653 name = "ral-rt2561s"; 2654 break; 2655 case PCI_PRODUCT_RALINK_RT2661: 2656 name = "ral-rt2661"; 2657 break; 2658 } 2659 2660 if (firmware_open("ral", name, &fh) != 0) { 2661 printf("%s: could not open microcode %s\n", 2662 sc->sc_dev.dv_xname, name); 2663 rt2661_stop(ifp, 1); 2664 return EIO; 2665 } 2666 2667 size = firmware_get_size(fh); 2668 if (!(ucode = firmware_malloc(size))) { 2669 printf("%s: could not alloc microcode memory\n", 2670 sc->sc_dev.dv_xname); 2671 firmware_close(fh); 2672 rt2661_stop(ifp, 1); 2673 return ENOMEM; 2674 } 2675 2676 if (firmware_read(fh, 0, ucode, size) != 0) { 2677 printf("%s: could not read microcode %s\n", 2678 sc->sc_dev.dv_xname, name); 2679 firmware_free(ucode, 0); 2680 firmware_close(fh); 2681 rt2661_stop(ifp, 1); 2682 return EIO; 2683 } 2684 2685 if (rt2661_load_microcode(sc, ucode, size) != 0) { 2686 printf("%s: could not load 8051 microcode\n", 2687 sc->sc_dev.dv_xname); 2688 firmware_free(ucode, 0); 2689 firmware_close(fh); 2690 rt2661_stop(ifp, 1); 2691 return EIO; 2692 } 2693 2694 firmware_free(ucode, 0); 2695 firmware_close(fh); 2696 sc->sc_flags |= RT2661_FWLOADED; 2697 } 2698 2699 /* initialize Tx rings */ 2700 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2701 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2702 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2703 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2704 2705 /* initialize Mgt ring */ 2706 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2707 2708 /* initialize Rx ring */ 2709 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2710 2711 /* initialize Tx rings sizes */ 2712 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2713 RT2661_TX_RING_COUNT << 24 | 2714 RT2661_TX_RING_COUNT << 16 | 2715 RT2661_TX_RING_COUNT << 8 | 2716 RT2661_TX_RING_COUNT); 2717 2718 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2719 RT2661_TX_DESC_WSIZE << 16 | 2720 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2721 RT2661_MGT_RING_COUNT); 2722 2723 /* initialize Rx rings */ 2724 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2725 RT2661_RX_DESC_BACK << 16 | 2726 RT2661_RX_DESC_WSIZE << 8 | 2727 RT2661_RX_RING_COUNT); 2728 2729 /* XXX: some magic here */ 2730 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2731 2732 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2733 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2734 2735 /* load base address of Rx ring */ 2736 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2737 2738 /* initialize MAC registers to default values */ 2739 for (i = 0; i < N(rt2661_def_mac); i++) 2740 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2741 2742 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2743 rt2661_set_macaddr(sc, ic->ic_myaddr); 2744 2745 /* set host ready */ 2746 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2747 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2748 2749 /* wait for BBP/RF to wakeup */ 2750 for (ntries = 0; ntries < 1000; ntries++) { 2751 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2752 break; 2753 DELAY(1000); 2754 } 2755 if (ntries == 1000) { 2756 printf("timeout waiting for BBP/RF to wakeup\n"); 2757 rt2661_stop(ifp, 1); 2758 return EIO; 2759 } 2760 2761 if (rt2661_bbp_init(sc) != 0) { 2762 rt2661_stop(ifp, 1); 2763 return EIO; 2764 } 2765 2766 /* select default channel */ 2767 sc->sc_curchan = ic->ic_curchan; 2768 rt2661_select_band(sc, sc->sc_curchan); 2769 rt2661_select_antenna(sc); 2770 rt2661_set_chan(sc, sc->sc_curchan); 2771 2772 /* update Rx filter */ 2773 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2774 2775 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2776 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2777 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2778 RT2661_DROP_ACKCTS; 2779 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2780 tmp |= RT2661_DROP_TODS; 2781 if (!(ifp->if_flags & IFF_PROMISC)) 2782 tmp |= RT2661_DROP_NOT_TO_ME; 2783 } 2784 2785 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2786 2787 /* clear STA registers */ 2788 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, star, N(star)); 2789 2790 /* initialize ASIC */ 2791 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2792 2793 /* clear any pending interrupt */ 2794 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2795 2796 /* enable interrupts */ 2797 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2798 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2799 2800 /* kick Rx */ 2801 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2802 2803 ifp->if_flags &= ~IFF_OACTIVE; 2804 ifp->if_flags |= IFF_RUNNING; 2805 2806 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2807 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2808 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2809 } else 2810 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2811 2812 return 0; 2813 #undef N 2814 } 2815 2816 static void 2817 rt2661_stop(struct ifnet *ifp, int disable) 2818 { 2819 struct rt2661_softc *sc = ifp->if_softc; 2820 struct ieee80211com *ic = &sc->sc_ic; 2821 uint32_t tmp; 2822 2823 sc->sc_tx_timer = 0; 2824 ifp->if_timer = 0; 2825 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2826 2827 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2828 2829 /* abort Tx (for all 5 Tx rings) */ 2830 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2831 2832 /* disable Rx (value remains after reset!) */ 2833 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2834 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2835 2836 /* reset ASIC */ 2837 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2838 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2839 2840 /* disable interrupts */ 2841 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2842 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2843 2844 /* clear any pending interrupt */ 2845 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2846 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2847 2848 /* reset Tx and Rx rings */ 2849 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2850 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2851 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2852 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2853 rt2661_reset_tx_ring(sc, &sc->mgtq); 2854 rt2661_reset_rx_ring(sc, &sc->rxq); 2855 2856 /* for CardBus, power down the socket */ 2857 if (disable && sc->sc_disable != NULL) { 2858 if (sc->sc_flags & RT2661_ENABLED) { 2859 (*sc->sc_disable)(sc); 2860 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2861 } 2862 } 2863 } 2864 2865 static int 2866 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2867 { 2868 int ntries; 2869 2870 /* reset 8051 */ 2871 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2872 2873 /* cancel any pending Host to MCU command */ 2874 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2875 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2876 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2877 2878 /* write 8051's microcode */ 2879 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2880 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2881 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2882 2883 /* kick 8051's ass */ 2884 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2885 2886 /* wait for 8051 to initialize */ 2887 for (ntries = 0; ntries < 500; ntries++) { 2888 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2889 break; 2890 DELAY(100); 2891 } 2892 if (ntries == 500) { 2893 printf("timeout waiting for MCU to initialize\n"); 2894 return EIO; 2895 } 2896 return 0; 2897 } 2898 2899 #ifdef notyet 2900 /* 2901 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2902 * false CCA count. This function is called periodically (every seconds) when 2903 * in the RUN state. Values taken from the reference driver. 2904 */ 2905 static void 2906 rt2661_rx_tune(struct rt2661_softc *sc) 2907 { 2908 uint8_t bbp17; 2909 uint16_t cca; 2910 int lo, hi, dbm; 2911 2912 /* 2913 * Tuning range depends on operating band and on the presence of an 2914 * external low-noise amplifier. 2915 */ 2916 lo = 0x20; 2917 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2918 lo += 0x08; 2919 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2920 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2921 lo += 0x10; 2922 hi = lo + 0x20; 2923 2924 /* retrieve false CCA count since last call (clear on read) */ 2925 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2926 2927 if (dbm >= -35) { 2928 bbp17 = 0x60; 2929 } else if (dbm >= -58) { 2930 bbp17 = hi; 2931 } else if (dbm >= -66) { 2932 bbp17 = lo + 0x10; 2933 } else if (dbm >= -74) { 2934 bbp17 = lo + 0x08; 2935 } else { 2936 /* RSSI < -74dBm, tune using false CCA count */ 2937 2938 bbp17 = sc->bbp17; /* current value */ 2939 2940 hi -= 2 * (-74 - dbm); 2941 if (hi < lo) 2942 hi = lo; 2943 2944 if (bbp17 > hi) { 2945 bbp17 = hi; 2946 2947 } else if (cca > 512) { 2948 if (++bbp17 > hi) 2949 bbp17 = hi; 2950 } else if (cca < 100) { 2951 if (--bbp17 < lo) 2952 bbp17 = lo; 2953 } 2954 } 2955 2956 if (bbp17 != sc->bbp17) { 2957 rt2661_bbp_write(sc, 17, bbp17); 2958 sc->bbp17 = bbp17; 2959 } 2960 } 2961 2962 /* 2963 * Enter/Leave radar detection mode. 2964 * This is for 802.11h additional regulatory domains. 2965 */ 2966 static void 2967 rt2661_radar_start(struct rt2661_softc *sc) 2968 { 2969 uint32_t tmp; 2970 2971 /* disable Rx */ 2972 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2973 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2974 2975 rt2661_bbp_write(sc, 82, 0x20); 2976 rt2661_bbp_write(sc, 83, 0x00); 2977 rt2661_bbp_write(sc, 84, 0x40); 2978 2979 /* save current BBP registers values */ 2980 sc->bbp18 = rt2661_bbp_read(sc, 18); 2981 sc->bbp21 = rt2661_bbp_read(sc, 21); 2982 sc->bbp22 = rt2661_bbp_read(sc, 22); 2983 sc->bbp16 = rt2661_bbp_read(sc, 16); 2984 sc->bbp17 = rt2661_bbp_read(sc, 17); 2985 sc->bbp64 = rt2661_bbp_read(sc, 64); 2986 2987 rt2661_bbp_write(sc, 18, 0xff); 2988 rt2661_bbp_write(sc, 21, 0x3f); 2989 rt2661_bbp_write(sc, 22, 0x3f); 2990 rt2661_bbp_write(sc, 16, 0xbd); 2991 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2992 rt2661_bbp_write(sc, 64, 0x21); 2993 2994 /* restore Rx filter */ 2995 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2996 } 2997 2998 static int 2999 rt2661_radar_stop(struct rt2661_softc *sc) 3000 { 3001 uint8_t bbp66; 3002 3003 /* read radar detection result */ 3004 bbp66 = rt2661_bbp_read(sc, 66); 3005 3006 /* restore BBP registers values */ 3007 rt2661_bbp_write(sc, 16, sc->bbp16); 3008 rt2661_bbp_write(sc, 17, sc->bbp17); 3009 rt2661_bbp_write(sc, 18, sc->bbp18); 3010 rt2661_bbp_write(sc, 21, sc->bbp21); 3011 rt2661_bbp_write(sc, 22, sc->bbp22); 3012 rt2661_bbp_write(sc, 64, sc->bbp64); 3013 3014 return bbp66 == 1; 3015 } 3016 #endif 3017 3018 static int 3019 rt2661_prepare_beacon(struct rt2661_softc *sc) 3020 { 3021 struct ieee80211com *ic = &sc->sc_ic; 3022 struct rt2661_tx_desc desc; 3023 struct mbuf *m0; 3024 struct ieee80211_beacon_offsets bo; 3025 int rate; 3026 3027 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 3028 3029 if (m0 == NULL) { 3030 printf("%s: could not allocate beacon frame\n", 3031 sc->sc_dev.dv_xname); 3032 return ENOBUFS; 3033 } 3034 3035 /* send beacons at the lowest available rate */ 3036 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2; 3037 3038 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 3039 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 3040 3041 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 3042 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 3043 3044 /* copy beacon header and payload into NIC memory */ 3045 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 3046 mtod(m0, uint8_t *), m0->m_pkthdr.len); 3047 3048 m_freem(m0); 3049 3050 return 0; 3051 } 3052 3053 /* 3054 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 3055 * and HostAP operating modes. 3056 */ 3057 static void 3058 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 3059 { 3060 struct ieee80211com *ic = &sc->sc_ic; 3061 uint32_t tmp; 3062 3063 if (ic->ic_opmode != IEEE80211_M_STA) { 3064 /* 3065 * Change default 16ms TBTT adjustment to 8ms. 3066 * Must be done before enabling beacon generation. 3067 */ 3068 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 3069 } 3070 3071 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 3072 3073 /* set beacon interval (in 1/16ms unit) */ 3074 tmp |= ic->ic_bss->ni_intval * 16; 3075 3076 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 3077 if (ic->ic_opmode == IEEE80211_M_STA) 3078 tmp |= RT2661_TSF_MODE(1); 3079 else 3080 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 3081 3082 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 3083 } 3084 3085 /* 3086 * Retrieve the "Received Signal Strength Indicator" from the raw values 3087 * contained in Rx descriptors. The computation depends on which band the 3088 * frame was received. Correction values taken from the reference driver. 3089 */ 3090 static int 3091 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 3092 { 3093 int lna, agc, rssi; 3094 3095 lna = (raw >> 5) & 0x3; 3096 agc = raw & 0x1f; 3097 3098 rssi = 2 * agc; 3099 3100 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3101 rssi += sc->rssi_2ghz_corr; 3102 3103 if (lna == 1) 3104 rssi -= 64; 3105 else if (lna == 2) 3106 rssi -= 74; 3107 else if (lna == 3) 3108 rssi -= 90; 3109 } else { 3110 rssi += sc->rssi_5ghz_corr; 3111 3112 if (lna == 1) 3113 rssi -= 64; 3114 else if (lna == 2) 3115 rssi -= 86; 3116 else if (lna == 3) 3117 rssi -= 100; 3118 } 3119 return rssi; 3120 } 3121
Indexes created Mon Sep 22 10:09:38 GMT 2025