rt2661.c revision 1.21
1 /* $NetBSD: rt2661.c,v 1.21 2007/12/09 20:27:58 jmcneill Exp $ */ 2 /* $OpenBSD: rt2661.c,v 1.17 2006/05/01 08:41:11 damien Exp $ */ 3 /* $FreeBSD: rt2560.c,v 1.5 2006/06/02 19:59:31 csjp Exp $ */ 4 5 /*- 6 * Copyright (c) 2006 7 * Damien Bergamini <damien.bergamini (at) free.fr> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2661.c,v 1.21 2007/12/09 20:27:58 jmcneill Exp $"); 29 30 #include "bpfilter.h" 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/device.h> 43 44 #include <sys/bus.h> 45 #include <machine/endian.h> 46 #include <sys/intr.h> 47 48 #if NBPFILTER > 0 49 #include <net/bpf.h> 50 #endif 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_ether.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 63 #include <net80211/ieee80211_var.h> 64 #include <net80211/ieee80211_rssadapt.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #include <dev/ic/rt2661reg.h> 68 #include <dev/ic/rt2661var.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <dev/firmload.h> 75 76 #ifdef RAL_DEBUG 77 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 78 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 79 int rt2661_debug = 0; 80 #else 81 #define DPRINTF(x) 82 #define DPRINTFN(n, x) 83 #endif 84 85 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 86 struct rt2661_tx_ring *, int); 87 static void rt2661_reset_tx_ring(struct rt2661_softc *, 88 struct rt2661_tx_ring *); 89 static void rt2661_free_tx_ring(struct rt2661_softc *, 90 struct rt2661_tx_ring *); 91 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 92 struct rt2661_rx_ring *, int); 93 static void rt2661_reset_rx_ring(struct rt2661_softc *, 94 struct rt2661_rx_ring *); 95 static void rt2661_free_rx_ring(struct rt2661_softc *, 96 struct rt2661_rx_ring *); 97 static struct ieee80211_node * 98 rt2661_node_alloc(struct ieee80211_node_table *); 99 static int rt2661_media_change(struct ifnet *); 100 static void rt2661_next_scan(void *); 101 static void rt2661_iter_func(void *, struct ieee80211_node *); 102 static void rt2661_rssadapt_updatestats(void *); 103 static int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 104 int); 105 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 106 static void rt2661_tx_intr(struct rt2661_softc *); 107 static void rt2661_tx_dma_intr(struct rt2661_softc *, 108 struct rt2661_tx_ring *); 109 static void rt2661_rx_intr(struct rt2661_softc *); 110 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 111 static void rt2661_mcu_wakeup(struct rt2661_softc *); 112 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 113 int rt2661_intr(void *); 114 #if NBPFILTER > 0 115 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 116 #endif 117 static int rt2661_ack_rate(struct ieee80211com *, int); 118 static uint16_t rt2661_txtime(int, int, uint32_t); 119 static uint8_t rt2661_plcp_signal(int); 120 static void rt2661_setup_tx_desc(struct rt2661_softc *, 121 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 122 const bus_dma_segment_t *, int, int); 123 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 124 struct ieee80211_node *); 125 static struct mbuf * 126 rt2661_get_rts(struct rt2661_softc *, 127 struct ieee80211_frame *, uint16_t); 128 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 129 struct ieee80211_node *, int); 130 static void rt2661_start(struct ifnet *); 131 static void rt2661_watchdog(struct ifnet *); 132 static int rt2661_reset(struct ifnet *); 133 static int rt2661_ioctl(struct ifnet *, u_long, void *); 134 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 135 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 136 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 137 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 138 static void rt2661_select_antenna(struct rt2661_softc *); 139 static void rt2661_enable_mrr(struct rt2661_softc *); 140 static void rt2661_set_txpreamble(struct rt2661_softc *); 141 static void rt2661_set_basicrates(struct rt2661_softc *, 142 const struct ieee80211_rateset *); 143 static void rt2661_select_band(struct rt2661_softc *, 144 struct ieee80211_channel *); 145 static void rt2661_set_chan(struct rt2661_softc *, 146 struct ieee80211_channel *); 147 static void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 148 static void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 149 static void rt2661_update_promisc(struct rt2661_softc *); 150 #if 0 151 static int rt2661_wme_update(struct ieee80211com *); 152 #endif 153 154 static void rt2661_update_slot(struct ifnet *); 155 static const char * 156 rt2661_get_rf(int); 157 static void rt2661_read_eeprom(struct rt2661_softc *); 158 static int rt2661_bbp_init(struct rt2661_softc *); 159 static int rt2661_init(struct ifnet *); 160 static void rt2661_stop(struct ifnet *, int); 161 static int rt2661_load_microcode(struct rt2661_softc *, const uint8_t *, 162 int); 163 #ifdef notyet 164 static void rt2661_rx_tune(struct rt2661_softc *); 165 static void rt2661_radar_start(struct rt2661_softc *); 166 static int rt2661_radar_stop(struct rt2661_softc *); 167 #endif 168 static int rt2661_prepare_beacon(struct rt2661_softc *); 169 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 170 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 171 172 /* 173 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 174 */ 175 static const struct ieee80211_rateset rt2661_rateset_11a = 176 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 177 178 static const struct ieee80211_rateset rt2661_rateset_11b = 179 { 4, { 2, 4, 11, 22 } }; 180 181 static const struct ieee80211_rateset rt2661_rateset_11g = 182 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 183 184 /* 185 * Default values for MAC registers; values taken from the reference driver. 186 */ 187 static const struct { 188 uint32_t reg; 189 uint32_t val; 190 } rt2661_def_mac[] = { 191 { RT2661_TXRX_CSR0, 0x0000b032 }, 192 { RT2661_TXRX_CSR1, 0x9eb39eb3 }, 193 { RT2661_TXRX_CSR2, 0x8a8b8c8d }, 194 { RT2661_TXRX_CSR3, 0x00858687 }, 195 { RT2661_TXRX_CSR7, 0x2e31353b }, 196 { RT2661_TXRX_CSR8, 0x2a2a2a2c }, 197 { RT2661_TXRX_CSR15, 0x0000000f }, 198 { RT2661_MAC_CSR6, 0x00000fff }, 199 { RT2661_MAC_CSR8, 0x016c030a }, 200 { RT2661_MAC_CSR10, 0x00000718 }, 201 { RT2661_MAC_CSR12, 0x00000004 }, 202 { RT2661_MAC_CSR13, 0x0000e000 }, 203 { RT2661_SEC_CSR0, 0x00000000 }, 204 { RT2661_SEC_CSR1, 0x00000000 }, 205 { RT2661_SEC_CSR5, 0x00000000 }, 206 { RT2661_PHY_CSR1, 0x000023b0 }, 207 { RT2661_PHY_CSR5, 0x060a100c }, 208 { RT2661_PHY_CSR6, 0x00080606 }, 209 { RT2661_PHY_CSR7, 0x00000a08 }, 210 { RT2661_PCI_CFG_CSR, 0x3cca4808 }, 211 { RT2661_AIFSN_CSR, 0x00002273 }, 212 { RT2661_CWMIN_CSR, 0x00002344 }, 213 { RT2661_CWMAX_CSR, 0x000034aa }, 214 { RT2661_TEST_MODE_CSR, 0x00000200 }, 215 { RT2661_M2H_CMD_DONE_CSR, 0xffffffff } 216 }; 217 218 /* 219 * Default values for BBP registers; values taken from the reference driver. 220 */ 221 static const struct { 222 uint8_t reg; 223 uint8_t val; 224 } rt2661_def_bbp[] = { 225 { 3, 0x00 }, 226 { 15, 0x30 }, 227 { 17, 0x20 }, 228 { 21, 0xc8 }, 229 { 22, 0x38 }, 230 { 23, 0x06 }, 231 { 24, 0xfe }, 232 { 25, 0x0a }, 233 { 26, 0x0d }, 234 { 34, 0x12 }, 235 { 37, 0x07 }, 236 { 39, 0xf8 }, 237 { 41, 0x60 }, 238 { 53, 0x10 }, 239 { 54, 0x18 }, 240 { 60, 0x10 }, 241 { 61, 0x04 }, 242 { 62, 0x04 }, 243 { 75, 0xfe }, 244 { 86, 0xfe }, 245 { 88, 0xfe }, 246 { 90, 0x0f }, 247 { 99, 0x00 }, 248 { 102, 0x16 }, 249 { 107, 0x04 } 250 }; 251 252 /* 253 * Default settings for RF registers; values taken from the reference driver. 254 */ 255 static const struct rfprog { 256 uint8_t chan; 257 uint32_t r1; 258 uint32_t r2; 259 uint32_t r3; 260 uint32_t r4; 261 } rt2661_rf5225_1[] = { 262 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, 263 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, 264 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, 265 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, 266 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, 267 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, 268 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, 269 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, 270 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, 271 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, 272 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, 273 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, 274 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, 275 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, 276 277 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, 278 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, 279 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, 280 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, 281 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, 282 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, 283 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, 284 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, 285 286 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, 287 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, 288 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, 289 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, 290 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, 291 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, 292 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, 293 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, 294 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, 295 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, 296 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, 297 298 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, 299 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, 300 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, 301 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, 302 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } 303 304 }, rt2661_rf5225_2[] = { 305 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, 306 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, 307 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, 308 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, 309 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, 310 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, 311 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, 312 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, 313 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, 314 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, 315 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, 316 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, 317 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, 318 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, 319 320 { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, 321 { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, 322 { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, 323 { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, 324 { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, 325 { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, 326 { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, 327 { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, 328 329 { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, 330 { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, 331 { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, 332 { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, 333 { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, 334 { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, 335 { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, 336 { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, 337 { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, 338 { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, 339 { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, 340 341 { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, 342 { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, 343 { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, 344 { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, 345 { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 } 346 }; 347 348 int 349 rt2661_attach(void *xsc, int id) 350 { 351 struct rt2661_softc *sc = xsc; 352 struct ieee80211com *ic = &sc->sc_ic; 353 struct ifnet *ifp = &sc->sc_if; 354 uint32_t val; 355 int error, i, ntries; 356 357 sc->sc_id = id; 358 359 callout_init(&sc->scan_ch, 0); 360 callout_init(&sc->rssadapt_ch, 0); 361 362 /* wait for NIC to initialize */ 363 for (ntries = 0; ntries < 1000; ntries++) { 364 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 365 break; 366 DELAY(1000); 367 } 368 if (ntries == 1000) { 369 aprint_error("%s: timeout waiting for NIC to initialize\n", 370 sc->sc_dev.dv_xname); 371 return EIO; 372 } 373 374 /* retrieve RF rev. no and various other things from EEPROM */ 375 rt2661_read_eeprom(sc); 376 aprint_normal("%s: 802.11 address %s\n", sc->sc_dev.dv_xname, 377 ether_sprintf(ic->ic_myaddr)); 378 379 aprint_normal("%s: MAC/BBP RT%X, RF %s\n", sc->sc_dev.dv_xname, val, 380 rt2661_get_rf(sc->rf_rev)); 381 382 /* 383 * Allocate Tx and Rx rings. 384 */ 385 error = rt2661_alloc_tx_ring(sc, &sc->txq[0], RT2661_TX_RING_COUNT); 386 if (error != 0) { 387 aprint_error("%s: could not allocate Tx ring 0\n", 388 sc->sc_dev.dv_xname); 389 goto fail1; 390 } 391 392 error = rt2661_alloc_tx_ring(sc, &sc->txq[1], RT2661_TX_RING_COUNT); 393 if (error != 0) { 394 aprint_error("%s: could not allocate Tx ring 1\n", 395 sc->sc_dev.dv_xname); 396 goto fail2; 397 } 398 399 error = rt2661_alloc_tx_ring(sc, &sc->txq[2], RT2661_TX_RING_COUNT); 400 if (error != 0) { 401 aprint_error("%s: could not allocate Tx ring 2\n", 402 sc->sc_dev.dv_xname); 403 goto fail3; 404 } 405 406 error = rt2661_alloc_tx_ring(sc, &sc->txq[3], RT2661_TX_RING_COUNT); 407 if (error != 0) { 408 aprint_error("%s: could not allocate Tx ring 3\n", 409 sc->sc_dev.dv_xname); 410 goto fail4; 411 } 412 413 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 414 if (error != 0) { 415 aprint_error("%s: could not allocate Mgt ring\n", 416 sc->sc_dev.dv_xname); 417 goto fail5; 418 } 419 420 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 421 if (error != 0) { 422 aprint_error("%s: could not allocate Rx ring\n", 423 sc->sc_dev.dv_xname); 424 goto fail6; 425 } 426 427 ifp->if_softc = sc; 428 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 429 ifp->if_init = rt2661_init; 430 ifp->if_stop = rt2661_stop; 431 ifp->if_ioctl = rt2661_ioctl; 432 ifp->if_start = rt2661_start; 433 ifp->if_watchdog = rt2661_watchdog; 434 IFQ_SET_READY(&ifp->if_snd); 435 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 436 437 ic->ic_ifp = ifp; 438 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 439 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 440 ic->ic_state = IEEE80211_S_INIT; 441 442 /* set device capabilities */ 443 ic->ic_caps = 444 IEEE80211_C_IBSS | /* IBSS mode supported */ 445 IEEE80211_C_MONITOR | /* monitor mode supported */ 446 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 447 IEEE80211_C_TXPMGT | /* tx power management */ 448 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 449 IEEE80211_C_SHSLOT | /* short slot time supported */ 450 IEEE80211_C_WPA; /* 802.11i */ 451 452 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 453 /* set supported .11a rates */ 454 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 455 456 /* set supported .11a channels */ 457 for (i = 36; i <= 64; i += 4) { 458 ic->ic_channels[i].ic_freq = 459 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 460 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 461 } 462 for (i = 100; i <= 140; i += 4) { 463 ic->ic_channels[i].ic_freq = 464 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 465 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 466 } 467 for (i = 149; i <= 165; i += 4) { 468 ic->ic_channels[i].ic_freq = 469 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 470 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 471 } 472 } 473 474 /* set supported .11b and .11g rates */ 475 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 476 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 477 478 /* set supported .11b and .11g channels (1 through 14) */ 479 for (i = 1; i <= 14; i++) { 480 ic->ic_channels[i].ic_freq = 481 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 482 ic->ic_channels[i].ic_flags = 483 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 484 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 485 } 486 487 if_attach(ifp); 488 ieee80211_ifattach(ic); 489 ic->ic_node_alloc = rt2661_node_alloc; 490 ic->ic_updateslot = rt2661_update_slot; 491 ic->ic_reset = rt2661_reset; 492 493 /* override state transition machine */ 494 sc->sc_newstate = ic->ic_newstate; 495 ic->ic_newstate = rt2661_newstate; 496 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 497 498 #if NBPFILTER > 0 499 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 500 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 501 502 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 503 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 504 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 505 506 sc->sc_txtap_len = sizeof sc->sc_txtapu; 507 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 508 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 509 #endif 510 511 ieee80211_announce(ic); 512 513 if (!pmf_device_register(&sc->sc_dev, NULL, NULL)) 514 aprint_error_dev(&sc->sc_dev, "couldn't establish power handler\n"); 515 else 516 pmf_class_network_register(&sc->sc_dev, ifp); 517 518 return 0; 519 520 fail6: rt2661_free_tx_ring(sc, &sc->mgtq); 521 fail5: rt2661_free_tx_ring(sc, &sc->txq[3]); 522 fail4: rt2661_free_tx_ring(sc, &sc->txq[2]); 523 fail3: rt2661_free_tx_ring(sc, &sc->txq[1]); 524 fail2: rt2661_free_tx_ring(sc, &sc->txq[0]); 525 fail1: return ENXIO; 526 } 527 528 int 529 rt2661_detach(void *xsc) 530 { 531 struct rt2661_softc *sc = xsc; 532 struct ifnet *ifp = &sc->sc_if; 533 534 callout_stop(&sc->scan_ch); 535 callout_stop(&sc->rssadapt_ch); 536 537 pmf_device_deregister(&sc->sc_dev); 538 539 ieee80211_ifdetach(&sc->sc_ic); 540 if_detach(ifp); 541 542 rt2661_free_tx_ring(sc, &sc->txq[0]); 543 rt2661_free_tx_ring(sc, &sc->txq[1]); 544 rt2661_free_tx_ring(sc, &sc->txq[2]); 545 rt2661_free_tx_ring(sc, &sc->txq[3]); 546 rt2661_free_tx_ring(sc, &sc->mgtq); 547 rt2661_free_rx_ring(sc, &sc->rxq); 548 549 return 0; 550 } 551 552 static int 553 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 554 int count) 555 { 556 int i, nsegs, error; 557 558 ring->count = count; 559 ring->queued = 0; 560 ring->cur = ring->next = ring->stat = 0; 561 562 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 563 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 564 if (error != 0) { 565 aprint_error("%s: could not create desc DMA map\n", 566 sc->sc_dev.dv_xname); 567 goto fail; 568 } 569 570 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 571 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 572 if (error != 0) { 573 aprint_error("%s: could not allocate DMA memory\n", 574 sc->sc_dev.dv_xname); 575 goto fail; 576 } 577 578 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 579 count * RT2661_TX_DESC_SIZE, (void **)&ring->desc, 580 BUS_DMA_NOWAIT); 581 if (error != 0) { 582 aprint_error("%s: could not map desc DMA memory\n", 583 sc->sc_dev.dv_xname); 584 goto fail; 585 } 586 587 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 588 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 589 if (error != 0) { 590 aprint_error("%s: could not load desc DMA map\n", 591 sc->sc_dev.dv_xname); 592 goto fail; 593 } 594 595 memset(ring->desc, 0, count * RT2661_TX_DESC_SIZE); 596 ring->physaddr = ring->map->dm_segs->ds_addr; 597 598 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 599 M_NOWAIT); 600 if (ring->data == NULL) { 601 aprint_error("%s: could not allocate soft data\n", 602 sc->sc_dev.dv_xname); 603 error = ENOMEM; 604 goto fail; 605 } 606 607 memset(ring->data, 0, count * sizeof (struct rt2661_tx_data)); 608 for (i = 0; i < count; i++) { 609 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 610 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 611 &ring->data[i].map); 612 if (error != 0) { 613 aprint_error("%s: could not create DMA map\n", 614 sc->sc_dev.dv_xname); 615 goto fail; 616 } 617 } 618 619 return 0; 620 621 fail: rt2661_free_tx_ring(sc, ring); 622 return error; 623 } 624 625 static void 626 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 627 { 628 struct rt2661_tx_desc *desc; 629 struct rt2661_tx_data *data; 630 int i; 631 632 for (i = 0; i < ring->count; i++) { 633 desc = &ring->desc[i]; 634 data = &ring->data[i]; 635 636 if (data->m != NULL) { 637 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 638 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 639 bus_dmamap_unload(sc->sc_dmat, data->map); 640 m_freem(data->m); 641 data->m = NULL; 642 } 643 644 if (data->ni != NULL) { 645 ieee80211_free_node(data->ni); 646 data->ni = NULL; 647 } 648 649 desc->flags = 0; 650 } 651 652 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 653 BUS_DMASYNC_PREWRITE); 654 655 ring->queued = 0; 656 ring->cur = ring->next = ring->stat = 0; 657 } 658 659 660 static void 661 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 662 { 663 struct rt2661_tx_data *data; 664 int i; 665 666 if (ring->desc != NULL) { 667 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 668 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 669 bus_dmamap_unload(sc->sc_dmat, ring->map); 670 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 671 ring->count * RT2661_TX_DESC_SIZE); 672 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 673 } 674 675 if (ring->data != NULL) { 676 for (i = 0; i < ring->count; i++) { 677 data = &ring->data[i]; 678 679 if (data->m != NULL) { 680 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 681 data->map->dm_mapsize, 682 BUS_DMASYNC_POSTWRITE); 683 bus_dmamap_unload(sc->sc_dmat, data->map); 684 m_freem(data->m); 685 } 686 687 if (data->ni != NULL) 688 ieee80211_free_node(data->ni); 689 690 if (data->map != NULL) 691 bus_dmamap_destroy(sc->sc_dmat, data->map); 692 } 693 free(ring->data, M_DEVBUF); 694 } 695 } 696 697 static int 698 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 699 int count) 700 { 701 struct rt2661_rx_desc *desc; 702 struct rt2661_rx_data *data; 703 int i, nsegs, error; 704 705 ring->count = count; 706 ring->cur = ring->next = 0; 707 708 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 709 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 710 if (error != 0) { 711 aprint_error("%s: could not create desc DMA map\n", 712 sc->sc_dev.dv_xname); 713 goto fail; 714 } 715 716 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 717 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 718 if (error != 0) { 719 aprint_error("%s: could not allocate DMA memory\n", 720 sc->sc_dev.dv_xname); 721 goto fail; 722 } 723 724 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 725 count * RT2661_RX_DESC_SIZE, (void **)&ring->desc, 726 BUS_DMA_NOWAIT); 727 if (error != 0) { 728 aprint_error("%s: could not map desc DMA memory\n", 729 sc->sc_dev.dv_xname); 730 goto fail; 731 } 732 733 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 734 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 735 if (error != 0) { 736 aprint_error("%s: could not load desc DMA map\n", 737 sc->sc_dev.dv_xname); 738 goto fail; 739 } 740 741 memset(ring->desc, 0, count * RT2661_RX_DESC_SIZE); 742 ring->physaddr = ring->map->dm_segs->ds_addr; 743 744 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 745 M_NOWAIT); 746 if (ring->data == NULL) { 747 aprint_error("%s: could not allocate soft data\n", 748 sc->sc_dev.dv_xname); 749 error = ENOMEM; 750 goto fail; 751 } 752 753 /* 754 * Pre-allocate Rx buffers and populate Rx ring. 755 */ 756 memset(ring->data, 0, count * sizeof (struct rt2661_rx_data)); 757 for (i = 0; i < count; i++) { 758 desc = &sc->rxq.desc[i]; 759 data = &sc->rxq.data[i]; 760 761 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 762 0, BUS_DMA_NOWAIT, &data->map); 763 if (error != 0) { 764 printf("%s: could not create DMA map\n", 765 sc->sc_dev.dv_xname); 766 goto fail; 767 } 768 769 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 770 if (data->m == NULL) { 771 printf("%s: could not allocate rx mbuf\n", 772 sc->sc_dev.dv_xname); 773 error = ENOMEM; 774 goto fail; 775 } 776 777 MCLGET(data->m, M_DONTWAIT); 778 if (!(data->m->m_flags & M_EXT)) { 779 printf("%s: could not allocate rx mbuf cluster\n", 780 sc->sc_dev.dv_xname); 781 error = ENOMEM; 782 goto fail; 783 } 784 785 error = bus_dmamap_load(sc->sc_dmat, data->map, 786 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 787 if (error != 0) { 788 printf("%s: could not load rx buf DMA map", 789 sc->sc_dev.dv_xname); 790 goto fail; 791 } 792 793 desc->flags = htole32(RT2661_RX_BUSY); 794 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 795 } 796 797 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 798 BUS_DMASYNC_PREWRITE); 799 800 return 0; 801 802 fail: rt2661_free_rx_ring(sc, ring); 803 return error; 804 } 805 806 static void 807 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 808 { 809 int i; 810 811 for (i = 0; i < ring->count; i++) 812 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 813 814 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 815 BUS_DMASYNC_PREWRITE); 816 817 ring->cur = ring->next = 0; 818 } 819 820 static void 821 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 822 { 823 struct rt2661_rx_data *data; 824 int i; 825 826 if (ring->desc != NULL) { 827 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 828 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 829 bus_dmamap_unload(sc->sc_dmat, ring->map); 830 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 831 ring->count * RT2661_RX_DESC_SIZE); 832 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 833 } 834 835 if (ring->data != NULL) { 836 for (i = 0; i < ring->count; i++) { 837 data = &ring->data[i]; 838 839 if (data->m != NULL) { 840 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 841 data->map->dm_mapsize, 842 BUS_DMASYNC_POSTREAD); 843 bus_dmamap_unload(sc->sc_dmat, data->map); 844 m_freem(data->m); 845 } 846 847 if (data->map != NULL) 848 bus_dmamap_destroy(sc->sc_dmat, data->map); 849 } 850 free(ring->data, M_DEVBUF); 851 } 852 } 853 854 static struct ieee80211_node * 855 rt2661_node_alloc(struct ieee80211_node_table *nt) 856 { 857 struct rt2661_node *rn; 858 859 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 860 M_NOWAIT | M_ZERO); 861 862 return (rn != NULL) ? &rn->ni : NULL; 863 } 864 865 static int 866 rt2661_media_change(struct ifnet *ifp) 867 { 868 int error; 869 870 error = ieee80211_media_change(ifp); 871 if (error != ENETRESET) 872 return error; 873 874 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 875 rt2661_init(ifp); 876 877 return 0; 878 } 879 880 /* 881 * This function is called periodically (every 200ms) during scanning to 882 * switch from one channel to another. 883 */ 884 static void 885 rt2661_next_scan(void *arg) 886 { 887 struct rt2661_softc *sc = arg; 888 struct ieee80211com *ic = &sc->sc_ic; 889 890 if (ic->ic_state == IEEE80211_S_SCAN) 891 ieee80211_next_scan(ic); 892 } 893 894 /* 895 * This function is called for each neighbor node. 896 */ 897 static void 898 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 899 { 900 struct rt2661_node *rn = (struct rt2661_node *)ni; 901 902 ieee80211_rssadapt_updatestats(&rn->rssadapt); 903 } 904 905 /* 906 * This function is called periodically (every 100ms) in RUN state to update 907 * the rate adaptation statistics. 908 */ 909 static void 910 rt2661_rssadapt_updatestats(void *arg) 911 { 912 struct rt2661_softc *sc = arg; 913 struct ieee80211com *ic = &sc->sc_ic; 914 915 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 916 917 callout_reset(&sc->rssadapt_ch, hz / 10, rt2661_rssadapt_updatestats, 918 sc); 919 } 920 921 static int 922 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 923 { 924 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 925 enum ieee80211_state ostate; 926 struct ieee80211_node *ni; 927 uint32_t tmp; 928 int error = 0; 929 930 ostate = ic->ic_state; 931 callout_stop(&sc->scan_ch); 932 933 switch (nstate) { 934 case IEEE80211_S_INIT: 935 callout_stop(&sc->rssadapt_ch); 936 937 if (ostate == IEEE80211_S_RUN) { 938 /* abort TSF synchronization */ 939 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 940 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 941 } 942 break; 943 944 case IEEE80211_S_SCAN: 945 rt2661_set_chan(sc, ic->ic_curchan); 946 callout_reset(&sc->scan_ch, hz / 5, rt2661_next_scan, sc); 947 break; 948 949 case IEEE80211_S_AUTH: 950 case IEEE80211_S_ASSOC: 951 rt2661_set_chan(sc, ic->ic_curchan); 952 break; 953 954 case IEEE80211_S_RUN: 955 rt2661_set_chan(sc, ic->ic_curchan); 956 957 ni = ic->ic_bss; 958 959 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 960 rt2661_enable_mrr(sc); 961 rt2661_set_txpreamble(sc); 962 rt2661_set_basicrates(sc, &ni->ni_rates); 963 rt2661_set_bssid(sc, ni->ni_bssid); 964 } 965 966 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 967 ic->ic_opmode == IEEE80211_M_IBSS) { 968 if ((error = rt2661_prepare_beacon(sc)) != 0) 969 break; 970 } 971 972 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 973 callout_reset(&sc->rssadapt_ch, hz / 10, 974 rt2661_rssadapt_updatestats, sc); 975 rt2661_enable_tsf_sync(sc); 976 } 977 break; 978 } 979 980 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 981 } 982 983 /* 984 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 985 * 93C66). 986 */ 987 static uint16_t 988 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 989 { 990 uint32_t tmp; 991 uint16_t val; 992 int n; 993 994 /* clock C once before the first command */ 995 RT2661_EEPROM_CTL(sc, 0); 996 997 RT2661_EEPROM_CTL(sc, RT2661_S); 998 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 999 RT2661_EEPROM_CTL(sc, RT2661_S); 1000 1001 /* write start bit (1) */ 1002 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 1003 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 1004 1005 /* write READ opcode (10) */ 1006 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 1007 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 1008 RT2661_EEPROM_CTL(sc, RT2661_S); 1009 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1010 1011 /* write address (A5-A0 or A7-A0) */ 1012 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 1013 for (; n >= 0; n--) { 1014 RT2661_EEPROM_CTL(sc, RT2661_S | 1015 (((addr >> n) & 1) << RT2661_SHIFT_D)); 1016 RT2661_EEPROM_CTL(sc, RT2661_S | 1017 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 1018 } 1019 1020 RT2661_EEPROM_CTL(sc, RT2661_S); 1021 1022 /* read data Q15-Q0 */ 1023 val = 0; 1024 for (n = 15; n >= 0; n--) { 1025 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1026 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 1027 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 1028 RT2661_EEPROM_CTL(sc, RT2661_S); 1029 } 1030 1031 RT2661_EEPROM_CTL(sc, 0); 1032 1033 /* clear Chip Select and clock C */ 1034 RT2661_EEPROM_CTL(sc, RT2661_S); 1035 RT2661_EEPROM_CTL(sc, 0); 1036 RT2661_EEPROM_CTL(sc, RT2661_C); 1037 1038 return val; 1039 } 1040 1041 static void 1042 rt2661_tx_intr(struct rt2661_softc *sc) 1043 { 1044 struct ieee80211com *ic = &sc->sc_ic; 1045 struct ifnet *ifp = &sc->sc_if; 1046 struct rt2661_tx_ring *txq; 1047 struct rt2661_tx_data *data; 1048 struct rt2661_node *rn; 1049 uint32_t val; 1050 int qid, retrycnt; 1051 1052 for (;;) { 1053 val = RAL_READ(sc, RT2661_STA_CSR4); 1054 if (!(val & RT2661_TX_STAT_VALID)) 1055 break; 1056 1057 /* retrieve the queue in which this frame was sent */ 1058 qid = RT2661_TX_QID(val); 1059 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 1060 1061 /* retrieve rate control algorithm context */ 1062 data = &txq->data[txq->stat]; 1063 rn = (struct rt2661_node *)data->ni; 1064 1065 /* if no frame has been sent, ignore */ 1066 if (rn == NULL) 1067 continue; 1068 1069 switch (RT2661_TX_RESULT(val)) { 1070 case RT2661_TX_SUCCESS: 1071 retrycnt = RT2661_TX_RETRYCNT(val); 1072 1073 DPRINTFN(10, ("data frame sent successfully after " 1074 "%d retries\n", retrycnt)); 1075 if (retrycnt == 0 && data->id.id_node != NULL) { 1076 ieee80211_rssadapt_raise_rate(ic, 1077 &rn->rssadapt, &data->id); 1078 } 1079 ifp->if_opackets++; 1080 break; 1081 1082 case RT2661_TX_RETRY_FAIL: 1083 DPRINTFN(9, ("sending data frame failed (too much " 1084 "retries)\n")); 1085 if (data->id.id_node != NULL) { 1086 ieee80211_rssadapt_lower_rate(ic, data->ni, 1087 &rn->rssadapt, &data->id); 1088 } 1089 ifp->if_oerrors++; 1090 break; 1091 1092 default: 1093 /* other failure */ 1094 printf("%s: sending data frame failed 0x%08x\n", 1095 sc->sc_dev.dv_xname, val); 1096 ifp->if_oerrors++; 1097 } 1098 1099 ieee80211_free_node(data->ni); 1100 data->ni = NULL; 1101 1102 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 1103 1104 txq->queued--; 1105 if (++txq->stat >= txq->count) /* faster than % count */ 1106 txq->stat = 0; 1107 } 1108 1109 sc->sc_tx_timer = 0; 1110 ifp->if_flags &= ~IFF_OACTIVE; 1111 rt2661_start(ifp); 1112 } 1113 1114 static void 1115 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1116 { 1117 struct rt2661_tx_desc *desc; 1118 struct rt2661_tx_data *data; 1119 1120 for (;;) { 1121 desc = &txq->desc[txq->next]; 1122 data = &txq->data[txq->next]; 1123 1124 bus_dmamap_sync(sc->sc_dmat, txq->map, 1125 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1126 BUS_DMASYNC_POSTREAD); 1127 1128 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1129 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1130 break; 1131 1132 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1133 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1134 bus_dmamap_unload(sc->sc_dmat, data->map); 1135 m_freem(data->m); 1136 data->m = NULL; 1137 /* node reference is released in rt2661_tx_intr() */ 1138 1139 /* descriptor is no longer valid */ 1140 desc->flags &= ~htole32(RT2661_TX_VALID); 1141 1142 bus_dmamap_sync(sc->sc_dmat, txq->map, 1143 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1144 BUS_DMASYNC_PREWRITE); 1145 1146 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1147 1148 if (++txq->next >= txq->count) /* faster than % count */ 1149 txq->next = 0; 1150 } 1151 } 1152 1153 static void 1154 rt2661_rx_intr(struct rt2661_softc *sc) 1155 { 1156 struct ieee80211com *ic = &sc->sc_ic; 1157 struct ifnet *ifp = &sc->sc_if; 1158 struct rt2661_rx_desc *desc; 1159 struct rt2661_rx_data *data; 1160 struct rt2661_node *rn; 1161 struct ieee80211_frame *wh; 1162 struct ieee80211_node *ni; 1163 struct mbuf *mnew, *m; 1164 int error; 1165 1166 for (;;) { 1167 desc = &sc->rxq.desc[sc->rxq.cur]; 1168 data = &sc->rxq.data[sc->rxq.cur]; 1169 1170 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1171 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1172 BUS_DMASYNC_POSTREAD); 1173 1174 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1175 break; 1176 1177 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1178 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1179 /* 1180 * This should not happen since we did not request 1181 * to receive those frames when we filled TXRX_CSR0. 1182 */ 1183 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1184 le32toh(desc->flags))); 1185 ifp->if_ierrors++; 1186 goto skip; 1187 } 1188 1189 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1190 ifp->if_ierrors++; 1191 goto skip; 1192 } 1193 1194 /* 1195 * Try to allocate a new mbuf for this ring element and load it 1196 * before processing the current mbuf. If the ring element 1197 * cannot be loaded, drop the received packet and reuse the old 1198 * mbuf. In the unlikely case that the old mbuf can't be 1199 * reloaded either, explicitly panic. 1200 */ 1201 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1202 if (mnew == NULL) { 1203 ifp->if_ierrors++; 1204 goto skip; 1205 } 1206 1207 MCLGET(mnew, M_DONTWAIT); 1208 if (!(mnew->m_flags & M_EXT)) { 1209 m_freem(mnew); 1210 ifp->if_ierrors++; 1211 goto skip; 1212 } 1213 1214 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1215 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1216 bus_dmamap_unload(sc->sc_dmat, data->map); 1217 1218 error = bus_dmamap_load(sc->sc_dmat, data->map, 1219 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1220 if (error != 0) { 1221 m_freem(mnew); 1222 1223 /* try to reload the old mbuf */ 1224 error = bus_dmamap_load(sc->sc_dmat, data->map, 1225 mtod(data->m, void *), MCLBYTES, NULL, 1226 BUS_DMA_NOWAIT); 1227 if (error != 0) { 1228 /* very unlikely that it will fail... */ 1229 panic("%s: could not load old rx mbuf", 1230 sc->sc_dev.dv_xname); 1231 } 1232 ifp->if_ierrors++; 1233 goto skip; 1234 } 1235 1236 /* 1237 * New mbuf successfully loaded, update Rx ring and continue 1238 * processing. 1239 */ 1240 m = data->m; 1241 data->m = mnew; 1242 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1243 1244 /* finalize mbuf */ 1245 m->m_pkthdr.rcvif = ifp; 1246 m->m_pkthdr.len = m->m_len = 1247 (le32toh(desc->flags) >> 16) & 0xfff; 1248 1249 #if NBPFILTER > 0 1250 if (sc->sc_drvbpf != NULL) { 1251 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1252 uint32_t tsf_lo, tsf_hi; 1253 1254 /* get timestamp (low and high 32 bits) */ 1255 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1256 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1257 1258 tap->wr_tsf = 1259 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1260 tap->wr_flags = 0; 1261 tap->wr_rate = rt2661_rxrate(desc); 1262 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1263 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1264 tap->wr_antsignal = desc->rssi; 1265 1266 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1267 } 1268 #endif 1269 1270 wh = mtod(m, struct ieee80211_frame *); 1271 ni = ieee80211_find_rxnode(ic, 1272 (struct ieee80211_frame_min *)wh); 1273 1274 /* send the frame to the 802.11 layer */ 1275 ieee80211_input(ic, m, ni, desc->rssi, 0); 1276 1277 1278 /* give rssi to the rate adatation algorithm */ 1279 rn = (struct rt2661_node *)ni; 1280 ieee80211_rssadapt_input(ic, ni, &rn->rssadapt, 1281 rt2661_get_rssi(sc, desc->rssi)); 1282 1283 /* node is no longer needed */ 1284 ieee80211_free_node(ni); 1285 1286 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1287 1288 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1289 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1290 BUS_DMASYNC_PREWRITE); 1291 1292 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1293 1294 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1295 } 1296 1297 /* 1298 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 1299 * without calling if_start(). 1300 */ 1301 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 1302 rt2661_start(ifp); 1303 } 1304 1305 /* ARGSUSED */ 1306 static void 1307 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1308 { 1309 /* do nothing */ 1310 } 1311 1312 static void 1313 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1314 { 1315 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1316 1317 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1318 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1319 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1320 1321 /* send wakeup command to MCU */ 1322 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1323 } 1324 1325 static void 1326 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1327 { 1328 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1329 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1330 } 1331 1332 int 1333 rt2661_intr(void *arg) 1334 { 1335 struct rt2661_softc *sc = arg; 1336 struct ifnet *ifp = &sc->sc_if; 1337 uint32_t r1, r2; 1338 1339 /* disable MAC and MCU interrupts */ 1340 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1341 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1342 1343 /* don't re-enable interrupts if we're shutting down */ 1344 if (!(ifp->if_flags & IFF_RUNNING)) 1345 return 0; 1346 1347 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1348 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1349 1350 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1351 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1352 1353 if (r1 & RT2661_MGT_DONE) 1354 rt2661_tx_dma_intr(sc, &sc->mgtq); 1355 1356 if (r1 & RT2661_RX_DONE) 1357 rt2661_rx_intr(sc); 1358 1359 if (r1 & RT2661_TX0_DMA_DONE) 1360 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1361 1362 if (r1 & RT2661_TX1_DMA_DONE) 1363 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1364 1365 if (r1 & RT2661_TX2_DMA_DONE) 1366 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1367 1368 if (r1 & RT2661_TX3_DMA_DONE) 1369 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1370 1371 if (r1 & RT2661_TX_DONE) 1372 rt2661_tx_intr(sc); 1373 1374 if (r2 & RT2661_MCU_CMD_DONE) 1375 rt2661_mcu_cmd_intr(sc); 1376 1377 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1378 rt2661_mcu_beacon_expire(sc); 1379 1380 if (r2 & RT2661_MCU_WAKEUP) 1381 rt2661_mcu_wakeup(sc); 1382 1383 /* re-enable MAC and MCU interrupts */ 1384 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1385 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1386 1387 return 1; 1388 } 1389 1390 /* quickly determine if a given rate is CCK or OFDM */ 1391 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1392 1393 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1394 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1395 1396 #define RAL_SIFS 10 /* us */ 1397 1398 /* 1399 * This function is only used by the Rx radiotap code. It returns the rate at 1400 * which a given frame was received. 1401 */ 1402 #if NBPFILTER > 0 1403 static uint8_t 1404 rt2661_rxrate(struct rt2661_rx_desc *desc) 1405 { 1406 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1407 /* reverse function of rt2661_plcp_signal */ 1408 switch (desc->rate & 0xf) { 1409 case 0xb: return 12; 1410 case 0xf: return 18; 1411 case 0xa: return 24; 1412 case 0xe: return 36; 1413 case 0x9: return 48; 1414 case 0xd: return 72; 1415 case 0x8: return 96; 1416 case 0xc: return 108; 1417 } 1418 } else { 1419 if (desc->rate == 10) 1420 return 2; 1421 if (desc->rate == 20) 1422 return 4; 1423 if (desc->rate == 55) 1424 return 11; 1425 if (desc->rate == 110) 1426 return 22; 1427 } 1428 return 2; /* should not get there */ 1429 } 1430 #endif 1431 1432 /* 1433 * Return the expected ack rate for a frame transmitted at rate `rate'. 1434 * XXX: this should depend on the destination node basic rate set. 1435 */ 1436 static int 1437 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1438 { 1439 switch (rate) { 1440 /* CCK rates */ 1441 case 2: 1442 return 2; 1443 case 4: 1444 case 11: 1445 case 22: 1446 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1447 1448 /* OFDM rates */ 1449 case 12: 1450 case 18: 1451 return 12; 1452 case 24: 1453 case 36: 1454 return 24; 1455 case 48: 1456 case 72: 1457 case 96: 1458 case 108: 1459 return 48; 1460 } 1461 1462 /* default to 1Mbps */ 1463 return 2; 1464 } 1465 1466 /* 1467 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1468 * The function automatically determines the operating mode depending on the 1469 * given rate. `flags' indicates whether short preamble is in use or not. 1470 */ 1471 static uint16_t 1472 rt2661_txtime(int len, int rate, uint32_t flags) 1473 { 1474 uint16_t txtime; 1475 1476 if (RAL_RATE_IS_OFDM(rate)) { 1477 /* IEEE Std 802.11a-1999, pp. 37 */ 1478 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1479 txtime = 16 + 4 + 4 * txtime + 6; 1480 } else { 1481 /* IEEE Std 802.11b-1999, pp. 28 */ 1482 txtime = (16 * len + rate - 1) / rate; 1483 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1484 txtime += 72 + 24; 1485 else 1486 txtime += 144 + 48; 1487 } 1488 return txtime; 1489 } 1490 1491 static uint8_t 1492 rt2661_plcp_signal(int rate) 1493 { 1494 switch (rate) { 1495 /* CCK rates (returned values are device-dependent) */ 1496 case 2: return 0x0; 1497 case 4: return 0x1; 1498 case 11: return 0x2; 1499 case 22: return 0x3; 1500 1501 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1502 case 12: return 0xb; 1503 case 18: return 0xf; 1504 case 24: return 0xa; 1505 case 36: return 0xe; 1506 case 48: return 0x9; 1507 case 72: return 0xd; 1508 case 96: return 0x8; 1509 case 108: return 0xc; 1510 1511 /* unsupported rates (should not get there) */ 1512 default: return 0xff; 1513 } 1514 } 1515 1516 static void 1517 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1518 uint32_t flags, uint16_t xflags, int len, int rate, 1519 const bus_dma_segment_t *segs, int nsegs, int ac) 1520 { 1521 struct ieee80211com *ic = &sc->sc_ic; 1522 uint16_t plcp_length; 1523 int i, remainder; 1524 1525 desc->flags = htole32(flags); 1526 desc->flags |= htole32(len << 16); 1527 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1528 1529 desc->xflags = htole16(xflags); 1530 desc->xflags |= htole16(nsegs << 13); 1531 1532 desc->wme = htole16( 1533 RT2661_QID(ac) | 1534 RT2661_AIFSN(2) | 1535 RT2661_LOGCWMIN(4) | 1536 RT2661_LOGCWMAX(10)); 1537 1538 /* 1539 * Remember in which queue this frame was sent. This field is driver 1540 * private data only. It will be made available by the NIC in STA_CSR4 1541 * on Tx interrupts. 1542 */ 1543 desc->qid = ac; 1544 1545 /* setup PLCP fields */ 1546 desc->plcp_signal = rt2661_plcp_signal(rate); 1547 desc->plcp_service = 4; 1548 1549 len += IEEE80211_CRC_LEN; 1550 if (RAL_RATE_IS_OFDM(rate)) { 1551 desc->flags |= htole32(RT2661_TX_OFDM); 1552 1553 plcp_length = len & 0xfff; 1554 desc->plcp_length_hi = plcp_length >> 6; 1555 desc->plcp_length_lo = plcp_length & 0x3f; 1556 } else { 1557 plcp_length = (16 * len + rate - 1) / rate; 1558 if (rate == 22) { 1559 remainder = (16 * len) % 22; 1560 if (remainder != 0 && remainder < 7) 1561 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1562 } 1563 desc->plcp_length_hi = plcp_length >> 8; 1564 desc->plcp_length_lo = plcp_length & 0xff; 1565 1566 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1567 desc->plcp_signal |= 0x08; 1568 } 1569 1570 /* RT2x61 supports scatter with up to 5 segments */ 1571 for (i = 0; i < nsegs; i++) { 1572 desc->addr[i] = htole32(segs[i].ds_addr); 1573 desc->len [i] = htole16(segs[i].ds_len); 1574 } 1575 } 1576 1577 static int 1578 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1579 struct ieee80211_node *ni) 1580 { 1581 struct ieee80211com *ic = &sc->sc_ic; 1582 struct rt2661_tx_desc *desc; 1583 struct rt2661_tx_data *data; 1584 struct ieee80211_frame *wh; 1585 struct ieee80211_key *k; 1586 uint16_t dur; 1587 uint32_t flags = 0; 1588 int rate, error; 1589 1590 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1591 data = &sc->mgtq.data[sc->mgtq.cur]; 1592 1593 /* send mgt frames at the lowest available rate */ 1594 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1595 1596 wh = mtod(m0, struct ieee80211_frame *); 1597 1598 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1599 k = ieee80211_crypto_encap(ic, ni, m0); 1600 if (k == NULL) { 1601 m_freem(m0); 1602 return ENOBUFS; 1603 } 1604 } 1605 1606 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1607 BUS_DMA_NOWAIT); 1608 if (error != 0) { 1609 printf("%s: could not map mbuf (error %d)\n", 1610 sc->sc_dev.dv_xname, error); 1611 m_freem(m0); 1612 return error; 1613 } 1614 1615 #if NBPFILTER > 0 1616 if (sc->sc_drvbpf != NULL) { 1617 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1618 1619 tap->wt_flags = 0; 1620 tap->wt_rate = rate; 1621 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1622 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1623 1624 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1625 } 1626 #endif 1627 1628 data->m = m0; 1629 data->ni = ni; 1630 1631 wh = mtod(m0, struct ieee80211_frame *); 1632 1633 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1634 flags |= RT2661_TX_NEED_ACK; 1635 1636 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1637 RAL_SIFS; 1638 *(uint16_t *)wh->i_dur = htole16(dur); 1639 1640 /* tell hardware to add timestamp in probe responses */ 1641 if ((wh->i_fc[0] & 1642 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1643 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1644 flags |= RT2661_TX_TIMESTAMP; 1645 } 1646 1647 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1648 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1649 RT2661_QID_MGT); 1650 1651 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1652 BUS_DMASYNC_PREWRITE); 1653 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1654 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1655 BUS_DMASYNC_PREWRITE); 1656 1657 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1658 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1659 1660 /* kick mgt */ 1661 sc->mgtq.queued++; 1662 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1663 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1664 1665 return 0; 1666 } 1667 1668 /* 1669 * Build a RTS control frame. 1670 */ 1671 static struct mbuf * 1672 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1673 uint16_t dur) 1674 { 1675 struct ieee80211_frame_rts *rts; 1676 struct mbuf *m; 1677 1678 MGETHDR(m, M_DONTWAIT, MT_DATA); 1679 if (m == NULL) { 1680 sc->sc_ic.ic_stats.is_tx_nobuf++; 1681 printf("%s: could not allocate RTS frame\n", 1682 sc->sc_dev.dv_xname); 1683 return NULL; 1684 } 1685 1686 rts = mtod(m, struct ieee80211_frame_rts *); 1687 1688 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1689 IEEE80211_FC0_SUBTYPE_RTS; 1690 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1691 *(uint16_t *)rts->i_dur = htole16(dur); 1692 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1693 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1694 1695 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1696 1697 return m; 1698 } 1699 1700 static int 1701 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1702 struct ieee80211_node *ni, int ac) 1703 { 1704 struct ieee80211com *ic = &sc->sc_ic; 1705 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1706 struct rt2661_tx_desc *desc; 1707 struct rt2661_tx_data *data; 1708 struct rt2661_node *rn; 1709 struct ieee80211_rateset *rs; 1710 struct ieee80211_frame *wh; 1711 struct ieee80211_key *k; 1712 struct mbuf *mnew; 1713 uint16_t dur; 1714 uint32_t flags = 0; 1715 int rate, error; 1716 1717 wh = mtod(m0, struct ieee80211_frame *); 1718 1719 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1720 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1721 rate = rs->rs_rates[ic->ic_fixed_rate]; 1722 } else { 1723 rs = &ni->ni_rates; 1724 rn = (struct rt2661_node *)ni; 1725 ni->ni_txrate = ieee80211_rssadapt_choose(&rn->rssadapt, rs, 1726 wh, m0->m_pkthdr.len, -1, NULL, 0); 1727 rate = rs->rs_rates[ni->ni_txrate]; 1728 } 1729 rate &= IEEE80211_RATE_VAL; 1730 1731 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1732 k = ieee80211_crypto_encap(ic, ni, m0); 1733 if (k == NULL) { 1734 m_freem(m0); 1735 return ENOBUFS; 1736 } 1737 1738 /* packet header may have moved, reset our local pointer */ 1739 wh = mtod(m0, struct ieee80211_frame *); 1740 } 1741 1742 /* 1743 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1744 * for directed frames only when the length of the MPDU is greater 1745 * than the length threshold indicated by [...]" ic_rtsthreshold. 1746 */ 1747 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1748 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1749 struct mbuf *m; 1750 int rtsrate, ackrate; 1751 1752 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1753 ackrate = rt2661_ack_rate(ic, rate); 1754 1755 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1756 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1757 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1758 3 * RAL_SIFS; 1759 1760 m = rt2661_get_rts(sc, wh, dur); 1761 1762 desc = &txq->desc[txq->cur]; 1763 data = &txq->data[txq->cur]; 1764 1765 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1766 BUS_DMA_NOWAIT); 1767 if (error != 0) { 1768 printf("%s: could not map mbuf (error %d)\n", 1769 sc->sc_dev.dv_xname, error); 1770 m_freem(m); 1771 m_freem(m0); 1772 return error; 1773 } 1774 1775 /* avoid multiple free() of the same node for each fragment */ 1776 ieee80211_ref_node(ni); 1777 1778 data->m = m; 1779 data->ni = ni; 1780 1781 /* RTS frames are not taken into account for rssadapt */ 1782 data->id.id_node = NULL; 1783 1784 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1785 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, 1786 data->map->dm_segs, data->map->dm_nsegs, ac); 1787 1788 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1789 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1790 bus_dmamap_sync(sc->sc_dmat, txq->map, 1791 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1792 BUS_DMASYNC_PREWRITE); 1793 1794 txq->queued++; 1795 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1796 1797 /* 1798 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1799 * asynchronous data frame shall be transmitted after the CTS 1800 * frame and a SIFS period. 1801 */ 1802 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1803 } 1804 1805 data = &txq->data[txq->cur]; 1806 desc = &txq->desc[txq->cur]; 1807 1808 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1809 BUS_DMA_NOWAIT); 1810 if (error != 0 && error != EFBIG) { 1811 printf("%s: could not map mbuf (error %d)\n", 1812 sc->sc_dev.dv_xname, error); 1813 m_freem(m0); 1814 return error; 1815 } 1816 if (error != 0) { 1817 /* too many fragments, linearize */ 1818 1819 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1820 if (mnew == NULL) { 1821 m_freem(m0); 1822 return ENOMEM; 1823 } 1824 1825 M_COPY_PKTHDR(mnew, m0); 1826 if (m0->m_pkthdr.len > MHLEN) { 1827 MCLGET(mnew, M_DONTWAIT); 1828 if (!(mnew->m_flags & M_EXT)) { 1829 m_freem(m0); 1830 m_freem(mnew); 1831 return ENOMEM; 1832 } 1833 } 1834 1835 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1836 m_freem(m0); 1837 mnew->m_len = mnew->m_pkthdr.len; 1838 m0 = mnew; 1839 1840 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1841 BUS_DMA_NOWAIT); 1842 if (error != 0) { 1843 printf("%s: could not map mbuf (error %d)\n", 1844 sc->sc_dev.dv_xname, error); 1845 m_freem(m0); 1846 return error; 1847 } 1848 1849 /* packet header have moved, reset our local pointer */ 1850 wh = mtod(m0, struct ieee80211_frame *); 1851 } 1852 1853 #if NBPFILTER > 0 1854 if (sc->sc_drvbpf != NULL) { 1855 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1856 1857 tap->wt_flags = 0; 1858 tap->wt_rate = rate; 1859 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1860 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1861 1862 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1863 } 1864 #endif 1865 1866 data->m = m0; 1867 data->ni = ni; 1868 1869 /* remember link conditions for rate adaptation algorithm */ 1870 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1871 data->id.id_len = m0->m_pkthdr.len; 1872 data->id.id_rateidx = ni->ni_txrate; 1873 data->id.id_node = ni; 1874 data->id.id_rssi = ni->ni_rssi; 1875 } else 1876 data->id.id_node = NULL; 1877 1878 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1879 flags |= RT2661_TX_NEED_ACK; 1880 1881 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1882 ic->ic_flags) + RAL_SIFS; 1883 *(uint16_t *)wh->i_dur = htole16(dur); 1884 } 1885 1886 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1887 data->map->dm_segs, data->map->dm_nsegs, ac); 1888 1889 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1890 BUS_DMASYNC_PREWRITE); 1891 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1892 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1893 1894 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1895 m0->m_pkthdr.len, txq->cur, rate)); 1896 1897 /* kick Tx */ 1898 txq->queued++; 1899 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1900 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1901 1902 return 0; 1903 } 1904 1905 static void 1906 rt2661_start(struct ifnet *ifp) 1907 { 1908 struct rt2661_softc *sc = ifp->if_softc; 1909 struct ieee80211com *ic = &sc->sc_ic; 1910 struct mbuf *m0; 1911 struct ether_header *eh; 1912 struct ieee80211_node *ni = NULL; 1913 int ac; 1914 1915 /* 1916 * net80211 may still try to send management frames even if the 1917 * IFF_RUNNING flag is not set... 1918 */ 1919 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1920 return; 1921 1922 for (;;) { 1923 IF_POLL(&ic->ic_mgtq, m0); 1924 if (m0 != NULL) { 1925 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1926 ifp->if_flags |= IFF_OACTIVE; 1927 break; 1928 } 1929 IF_DEQUEUE(&ic->ic_mgtq, m0); 1930 if (m0 == NULL) 1931 break; 1932 1933 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1934 m0->m_pkthdr.rcvif = NULL; 1935 #if NBPFILTER > 0 1936 if (ic->ic_rawbpf != NULL) 1937 bpf_mtap(ic->ic_rawbpf, m0); 1938 #endif 1939 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1940 break; 1941 1942 } else { 1943 if (ic->ic_state != IEEE80211_S_RUN) 1944 break; 1945 IFQ_DEQUEUE(&ifp->if_snd, m0); 1946 if (m0 == NULL) 1947 break; 1948 1949 if (m0->m_len < sizeof (struct ether_header) && 1950 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1951 continue; 1952 1953 eh = mtod(m0, struct ether_header *); 1954 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1955 if (ni == NULL) { 1956 m_freem(m0); 1957 ifp->if_oerrors++; 1958 continue; 1959 } 1960 1961 1962 /* classify mbuf so we can find which tx ring to use */ 1963 if (ieee80211_classify(ic, m0, ni) != 0) { 1964 m_freem(m0); 1965 ieee80211_free_node(ni); 1966 ifp->if_oerrors++; 1967 continue; 1968 } 1969 1970 /* no QoS encapsulation for EAPOL frames */ 1971 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 1972 M_WME_GETAC(m0) : WME_AC_BE; 1973 1974 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1975 /* there is no place left in this ring */ 1976 ifp->if_flags |= IFF_OACTIVE; 1977 break; 1978 } 1979 #if NBPFILTER > 0 1980 if (ifp->if_bpf != NULL) 1981 bpf_mtap(ifp->if_bpf, m0); 1982 #endif 1983 m0 = ieee80211_encap(ic, m0, ni); 1984 if (m0 == NULL) { 1985 ieee80211_free_node(ni); 1986 ifp->if_oerrors++; 1987 continue; 1988 } 1989 #if NBPFILTER > 0 1990 if (ic->ic_rawbpf != NULL) 1991 bpf_mtap(ic->ic_rawbpf, m0); 1992 #endif 1993 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1994 if (ni != NULL) 1995 ieee80211_free_node(ni); 1996 ifp->if_oerrors++; 1997 break; 1998 } 1999 } 2000 2001 sc->sc_tx_timer = 5; 2002 ifp->if_timer = 1; 2003 } 2004 } 2005 2006 static void 2007 rt2661_watchdog(struct ifnet *ifp) 2008 { 2009 struct rt2661_softc *sc = ifp->if_softc; 2010 2011 ifp->if_timer = 0; 2012 2013 if (sc->sc_tx_timer > 0) { 2014 if (--sc->sc_tx_timer == 0) { 2015 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2016 rt2661_init(ifp); 2017 ifp->if_oerrors++; 2018 return; 2019 } 2020 ifp->if_timer = 1; 2021 } 2022 2023 ieee80211_watchdog(&sc->sc_ic); 2024 } 2025 2026 /* 2027 * This function allows for fast channel switching in monitor mode (used by 2028 * kismet). In IBSS mode, we must explicitly reset the interface to 2029 * generate a new beacon frame. 2030 */ 2031 static int 2032 rt2661_reset(struct ifnet *ifp) 2033 { 2034 struct rt2661_softc *sc = ifp->if_softc; 2035 struct ieee80211com *ic = &sc->sc_ic; 2036 2037 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2038 return ENETRESET; 2039 2040 rt2661_set_chan(sc, ic->ic_curchan); 2041 2042 return 0; 2043 } 2044 2045 static int 2046 rt2661_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2047 { 2048 struct rt2661_softc *sc = ifp->if_softc; 2049 struct ieee80211com *ic = &sc->sc_ic; 2050 int s, error = 0; 2051 2052 s = splnet(); 2053 2054 switch (cmd) { 2055 case SIOCSIFFLAGS: 2056 if (ifp->if_flags & IFF_UP) { 2057 if (ifp->if_flags & IFF_RUNNING) 2058 rt2661_update_promisc(sc); 2059 else 2060 rt2661_init(ifp); 2061 } else { 2062 if (ifp->if_flags & IFF_RUNNING) 2063 rt2661_stop(ifp, 1); 2064 } 2065 break; 2066 2067 case SIOCADDMULTI: 2068 case SIOCDELMULTI: 2069 /* XXX no h/w multicast filter? --dyoung */ 2070 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2071 error = 0; 2072 break; 2073 2074 case SIOCS80211CHANNEL: 2075 /* 2076 * This allows for fast channel switching in monitor mode 2077 * (used by kismet). In IBSS mode, we must explicitly reset 2078 * the interface to generate a new beacon frame. 2079 */ 2080 error = ieee80211_ioctl(ic, cmd, data); 2081 if (error == ENETRESET && 2082 ic->ic_opmode == IEEE80211_M_MONITOR) { 2083 rt2661_set_chan(sc, ic->ic_ibss_chan); 2084 error = 0; 2085 } 2086 break; 2087 2088 default: 2089 error = ieee80211_ioctl(ic, cmd, data); 2090 2091 } 2092 2093 if (error == ENETRESET) { 2094 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2095 (IFF_UP | IFF_RUNNING)) 2096 rt2661_init(ifp); 2097 error = 0; 2098 } 2099 2100 splx(s); 2101 2102 return error; 2103 } 2104 2105 static void 2106 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 2107 { 2108 uint32_t tmp; 2109 int ntries; 2110 2111 for (ntries = 0; ntries < 100; ntries++) { 2112 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2113 break; 2114 DELAY(1); 2115 } 2116 if (ntries == 100) { 2117 printf("%s: could not write to BBP\n", sc->sc_dev.dv_xname); 2118 return; 2119 } 2120 2121 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 2122 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 2123 2124 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 2125 } 2126 2127 static uint8_t 2128 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2129 { 2130 uint32_t val; 2131 int ntries; 2132 2133 for (ntries = 0; ntries < 100; ntries++) { 2134 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2135 break; 2136 DELAY(1); 2137 } 2138 if (ntries == 100) { 2139 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 2140 return 0; 2141 } 2142 2143 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2144 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2145 2146 for (ntries = 0; ntries < 100; ntries++) { 2147 val = RAL_READ(sc, RT2661_PHY_CSR3); 2148 if (!(val & RT2661_BBP_BUSY)) 2149 return val & 0xff; 2150 DELAY(1); 2151 } 2152 2153 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 2154 return 0; 2155 } 2156 2157 static void 2158 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2159 { 2160 uint32_t tmp; 2161 int ntries; 2162 2163 for (ntries = 0; ntries < 100; ntries++) { 2164 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2165 break; 2166 DELAY(1); 2167 } 2168 if (ntries == 100) { 2169 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 2170 return; 2171 } 2172 2173 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2174 (reg & 3); 2175 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2176 2177 /* remember last written value in sc */ 2178 sc->rf_regs[reg] = val; 2179 2180 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2181 } 2182 2183 static int 2184 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2185 { 2186 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2187 return EIO; /* there is already a command pending */ 2188 2189 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2190 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2191 2192 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2193 2194 return 0; 2195 } 2196 2197 static void 2198 rt2661_select_antenna(struct rt2661_softc *sc) 2199 { 2200 uint8_t bbp4, bbp77; 2201 uint32_t tmp; 2202 2203 bbp4 = rt2661_bbp_read(sc, 4); 2204 bbp77 = rt2661_bbp_read(sc, 77); 2205 2206 /* TBD */ 2207 2208 /* make sure Rx is disabled before switching antenna */ 2209 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2210 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2211 2212 rt2661_bbp_write(sc, 4, bbp4); 2213 rt2661_bbp_write(sc, 77, bbp77); 2214 2215 /* restore Rx filter */ 2216 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2217 } 2218 2219 /* 2220 * Enable multi-rate retries for frames sent at OFDM rates. 2221 * In 802.11b/g mode, allow fallback to CCK rates. 2222 */ 2223 static void 2224 rt2661_enable_mrr(struct rt2661_softc *sc) 2225 { 2226 struct ieee80211com *ic = &sc->sc_ic; 2227 uint32_t tmp; 2228 2229 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2230 2231 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2232 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2233 tmp |= RT2661_MRR_CCK_FALLBACK; 2234 tmp |= RT2661_MRR_ENABLED; 2235 2236 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2237 } 2238 2239 static void 2240 rt2661_set_txpreamble(struct rt2661_softc *sc) 2241 { 2242 uint32_t tmp; 2243 2244 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2245 2246 tmp &= ~RT2661_SHORT_PREAMBLE; 2247 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2248 tmp |= RT2661_SHORT_PREAMBLE; 2249 2250 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2251 } 2252 2253 static void 2254 rt2661_set_basicrates(struct rt2661_softc *sc, 2255 const struct ieee80211_rateset *rs) 2256 { 2257 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2258 uint32_t mask = 0; 2259 uint8_t rate; 2260 int i, j; 2261 2262 for (i = 0; i < rs->rs_nrates; i++) { 2263 rate = rs->rs_rates[i]; 2264 2265 if (!(rate & IEEE80211_RATE_BASIC)) 2266 continue; 2267 2268 /* 2269 * Find h/w rate index. We know it exists because the rate 2270 * set has already been negotiated. 2271 */ 2272 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++); 2273 2274 mask |= 1 << j; 2275 } 2276 2277 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2278 2279 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2280 #undef RV 2281 } 2282 2283 /* 2284 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2285 * driver. 2286 */ 2287 static void 2288 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2289 { 2290 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2291 uint32_t tmp; 2292 2293 /* update all BBP registers that depend on the band */ 2294 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2295 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2296 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2297 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2298 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2299 } 2300 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2301 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2302 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2303 } 2304 2305 rt2661_bbp_write(sc, 17, bbp17); 2306 rt2661_bbp_write(sc, 96, bbp96); 2307 rt2661_bbp_write(sc, 104, bbp104); 2308 2309 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2310 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2311 rt2661_bbp_write(sc, 75, 0x80); 2312 rt2661_bbp_write(sc, 86, 0x80); 2313 rt2661_bbp_write(sc, 88, 0x80); 2314 } 2315 2316 rt2661_bbp_write(sc, 35, bbp35); 2317 rt2661_bbp_write(sc, 97, bbp97); 2318 rt2661_bbp_write(sc, 98, bbp98); 2319 2320 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2321 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2322 if (IEEE80211_IS_CHAN_2GHZ(c)) 2323 tmp |= RT2661_PA_PE_2GHZ; 2324 else 2325 tmp |= RT2661_PA_PE_5GHZ; 2326 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2327 } 2328 2329 static void 2330 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2331 { 2332 struct ieee80211com *ic = &sc->sc_ic; 2333 const struct rfprog *rfprog; 2334 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2335 int8_t power; 2336 u_int i, chan; 2337 2338 chan = ieee80211_chan2ieee(ic, c); 2339 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2340 return; 2341 2342 /* select the appropriate RF settings based on what EEPROM says */ 2343 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2344 2345 /* find the settings for this channel (we know it exists) */ 2346 for (i = 0; rfprog[i].chan != chan; i++); 2347 2348 power = sc->txpow[i]; 2349 if (power < 0) { 2350 bbp94 += power; 2351 power = 0; 2352 } else if (power > 31) { 2353 bbp94 += power - 31; 2354 power = 31; 2355 } 2356 2357 /* 2358 * If we've yet to select a channel, or we are switching from the 2359 * 2GHz band to the 5GHz band or vice-versa, BBP registers need to 2360 * be reprogrammed. 2361 */ 2362 if (sc->sc_curchan == NULL || c->ic_flags != sc->sc_curchan->ic_flags) { 2363 rt2661_select_band(sc, c); 2364 rt2661_select_antenna(sc); 2365 } 2366 sc->sc_curchan = c; 2367 2368 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2369 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2370 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2371 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2372 2373 DELAY(200); 2374 2375 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2376 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2377 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2378 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2379 2380 DELAY(200); 2381 2382 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2383 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2384 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2385 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2386 2387 /* enable smart mode for MIMO-capable RFs */ 2388 bbp3 = rt2661_bbp_read(sc, 3); 2389 2390 bbp3 &= ~RT2661_SMART_MODE; 2391 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2392 bbp3 |= RT2661_SMART_MODE; 2393 2394 rt2661_bbp_write(sc, 3, bbp3); 2395 2396 if (bbp94 != RT2661_BBPR94_DEFAULT) 2397 rt2661_bbp_write(sc, 94, bbp94); 2398 2399 /* 5GHz radio needs a 1ms delay here */ 2400 if (IEEE80211_IS_CHAN_5GHZ(c)) 2401 DELAY(1000); 2402 } 2403 2404 static void 2405 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2406 { 2407 uint32_t tmp; 2408 2409 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2410 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2411 2412 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2413 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2414 } 2415 2416 static void 2417 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2418 { 2419 uint32_t tmp; 2420 2421 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2422 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2423 2424 tmp = addr[4] | addr[5] << 8; 2425 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2426 } 2427 2428 static void 2429 rt2661_update_promisc(struct rt2661_softc *sc) 2430 { 2431 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2432 uint32_t tmp; 2433 2434 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2435 2436 tmp &= ~RT2661_DROP_NOT_TO_ME; 2437 if (!(ifp->if_flags & IFF_PROMISC)) 2438 tmp |= RT2661_DROP_NOT_TO_ME; 2439 2440 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2441 2442 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2443 "entering" : "leaving")); 2444 } 2445 2446 #if 0 2447 /* 2448 * Update QoS (802.11e) settings for each h/w Tx ring. 2449 */ 2450 static int 2451 rt2661_wme_update(struct ieee80211com *ic) 2452 { 2453 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2454 const struct wmeParams *wmep; 2455 2456 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2457 2458 /* XXX: not sure about shifts. */ 2459 /* XXX: the reference driver plays with AC_VI settings too. */ 2460 2461 /* update TxOp */ 2462 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2463 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2464 wmep[WME_AC_BK].wmep_txopLimit); 2465 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2466 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2467 wmep[WME_AC_VO].wmep_txopLimit); 2468 2469 /* update CWmin */ 2470 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2471 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2472 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2473 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2474 wmep[WME_AC_VO].wmep_logcwmin); 2475 2476 /* update CWmax */ 2477 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2478 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2479 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2480 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2481 wmep[WME_AC_VO].wmep_logcwmax); 2482 2483 /* update Aifsn */ 2484 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2485 wmep[WME_AC_BE].wmep_aifsn << 12 | 2486 wmep[WME_AC_BK].wmep_aifsn << 8 | 2487 wmep[WME_AC_VI].wmep_aifsn << 4 | 2488 wmep[WME_AC_VO].wmep_aifsn); 2489 2490 return 0; 2491 } 2492 #endif 2493 2494 static void 2495 rt2661_update_slot(struct ifnet *ifp) 2496 { 2497 struct rt2661_softc *sc = ifp->if_softc; 2498 struct ieee80211com *ic = &sc->sc_ic; 2499 uint8_t slottime; 2500 uint32_t tmp; 2501 2502 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2503 2504 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2505 tmp = (tmp & ~0xff) | slottime; 2506 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2507 } 2508 2509 static const char * 2510 rt2661_get_rf(int rev) 2511 { 2512 switch (rev) { 2513 case RT2661_RF_5225: return "RT5225"; 2514 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2515 case RT2661_RF_2527: return "RT2527"; 2516 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2517 default: return "unknown"; 2518 } 2519 } 2520 2521 static void 2522 rt2661_read_eeprom(struct rt2661_softc *sc) 2523 { 2524 struct ieee80211com *ic = &sc->sc_ic; 2525 uint16_t val; 2526 int i; 2527 2528 /* read MAC address */ 2529 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2530 ic->ic_myaddr[0] = val & 0xff; 2531 ic->ic_myaddr[1] = val >> 8; 2532 2533 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2534 ic->ic_myaddr[2] = val & 0xff; 2535 ic->ic_myaddr[3] = val >> 8; 2536 2537 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2538 ic->ic_myaddr[4] = val & 0xff; 2539 ic->ic_myaddr[5] = val >> 8; 2540 2541 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2542 /* XXX: test if different from 0xffff? */ 2543 sc->rf_rev = (val >> 11) & 0x1f; 2544 sc->hw_radio = (val >> 10) & 0x1; 2545 sc->rx_ant = (val >> 4) & 0x3; 2546 sc->tx_ant = (val >> 2) & 0x3; 2547 sc->nb_ant = val & 0x3; 2548 2549 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2550 2551 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2552 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2553 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2554 2555 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2556 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2557 2558 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2559 if ((val & 0xff) != 0xff) 2560 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2561 2562 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2563 if ((val & 0xff) != 0xff) 2564 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2565 2566 /* adjust RSSI correction for external low-noise amplifier */ 2567 if (sc->ext_2ghz_lna) 2568 sc->rssi_2ghz_corr -= 14; 2569 if (sc->ext_5ghz_lna) 2570 sc->rssi_5ghz_corr -= 14; 2571 2572 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2573 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2574 2575 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2576 if ((val >> 8) != 0xff) 2577 sc->rfprog = (val >> 8) & 0x3; 2578 if ((val & 0xff) != 0xff) 2579 sc->rffreq = val & 0xff; 2580 2581 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2582 2583 /* read Tx power for all a/b/g channels */ 2584 for (i = 0; i < 19; i++) { 2585 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2586 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2587 DPRINTF(("Channel=%d Tx power=%d\n", 2588 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2589 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2590 DPRINTF(("Channel=%d Tx power=%d\n", 2591 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2592 } 2593 2594 /* read vendor-specific BBP values */ 2595 for (i = 0; i < 16; i++) { 2596 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2597 if (val == 0 || val == 0xffff) 2598 continue; /* skip invalid entries */ 2599 sc->bbp_prom[i].reg = val >> 8; 2600 sc->bbp_prom[i].val = val & 0xff; 2601 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2602 sc->bbp_prom[i].val)); 2603 } 2604 } 2605 2606 static int 2607 rt2661_bbp_init(struct rt2661_softc *sc) 2608 { 2609 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2610 int i, ntries; 2611 uint8_t val; 2612 2613 /* wait for BBP to be ready */ 2614 for (ntries = 0; ntries < 100; ntries++) { 2615 val = rt2661_bbp_read(sc, 0); 2616 if (val != 0 && val != 0xff) 2617 break; 2618 DELAY(100); 2619 } 2620 if (ntries == 100) { 2621 printf("%s: timeout waiting for BBP\n", sc->sc_dev.dv_xname); 2622 return EIO; 2623 } 2624 2625 /* initialize BBP registers to default values */ 2626 for (i = 0; i < N(rt2661_def_bbp); i++) { 2627 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2628 rt2661_def_bbp[i].val); 2629 } 2630 2631 /* write vendor-specific BBP values (from EEPROM) */ 2632 for (i = 0; i < 16; i++) { 2633 if (sc->bbp_prom[i].reg == 0) 2634 continue; 2635 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2636 } 2637 2638 return 0; 2639 #undef N 2640 } 2641 2642 static int 2643 rt2661_init(struct ifnet *ifp) 2644 { 2645 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2646 struct rt2661_softc *sc = ifp->if_softc; 2647 struct ieee80211com *ic = &sc->sc_ic; 2648 const char *name = NULL; /* make lint happy */ 2649 uint8_t *ucode; 2650 size_t size; 2651 uint32_t tmp, star[3]; 2652 int i, ntries; 2653 firmware_handle_t fh; 2654 2655 /* for CardBus, power on the socket */ 2656 if (!(sc->sc_flags & RT2661_ENABLED)) { 2657 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2658 printf("%s: could not enable device\n", 2659 sc->sc_dev.dv_xname); 2660 return EIO; 2661 } 2662 sc->sc_flags |= RT2661_ENABLED; 2663 } 2664 2665 rt2661_stop(ifp, 0); 2666 2667 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2668 switch (sc->sc_id) { 2669 case PCI_PRODUCT_RALINK_RT2561: 2670 name = "ral-rt2561"; 2671 break; 2672 case PCI_PRODUCT_RALINK_RT2561S: 2673 name = "ral-rt2561s"; 2674 break; 2675 case PCI_PRODUCT_RALINK_RT2661: 2676 name = "ral-rt2661"; 2677 break; 2678 } 2679 2680 if (firmware_open("ral", name, &fh) != 0) { 2681 printf("%s: could not open microcode %s\n", 2682 sc->sc_dev.dv_xname, name); 2683 rt2661_stop(ifp, 1); 2684 return EIO; 2685 } 2686 2687 size = firmware_get_size(fh); 2688 if (!(ucode = firmware_malloc(size))) { 2689 printf("%s: could not alloc microcode memory\n", 2690 sc->sc_dev.dv_xname); 2691 firmware_close(fh); 2692 rt2661_stop(ifp, 1); 2693 return ENOMEM; 2694 } 2695 2696 if (firmware_read(fh, 0, ucode, size) != 0) { 2697 printf("%s: could not read microcode %s\n", 2698 sc->sc_dev.dv_xname, name); 2699 firmware_free(ucode, 0); 2700 firmware_close(fh); 2701 rt2661_stop(ifp, 1); 2702 return EIO; 2703 } 2704 2705 if (rt2661_load_microcode(sc, ucode, size) != 0) { 2706 printf("%s: could not load 8051 microcode\n", 2707 sc->sc_dev.dv_xname); 2708 firmware_free(ucode, 0); 2709 firmware_close(fh); 2710 rt2661_stop(ifp, 1); 2711 return EIO; 2712 } 2713 2714 firmware_free(ucode, 0); 2715 firmware_close(fh); 2716 sc->sc_flags |= RT2661_FWLOADED; 2717 } 2718 2719 /* initialize Tx rings */ 2720 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2721 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2722 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2723 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2724 2725 /* initialize Mgt ring */ 2726 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2727 2728 /* initialize Rx ring */ 2729 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2730 2731 /* initialize Tx rings sizes */ 2732 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2733 RT2661_TX_RING_COUNT << 24 | 2734 RT2661_TX_RING_COUNT << 16 | 2735 RT2661_TX_RING_COUNT << 8 | 2736 RT2661_TX_RING_COUNT); 2737 2738 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2739 RT2661_TX_DESC_WSIZE << 16 | 2740 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2741 RT2661_MGT_RING_COUNT); 2742 2743 /* initialize Rx rings */ 2744 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2745 RT2661_RX_DESC_BACK << 16 | 2746 RT2661_RX_DESC_WSIZE << 8 | 2747 RT2661_RX_RING_COUNT); 2748 2749 /* XXX: some magic here */ 2750 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2751 2752 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2753 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2754 2755 /* load base address of Rx ring */ 2756 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2757 2758 /* initialize MAC registers to default values */ 2759 for (i = 0; i < N(rt2661_def_mac); i++) 2760 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2761 2762 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2763 rt2661_set_macaddr(sc, ic->ic_myaddr); 2764 2765 /* set host ready */ 2766 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2767 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2768 2769 /* wait for BBP/RF to wakeup */ 2770 for (ntries = 0; ntries < 1000; ntries++) { 2771 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2772 break; 2773 DELAY(1000); 2774 } 2775 if (ntries == 1000) { 2776 printf("timeout waiting for BBP/RF to wakeup\n"); 2777 rt2661_stop(ifp, 1); 2778 return EIO; 2779 } 2780 2781 if (rt2661_bbp_init(sc) != 0) { 2782 rt2661_stop(ifp, 1); 2783 return EIO; 2784 } 2785 2786 /* select default channel */ 2787 sc->sc_curchan = ic->ic_curchan; 2788 rt2661_select_band(sc, sc->sc_curchan); 2789 rt2661_select_antenna(sc); 2790 rt2661_set_chan(sc, sc->sc_curchan); 2791 2792 /* update Rx filter */ 2793 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2794 2795 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2796 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2797 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2798 RT2661_DROP_ACKCTS; 2799 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2800 tmp |= RT2661_DROP_TODS; 2801 if (!(ifp->if_flags & IFF_PROMISC)) 2802 tmp |= RT2661_DROP_NOT_TO_ME; 2803 } 2804 2805 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2806 2807 /* clear STA registers */ 2808 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, star, N(star)); 2809 2810 /* initialize ASIC */ 2811 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2812 2813 /* clear any pending interrupt */ 2814 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2815 2816 /* enable interrupts */ 2817 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2818 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2819 2820 /* kick Rx */ 2821 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2822 2823 ifp->if_flags &= ~IFF_OACTIVE; 2824 ifp->if_flags |= IFF_RUNNING; 2825 2826 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2827 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2828 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2829 } else 2830 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2831 2832 return 0; 2833 #undef N 2834 } 2835 2836 static void 2837 rt2661_stop(struct ifnet *ifp, int disable) 2838 { 2839 struct rt2661_softc *sc = ifp->if_softc; 2840 struct ieee80211com *ic = &sc->sc_ic; 2841 uint32_t tmp; 2842 2843 sc->sc_tx_timer = 0; 2844 ifp->if_timer = 0; 2845 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2846 2847 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2848 2849 /* abort Tx (for all 5 Tx rings) */ 2850 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2851 2852 /* disable Rx (value remains after reset!) */ 2853 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2854 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2855 2856 /* reset ASIC */ 2857 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2858 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2859 2860 /* disable interrupts */ 2861 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2862 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2863 2864 /* clear any pending interrupt */ 2865 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2866 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2867 2868 /* reset Tx and Rx rings */ 2869 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2870 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2871 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2872 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2873 rt2661_reset_tx_ring(sc, &sc->mgtq); 2874 rt2661_reset_rx_ring(sc, &sc->rxq); 2875 2876 /* for CardBus, power down the socket */ 2877 if (disable && sc->sc_disable != NULL) { 2878 if (sc->sc_flags & RT2661_ENABLED) { 2879 (*sc->sc_disable)(sc); 2880 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2881 } 2882 } 2883 } 2884 2885 static int 2886 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2887 { 2888 int ntries; 2889 2890 /* reset 8051 */ 2891 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2892 2893 /* cancel any pending Host to MCU command */ 2894 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2895 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2896 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2897 2898 /* write 8051's microcode */ 2899 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2900 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2901 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2902 2903 /* kick 8051's ass */ 2904 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2905 2906 /* wait for 8051 to initialize */ 2907 for (ntries = 0; ntries < 500; ntries++) { 2908 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2909 break; 2910 DELAY(100); 2911 } 2912 if (ntries == 500) { 2913 printf("timeout waiting for MCU to initialize\n"); 2914 return EIO; 2915 } 2916 return 0; 2917 } 2918 2919 #ifdef notyet 2920 /* 2921 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2922 * false CCA count. This function is called periodically (every seconds) when 2923 * in the RUN state. Values taken from the reference driver. 2924 */ 2925 static void 2926 rt2661_rx_tune(struct rt2661_softc *sc) 2927 { 2928 uint8_t bbp17; 2929 uint16_t cca; 2930 int lo, hi, dbm; 2931 2932 /* 2933 * Tuning range depends on operating band and on the presence of an 2934 * external low-noise amplifier. 2935 */ 2936 lo = 0x20; 2937 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2938 lo += 0x08; 2939 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2940 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2941 lo += 0x10; 2942 hi = lo + 0x20; 2943 2944 /* retrieve false CCA count since last call (clear on read) */ 2945 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2946 2947 if (dbm >= -35) { 2948 bbp17 = 0x60; 2949 } else if (dbm >= -58) { 2950 bbp17 = hi; 2951 } else if (dbm >= -66) { 2952 bbp17 = lo + 0x10; 2953 } else if (dbm >= -74) { 2954 bbp17 = lo + 0x08; 2955 } else { 2956 /* RSSI < -74dBm, tune using false CCA count */ 2957 2958 bbp17 = sc->bbp17; /* current value */ 2959 2960 hi -= 2 * (-74 - dbm); 2961 if (hi < lo) 2962 hi = lo; 2963 2964 if (bbp17 > hi) { 2965 bbp17 = hi; 2966 2967 } else if (cca > 512) { 2968 if (++bbp17 > hi) 2969 bbp17 = hi; 2970 } else if (cca < 100) { 2971 if (--bbp17 < lo) 2972 bbp17 = lo; 2973 } 2974 } 2975 2976 if (bbp17 != sc->bbp17) { 2977 rt2661_bbp_write(sc, 17, bbp17); 2978 sc->bbp17 = bbp17; 2979 } 2980 } 2981 2982 /* 2983 * Enter/Leave radar detection mode. 2984 * This is for 802.11h additional regulatory domains. 2985 */ 2986 static void 2987 rt2661_radar_start(struct rt2661_softc *sc) 2988 { 2989 uint32_t tmp; 2990 2991 /* disable Rx */ 2992 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2993 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2994 2995 rt2661_bbp_write(sc, 82, 0x20); 2996 rt2661_bbp_write(sc, 83, 0x00); 2997 rt2661_bbp_write(sc, 84, 0x40); 2998 2999 /* save current BBP registers values */ 3000 sc->bbp18 = rt2661_bbp_read(sc, 18); 3001 sc->bbp21 = rt2661_bbp_read(sc, 21); 3002 sc->bbp22 = rt2661_bbp_read(sc, 22); 3003 sc->bbp16 = rt2661_bbp_read(sc, 16); 3004 sc->bbp17 = rt2661_bbp_read(sc, 17); 3005 sc->bbp64 = rt2661_bbp_read(sc, 64); 3006 3007 rt2661_bbp_write(sc, 18, 0xff); 3008 rt2661_bbp_write(sc, 21, 0x3f); 3009 rt2661_bbp_write(sc, 22, 0x3f); 3010 rt2661_bbp_write(sc, 16, 0xbd); 3011 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 3012 rt2661_bbp_write(sc, 64, 0x21); 3013 3014 /* restore Rx filter */ 3015 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 3016 } 3017 3018 static int 3019 rt2661_radar_stop(struct rt2661_softc *sc) 3020 { 3021 uint8_t bbp66; 3022 3023 /* read radar detection result */ 3024 bbp66 = rt2661_bbp_read(sc, 66); 3025 3026 /* restore BBP registers values */ 3027 rt2661_bbp_write(sc, 16, sc->bbp16); 3028 rt2661_bbp_write(sc, 17, sc->bbp17); 3029 rt2661_bbp_write(sc, 18, sc->bbp18); 3030 rt2661_bbp_write(sc, 21, sc->bbp21); 3031 rt2661_bbp_write(sc, 22, sc->bbp22); 3032 rt2661_bbp_write(sc, 64, sc->bbp64); 3033 3034 return bbp66 == 1; 3035 } 3036 #endif 3037 3038 static int 3039 rt2661_prepare_beacon(struct rt2661_softc *sc) 3040 { 3041 struct ieee80211com *ic = &sc->sc_ic; 3042 struct rt2661_tx_desc desc; 3043 struct mbuf *m0; 3044 struct ieee80211_beacon_offsets bo; 3045 int rate; 3046 3047 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 3048 3049 if (m0 == NULL) { 3050 printf("%s: could not allocate beacon frame\n", 3051 sc->sc_dev.dv_xname); 3052 return ENOBUFS; 3053 } 3054 3055 /* send beacons at the lowest available rate */ 3056 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2; 3057 3058 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 3059 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 3060 3061 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 3062 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 3063 3064 /* copy beacon header and payload into NIC memory */ 3065 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 3066 mtod(m0, uint8_t *), m0->m_pkthdr.len); 3067 3068 m_freem(m0); 3069 3070 return 0; 3071 } 3072 3073 /* 3074 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 3075 * and HostAP operating modes. 3076 */ 3077 static void 3078 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 3079 { 3080 struct ieee80211com *ic = &sc->sc_ic; 3081 uint32_t tmp; 3082 3083 if (ic->ic_opmode != IEEE80211_M_STA) { 3084 /* 3085 * Change default 16ms TBTT adjustment to 8ms. 3086 * Must be done before enabling beacon generation. 3087 */ 3088 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 3089 } 3090 3091 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 3092 3093 /* set beacon interval (in 1/16ms unit) */ 3094 tmp |= ic->ic_bss->ni_intval * 16; 3095 3096 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 3097 if (ic->ic_opmode == IEEE80211_M_STA) 3098 tmp |= RT2661_TSF_MODE(1); 3099 else 3100 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 3101 3102 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 3103 } 3104 3105 /* 3106 * Retrieve the "Received Signal Strength Indicator" from the raw values 3107 * contained in Rx descriptors. The computation depends on which band the 3108 * frame was received. Correction values taken from the reference driver. 3109 */ 3110 static int 3111 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 3112 { 3113 int lna, agc, rssi; 3114 3115 lna = (raw >> 5) & 0x3; 3116 agc = raw & 0x1f; 3117 3118 rssi = 2 * agc; 3119 3120 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3121 rssi += sc->rssi_2ghz_corr; 3122 3123 if (lna == 1) 3124 rssi -= 64; 3125 else if (lna == 2) 3126 rssi -= 74; 3127 else if (lna == 3) 3128 rssi -= 90; 3129 } else { 3130 rssi += sc->rssi_5ghz_corr; 3131 3132 if (lna == 1) 3133 rssi -= 64; 3134 else if (lna == 2) 3135 rssi -= 86; 3136 else if (lna == 3) 3137 rssi -= 100; 3138 } 3139 return rssi; 3140 } 3141
Indexes created Tue Sep 23 07:09:52 GMT 2025