rt2661.c revision 1.22
1 /* $NetBSD: rt2661.c,v 1.22 2008/03/17 17:22:49 xtraeme Exp $ */ 2 /* $OpenBSD: rt2661.c,v 1.17 2006/05/01 08:41:11 damien Exp $ */ 3 /* $FreeBSD: rt2560.c,v 1.5 2006/06/02 19:59:31 csjp Exp $ */ 4 5 /*- 6 * Copyright (c) 2006 7 * Damien Bergamini <damien.bergamini (at) free.fr> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2661.c,v 1.22 2008/03/17 17:22:49 xtraeme Exp $"); 29 30 #include "bpfilter.h" 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/device.h> 43 44 #include <sys/bus.h> 45 #include <machine/endian.h> 46 #include <sys/intr.h> 47 48 #if NBPFILTER > 0 49 #include <net/bpf.h> 50 #endif 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_ether.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 63 #include <net80211/ieee80211_var.h> 64 #include <net80211/ieee80211_rssadapt.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #include <dev/ic/rt2661reg.h> 68 #include <dev/ic/rt2661var.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <dev/firmload.h> 75 76 #ifdef RAL_DEBUG 77 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 78 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 79 int rt2661_debug = 0; 80 #else 81 #define DPRINTF(x) 82 #define DPRINTFN(n, x) 83 #endif 84 85 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 86 struct rt2661_tx_ring *, int); 87 static void rt2661_reset_tx_ring(struct rt2661_softc *, 88 struct rt2661_tx_ring *); 89 static void rt2661_free_tx_ring(struct rt2661_softc *, 90 struct rt2661_tx_ring *); 91 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 92 struct rt2661_rx_ring *, int); 93 static void rt2661_reset_rx_ring(struct rt2661_softc *, 94 struct rt2661_rx_ring *); 95 static void rt2661_free_rx_ring(struct rt2661_softc *, 96 struct rt2661_rx_ring *); 97 static struct ieee80211_node * 98 rt2661_node_alloc(struct ieee80211_node_table *); 99 static int rt2661_media_change(struct ifnet *); 100 static void rt2661_next_scan(void *); 101 static void rt2661_iter_func(void *, struct ieee80211_node *); 102 static void rt2661_rssadapt_updatestats(void *); 103 static int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 104 int); 105 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 106 static void rt2661_tx_intr(struct rt2661_softc *); 107 static void rt2661_tx_dma_intr(struct rt2661_softc *, 108 struct rt2661_tx_ring *); 109 static void rt2661_rx_intr(struct rt2661_softc *); 110 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 111 static void rt2661_mcu_wakeup(struct rt2661_softc *); 112 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 113 int rt2661_intr(void *); 114 #if NBPFILTER > 0 115 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 116 #endif 117 static int rt2661_ack_rate(struct ieee80211com *, int); 118 static uint16_t rt2661_txtime(int, int, uint32_t); 119 static uint8_t rt2661_plcp_signal(int); 120 static void rt2661_setup_tx_desc(struct rt2661_softc *, 121 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 122 const bus_dma_segment_t *, int, int); 123 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 124 struct ieee80211_node *); 125 static struct mbuf * 126 rt2661_get_rts(struct rt2661_softc *, 127 struct ieee80211_frame *, uint16_t); 128 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 129 struct ieee80211_node *, int); 130 static void rt2661_start(struct ifnet *); 131 static void rt2661_watchdog(struct ifnet *); 132 static int rt2661_reset(struct ifnet *); 133 static int rt2661_ioctl(struct ifnet *, u_long, void *); 134 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 135 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 136 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 137 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 138 static void rt2661_select_antenna(struct rt2661_softc *); 139 static void rt2661_enable_mrr(struct rt2661_softc *); 140 static void rt2661_set_txpreamble(struct rt2661_softc *); 141 static void rt2661_set_basicrates(struct rt2661_softc *, 142 const struct ieee80211_rateset *); 143 static void rt2661_select_band(struct rt2661_softc *, 144 struct ieee80211_channel *); 145 static void rt2661_set_chan(struct rt2661_softc *, 146 struct ieee80211_channel *); 147 static void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 148 static void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 149 static void rt2661_update_promisc(struct rt2661_softc *); 150 #if 0 151 static int rt2661_wme_update(struct ieee80211com *); 152 #endif 153 154 static void rt2661_update_slot(struct ifnet *); 155 static const char * 156 rt2661_get_rf(int); 157 static void rt2661_read_eeprom(struct rt2661_softc *); 158 static int rt2661_bbp_init(struct rt2661_softc *); 159 static int rt2661_init(struct ifnet *); 160 static void rt2661_stop(struct ifnet *, int); 161 static int rt2661_load_microcode(struct rt2661_softc *, const uint8_t *, 162 int); 163 #ifdef notyet 164 static void rt2661_rx_tune(struct rt2661_softc *); 165 static void rt2661_radar_start(struct rt2661_softc *); 166 static int rt2661_radar_stop(struct rt2661_softc *); 167 #endif 168 static int rt2661_prepare_beacon(struct rt2661_softc *); 169 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 170 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 171 172 /* 173 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 174 */ 175 static const struct ieee80211_rateset rt2661_rateset_11a = 176 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 177 178 static const struct ieee80211_rateset rt2661_rateset_11b = 179 { 4, { 2, 4, 11, 22 } }; 180 181 static const struct ieee80211_rateset rt2661_rateset_11g = 182 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 183 184 /* 185 * Default values for MAC registers; values taken from the reference driver. 186 */ 187 static const struct { 188 uint32_t reg; 189 uint32_t val; 190 } rt2661_def_mac[] = { 191 { RT2661_TXRX_CSR0, 0x0000b032 }, 192 { RT2661_TXRX_CSR1, 0x9eb39eb3 }, 193 { RT2661_TXRX_CSR2, 0x8a8b8c8d }, 194 { RT2661_TXRX_CSR3, 0x00858687 }, 195 { RT2661_TXRX_CSR7, 0x2e31353b }, 196 { RT2661_TXRX_CSR8, 0x2a2a2a2c }, 197 { RT2661_TXRX_CSR15, 0x0000000f }, 198 { RT2661_MAC_CSR6, 0x00000fff }, 199 { RT2661_MAC_CSR8, 0x016c030a }, 200 { RT2661_MAC_CSR10, 0x00000718 }, 201 { RT2661_MAC_CSR12, 0x00000004 }, 202 { RT2661_MAC_CSR13, 0x0000e000 }, 203 { RT2661_SEC_CSR0, 0x00000000 }, 204 { RT2661_SEC_CSR1, 0x00000000 }, 205 { RT2661_SEC_CSR5, 0x00000000 }, 206 { RT2661_PHY_CSR1, 0x000023b0 }, 207 { RT2661_PHY_CSR5, 0x060a100c }, 208 { RT2661_PHY_CSR6, 0x00080606 }, 209 { RT2661_PHY_CSR7, 0x00000a08 }, 210 { RT2661_PCI_CFG_CSR, 0x3cca4808 }, 211 { RT2661_AIFSN_CSR, 0x00002273 }, 212 { RT2661_CWMIN_CSR, 0x00002344 }, 213 { RT2661_CWMAX_CSR, 0x000034aa }, 214 { RT2661_TEST_MODE_CSR, 0x00000200 }, 215 { RT2661_M2H_CMD_DONE_CSR, 0xffffffff } 216 }; 217 218 /* 219 * Default values for BBP registers; values taken from the reference driver. 220 */ 221 static const struct { 222 uint8_t reg; 223 uint8_t val; 224 } rt2661_def_bbp[] = { 225 { 3, 0x00 }, 226 { 15, 0x30 }, 227 { 17, 0x20 }, 228 { 21, 0xc8 }, 229 { 22, 0x38 }, 230 { 23, 0x06 }, 231 { 24, 0xfe }, 232 { 25, 0x0a }, 233 { 26, 0x0d }, 234 { 34, 0x12 }, 235 { 37, 0x07 }, 236 { 39, 0xf8 }, 237 { 41, 0x60 }, 238 { 53, 0x10 }, 239 { 54, 0x18 }, 240 { 60, 0x10 }, 241 { 61, 0x04 }, 242 { 62, 0x04 }, 243 { 75, 0xfe }, 244 { 86, 0xfe }, 245 { 88, 0xfe }, 246 { 90, 0x0f }, 247 { 99, 0x00 }, 248 { 102, 0x16 }, 249 { 107, 0x04 } 250 }; 251 252 /* 253 * Default settings for RF registers; values taken from the reference driver. 254 */ 255 static const struct rfprog { 256 uint8_t chan; 257 uint32_t r1; 258 uint32_t r2; 259 uint32_t r3; 260 uint32_t r4; 261 } rt2661_rf5225_1[] = { 262 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, 263 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, 264 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, 265 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, 266 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, 267 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, 268 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, 269 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, 270 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, 271 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, 272 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, 273 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, 274 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, 275 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, 276 277 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, 278 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, 279 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, 280 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, 281 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, 282 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, 283 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, 284 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, 285 286 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, 287 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, 288 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, 289 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, 290 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, 291 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, 292 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, 293 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, 294 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, 295 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, 296 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, 297 298 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, 299 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, 300 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, 301 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, 302 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } 303 304 }, rt2661_rf5225_2[] = { 305 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, 306 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, 307 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, 308 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, 309 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, 310 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, 311 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, 312 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, 313 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, 314 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, 315 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, 316 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, 317 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, 318 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, 319 320 { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, 321 { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, 322 { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, 323 { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, 324 { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, 325 { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, 326 { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, 327 { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, 328 329 { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, 330 { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, 331 { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, 332 { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, 333 { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, 334 { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, 335 { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, 336 { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, 337 { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, 338 { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, 339 { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, 340 341 { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, 342 { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, 343 { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, 344 { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, 345 { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 } 346 }; 347 348 int 349 rt2661_attach(void *xsc, int id) 350 { 351 struct rt2661_softc *sc = xsc; 352 struct ieee80211com *ic = &sc->sc_ic; 353 struct ifnet *ifp = &sc->sc_if; 354 uint32_t val; 355 int error, i, ntries; 356 357 sc->sc_id = id; 358 359 callout_init(&sc->scan_ch, 0); 360 callout_init(&sc->rssadapt_ch, 0); 361 362 /* wait for NIC to initialize */ 363 for (ntries = 0; ntries < 1000; ntries++) { 364 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 365 break; 366 DELAY(1000); 367 } 368 if (ntries == 1000) { 369 aprint_error("%s: timeout waiting for NIC to initialize\n", 370 sc->sc_dev.dv_xname); 371 return EIO; 372 } 373 374 /* retrieve RF rev. no and various other things from EEPROM */ 375 rt2661_read_eeprom(sc); 376 aprint_normal("%s: 802.11 address %s\n", sc->sc_dev.dv_xname, 377 ether_sprintf(ic->ic_myaddr)); 378 379 aprint_normal("%s: MAC/BBP RT%X, RF %s\n", sc->sc_dev.dv_xname, val, 380 rt2661_get_rf(sc->rf_rev)); 381 382 /* 383 * Allocate Tx and Rx rings. 384 */ 385 error = rt2661_alloc_tx_ring(sc, &sc->txq[0], RT2661_TX_RING_COUNT); 386 if (error != 0) { 387 aprint_error("%s: could not allocate Tx ring 0\n", 388 sc->sc_dev.dv_xname); 389 goto fail1; 390 } 391 392 error = rt2661_alloc_tx_ring(sc, &sc->txq[1], RT2661_TX_RING_COUNT); 393 if (error != 0) { 394 aprint_error("%s: could not allocate Tx ring 1\n", 395 sc->sc_dev.dv_xname); 396 goto fail2; 397 } 398 399 error = rt2661_alloc_tx_ring(sc, &sc->txq[2], RT2661_TX_RING_COUNT); 400 if (error != 0) { 401 aprint_error("%s: could not allocate Tx ring 2\n", 402 sc->sc_dev.dv_xname); 403 goto fail3; 404 } 405 406 error = rt2661_alloc_tx_ring(sc, &sc->txq[3], RT2661_TX_RING_COUNT); 407 if (error != 0) { 408 aprint_error("%s: could not allocate Tx ring 3\n", 409 sc->sc_dev.dv_xname); 410 goto fail4; 411 } 412 413 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 414 if (error != 0) { 415 aprint_error("%s: could not allocate Mgt ring\n", 416 sc->sc_dev.dv_xname); 417 goto fail5; 418 } 419 420 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 421 if (error != 0) { 422 aprint_error("%s: could not allocate Rx ring\n", 423 sc->sc_dev.dv_xname); 424 goto fail6; 425 } 426 427 ifp->if_softc = sc; 428 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 429 ifp->if_init = rt2661_init; 430 ifp->if_stop = rt2661_stop; 431 ifp->if_ioctl = rt2661_ioctl; 432 ifp->if_start = rt2661_start; 433 ifp->if_watchdog = rt2661_watchdog; 434 IFQ_SET_READY(&ifp->if_snd); 435 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 436 437 ic->ic_ifp = ifp; 438 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 439 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 440 ic->ic_state = IEEE80211_S_INIT; 441 442 /* set device capabilities */ 443 ic->ic_caps = 444 IEEE80211_C_IBSS | /* IBSS mode supported */ 445 IEEE80211_C_MONITOR | /* monitor mode supported */ 446 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 447 IEEE80211_C_TXPMGT | /* tx power management */ 448 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 449 IEEE80211_C_SHSLOT | /* short slot time supported */ 450 IEEE80211_C_WPA; /* 802.11i */ 451 452 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 453 /* set supported .11a rates */ 454 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 455 456 /* set supported .11a channels */ 457 for (i = 36; i <= 64; i += 4) { 458 ic->ic_channels[i].ic_freq = 459 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 460 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 461 } 462 for (i = 100; i <= 140; i += 4) { 463 ic->ic_channels[i].ic_freq = 464 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 465 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 466 } 467 for (i = 149; i <= 165; i += 4) { 468 ic->ic_channels[i].ic_freq = 469 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 470 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 471 } 472 } 473 474 /* set supported .11b and .11g rates */ 475 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 476 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 477 478 /* set supported .11b and .11g channels (1 through 14) */ 479 for (i = 1; i <= 14; i++) { 480 ic->ic_channels[i].ic_freq = 481 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 482 ic->ic_channels[i].ic_flags = 483 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 484 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 485 } 486 487 if_attach(ifp); 488 ieee80211_ifattach(ic); 489 ic->ic_node_alloc = rt2661_node_alloc; 490 ic->ic_updateslot = rt2661_update_slot; 491 ic->ic_reset = rt2661_reset; 492 493 /* override state transition machine */ 494 sc->sc_newstate = ic->ic_newstate; 495 ic->ic_newstate = rt2661_newstate; 496 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 497 498 #if NBPFILTER > 0 499 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 500 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 501 502 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 503 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 504 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 505 506 sc->sc_txtap_len = sizeof sc->sc_txtapu; 507 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 508 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 509 #endif 510 511 ieee80211_announce(ic); 512 513 if (!pmf_device_register(&sc->sc_dev, NULL, NULL)) 514 aprint_error_dev(&sc->sc_dev, "couldn't establish power handler\n"); 515 else 516 pmf_class_network_register(&sc->sc_dev, ifp); 517 518 return 0; 519 520 fail6: rt2661_free_tx_ring(sc, &sc->mgtq); 521 fail5: rt2661_free_tx_ring(sc, &sc->txq[3]); 522 fail4: rt2661_free_tx_ring(sc, &sc->txq[2]); 523 fail3: rt2661_free_tx_ring(sc, &sc->txq[1]); 524 fail2: rt2661_free_tx_ring(sc, &sc->txq[0]); 525 fail1: return ENXIO; 526 } 527 528 int 529 rt2661_detach(void *xsc) 530 { 531 struct rt2661_softc *sc = xsc; 532 struct ifnet *ifp = &sc->sc_if; 533 534 callout_stop(&sc->scan_ch); 535 callout_stop(&sc->rssadapt_ch); 536 537 pmf_device_deregister(&sc->sc_dev); 538 539 ieee80211_ifdetach(&sc->sc_ic); 540 if_detach(ifp); 541 542 rt2661_free_tx_ring(sc, &sc->txq[0]); 543 rt2661_free_tx_ring(sc, &sc->txq[1]); 544 rt2661_free_tx_ring(sc, &sc->txq[2]); 545 rt2661_free_tx_ring(sc, &sc->txq[3]); 546 rt2661_free_tx_ring(sc, &sc->mgtq); 547 rt2661_free_rx_ring(sc, &sc->rxq); 548 549 return 0; 550 } 551 552 static int 553 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 554 int count) 555 { 556 int i, nsegs, error; 557 558 ring->count = count; 559 ring->queued = 0; 560 ring->cur = ring->next = ring->stat = 0; 561 562 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 563 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 564 if (error != 0) { 565 aprint_error("%s: could not create desc DMA map\n", 566 sc->sc_dev.dv_xname); 567 goto fail; 568 } 569 570 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 571 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 572 if (error != 0) { 573 aprint_error("%s: could not allocate DMA memory\n", 574 sc->sc_dev.dv_xname); 575 goto fail; 576 } 577 578 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 579 count * RT2661_TX_DESC_SIZE, (void **)&ring->desc, 580 BUS_DMA_NOWAIT); 581 if (error != 0) { 582 aprint_error("%s: could not map desc DMA memory\n", 583 sc->sc_dev.dv_xname); 584 goto fail; 585 } 586 587 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 588 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 589 if (error != 0) { 590 aprint_error("%s: could not load desc DMA map\n", 591 sc->sc_dev.dv_xname); 592 goto fail; 593 } 594 595 memset(ring->desc, 0, count * RT2661_TX_DESC_SIZE); 596 ring->physaddr = ring->map->dm_segs->ds_addr; 597 598 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 599 M_NOWAIT); 600 if (ring->data == NULL) { 601 aprint_error("%s: could not allocate soft data\n", 602 sc->sc_dev.dv_xname); 603 error = ENOMEM; 604 goto fail; 605 } 606 607 memset(ring->data, 0, count * sizeof (struct rt2661_tx_data)); 608 for (i = 0; i < count; i++) { 609 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 610 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 611 &ring->data[i].map); 612 if (error != 0) { 613 aprint_error("%s: could not create DMA map\n", 614 sc->sc_dev.dv_xname); 615 goto fail; 616 } 617 } 618 619 return 0; 620 621 fail: rt2661_free_tx_ring(sc, ring); 622 return error; 623 } 624 625 static void 626 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 627 { 628 struct rt2661_tx_desc *desc; 629 struct rt2661_tx_data *data; 630 int i; 631 632 for (i = 0; i < ring->count; i++) { 633 desc = &ring->desc[i]; 634 data = &ring->data[i]; 635 636 if (data->m != NULL) { 637 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 638 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 639 bus_dmamap_unload(sc->sc_dmat, data->map); 640 m_freem(data->m); 641 data->m = NULL; 642 } 643 644 if (data->ni != NULL) { 645 ieee80211_free_node(data->ni); 646 data->ni = NULL; 647 } 648 649 desc->flags = 0; 650 } 651 652 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 653 BUS_DMASYNC_PREWRITE); 654 655 ring->queued = 0; 656 ring->cur = ring->next = ring->stat = 0; 657 } 658 659 660 static void 661 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 662 { 663 struct rt2661_tx_data *data; 664 int i; 665 666 if (ring->desc != NULL) { 667 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 668 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 669 bus_dmamap_unload(sc->sc_dmat, ring->map); 670 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 671 ring->count * RT2661_TX_DESC_SIZE); 672 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 673 } 674 675 if (ring->data != NULL) { 676 for (i = 0; i < ring->count; i++) { 677 data = &ring->data[i]; 678 679 if (data->m != NULL) { 680 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 681 data->map->dm_mapsize, 682 BUS_DMASYNC_POSTWRITE); 683 bus_dmamap_unload(sc->sc_dmat, data->map); 684 m_freem(data->m); 685 } 686 687 if (data->ni != NULL) 688 ieee80211_free_node(data->ni); 689 690 if (data->map != NULL) 691 bus_dmamap_destroy(sc->sc_dmat, data->map); 692 } 693 free(ring->data, M_DEVBUF); 694 } 695 } 696 697 static int 698 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 699 int count) 700 { 701 struct rt2661_rx_desc *desc; 702 struct rt2661_rx_data *data; 703 int i, nsegs, error; 704 705 ring->count = count; 706 ring->cur = ring->next = 0; 707 708 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 709 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 710 if (error != 0) { 711 aprint_error("%s: could not create desc DMA map\n", 712 sc->sc_dev.dv_xname); 713 goto fail; 714 } 715 716 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 717 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 718 if (error != 0) { 719 aprint_error("%s: could not allocate DMA memory\n", 720 sc->sc_dev.dv_xname); 721 goto fail; 722 } 723 724 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 725 count * RT2661_RX_DESC_SIZE, (void **)&ring->desc, 726 BUS_DMA_NOWAIT); 727 if (error != 0) { 728 aprint_error("%s: could not map desc DMA memory\n", 729 sc->sc_dev.dv_xname); 730 goto fail; 731 } 732 733 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 734 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 735 if (error != 0) { 736 aprint_error("%s: could not load desc DMA map\n", 737 sc->sc_dev.dv_xname); 738 goto fail; 739 } 740 741 memset(ring->desc, 0, count * RT2661_RX_DESC_SIZE); 742 ring->physaddr = ring->map->dm_segs->ds_addr; 743 744 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 745 M_NOWAIT); 746 if (ring->data == NULL) { 747 aprint_error("%s: could not allocate soft data\n", 748 sc->sc_dev.dv_xname); 749 error = ENOMEM; 750 goto fail; 751 } 752 753 /* 754 * Pre-allocate Rx buffers and populate Rx ring. 755 */ 756 memset(ring->data, 0, count * sizeof (struct rt2661_rx_data)); 757 for (i = 0; i < count; i++) { 758 desc = &sc->rxq.desc[i]; 759 data = &sc->rxq.data[i]; 760 761 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 762 0, BUS_DMA_NOWAIT, &data->map); 763 if (error != 0) { 764 printf("%s: could not create DMA map\n", 765 sc->sc_dev.dv_xname); 766 goto fail; 767 } 768 769 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 770 if (data->m == NULL) { 771 printf("%s: could not allocate rx mbuf\n", 772 sc->sc_dev.dv_xname); 773 error = ENOMEM; 774 goto fail; 775 } 776 777 MCLGET(data->m, M_DONTWAIT); 778 if (!(data->m->m_flags & M_EXT)) { 779 printf("%s: could not allocate rx mbuf cluster\n", 780 sc->sc_dev.dv_xname); 781 error = ENOMEM; 782 goto fail; 783 } 784 785 error = bus_dmamap_load(sc->sc_dmat, data->map, 786 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 787 if (error != 0) { 788 printf("%s: could not load rx buf DMA map", 789 sc->sc_dev.dv_xname); 790 goto fail; 791 } 792 793 desc->flags = htole32(RT2661_RX_BUSY); 794 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 795 } 796 797 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 798 BUS_DMASYNC_PREWRITE); 799 800 return 0; 801 802 fail: rt2661_free_rx_ring(sc, ring); 803 return error; 804 } 805 806 static void 807 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 808 { 809 int i; 810 811 for (i = 0; i < ring->count; i++) 812 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 813 814 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 815 BUS_DMASYNC_PREWRITE); 816 817 ring->cur = ring->next = 0; 818 } 819 820 static void 821 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 822 { 823 struct rt2661_rx_data *data; 824 int i; 825 826 if (ring->desc != NULL) { 827 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 828 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 829 bus_dmamap_unload(sc->sc_dmat, ring->map); 830 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 831 ring->count * RT2661_RX_DESC_SIZE); 832 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 833 } 834 835 if (ring->data != NULL) { 836 for (i = 0; i < ring->count; i++) { 837 data = &ring->data[i]; 838 839 if (data->m != NULL) { 840 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 841 data->map->dm_mapsize, 842 BUS_DMASYNC_POSTREAD); 843 bus_dmamap_unload(sc->sc_dmat, data->map); 844 m_freem(data->m); 845 } 846 847 if (data->map != NULL) 848 bus_dmamap_destroy(sc->sc_dmat, data->map); 849 } 850 free(ring->data, M_DEVBUF); 851 } 852 } 853 854 static struct ieee80211_node * 855 rt2661_node_alloc(struct ieee80211_node_table *nt) 856 { 857 struct rt2661_node *rn; 858 859 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 860 M_NOWAIT | M_ZERO); 861 862 return (rn != NULL) ? &rn->ni : NULL; 863 } 864 865 static int 866 rt2661_media_change(struct ifnet *ifp) 867 { 868 int error; 869 870 error = ieee80211_media_change(ifp); 871 if (error != ENETRESET) 872 return error; 873 874 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 875 rt2661_init(ifp); 876 877 return 0; 878 } 879 880 /* 881 * This function is called periodically (every 200ms) during scanning to 882 * switch from one channel to another. 883 */ 884 static void 885 rt2661_next_scan(void *arg) 886 { 887 struct rt2661_softc *sc = arg; 888 struct ieee80211com *ic = &sc->sc_ic; 889 890 if (ic->ic_state == IEEE80211_S_SCAN) 891 ieee80211_next_scan(ic); 892 } 893 894 /* 895 * This function is called for each neighbor node. 896 */ 897 static void 898 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 899 { 900 struct rt2661_node *rn = (struct rt2661_node *)ni; 901 902 ieee80211_rssadapt_updatestats(&rn->rssadapt); 903 } 904 905 /* 906 * This function is called periodically (every 100ms) in RUN state to update 907 * the rate adaptation statistics. 908 */ 909 static void 910 rt2661_rssadapt_updatestats(void *arg) 911 { 912 struct rt2661_softc *sc = arg; 913 struct ieee80211com *ic = &sc->sc_ic; 914 915 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 916 917 callout_reset(&sc->rssadapt_ch, hz / 10, rt2661_rssadapt_updatestats, 918 sc); 919 } 920 921 static int 922 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 923 { 924 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 925 enum ieee80211_state ostate; 926 struct ieee80211_node *ni; 927 uint32_t tmp; 928 int error = 0; 929 930 ostate = ic->ic_state; 931 callout_stop(&sc->scan_ch); 932 933 switch (nstate) { 934 case IEEE80211_S_INIT: 935 callout_stop(&sc->rssadapt_ch); 936 937 if (ostate == IEEE80211_S_RUN) { 938 /* abort TSF synchronization */ 939 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 940 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 941 } 942 break; 943 944 case IEEE80211_S_SCAN: 945 rt2661_set_chan(sc, ic->ic_curchan); 946 callout_reset(&sc->scan_ch, hz / 5, rt2661_next_scan, sc); 947 break; 948 949 case IEEE80211_S_AUTH: 950 case IEEE80211_S_ASSOC: 951 rt2661_set_chan(sc, ic->ic_curchan); 952 break; 953 954 case IEEE80211_S_RUN: 955 rt2661_set_chan(sc, ic->ic_curchan); 956 957 ni = ic->ic_bss; 958 959 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 960 rt2661_enable_mrr(sc); 961 rt2661_set_txpreamble(sc); 962 rt2661_set_basicrates(sc, &ni->ni_rates); 963 rt2661_set_bssid(sc, ni->ni_bssid); 964 } 965 966 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 967 ic->ic_opmode == IEEE80211_M_IBSS) { 968 if ((error = rt2661_prepare_beacon(sc)) != 0) 969 break; 970 } 971 972 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 973 callout_reset(&sc->rssadapt_ch, hz / 10, 974 rt2661_rssadapt_updatestats, sc); 975 rt2661_enable_tsf_sync(sc); 976 } 977 break; 978 } 979 980 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 981 } 982 983 /* 984 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 985 * 93C66). 986 */ 987 static uint16_t 988 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 989 { 990 uint32_t tmp; 991 uint16_t val; 992 int n; 993 994 /* clock C once before the first command */ 995 RT2661_EEPROM_CTL(sc, 0); 996 997 RT2661_EEPROM_CTL(sc, RT2661_S); 998 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 999 RT2661_EEPROM_CTL(sc, RT2661_S); 1000 1001 /* write start bit (1) */ 1002 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 1003 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 1004 1005 /* write READ opcode (10) */ 1006 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 1007 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 1008 RT2661_EEPROM_CTL(sc, RT2661_S); 1009 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1010 1011 /* write address (A5-A0 or A7-A0) */ 1012 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 1013 for (; n >= 0; n--) { 1014 RT2661_EEPROM_CTL(sc, RT2661_S | 1015 (((addr >> n) & 1) << RT2661_SHIFT_D)); 1016 RT2661_EEPROM_CTL(sc, RT2661_S | 1017 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 1018 } 1019 1020 RT2661_EEPROM_CTL(sc, RT2661_S); 1021 1022 /* read data Q15-Q0 */ 1023 val = 0; 1024 for (n = 15; n >= 0; n--) { 1025 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1026 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 1027 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 1028 RT2661_EEPROM_CTL(sc, RT2661_S); 1029 } 1030 1031 RT2661_EEPROM_CTL(sc, 0); 1032 1033 /* clear Chip Select and clock C */ 1034 RT2661_EEPROM_CTL(sc, RT2661_S); 1035 RT2661_EEPROM_CTL(sc, 0); 1036 RT2661_EEPROM_CTL(sc, RT2661_C); 1037 1038 return val; 1039 } 1040 1041 static void 1042 rt2661_tx_intr(struct rt2661_softc *sc) 1043 { 1044 struct ieee80211com *ic = &sc->sc_ic; 1045 struct ifnet *ifp = &sc->sc_if; 1046 struct rt2661_tx_ring *txq; 1047 struct rt2661_tx_data *data; 1048 struct rt2661_node *rn; 1049 uint32_t val; 1050 int qid, retrycnt; 1051 1052 for (;;) { 1053 val = RAL_READ(sc, RT2661_STA_CSR4); 1054 if (!(val & RT2661_TX_STAT_VALID)) 1055 break; 1056 1057 /* retrieve the queue in which this frame was sent */ 1058 qid = RT2661_TX_QID(val); 1059 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 1060 1061 /* retrieve rate control algorithm context */ 1062 data = &txq->data[txq->stat]; 1063 rn = (struct rt2661_node *)data->ni; 1064 1065 /* if no frame has been sent, ignore */ 1066 if (rn == NULL) 1067 continue; 1068 1069 switch (RT2661_TX_RESULT(val)) { 1070 case RT2661_TX_SUCCESS: 1071 retrycnt = RT2661_TX_RETRYCNT(val); 1072 1073 DPRINTFN(10, ("data frame sent successfully after " 1074 "%d retries\n", retrycnt)); 1075 if (retrycnt == 0 && data->id.id_node != NULL) { 1076 ieee80211_rssadapt_raise_rate(ic, 1077 &rn->rssadapt, &data->id); 1078 } 1079 ifp->if_opackets++; 1080 break; 1081 1082 case RT2661_TX_RETRY_FAIL: 1083 DPRINTFN(9, ("sending data frame failed (too much " 1084 "retries)\n")); 1085 if (data->id.id_node != NULL) { 1086 ieee80211_rssadapt_lower_rate(ic, data->ni, 1087 &rn->rssadapt, &data->id); 1088 } 1089 ifp->if_oerrors++; 1090 break; 1091 1092 default: 1093 /* other failure */ 1094 printf("%s: sending data frame failed 0x%08x\n", 1095 sc->sc_dev.dv_xname, val); 1096 ifp->if_oerrors++; 1097 } 1098 1099 ieee80211_free_node(data->ni); 1100 data->ni = NULL; 1101 1102 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 1103 1104 txq->queued--; 1105 if (++txq->stat >= txq->count) /* faster than % count */ 1106 txq->stat = 0; 1107 } 1108 1109 sc->sc_tx_timer = 0; 1110 ifp->if_flags &= ~IFF_OACTIVE; 1111 rt2661_start(ifp); 1112 } 1113 1114 static void 1115 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1116 { 1117 struct rt2661_tx_desc *desc; 1118 struct rt2661_tx_data *data; 1119 1120 for (;;) { 1121 desc = &txq->desc[txq->next]; 1122 data = &txq->data[txq->next]; 1123 1124 bus_dmamap_sync(sc->sc_dmat, txq->map, 1125 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1126 BUS_DMASYNC_POSTREAD); 1127 1128 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1129 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1130 break; 1131 1132 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1133 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1134 bus_dmamap_unload(sc->sc_dmat, data->map); 1135 m_freem(data->m); 1136 data->m = NULL; 1137 /* node reference is released in rt2661_tx_intr() */ 1138 1139 /* descriptor is no longer valid */ 1140 desc->flags &= ~htole32(RT2661_TX_VALID); 1141 1142 bus_dmamap_sync(sc->sc_dmat, txq->map, 1143 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1144 BUS_DMASYNC_PREWRITE); 1145 1146 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1147 1148 if (++txq->next >= txq->count) /* faster than % count */ 1149 txq->next = 0; 1150 } 1151 } 1152 1153 static void 1154 rt2661_rx_intr(struct rt2661_softc *sc) 1155 { 1156 struct ieee80211com *ic = &sc->sc_ic; 1157 struct ifnet *ifp = &sc->sc_if; 1158 struct rt2661_rx_desc *desc; 1159 struct rt2661_rx_data *data; 1160 struct rt2661_node *rn; 1161 struct ieee80211_frame *wh; 1162 struct ieee80211_node *ni; 1163 struct mbuf *mnew, *m; 1164 int error; 1165 1166 for (;;) { 1167 desc = &sc->rxq.desc[sc->rxq.cur]; 1168 data = &sc->rxq.data[sc->rxq.cur]; 1169 1170 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1171 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1172 BUS_DMASYNC_POSTREAD); 1173 1174 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1175 break; 1176 1177 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1178 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1179 /* 1180 * This should not happen since we did not request 1181 * to receive those frames when we filled TXRX_CSR0. 1182 */ 1183 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1184 le32toh(desc->flags))); 1185 ifp->if_ierrors++; 1186 goto skip; 1187 } 1188 1189 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1190 ifp->if_ierrors++; 1191 goto skip; 1192 } 1193 1194 /* 1195 * Try to allocate a new mbuf for this ring element and load it 1196 * before processing the current mbuf. If the ring element 1197 * cannot be loaded, drop the received packet and reuse the old 1198 * mbuf. In the unlikely case that the old mbuf can't be 1199 * reloaded either, explicitly panic. 1200 */ 1201 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1202 if (mnew == NULL) { 1203 ifp->if_ierrors++; 1204 goto skip; 1205 } 1206 1207 MCLGET(mnew, M_DONTWAIT); 1208 if (!(mnew->m_flags & M_EXT)) { 1209 m_freem(mnew); 1210 ifp->if_ierrors++; 1211 goto skip; 1212 } 1213 1214 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1215 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1216 bus_dmamap_unload(sc->sc_dmat, data->map); 1217 1218 error = bus_dmamap_load(sc->sc_dmat, data->map, 1219 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1220 if (error != 0) { 1221 m_freem(mnew); 1222 1223 /* try to reload the old mbuf */ 1224 error = bus_dmamap_load(sc->sc_dmat, data->map, 1225 mtod(data->m, void *), MCLBYTES, NULL, 1226 BUS_DMA_NOWAIT); 1227 if (error != 0) { 1228 /* very unlikely that it will fail... */ 1229 panic("%s: could not load old rx mbuf", 1230 sc->sc_dev.dv_xname); 1231 } 1232 /* physical address may have changed */ 1233 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1234 ifp->if_ierrors++; 1235 goto skip; 1236 } 1237 1238 /* 1239 * New mbuf successfully loaded, update Rx ring and continue 1240 * processing. 1241 */ 1242 m = data->m; 1243 data->m = mnew; 1244 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1245 1246 /* finalize mbuf */ 1247 m->m_pkthdr.rcvif = ifp; 1248 m->m_pkthdr.len = m->m_len = 1249 (le32toh(desc->flags) >> 16) & 0xfff; 1250 1251 #if NBPFILTER > 0 1252 if (sc->sc_drvbpf != NULL) { 1253 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1254 uint32_t tsf_lo, tsf_hi; 1255 1256 /* get timestamp (low and high 32 bits) */ 1257 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1258 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1259 1260 tap->wr_tsf = 1261 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1262 tap->wr_flags = 0; 1263 tap->wr_rate = rt2661_rxrate(desc); 1264 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1265 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1266 tap->wr_antsignal = desc->rssi; 1267 1268 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1269 } 1270 #endif 1271 1272 wh = mtod(m, struct ieee80211_frame *); 1273 ni = ieee80211_find_rxnode(ic, 1274 (struct ieee80211_frame_min *)wh); 1275 1276 /* send the frame to the 802.11 layer */ 1277 ieee80211_input(ic, m, ni, desc->rssi, 0); 1278 1279 1280 /* give rssi to the rate adatation algorithm */ 1281 rn = (struct rt2661_node *)ni; 1282 ieee80211_rssadapt_input(ic, ni, &rn->rssadapt, 1283 rt2661_get_rssi(sc, desc->rssi)); 1284 1285 /* node is no longer needed */ 1286 ieee80211_free_node(ni); 1287 1288 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1289 1290 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1291 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1292 BUS_DMASYNC_PREWRITE); 1293 1294 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1295 1296 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1297 } 1298 1299 /* 1300 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 1301 * without calling if_start(). 1302 */ 1303 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 1304 rt2661_start(ifp); 1305 } 1306 1307 /* ARGSUSED */ 1308 static void 1309 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1310 { 1311 /* do nothing */ 1312 } 1313 1314 static void 1315 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1316 { 1317 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1318 1319 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1320 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1321 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1322 1323 /* send wakeup command to MCU */ 1324 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1325 } 1326 1327 static void 1328 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1329 { 1330 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1331 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1332 } 1333 1334 int 1335 rt2661_intr(void *arg) 1336 { 1337 struct rt2661_softc *sc = arg; 1338 struct ifnet *ifp = &sc->sc_if; 1339 uint32_t r1, r2; 1340 1341 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1342 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1343 if (r1 == 0 && r2 == 0) 1344 return 0; /* not for us */ 1345 1346 /* disable MAC and MCU interrupts */ 1347 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1348 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1349 1350 /* acknowledge interrupts */ 1351 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1352 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1353 1354 /* don't re-enable interrupts if we're shutting down */ 1355 if (!(ifp->if_flags & IFF_RUNNING)) 1356 return 0; 1357 1358 if (r1 & RT2661_MGT_DONE) 1359 rt2661_tx_dma_intr(sc, &sc->mgtq); 1360 1361 if (r1 & RT2661_RX_DONE) 1362 rt2661_rx_intr(sc); 1363 1364 if (r1 & RT2661_TX0_DMA_DONE) 1365 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1366 1367 if (r1 & RT2661_TX1_DMA_DONE) 1368 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1369 1370 if (r1 & RT2661_TX2_DMA_DONE) 1371 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1372 1373 if (r1 & RT2661_TX3_DMA_DONE) 1374 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1375 1376 if (r1 & RT2661_TX_DONE) 1377 rt2661_tx_intr(sc); 1378 1379 if (r2 & RT2661_MCU_CMD_DONE) 1380 rt2661_mcu_cmd_intr(sc); 1381 1382 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1383 rt2661_mcu_beacon_expire(sc); 1384 1385 if (r2 & RT2661_MCU_WAKEUP) 1386 rt2661_mcu_wakeup(sc); 1387 1388 /* re-enable MAC and MCU interrupts */ 1389 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1390 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1391 1392 return 1; 1393 } 1394 1395 /* quickly determine if a given rate is CCK or OFDM */ 1396 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1397 1398 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1399 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1400 1401 #define RAL_SIFS 10 /* us */ 1402 1403 /* 1404 * This function is only used by the Rx radiotap code. It returns the rate at 1405 * which a given frame was received. 1406 */ 1407 #if NBPFILTER > 0 1408 static uint8_t 1409 rt2661_rxrate(struct rt2661_rx_desc *desc) 1410 { 1411 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1412 /* reverse function of rt2661_plcp_signal */ 1413 switch (desc->rate & 0xf) { 1414 case 0xb: return 12; 1415 case 0xf: return 18; 1416 case 0xa: return 24; 1417 case 0xe: return 36; 1418 case 0x9: return 48; 1419 case 0xd: return 72; 1420 case 0x8: return 96; 1421 case 0xc: return 108; 1422 } 1423 } else { 1424 if (desc->rate == 10) 1425 return 2; 1426 if (desc->rate == 20) 1427 return 4; 1428 if (desc->rate == 55) 1429 return 11; 1430 if (desc->rate == 110) 1431 return 22; 1432 } 1433 return 2; /* should not get there */ 1434 } 1435 #endif 1436 1437 /* 1438 * Return the expected ack rate for a frame transmitted at rate `rate'. 1439 * XXX: this should depend on the destination node basic rate set. 1440 */ 1441 static int 1442 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1443 { 1444 switch (rate) { 1445 /* CCK rates */ 1446 case 2: 1447 return 2; 1448 case 4: 1449 case 11: 1450 case 22: 1451 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1452 1453 /* OFDM rates */ 1454 case 12: 1455 case 18: 1456 return 12; 1457 case 24: 1458 case 36: 1459 return 24; 1460 case 48: 1461 case 72: 1462 case 96: 1463 case 108: 1464 return 48; 1465 } 1466 1467 /* default to 1Mbps */ 1468 return 2; 1469 } 1470 1471 /* 1472 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1473 * The function automatically determines the operating mode depending on the 1474 * given rate. `flags' indicates whether short preamble is in use or not. 1475 */ 1476 static uint16_t 1477 rt2661_txtime(int len, int rate, uint32_t flags) 1478 { 1479 uint16_t txtime; 1480 1481 if (RAL_RATE_IS_OFDM(rate)) { 1482 /* IEEE Std 802.11a-1999, pp. 37 */ 1483 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1484 txtime = 16 + 4 + 4 * txtime + 6; 1485 } else { 1486 /* IEEE Std 802.11b-1999, pp. 28 */ 1487 txtime = (16 * len + rate - 1) / rate; 1488 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1489 txtime += 72 + 24; 1490 else 1491 txtime += 144 + 48; 1492 } 1493 return txtime; 1494 } 1495 1496 static uint8_t 1497 rt2661_plcp_signal(int rate) 1498 { 1499 switch (rate) { 1500 /* CCK rates (returned values are device-dependent) */ 1501 case 2: return 0x0; 1502 case 4: return 0x1; 1503 case 11: return 0x2; 1504 case 22: return 0x3; 1505 1506 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1507 case 12: return 0xb; 1508 case 18: return 0xf; 1509 case 24: return 0xa; 1510 case 36: return 0xe; 1511 case 48: return 0x9; 1512 case 72: return 0xd; 1513 case 96: return 0x8; 1514 case 108: return 0xc; 1515 1516 /* unsupported rates (should not get there) */ 1517 default: return 0xff; 1518 } 1519 } 1520 1521 static void 1522 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1523 uint32_t flags, uint16_t xflags, int len, int rate, 1524 const bus_dma_segment_t *segs, int nsegs, int ac) 1525 { 1526 struct ieee80211com *ic = &sc->sc_ic; 1527 uint16_t plcp_length; 1528 int i, remainder; 1529 1530 desc->flags = htole32(flags); 1531 desc->flags |= htole32(len << 16); 1532 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1533 1534 desc->xflags = htole16(xflags); 1535 desc->xflags |= htole16(nsegs << 13); 1536 1537 desc->wme = htole16( 1538 RT2661_QID(ac) | 1539 RT2661_AIFSN(2) | 1540 RT2661_LOGCWMIN(4) | 1541 RT2661_LOGCWMAX(10)); 1542 1543 /* 1544 * Remember in which queue this frame was sent. This field is driver 1545 * private data only. It will be made available by the NIC in STA_CSR4 1546 * on Tx interrupts. 1547 */ 1548 desc->qid = ac; 1549 1550 /* setup PLCP fields */ 1551 desc->plcp_signal = rt2661_plcp_signal(rate); 1552 desc->plcp_service = 4; 1553 1554 len += IEEE80211_CRC_LEN; 1555 if (RAL_RATE_IS_OFDM(rate)) { 1556 desc->flags |= htole32(RT2661_TX_OFDM); 1557 1558 plcp_length = len & 0xfff; 1559 desc->plcp_length_hi = plcp_length >> 6; 1560 desc->plcp_length_lo = plcp_length & 0x3f; 1561 } else { 1562 plcp_length = (16 * len + rate - 1) / rate; 1563 if (rate == 22) { 1564 remainder = (16 * len) % 22; 1565 if (remainder != 0 && remainder < 7) 1566 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1567 } 1568 desc->plcp_length_hi = plcp_length >> 8; 1569 desc->plcp_length_lo = plcp_length & 0xff; 1570 1571 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1572 desc->plcp_signal |= 0x08; 1573 } 1574 1575 /* RT2x61 supports scatter with up to 5 segments */ 1576 for (i = 0; i < nsegs; i++) { 1577 desc->addr[i] = htole32(segs[i].ds_addr); 1578 desc->len [i] = htole16(segs[i].ds_len); 1579 } 1580 } 1581 1582 static int 1583 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1584 struct ieee80211_node *ni) 1585 { 1586 struct ieee80211com *ic = &sc->sc_ic; 1587 struct rt2661_tx_desc *desc; 1588 struct rt2661_tx_data *data; 1589 struct ieee80211_frame *wh; 1590 struct ieee80211_key *k; 1591 uint16_t dur; 1592 uint32_t flags = 0; 1593 int rate, error; 1594 1595 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1596 data = &sc->mgtq.data[sc->mgtq.cur]; 1597 1598 /* send mgt frames at the lowest available rate */ 1599 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1600 1601 wh = mtod(m0, struct ieee80211_frame *); 1602 1603 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1604 k = ieee80211_crypto_encap(ic, ni, m0); 1605 if (k == NULL) { 1606 m_freem(m0); 1607 return ENOBUFS; 1608 } 1609 } 1610 1611 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1612 BUS_DMA_NOWAIT); 1613 if (error != 0) { 1614 printf("%s: could not map mbuf (error %d)\n", 1615 sc->sc_dev.dv_xname, error); 1616 m_freem(m0); 1617 return error; 1618 } 1619 1620 #if NBPFILTER > 0 1621 if (sc->sc_drvbpf != NULL) { 1622 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1623 1624 tap->wt_flags = 0; 1625 tap->wt_rate = rate; 1626 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1627 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1628 1629 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1630 } 1631 #endif 1632 1633 data->m = m0; 1634 data->ni = ni; 1635 1636 wh = mtod(m0, struct ieee80211_frame *); 1637 1638 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1639 flags |= RT2661_TX_NEED_ACK; 1640 1641 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1642 RAL_SIFS; 1643 *(uint16_t *)wh->i_dur = htole16(dur); 1644 1645 /* tell hardware to add timestamp in probe responses */ 1646 if ((wh->i_fc[0] & 1647 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1648 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1649 flags |= RT2661_TX_TIMESTAMP; 1650 } 1651 1652 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1653 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1654 RT2661_QID_MGT); 1655 1656 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1657 BUS_DMASYNC_PREWRITE); 1658 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1659 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1660 BUS_DMASYNC_PREWRITE); 1661 1662 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1663 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1664 1665 /* kick mgt */ 1666 sc->mgtq.queued++; 1667 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1668 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1669 1670 return 0; 1671 } 1672 1673 /* 1674 * Build a RTS control frame. 1675 */ 1676 static struct mbuf * 1677 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1678 uint16_t dur) 1679 { 1680 struct ieee80211_frame_rts *rts; 1681 struct mbuf *m; 1682 1683 MGETHDR(m, M_DONTWAIT, MT_DATA); 1684 if (m == NULL) { 1685 sc->sc_ic.ic_stats.is_tx_nobuf++; 1686 printf("%s: could not allocate RTS frame\n", 1687 sc->sc_dev.dv_xname); 1688 return NULL; 1689 } 1690 1691 rts = mtod(m, struct ieee80211_frame_rts *); 1692 1693 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1694 IEEE80211_FC0_SUBTYPE_RTS; 1695 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1696 *(uint16_t *)rts->i_dur = htole16(dur); 1697 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1698 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1699 1700 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1701 1702 return m; 1703 } 1704 1705 static int 1706 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1707 struct ieee80211_node *ni, int ac) 1708 { 1709 struct ieee80211com *ic = &sc->sc_ic; 1710 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1711 struct rt2661_tx_desc *desc; 1712 struct rt2661_tx_data *data; 1713 struct rt2661_node *rn; 1714 struct ieee80211_rateset *rs; 1715 struct ieee80211_frame *wh; 1716 struct ieee80211_key *k; 1717 struct mbuf *mnew; 1718 uint16_t dur; 1719 uint32_t flags = 0; 1720 int rate, error; 1721 1722 wh = mtod(m0, struct ieee80211_frame *); 1723 1724 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1725 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1726 rate = rs->rs_rates[ic->ic_fixed_rate]; 1727 } else { 1728 rs = &ni->ni_rates; 1729 rn = (struct rt2661_node *)ni; 1730 ni->ni_txrate = ieee80211_rssadapt_choose(&rn->rssadapt, rs, 1731 wh, m0->m_pkthdr.len, -1, NULL, 0); 1732 rate = rs->rs_rates[ni->ni_txrate]; 1733 } 1734 rate &= IEEE80211_RATE_VAL; 1735 1736 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1737 k = ieee80211_crypto_encap(ic, ni, m0); 1738 if (k == NULL) { 1739 m_freem(m0); 1740 return ENOBUFS; 1741 } 1742 1743 /* packet header may have moved, reset our local pointer */ 1744 wh = mtod(m0, struct ieee80211_frame *); 1745 } 1746 1747 /* 1748 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1749 * for directed frames only when the length of the MPDU is greater 1750 * than the length threshold indicated by [...]" ic_rtsthreshold. 1751 */ 1752 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1753 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1754 struct mbuf *m; 1755 int rtsrate, ackrate; 1756 1757 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1758 ackrate = rt2661_ack_rate(ic, rate); 1759 1760 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1761 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1762 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1763 3 * RAL_SIFS; 1764 1765 m = rt2661_get_rts(sc, wh, dur); 1766 1767 desc = &txq->desc[txq->cur]; 1768 data = &txq->data[txq->cur]; 1769 1770 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1771 BUS_DMA_NOWAIT); 1772 if (error != 0) { 1773 printf("%s: could not map mbuf (error %d)\n", 1774 sc->sc_dev.dv_xname, error); 1775 m_freem(m); 1776 m_freem(m0); 1777 return error; 1778 } 1779 1780 /* avoid multiple free() of the same node for each fragment */ 1781 ieee80211_ref_node(ni); 1782 1783 data->m = m; 1784 data->ni = ni; 1785 1786 /* RTS frames are not taken into account for rssadapt */ 1787 data->id.id_node = NULL; 1788 1789 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1790 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, 1791 data->map->dm_segs, data->map->dm_nsegs, ac); 1792 1793 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1794 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1795 bus_dmamap_sync(sc->sc_dmat, txq->map, 1796 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1797 BUS_DMASYNC_PREWRITE); 1798 1799 txq->queued++; 1800 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1801 1802 /* 1803 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1804 * asynchronous data frame shall be transmitted after the CTS 1805 * frame and a SIFS period. 1806 */ 1807 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1808 } 1809 1810 data = &txq->data[txq->cur]; 1811 desc = &txq->desc[txq->cur]; 1812 1813 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1814 BUS_DMA_NOWAIT); 1815 if (error != 0 && error != EFBIG) { 1816 printf("%s: could not map mbuf (error %d)\n", 1817 sc->sc_dev.dv_xname, error); 1818 m_freem(m0); 1819 return error; 1820 } 1821 if (error != 0) { 1822 /* too many fragments, linearize */ 1823 1824 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1825 if (mnew == NULL) { 1826 m_freem(m0); 1827 return ENOMEM; 1828 } 1829 1830 M_COPY_PKTHDR(mnew, m0); 1831 if (m0->m_pkthdr.len > MHLEN) { 1832 MCLGET(mnew, M_DONTWAIT); 1833 if (!(mnew->m_flags & M_EXT)) { 1834 m_freem(m0); 1835 m_freem(mnew); 1836 return ENOMEM; 1837 } 1838 } 1839 1840 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1841 m_freem(m0); 1842 mnew->m_len = mnew->m_pkthdr.len; 1843 m0 = mnew; 1844 1845 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1846 BUS_DMA_NOWAIT); 1847 if (error != 0) { 1848 printf("%s: could not map mbuf (error %d)\n", 1849 sc->sc_dev.dv_xname, error); 1850 m_freem(m0); 1851 return error; 1852 } 1853 1854 /* packet header have moved, reset our local pointer */ 1855 wh = mtod(m0, struct ieee80211_frame *); 1856 } 1857 1858 #if NBPFILTER > 0 1859 if (sc->sc_drvbpf != NULL) { 1860 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1861 1862 tap->wt_flags = 0; 1863 tap->wt_rate = rate; 1864 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1865 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1866 1867 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1868 } 1869 #endif 1870 1871 data->m = m0; 1872 data->ni = ni; 1873 1874 /* remember link conditions for rate adaptation algorithm */ 1875 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1876 data->id.id_len = m0->m_pkthdr.len; 1877 data->id.id_rateidx = ni->ni_txrate; 1878 data->id.id_node = ni; 1879 data->id.id_rssi = ni->ni_rssi; 1880 } else 1881 data->id.id_node = NULL; 1882 1883 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1884 flags |= RT2661_TX_NEED_ACK; 1885 1886 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1887 ic->ic_flags) + RAL_SIFS; 1888 *(uint16_t *)wh->i_dur = htole16(dur); 1889 } 1890 1891 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1892 data->map->dm_segs, data->map->dm_nsegs, ac); 1893 1894 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1895 BUS_DMASYNC_PREWRITE); 1896 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1897 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1898 1899 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1900 m0->m_pkthdr.len, txq->cur, rate)); 1901 1902 /* kick Tx */ 1903 txq->queued++; 1904 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1905 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1906 1907 return 0; 1908 } 1909 1910 static void 1911 rt2661_start(struct ifnet *ifp) 1912 { 1913 struct rt2661_softc *sc = ifp->if_softc; 1914 struct ieee80211com *ic = &sc->sc_ic; 1915 struct mbuf *m0; 1916 struct ether_header *eh; 1917 struct ieee80211_node *ni = NULL; 1918 int ac; 1919 1920 /* 1921 * net80211 may still try to send management frames even if the 1922 * IFF_RUNNING flag is not set... 1923 */ 1924 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1925 return; 1926 1927 for (;;) { 1928 IF_POLL(&ic->ic_mgtq, m0); 1929 if (m0 != NULL) { 1930 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1931 ifp->if_flags |= IFF_OACTIVE; 1932 break; 1933 } 1934 IF_DEQUEUE(&ic->ic_mgtq, m0); 1935 if (m0 == NULL) 1936 break; 1937 1938 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1939 m0->m_pkthdr.rcvif = NULL; 1940 #if NBPFILTER > 0 1941 if (ic->ic_rawbpf != NULL) 1942 bpf_mtap(ic->ic_rawbpf, m0); 1943 #endif 1944 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1945 break; 1946 1947 } else { 1948 if (ic->ic_state != IEEE80211_S_RUN) 1949 break; 1950 IFQ_DEQUEUE(&ifp->if_snd, m0); 1951 if (m0 == NULL) 1952 break; 1953 1954 if (m0->m_len < sizeof (struct ether_header) && 1955 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1956 continue; 1957 1958 eh = mtod(m0, struct ether_header *); 1959 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1960 if (ni == NULL) { 1961 m_freem(m0); 1962 ifp->if_oerrors++; 1963 continue; 1964 } 1965 1966 1967 /* classify mbuf so we can find which tx ring to use */ 1968 if (ieee80211_classify(ic, m0, ni) != 0) { 1969 m_freem(m0); 1970 ieee80211_free_node(ni); 1971 ifp->if_oerrors++; 1972 continue; 1973 } 1974 1975 /* no QoS encapsulation for EAPOL frames */ 1976 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 1977 M_WME_GETAC(m0) : WME_AC_BE; 1978 1979 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1980 /* there is no place left in this ring */ 1981 ifp->if_flags |= IFF_OACTIVE; 1982 break; 1983 } 1984 #if NBPFILTER > 0 1985 if (ifp->if_bpf != NULL) 1986 bpf_mtap(ifp->if_bpf, m0); 1987 #endif 1988 m0 = ieee80211_encap(ic, m0, ni); 1989 if (m0 == NULL) { 1990 ieee80211_free_node(ni); 1991 ifp->if_oerrors++; 1992 continue; 1993 } 1994 #if NBPFILTER > 0 1995 if (ic->ic_rawbpf != NULL) 1996 bpf_mtap(ic->ic_rawbpf, m0); 1997 #endif 1998 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1999 if (ni != NULL) 2000 ieee80211_free_node(ni); 2001 ifp->if_oerrors++; 2002 break; 2003 } 2004 } 2005 2006 sc->sc_tx_timer = 5; 2007 ifp->if_timer = 1; 2008 } 2009 } 2010 2011 static void 2012 rt2661_watchdog(struct ifnet *ifp) 2013 { 2014 struct rt2661_softc *sc = ifp->if_softc; 2015 2016 ifp->if_timer = 0; 2017 2018 if (sc->sc_tx_timer > 0) { 2019 if (--sc->sc_tx_timer == 0) { 2020 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2021 rt2661_init(ifp); 2022 ifp->if_oerrors++; 2023 return; 2024 } 2025 ifp->if_timer = 1; 2026 } 2027 2028 ieee80211_watchdog(&sc->sc_ic); 2029 } 2030 2031 /* 2032 * This function allows for fast channel switching in monitor mode (used by 2033 * kismet). In IBSS mode, we must explicitly reset the interface to 2034 * generate a new beacon frame. 2035 */ 2036 static int 2037 rt2661_reset(struct ifnet *ifp) 2038 { 2039 struct rt2661_softc *sc = ifp->if_softc; 2040 struct ieee80211com *ic = &sc->sc_ic; 2041 2042 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2043 return ENETRESET; 2044 2045 rt2661_set_chan(sc, ic->ic_curchan); 2046 2047 return 0; 2048 } 2049 2050 static int 2051 rt2661_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2052 { 2053 struct rt2661_softc *sc = ifp->if_softc; 2054 struct ieee80211com *ic = &sc->sc_ic; 2055 int s, error = 0; 2056 2057 s = splnet(); 2058 2059 switch (cmd) { 2060 case SIOCSIFFLAGS: 2061 if (ifp->if_flags & IFF_UP) { 2062 if (ifp->if_flags & IFF_RUNNING) 2063 rt2661_update_promisc(sc); 2064 else 2065 rt2661_init(ifp); 2066 } else { 2067 if (ifp->if_flags & IFF_RUNNING) 2068 rt2661_stop(ifp, 1); 2069 } 2070 break; 2071 2072 case SIOCADDMULTI: 2073 case SIOCDELMULTI: 2074 /* XXX no h/w multicast filter? --dyoung */ 2075 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2076 error = 0; 2077 break; 2078 2079 case SIOCS80211CHANNEL: 2080 /* 2081 * This allows for fast channel switching in monitor mode 2082 * (used by kismet). In IBSS mode, we must explicitly reset 2083 * the interface to generate a new beacon frame. 2084 */ 2085 error = ieee80211_ioctl(ic, cmd, data); 2086 if (error == ENETRESET && 2087 ic->ic_opmode == IEEE80211_M_MONITOR) { 2088 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2089 (IFF_UP | IFF_RUNNING)) 2090 rt2661_set_chan(sc, ic->ic_ibss_chan); 2091 error = 0; 2092 } 2093 break; 2094 2095 default: 2096 error = ieee80211_ioctl(ic, cmd, data); 2097 2098 } 2099 2100 if (error == ENETRESET) { 2101 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2102 (IFF_UP | IFF_RUNNING)) 2103 rt2661_init(ifp); 2104 error = 0; 2105 } 2106 2107 splx(s); 2108 2109 return error; 2110 } 2111 2112 static void 2113 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 2114 { 2115 uint32_t tmp; 2116 int ntries; 2117 2118 for (ntries = 0; ntries < 100; ntries++) { 2119 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2120 break; 2121 DELAY(1); 2122 } 2123 if (ntries == 100) { 2124 printf("%s: could not write to BBP\n", sc->sc_dev.dv_xname); 2125 return; 2126 } 2127 2128 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 2129 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 2130 2131 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 2132 } 2133 2134 static uint8_t 2135 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2136 { 2137 uint32_t val; 2138 int ntries; 2139 2140 for (ntries = 0; ntries < 100; ntries++) { 2141 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2142 break; 2143 DELAY(1); 2144 } 2145 if (ntries == 100) { 2146 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 2147 return 0; 2148 } 2149 2150 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2151 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2152 2153 for (ntries = 0; ntries < 100; ntries++) { 2154 val = RAL_READ(sc, RT2661_PHY_CSR3); 2155 if (!(val & RT2661_BBP_BUSY)) 2156 return val & 0xff; 2157 DELAY(1); 2158 } 2159 2160 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 2161 return 0; 2162 } 2163 2164 static void 2165 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2166 { 2167 uint32_t tmp; 2168 int ntries; 2169 2170 for (ntries = 0; ntries < 100; ntries++) { 2171 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2172 break; 2173 DELAY(1); 2174 } 2175 if (ntries == 100) { 2176 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 2177 return; 2178 } 2179 2180 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2181 (reg & 3); 2182 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2183 2184 /* remember last written value in sc */ 2185 sc->rf_regs[reg] = val; 2186 2187 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2188 } 2189 2190 static int 2191 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2192 { 2193 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2194 return EIO; /* there is already a command pending */ 2195 2196 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2197 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2198 2199 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2200 2201 return 0; 2202 } 2203 2204 static void 2205 rt2661_select_antenna(struct rt2661_softc *sc) 2206 { 2207 uint8_t bbp4, bbp77; 2208 uint32_t tmp; 2209 2210 bbp4 = rt2661_bbp_read(sc, 4); 2211 bbp77 = rt2661_bbp_read(sc, 77); 2212 2213 /* TBD */ 2214 2215 /* make sure Rx is disabled before switching antenna */ 2216 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2217 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2218 2219 rt2661_bbp_write(sc, 4, bbp4); 2220 rt2661_bbp_write(sc, 77, bbp77); 2221 2222 /* restore Rx filter */ 2223 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2224 } 2225 2226 /* 2227 * Enable multi-rate retries for frames sent at OFDM rates. 2228 * In 802.11b/g mode, allow fallback to CCK rates. 2229 */ 2230 static void 2231 rt2661_enable_mrr(struct rt2661_softc *sc) 2232 { 2233 struct ieee80211com *ic = &sc->sc_ic; 2234 uint32_t tmp; 2235 2236 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2237 2238 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2239 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2240 tmp |= RT2661_MRR_CCK_FALLBACK; 2241 tmp |= RT2661_MRR_ENABLED; 2242 2243 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2244 } 2245 2246 static void 2247 rt2661_set_txpreamble(struct rt2661_softc *sc) 2248 { 2249 uint32_t tmp; 2250 2251 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2252 2253 tmp &= ~RT2661_SHORT_PREAMBLE; 2254 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2255 tmp |= RT2661_SHORT_PREAMBLE; 2256 2257 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2258 } 2259 2260 static void 2261 rt2661_set_basicrates(struct rt2661_softc *sc, 2262 const struct ieee80211_rateset *rs) 2263 { 2264 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2265 uint32_t mask = 0; 2266 uint8_t rate; 2267 int i, j; 2268 2269 for (i = 0; i < rs->rs_nrates; i++) { 2270 rate = rs->rs_rates[i]; 2271 2272 if (!(rate & IEEE80211_RATE_BASIC)) 2273 continue; 2274 2275 /* 2276 * Find h/w rate index. We know it exists because the rate 2277 * set has already been negotiated. 2278 */ 2279 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++); 2280 2281 mask |= 1 << j; 2282 } 2283 2284 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2285 2286 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2287 #undef RV 2288 } 2289 2290 /* 2291 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2292 * driver. 2293 */ 2294 static void 2295 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2296 { 2297 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2298 uint32_t tmp; 2299 2300 /* update all BBP registers that depend on the band */ 2301 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2302 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2303 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2304 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2305 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2306 } 2307 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2308 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2309 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2310 } 2311 2312 rt2661_bbp_write(sc, 17, bbp17); 2313 rt2661_bbp_write(sc, 96, bbp96); 2314 rt2661_bbp_write(sc, 104, bbp104); 2315 2316 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2317 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2318 rt2661_bbp_write(sc, 75, 0x80); 2319 rt2661_bbp_write(sc, 86, 0x80); 2320 rt2661_bbp_write(sc, 88, 0x80); 2321 } 2322 2323 rt2661_bbp_write(sc, 35, bbp35); 2324 rt2661_bbp_write(sc, 97, bbp97); 2325 rt2661_bbp_write(sc, 98, bbp98); 2326 2327 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2328 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2329 if (IEEE80211_IS_CHAN_2GHZ(c)) 2330 tmp |= RT2661_PA_PE_2GHZ; 2331 else 2332 tmp |= RT2661_PA_PE_5GHZ; 2333 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2334 } 2335 2336 static void 2337 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2338 { 2339 struct ieee80211com *ic = &sc->sc_ic; 2340 const struct rfprog *rfprog; 2341 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2342 int8_t power; 2343 u_int i, chan; 2344 2345 chan = ieee80211_chan2ieee(ic, c); 2346 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2347 return; 2348 2349 /* select the appropriate RF settings based on what EEPROM says */ 2350 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2351 2352 /* find the settings for this channel (we know it exists) */ 2353 for (i = 0; rfprog[i].chan != chan; i++); 2354 2355 power = sc->txpow[i]; 2356 if (power < 0) { 2357 bbp94 += power; 2358 power = 0; 2359 } else if (power > 31) { 2360 bbp94 += power - 31; 2361 power = 31; 2362 } 2363 2364 /* 2365 * If we've yet to select a channel, or we are switching from the 2366 * 2GHz band to the 5GHz band or vice-versa, BBP registers need to 2367 * be reprogrammed. 2368 */ 2369 if (sc->sc_curchan == NULL || c->ic_flags != sc->sc_curchan->ic_flags) { 2370 rt2661_select_band(sc, c); 2371 rt2661_select_antenna(sc); 2372 } 2373 sc->sc_curchan = c; 2374 2375 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2376 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2377 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2378 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2379 2380 DELAY(200); 2381 2382 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2383 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2384 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2385 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2386 2387 DELAY(200); 2388 2389 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2390 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2391 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2392 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2393 2394 /* enable smart mode for MIMO-capable RFs */ 2395 bbp3 = rt2661_bbp_read(sc, 3); 2396 2397 bbp3 &= ~RT2661_SMART_MODE; 2398 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2399 bbp3 |= RT2661_SMART_MODE; 2400 2401 rt2661_bbp_write(sc, 3, bbp3); 2402 2403 if (bbp94 != RT2661_BBPR94_DEFAULT) 2404 rt2661_bbp_write(sc, 94, bbp94); 2405 2406 /* 5GHz radio needs a 1ms delay here */ 2407 if (IEEE80211_IS_CHAN_5GHZ(c)) 2408 DELAY(1000); 2409 } 2410 2411 static void 2412 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2413 { 2414 uint32_t tmp; 2415 2416 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2417 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2418 2419 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2420 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2421 } 2422 2423 static void 2424 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2425 { 2426 uint32_t tmp; 2427 2428 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2429 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2430 2431 tmp = addr[4] | addr[5] << 8; 2432 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2433 } 2434 2435 static void 2436 rt2661_update_promisc(struct rt2661_softc *sc) 2437 { 2438 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2439 uint32_t tmp; 2440 2441 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2442 2443 tmp &= ~RT2661_DROP_NOT_TO_ME; 2444 if (!(ifp->if_flags & IFF_PROMISC)) 2445 tmp |= RT2661_DROP_NOT_TO_ME; 2446 2447 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2448 2449 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2450 "entering" : "leaving")); 2451 } 2452 2453 #if 0 2454 /* 2455 * Update QoS (802.11e) settings for each h/w Tx ring. 2456 */ 2457 static int 2458 rt2661_wme_update(struct ieee80211com *ic) 2459 { 2460 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2461 const struct wmeParams *wmep; 2462 2463 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2464 2465 /* XXX: not sure about shifts. */ 2466 /* XXX: the reference driver plays with AC_VI settings too. */ 2467 2468 /* update TxOp */ 2469 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2470 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2471 wmep[WME_AC_BK].wmep_txopLimit); 2472 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2473 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2474 wmep[WME_AC_VO].wmep_txopLimit); 2475 2476 /* update CWmin */ 2477 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2478 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2479 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2480 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2481 wmep[WME_AC_VO].wmep_logcwmin); 2482 2483 /* update CWmax */ 2484 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2485 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2486 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2487 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2488 wmep[WME_AC_VO].wmep_logcwmax); 2489 2490 /* update Aifsn */ 2491 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2492 wmep[WME_AC_BE].wmep_aifsn << 12 | 2493 wmep[WME_AC_BK].wmep_aifsn << 8 | 2494 wmep[WME_AC_VI].wmep_aifsn << 4 | 2495 wmep[WME_AC_VO].wmep_aifsn); 2496 2497 return 0; 2498 } 2499 #endif 2500 2501 static void 2502 rt2661_update_slot(struct ifnet *ifp) 2503 { 2504 struct rt2661_softc *sc = ifp->if_softc; 2505 struct ieee80211com *ic = &sc->sc_ic; 2506 uint8_t slottime; 2507 uint32_t tmp; 2508 2509 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2510 2511 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2512 tmp = (tmp & ~0xff) | slottime; 2513 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2514 } 2515 2516 static const char * 2517 rt2661_get_rf(int rev) 2518 { 2519 switch (rev) { 2520 case RT2661_RF_5225: return "RT5225"; 2521 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2522 case RT2661_RF_2527: return "RT2527"; 2523 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2524 default: return "unknown"; 2525 } 2526 } 2527 2528 static void 2529 rt2661_read_eeprom(struct rt2661_softc *sc) 2530 { 2531 struct ieee80211com *ic = &sc->sc_ic; 2532 uint16_t val; 2533 int i; 2534 2535 /* read MAC address */ 2536 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2537 ic->ic_myaddr[0] = val & 0xff; 2538 ic->ic_myaddr[1] = val >> 8; 2539 2540 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2541 ic->ic_myaddr[2] = val & 0xff; 2542 ic->ic_myaddr[3] = val >> 8; 2543 2544 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2545 ic->ic_myaddr[4] = val & 0xff; 2546 ic->ic_myaddr[5] = val >> 8; 2547 2548 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2549 /* XXX: test if different from 0xffff? */ 2550 sc->rf_rev = (val >> 11) & 0x1f; 2551 sc->hw_radio = (val >> 10) & 0x1; 2552 sc->rx_ant = (val >> 4) & 0x3; 2553 sc->tx_ant = (val >> 2) & 0x3; 2554 sc->nb_ant = val & 0x3; 2555 2556 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2557 2558 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2559 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2560 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2561 2562 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2563 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2564 2565 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2566 if ((val & 0xff) != 0xff) 2567 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2568 2569 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2570 if ((val & 0xff) != 0xff) 2571 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2572 2573 /* adjust RSSI correction for external low-noise amplifier */ 2574 if (sc->ext_2ghz_lna) 2575 sc->rssi_2ghz_corr -= 14; 2576 if (sc->ext_5ghz_lna) 2577 sc->rssi_5ghz_corr -= 14; 2578 2579 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2580 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2581 2582 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2583 if ((val >> 8) != 0xff) 2584 sc->rfprog = (val >> 8) & 0x3; 2585 if ((val & 0xff) != 0xff) 2586 sc->rffreq = val & 0xff; 2587 2588 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2589 2590 /* read Tx power for all a/b/g channels */ 2591 for (i = 0; i < 19; i++) { 2592 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2593 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2594 DPRINTF(("Channel=%d Tx power=%d\n", 2595 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2596 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2597 DPRINTF(("Channel=%d Tx power=%d\n", 2598 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2599 } 2600 2601 /* read vendor-specific BBP values */ 2602 for (i = 0; i < 16; i++) { 2603 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2604 if (val == 0 || val == 0xffff) 2605 continue; /* skip invalid entries */ 2606 sc->bbp_prom[i].reg = val >> 8; 2607 sc->bbp_prom[i].val = val & 0xff; 2608 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2609 sc->bbp_prom[i].val)); 2610 } 2611 } 2612 2613 static int 2614 rt2661_bbp_init(struct rt2661_softc *sc) 2615 { 2616 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2617 int i, ntries; 2618 uint8_t val; 2619 2620 /* wait for BBP to be ready */ 2621 for (ntries = 0; ntries < 100; ntries++) { 2622 val = rt2661_bbp_read(sc, 0); 2623 if (val != 0 && val != 0xff) 2624 break; 2625 DELAY(100); 2626 } 2627 if (ntries == 100) { 2628 printf("%s: timeout waiting for BBP\n", sc->sc_dev.dv_xname); 2629 return EIO; 2630 } 2631 2632 /* initialize BBP registers to default values */ 2633 for (i = 0; i < N(rt2661_def_bbp); i++) { 2634 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2635 rt2661_def_bbp[i].val); 2636 } 2637 2638 /* write vendor-specific BBP values (from EEPROM) */ 2639 for (i = 0; i < 16; i++) { 2640 if (sc->bbp_prom[i].reg == 0) 2641 continue; 2642 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2643 } 2644 2645 return 0; 2646 #undef N 2647 } 2648 2649 static int 2650 rt2661_init(struct ifnet *ifp) 2651 { 2652 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2653 struct rt2661_softc *sc = ifp->if_softc; 2654 struct ieee80211com *ic = &sc->sc_ic; 2655 const char *name = NULL; /* make lint happy */ 2656 uint8_t *ucode; 2657 size_t size; 2658 uint32_t tmp, star[3]; 2659 int i, ntries; 2660 firmware_handle_t fh; 2661 2662 /* for CardBus, power on the socket */ 2663 if (!(sc->sc_flags & RT2661_ENABLED)) { 2664 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2665 printf("%s: could not enable device\n", 2666 sc->sc_dev.dv_xname); 2667 return EIO; 2668 } 2669 sc->sc_flags |= RT2661_ENABLED; 2670 } 2671 2672 rt2661_stop(ifp, 0); 2673 2674 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2675 switch (sc->sc_id) { 2676 case PCI_PRODUCT_RALINK_RT2561: 2677 name = "ral-rt2561"; 2678 break; 2679 case PCI_PRODUCT_RALINK_RT2561S: 2680 name = "ral-rt2561s"; 2681 break; 2682 case PCI_PRODUCT_RALINK_RT2661: 2683 name = "ral-rt2661"; 2684 break; 2685 } 2686 2687 if (firmware_open("ral", name, &fh) != 0) { 2688 printf("%s: could not open microcode %s\n", 2689 sc->sc_dev.dv_xname, name); 2690 rt2661_stop(ifp, 1); 2691 return EIO; 2692 } 2693 2694 size = firmware_get_size(fh); 2695 if (!(ucode = firmware_malloc(size))) { 2696 printf("%s: could not alloc microcode memory\n", 2697 sc->sc_dev.dv_xname); 2698 firmware_close(fh); 2699 rt2661_stop(ifp, 1); 2700 return ENOMEM; 2701 } 2702 2703 if (firmware_read(fh, 0, ucode, size) != 0) { 2704 printf("%s: could not read microcode %s\n", 2705 sc->sc_dev.dv_xname, name); 2706 firmware_free(ucode, 0); 2707 firmware_close(fh); 2708 rt2661_stop(ifp, 1); 2709 return EIO; 2710 } 2711 2712 if (rt2661_load_microcode(sc, ucode, size) != 0) { 2713 printf("%s: could not load 8051 microcode\n", 2714 sc->sc_dev.dv_xname); 2715 firmware_free(ucode, 0); 2716 firmware_close(fh); 2717 rt2661_stop(ifp, 1); 2718 return EIO; 2719 } 2720 2721 firmware_free(ucode, 0); 2722 firmware_close(fh); 2723 sc->sc_flags |= RT2661_FWLOADED; 2724 } 2725 2726 /* initialize Tx rings */ 2727 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2728 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2729 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2730 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2731 2732 /* initialize Mgt ring */ 2733 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2734 2735 /* initialize Rx ring */ 2736 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2737 2738 /* initialize Tx rings sizes */ 2739 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2740 RT2661_TX_RING_COUNT << 24 | 2741 RT2661_TX_RING_COUNT << 16 | 2742 RT2661_TX_RING_COUNT << 8 | 2743 RT2661_TX_RING_COUNT); 2744 2745 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2746 RT2661_TX_DESC_WSIZE << 16 | 2747 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2748 RT2661_MGT_RING_COUNT); 2749 2750 /* initialize Rx rings */ 2751 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2752 RT2661_RX_DESC_BACK << 16 | 2753 RT2661_RX_DESC_WSIZE << 8 | 2754 RT2661_RX_RING_COUNT); 2755 2756 /* XXX: some magic here */ 2757 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2758 2759 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2760 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2761 2762 /* load base address of Rx ring */ 2763 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2764 2765 /* initialize MAC registers to default values */ 2766 for (i = 0; i < N(rt2661_def_mac); i++) 2767 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2768 2769 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2770 rt2661_set_macaddr(sc, ic->ic_myaddr); 2771 2772 /* set host ready */ 2773 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2774 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2775 2776 /* wait for BBP/RF to wakeup */ 2777 for (ntries = 0; ntries < 1000; ntries++) { 2778 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2779 break; 2780 DELAY(1000); 2781 } 2782 if (ntries == 1000) { 2783 printf("timeout waiting for BBP/RF to wakeup\n"); 2784 rt2661_stop(ifp, 1); 2785 return EIO; 2786 } 2787 2788 if (rt2661_bbp_init(sc) != 0) { 2789 rt2661_stop(ifp, 1); 2790 return EIO; 2791 } 2792 2793 /* select default channel */ 2794 sc->sc_curchan = ic->ic_curchan; 2795 rt2661_select_band(sc, sc->sc_curchan); 2796 rt2661_select_antenna(sc); 2797 rt2661_set_chan(sc, sc->sc_curchan); 2798 2799 /* update Rx filter */ 2800 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2801 2802 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2803 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2804 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2805 RT2661_DROP_ACKCTS; 2806 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2807 tmp |= RT2661_DROP_TODS; 2808 if (!(ifp->if_flags & IFF_PROMISC)) 2809 tmp |= RT2661_DROP_NOT_TO_ME; 2810 } 2811 2812 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2813 2814 /* clear STA registers */ 2815 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, star, N(star)); 2816 2817 /* initialize ASIC */ 2818 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2819 2820 /* clear any pending interrupt */ 2821 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2822 2823 /* enable interrupts */ 2824 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2825 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2826 2827 /* kick Rx */ 2828 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2829 2830 ifp->if_flags &= ~IFF_OACTIVE; 2831 ifp->if_flags |= IFF_RUNNING; 2832 2833 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2834 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2835 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2836 } else 2837 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2838 2839 return 0; 2840 #undef N 2841 } 2842 2843 static void 2844 rt2661_stop(struct ifnet *ifp, int disable) 2845 { 2846 struct rt2661_softc *sc = ifp->if_softc; 2847 struct ieee80211com *ic = &sc->sc_ic; 2848 uint32_t tmp; 2849 2850 sc->sc_tx_timer = 0; 2851 ifp->if_timer = 0; 2852 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2853 2854 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2855 2856 /* abort Tx (for all 5 Tx rings) */ 2857 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2858 2859 /* disable Rx (value remains after reset!) */ 2860 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2861 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2862 2863 /* reset ASIC */ 2864 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2865 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2866 2867 /* disable interrupts */ 2868 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2869 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2870 2871 /* clear any pending interrupt */ 2872 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2873 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2874 2875 /* reset Tx and Rx rings */ 2876 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2877 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2878 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2879 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2880 rt2661_reset_tx_ring(sc, &sc->mgtq); 2881 rt2661_reset_rx_ring(sc, &sc->rxq); 2882 2883 /* for CardBus, power down the socket */ 2884 if (disable && sc->sc_disable != NULL) { 2885 if (sc->sc_flags & RT2661_ENABLED) { 2886 (*sc->sc_disable)(sc); 2887 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2888 } 2889 } 2890 } 2891 2892 static int 2893 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2894 { 2895 int ntries; 2896 2897 /* reset 8051 */ 2898 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2899 2900 /* cancel any pending Host to MCU command */ 2901 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2902 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2903 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2904 2905 /* write 8051's microcode */ 2906 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2907 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2908 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2909 2910 /* kick 8051's ass */ 2911 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2912 2913 /* wait for 8051 to initialize */ 2914 for (ntries = 0; ntries < 500; ntries++) { 2915 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2916 break; 2917 DELAY(100); 2918 } 2919 if (ntries == 500) { 2920 printf("timeout waiting for MCU to initialize\n"); 2921 return EIO; 2922 } 2923 return 0; 2924 } 2925 2926 #ifdef notyet 2927 /* 2928 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2929 * false CCA count. This function is called periodically (every seconds) when 2930 * in the RUN state. Values taken from the reference driver. 2931 */ 2932 static void 2933 rt2661_rx_tune(struct rt2661_softc *sc) 2934 { 2935 uint8_t bbp17; 2936 uint16_t cca; 2937 int lo, hi, dbm; 2938 2939 /* 2940 * Tuning range depends on operating band and on the presence of an 2941 * external low-noise amplifier. 2942 */ 2943 lo = 0x20; 2944 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2945 lo += 0x08; 2946 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2947 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2948 lo += 0x10; 2949 hi = lo + 0x20; 2950 2951 /* retrieve false CCA count since last call (clear on read) */ 2952 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2953 2954 if (dbm >= -35) { 2955 bbp17 = 0x60; 2956 } else if (dbm >= -58) { 2957 bbp17 = hi; 2958 } else if (dbm >= -66) { 2959 bbp17 = lo + 0x10; 2960 } else if (dbm >= -74) { 2961 bbp17 = lo + 0x08; 2962 } else { 2963 /* RSSI < -74dBm, tune using false CCA count */ 2964 2965 bbp17 = sc->bbp17; /* current value */ 2966 2967 hi -= 2 * (-74 - dbm); 2968 if (hi < lo) 2969 hi = lo; 2970 2971 if (bbp17 > hi) { 2972 bbp17 = hi; 2973 2974 } else if (cca > 512) { 2975 if (++bbp17 > hi) 2976 bbp17 = hi; 2977 } else if (cca < 100) { 2978 if (--bbp17 < lo) 2979 bbp17 = lo; 2980 } 2981 } 2982 2983 if (bbp17 != sc->bbp17) { 2984 rt2661_bbp_write(sc, 17, bbp17); 2985 sc->bbp17 = bbp17; 2986 } 2987 } 2988 2989 /* 2990 * Enter/Leave radar detection mode. 2991 * This is for 802.11h additional regulatory domains. 2992 */ 2993 static void 2994 rt2661_radar_start(struct rt2661_softc *sc) 2995 { 2996 uint32_t tmp; 2997 2998 /* disable Rx */ 2999 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 3000 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 3001 3002 rt2661_bbp_write(sc, 82, 0x20); 3003 rt2661_bbp_write(sc, 83, 0x00); 3004 rt2661_bbp_write(sc, 84, 0x40); 3005 3006 /* save current BBP registers values */ 3007 sc->bbp18 = rt2661_bbp_read(sc, 18); 3008 sc->bbp21 = rt2661_bbp_read(sc, 21); 3009 sc->bbp22 = rt2661_bbp_read(sc, 22); 3010 sc->bbp16 = rt2661_bbp_read(sc, 16); 3011 sc->bbp17 = rt2661_bbp_read(sc, 17); 3012 sc->bbp64 = rt2661_bbp_read(sc, 64); 3013 3014 rt2661_bbp_write(sc, 18, 0xff); 3015 rt2661_bbp_write(sc, 21, 0x3f); 3016 rt2661_bbp_write(sc, 22, 0x3f); 3017 rt2661_bbp_write(sc, 16, 0xbd); 3018 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 3019 rt2661_bbp_write(sc, 64, 0x21); 3020 3021 /* restore Rx filter */ 3022 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 3023 } 3024 3025 static int 3026 rt2661_radar_stop(struct rt2661_softc *sc) 3027 { 3028 uint8_t bbp66; 3029 3030 /* read radar detection result */ 3031 bbp66 = rt2661_bbp_read(sc, 66); 3032 3033 /* restore BBP registers values */ 3034 rt2661_bbp_write(sc, 16, sc->bbp16); 3035 rt2661_bbp_write(sc, 17, sc->bbp17); 3036 rt2661_bbp_write(sc, 18, sc->bbp18); 3037 rt2661_bbp_write(sc, 21, sc->bbp21); 3038 rt2661_bbp_write(sc, 22, sc->bbp22); 3039 rt2661_bbp_write(sc, 64, sc->bbp64); 3040 3041 return bbp66 == 1; 3042 } 3043 #endif 3044 3045 static int 3046 rt2661_prepare_beacon(struct rt2661_softc *sc) 3047 { 3048 struct ieee80211com *ic = &sc->sc_ic; 3049 struct rt2661_tx_desc desc; 3050 struct mbuf *m0; 3051 struct ieee80211_beacon_offsets bo; 3052 int rate; 3053 3054 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 3055 3056 if (m0 == NULL) { 3057 printf("%s: could not allocate beacon frame\n", 3058 sc->sc_dev.dv_xname); 3059 return ENOBUFS; 3060 } 3061 3062 /* send beacons at the lowest available rate */ 3063 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2; 3064 3065 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 3066 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 3067 3068 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 3069 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 3070 3071 /* copy beacon header and payload into NIC memory */ 3072 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 3073 mtod(m0, uint8_t *), m0->m_pkthdr.len); 3074 3075 m_freem(m0); 3076 3077 return 0; 3078 } 3079 3080 /* 3081 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 3082 * and HostAP operating modes. 3083 */ 3084 static void 3085 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 3086 { 3087 struct ieee80211com *ic = &sc->sc_ic; 3088 uint32_t tmp; 3089 3090 if (ic->ic_opmode != IEEE80211_M_STA) { 3091 /* 3092 * Change default 16ms TBTT adjustment to 8ms. 3093 * Must be done before enabling beacon generation. 3094 */ 3095 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 3096 } 3097 3098 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 3099 3100 /* set beacon interval (in 1/16ms unit) */ 3101 tmp |= ic->ic_bss->ni_intval * 16; 3102 3103 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 3104 if (ic->ic_opmode == IEEE80211_M_STA) 3105 tmp |= RT2661_TSF_MODE(1); 3106 else 3107 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 3108 3109 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 3110 } 3111 3112 /* 3113 * Retrieve the "Received Signal Strength Indicator" from the raw values 3114 * contained in Rx descriptors. The computation depends on which band the 3115 * frame was received. Correction values taken from the reference driver. 3116 */ 3117 static int 3118 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 3119 { 3120 int lna, agc, rssi; 3121 3122 lna = (raw >> 5) & 0x3; 3123 agc = raw & 0x1f; 3124 3125 rssi = 2 * agc; 3126 3127 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3128 rssi += sc->rssi_2ghz_corr; 3129 3130 if (lna == 1) 3131 rssi -= 64; 3132 else if (lna == 2) 3133 rssi -= 74; 3134 else if (lna == 3) 3135 rssi -= 90; 3136 } else { 3137 rssi += sc->rssi_5ghz_corr; 3138 3139 if (lna == 1) 3140 rssi -= 64; 3141 else if (lna == 2) 3142 rssi -= 86; 3143 else if (lna == 3) 3144 rssi -= 100; 3145 } 3146 return rssi; 3147 } 3148
Indexes created Tue Sep 23 07:09:52 GMT 2025