rt2661.c revision 1.23
1 /* $NetBSD: rt2661.c,v 1.23 2008/04/08 12:07:27 cegger Exp $ */ 2 /* $OpenBSD: rt2661.c,v 1.17 2006/05/01 08:41:11 damien Exp $ */ 3 /* $FreeBSD: rt2560.c,v 1.5 2006/06/02 19:59:31 csjp Exp $ */ 4 5 /*- 6 * Copyright (c) 2006 7 * Damien Bergamini <damien.bergamini (at) free.fr> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2661.c,v 1.23 2008/04/08 12:07:27 cegger Exp $"); 29 30 #include "bpfilter.h" 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/device.h> 43 44 #include <sys/bus.h> 45 #include <machine/endian.h> 46 #include <sys/intr.h> 47 48 #if NBPFILTER > 0 49 #include <net/bpf.h> 50 #endif 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_ether.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 63 #include <net80211/ieee80211_var.h> 64 #include <net80211/ieee80211_rssadapt.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #include <dev/ic/rt2661reg.h> 68 #include <dev/ic/rt2661var.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <dev/firmload.h> 75 76 #ifdef RAL_DEBUG 77 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 78 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 79 int rt2661_debug = 0; 80 #else 81 #define DPRINTF(x) 82 #define DPRINTFN(n, x) 83 #endif 84 85 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 86 struct rt2661_tx_ring *, int); 87 static void rt2661_reset_tx_ring(struct rt2661_softc *, 88 struct rt2661_tx_ring *); 89 static void rt2661_free_tx_ring(struct rt2661_softc *, 90 struct rt2661_tx_ring *); 91 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 92 struct rt2661_rx_ring *, int); 93 static void rt2661_reset_rx_ring(struct rt2661_softc *, 94 struct rt2661_rx_ring *); 95 static void rt2661_free_rx_ring(struct rt2661_softc *, 96 struct rt2661_rx_ring *); 97 static struct ieee80211_node * 98 rt2661_node_alloc(struct ieee80211_node_table *); 99 static int rt2661_media_change(struct ifnet *); 100 static void rt2661_next_scan(void *); 101 static void rt2661_iter_func(void *, struct ieee80211_node *); 102 static void rt2661_rssadapt_updatestats(void *); 103 static int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 104 int); 105 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 106 static void rt2661_tx_intr(struct rt2661_softc *); 107 static void rt2661_tx_dma_intr(struct rt2661_softc *, 108 struct rt2661_tx_ring *); 109 static void rt2661_rx_intr(struct rt2661_softc *); 110 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 111 static void rt2661_mcu_wakeup(struct rt2661_softc *); 112 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 113 int rt2661_intr(void *); 114 #if NBPFILTER > 0 115 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 116 #endif 117 static int rt2661_ack_rate(struct ieee80211com *, int); 118 static uint16_t rt2661_txtime(int, int, uint32_t); 119 static uint8_t rt2661_plcp_signal(int); 120 static void rt2661_setup_tx_desc(struct rt2661_softc *, 121 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 122 const bus_dma_segment_t *, int, int); 123 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 124 struct ieee80211_node *); 125 static struct mbuf * 126 rt2661_get_rts(struct rt2661_softc *, 127 struct ieee80211_frame *, uint16_t); 128 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 129 struct ieee80211_node *, int); 130 static void rt2661_start(struct ifnet *); 131 static void rt2661_watchdog(struct ifnet *); 132 static int rt2661_reset(struct ifnet *); 133 static int rt2661_ioctl(struct ifnet *, u_long, void *); 134 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 135 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 136 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 137 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 138 static void rt2661_select_antenna(struct rt2661_softc *); 139 static void rt2661_enable_mrr(struct rt2661_softc *); 140 static void rt2661_set_txpreamble(struct rt2661_softc *); 141 static void rt2661_set_basicrates(struct rt2661_softc *, 142 const struct ieee80211_rateset *); 143 static void rt2661_select_band(struct rt2661_softc *, 144 struct ieee80211_channel *); 145 static void rt2661_set_chan(struct rt2661_softc *, 146 struct ieee80211_channel *); 147 static void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 148 static void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 149 static void rt2661_update_promisc(struct rt2661_softc *); 150 #if 0 151 static int rt2661_wme_update(struct ieee80211com *); 152 #endif 153 154 static void rt2661_update_slot(struct ifnet *); 155 static const char * 156 rt2661_get_rf(int); 157 static void rt2661_read_eeprom(struct rt2661_softc *); 158 static int rt2661_bbp_init(struct rt2661_softc *); 159 static int rt2661_init(struct ifnet *); 160 static void rt2661_stop(struct ifnet *, int); 161 static int rt2661_load_microcode(struct rt2661_softc *, const uint8_t *, 162 int); 163 #ifdef notyet 164 static void rt2661_rx_tune(struct rt2661_softc *); 165 static void rt2661_radar_start(struct rt2661_softc *); 166 static int rt2661_radar_stop(struct rt2661_softc *); 167 #endif 168 static int rt2661_prepare_beacon(struct rt2661_softc *); 169 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 170 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 171 172 /* 173 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 174 */ 175 static const struct ieee80211_rateset rt2661_rateset_11a = 176 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 177 178 static const struct ieee80211_rateset rt2661_rateset_11b = 179 { 4, { 2, 4, 11, 22 } }; 180 181 static const struct ieee80211_rateset rt2661_rateset_11g = 182 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 183 184 /* 185 * Default values for MAC registers; values taken from the reference driver. 186 */ 187 static const struct { 188 uint32_t reg; 189 uint32_t val; 190 } rt2661_def_mac[] = { 191 { RT2661_TXRX_CSR0, 0x0000b032 }, 192 { RT2661_TXRX_CSR1, 0x9eb39eb3 }, 193 { RT2661_TXRX_CSR2, 0x8a8b8c8d }, 194 { RT2661_TXRX_CSR3, 0x00858687 }, 195 { RT2661_TXRX_CSR7, 0x2e31353b }, 196 { RT2661_TXRX_CSR8, 0x2a2a2a2c }, 197 { RT2661_TXRX_CSR15, 0x0000000f }, 198 { RT2661_MAC_CSR6, 0x00000fff }, 199 { RT2661_MAC_CSR8, 0x016c030a }, 200 { RT2661_MAC_CSR10, 0x00000718 }, 201 { RT2661_MAC_CSR12, 0x00000004 }, 202 { RT2661_MAC_CSR13, 0x0000e000 }, 203 { RT2661_SEC_CSR0, 0x00000000 }, 204 { RT2661_SEC_CSR1, 0x00000000 }, 205 { RT2661_SEC_CSR5, 0x00000000 }, 206 { RT2661_PHY_CSR1, 0x000023b0 }, 207 { RT2661_PHY_CSR5, 0x060a100c }, 208 { RT2661_PHY_CSR6, 0x00080606 }, 209 { RT2661_PHY_CSR7, 0x00000a08 }, 210 { RT2661_PCI_CFG_CSR, 0x3cca4808 }, 211 { RT2661_AIFSN_CSR, 0x00002273 }, 212 { RT2661_CWMIN_CSR, 0x00002344 }, 213 { RT2661_CWMAX_CSR, 0x000034aa }, 214 { RT2661_TEST_MODE_CSR, 0x00000200 }, 215 { RT2661_M2H_CMD_DONE_CSR, 0xffffffff } 216 }; 217 218 /* 219 * Default values for BBP registers; values taken from the reference driver. 220 */ 221 static const struct { 222 uint8_t reg; 223 uint8_t val; 224 } rt2661_def_bbp[] = { 225 { 3, 0x00 }, 226 { 15, 0x30 }, 227 { 17, 0x20 }, 228 { 21, 0xc8 }, 229 { 22, 0x38 }, 230 { 23, 0x06 }, 231 { 24, 0xfe }, 232 { 25, 0x0a }, 233 { 26, 0x0d }, 234 { 34, 0x12 }, 235 { 37, 0x07 }, 236 { 39, 0xf8 }, 237 { 41, 0x60 }, 238 { 53, 0x10 }, 239 { 54, 0x18 }, 240 { 60, 0x10 }, 241 { 61, 0x04 }, 242 { 62, 0x04 }, 243 { 75, 0xfe }, 244 { 86, 0xfe }, 245 { 88, 0xfe }, 246 { 90, 0x0f }, 247 { 99, 0x00 }, 248 { 102, 0x16 }, 249 { 107, 0x04 } 250 }; 251 252 /* 253 * Default settings for RF registers; values taken from the reference driver. 254 */ 255 static const struct rfprog { 256 uint8_t chan; 257 uint32_t r1; 258 uint32_t r2; 259 uint32_t r3; 260 uint32_t r4; 261 } rt2661_rf5225_1[] = { 262 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, 263 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, 264 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, 265 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, 266 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, 267 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, 268 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, 269 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, 270 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, 271 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, 272 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, 273 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, 274 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, 275 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, 276 277 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, 278 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, 279 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, 280 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, 281 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, 282 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, 283 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, 284 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, 285 286 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, 287 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, 288 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, 289 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, 290 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, 291 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, 292 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, 293 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, 294 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, 295 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, 296 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, 297 298 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, 299 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, 300 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, 301 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, 302 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } 303 304 }, rt2661_rf5225_2[] = { 305 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, 306 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, 307 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, 308 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, 309 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, 310 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, 311 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, 312 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, 313 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, 314 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, 315 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, 316 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, 317 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, 318 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, 319 320 { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, 321 { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, 322 { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, 323 { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, 324 { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, 325 { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, 326 { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, 327 { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, 328 329 { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, 330 { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, 331 { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, 332 { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, 333 { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, 334 { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, 335 { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, 336 { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, 337 { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, 338 { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, 339 { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, 340 341 { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, 342 { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, 343 { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, 344 { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, 345 { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 } 346 }; 347 348 int 349 rt2661_attach(void *xsc, int id) 350 { 351 struct rt2661_softc *sc = xsc; 352 struct ieee80211com *ic = &sc->sc_ic; 353 struct ifnet *ifp = &sc->sc_if; 354 uint32_t val; 355 int error, i, ntries; 356 357 sc->sc_id = id; 358 359 callout_init(&sc->scan_ch, 0); 360 callout_init(&sc->rssadapt_ch, 0); 361 362 /* wait for NIC to initialize */ 363 for (ntries = 0; ntries < 1000; ntries++) { 364 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 365 break; 366 DELAY(1000); 367 } 368 if (ntries == 1000) { 369 aprint_error_dev(&sc->sc_dev, "timeout waiting for NIC to initialize\n"); 370 return EIO; 371 } 372 373 /* retrieve RF rev. no and various other things from EEPROM */ 374 rt2661_read_eeprom(sc); 375 aprint_normal_dev(&sc->sc_dev, "802.11 address %s\n", 376 ether_sprintf(ic->ic_myaddr)); 377 378 aprint_normal_dev(&sc->sc_dev, "MAC/BBP RT%X, RF %s\n", val, 379 rt2661_get_rf(sc->rf_rev)); 380 381 /* 382 * Allocate Tx and Rx rings. 383 */ 384 error = rt2661_alloc_tx_ring(sc, &sc->txq[0], RT2661_TX_RING_COUNT); 385 if (error != 0) { 386 aprint_error_dev(&sc->sc_dev, "could not allocate Tx ring 0\n"); 387 goto fail1; 388 } 389 390 error = rt2661_alloc_tx_ring(sc, &sc->txq[1], RT2661_TX_RING_COUNT); 391 if (error != 0) { 392 aprint_error_dev(&sc->sc_dev, "could not allocate Tx ring 1\n"); 393 goto fail2; 394 } 395 396 error = rt2661_alloc_tx_ring(sc, &sc->txq[2], RT2661_TX_RING_COUNT); 397 if (error != 0) { 398 aprint_error_dev(&sc->sc_dev, "could not allocate Tx ring 2\n"); 399 goto fail3; 400 } 401 402 error = rt2661_alloc_tx_ring(sc, &sc->txq[3], RT2661_TX_RING_COUNT); 403 if (error != 0) { 404 aprint_error_dev(&sc->sc_dev, "could not allocate Tx ring 3\n"); 405 goto fail4; 406 } 407 408 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 409 if (error != 0) { 410 aprint_error_dev(&sc->sc_dev, "could not allocate Mgt ring\n"); 411 goto fail5; 412 } 413 414 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 415 if (error != 0) { 416 aprint_error_dev(&sc->sc_dev, "could not allocate Rx ring\n"); 417 goto fail6; 418 } 419 420 ifp->if_softc = sc; 421 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 422 ifp->if_init = rt2661_init; 423 ifp->if_stop = rt2661_stop; 424 ifp->if_ioctl = rt2661_ioctl; 425 ifp->if_start = rt2661_start; 426 ifp->if_watchdog = rt2661_watchdog; 427 IFQ_SET_READY(&ifp->if_snd); 428 memcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 429 430 ic->ic_ifp = ifp; 431 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 432 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 433 ic->ic_state = IEEE80211_S_INIT; 434 435 /* set device capabilities */ 436 ic->ic_caps = 437 IEEE80211_C_IBSS | /* IBSS mode supported */ 438 IEEE80211_C_MONITOR | /* monitor mode supported */ 439 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 440 IEEE80211_C_TXPMGT | /* tx power management */ 441 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 442 IEEE80211_C_SHSLOT | /* short slot time supported */ 443 IEEE80211_C_WPA; /* 802.11i */ 444 445 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 446 /* set supported .11a rates */ 447 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 448 449 /* set supported .11a channels */ 450 for (i = 36; i <= 64; i += 4) { 451 ic->ic_channels[i].ic_freq = 452 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 453 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 454 } 455 for (i = 100; i <= 140; i += 4) { 456 ic->ic_channels[i].ic_freq = 457 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 458 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 459 } 460 for (i = 149; i <= 165; i += 4) { 461 ic->ic_channels[i].ic_freq = 462 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 463 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 464 } 465 } 466 467 /* set supported .11b and .11g rates */ 468 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 469 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 470 471 /* set supported .11b and .11g channels (1 through 14) */ 472 for (i = 1; i <= 14; i++) { 473 ic->ic_channels[i].ic_freq = 474 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 475 ic->ic_channels[i].ic_flags = 476 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 477 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 478 } 479 480 if_attach(ifp); 481 ieee80211_ifattach(ic); 482 ic->ic_node_alloc = rt2661_node_alloc; 483 ic->ic_updateslot = rt2661_update_slot; 484 ic->ic_reset = rt2661_reset; 485 486 /* override state transition machine */ 487 sc->sc_newstate = ic->ic_newstate; 488 ic->ic_newstate = rt2661_newstate; 489 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 490 491 #if NBPFILTER > 0 492 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 493 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 494 495 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 496 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 497 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 498 499 sc->sc_txtap_len = sizeof sc->sc_txtapu; 500 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 501 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 502 #endif 503 504 ieee80211_announce(ic); 505 506 if (!pmf_device_register(&sc->sc_dev, NULL, NULL)) 507 aprint_error_dev(&sc->sc_dev, "couldn't establish power handler\n"); 508 else 509 pmf_class_network_register(&sc->sc_dev, ifp); 510 511 return 0; 512 513 fail6: rt2661_free_tx_ring(sc, &sc->mgtq); 514 fail5: rt2661_free_tx_ring(sc, &sc->txq[3]); 515 fail4: rt2661_free_tx_ring(sc, &sc->txq[2]); 516 fail3: rt2661_free_tx_ring(sc, &sc->txq[1]); 517 fail2: rt2661_free_tx_ring(sc, &sc->txq[0]); 518 fail1: return ENXIO; 519 } 520 521 int 522 rt2661_detach(void *xsc) 523 { 524 struct rt2661_softc *sc = xsc; 525 struct ifnet *ifp = &sc->sc_if; 526 527 callout_stop(&sc->scan_ch); 528 callout_stop(&sc->rssadapt_ch); 529 530 pmf_device_deregister(&sc->sc_dev); 531 532 ieee80211_ifdetach(&sc->sc_ic); 533 if_detach(ifp); 534 535 rt2661_free_tx_ring(sc, &sc->txq[0]); 536 rt2661_free_tx_ring(sc, &sc->txq[1]); 537 rt2661_free_tx_ring(sc, &sc->txq[2]); 538 rt2661_free_tx_ring(sc, &sc->txq[3]); 539 rt2661_free_tx_ring(sc, &sc->mgtq); 540 rt2661_free_rx_ring(sc, &sc->rxq); 541 542 return 0; 543 } 544 545 static int 546 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 547 int count) 548 { 549 int i, nsegs, error; 550 551 ring->count = count; 552 ring->queued = 0; 553 ring->cur = ring->next = ring->stat = 0; 554 555 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 556 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 557 if (error != 0) { 558 aprint_error_dev(&sc->sc_dev, "could not create desc DMA map\n"); 559 goto fail; 560 } 561 562 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 563 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 564 if (error != 0) { 565 aprint_error_dev(&sc->sc_dev, "could not allocate DMA memory\n"); 566 goto fail; 567 } 568 569 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 570 count * RT2661_TX_DESC_SIZE, (void **)&ring->desc, 571 BUS_DMA_NOWAIT); 572 if (error != 0) { 573 aprint_error_dev(&sc->sc_dev, "could not map desc DMA memory\n"); 574 goto fail; 575 } 576 577 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 578 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 579 if (error != 0) { 580 aprint_error_dev(&sc->sc_dev, "could not load desc DMA map\n"); 581 goto fail; 582 } 583 584 memset(ring->desc, 0, count * RT2661_TX_DESC_SIZE); 585 ring->physaddr = ring->map->dm_segs->ds_addr; 586 587 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 588 M_NOWAIT); 589 if (ring->data == NULL) { 590 aprint_error_dev(&sc->sc_dev, "could not allocate soft data\n"); 591 error = ENOMEM; 592 goto fail; 593 } 594 595 memset(ring->data, 0, count * sizeof (struct rt2661_tx_data)); 596 for (i = 0; i < count; i++) { 597 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 598 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 599 &ring->data[i].map); 600 if (error != 0) { 601 aprint_error_dev(&sc->sc_dev, "could not create DMA map\n"); 602 goto fail; 603 } 604 } 605 606 return 0; 607 608 fail: rt2661_free_tx_ring(sc, ring); 609 return error; 610 } 611 612 static void 613 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 614 { 615 struct rt2661_tx_desc *desc; 616 struct rt2661_tx_data *data; 617 int i; 618 619 for (i = 0; i < ring->count; i++) { 620 desc = &ring->desc[i]; 621 data = &ring->data[i]; 622 623 if (data->m != NULL) { 624 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 625 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 626 bus_dmamap_unload(sc->sc_dmat, data->map); 627 m_freem(data->m); 628 data->m = NULL; 629 } 630 631 if (data->ni != NULL) { 632 ieee80211_free_node(data->ni); 633 data->ni = NULL; 634 } 635 636 desc->flags = 0; 637 } 638 639 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 640 BUS_DMASYNC_PREWRITE); 641 642 ring->queued = 0; 643 ring->cur = ring->next = ring->stat = 0; 644 } 645 646 647 static void 648 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 649 { 650 struct rt2661_tx_data *data; 651 int i; 652 653 if (ring->desc != NULL) { 654 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 655 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 656 bus_dmamap_unload(sc->sc_dmat, ring->map); 657 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 658 ring->count * RT2661_TX_DESC_SIZE); 659 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 660 } 661 662 if (ring->data != NULL) { 663 for (i = 0; i < ring->count; i++) { 664 data = &ring->data[i]; 665 666 if (data->m != NULL) { 667 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 668 data->map->dm_mapsize, 669 BUS_DMASYNC_POSTWRITE); 670 bus_dmamap_unload(sc->sc_dmat, data->map); 671 m_freem(data->m); 672 } 673 674 if (data->ni != NULL) 675 ieee80211_free_node(data->ni); 676 677 if (data->map != NULL) 678 bus_dmamap_destroy(sc->sc_dmat, data->map); 679 } 680 free(ring->data, M_DEVBUF); 681 } 682 } 683 684 static int 685 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 686 int count) 687 { 688 struct rt2661_rx_desc *desc; 689 struct rt2661_rx_data *data; 690 int i, nsegs, error; 691 692 ring->count = count; 693 ring->cur = ring->next = 0; 694 695 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 696 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 697 if (error != 0) { 698 aprint_error_dev(&sc->sc_dev, "could not create desc DMA map\n"); 699 goto fail; 700 } 701 702 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 703 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 704 if (error != 0) { 705 aprint_error_dev(&sc->sc_dev, "could not allocate DMA memory\n"); 706 goto fail; 707 } 708 709 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 710 count * RT2661_RX_DESC_SIZE, (void **)&ring->desc, 711 BUS_DMA_NOWAIT); 712 if (error != 0) { 713 aprint_error_dev(&sc->sc_dev, "could not map desc DMA memory\n"); 714 goto fail; 715 } 716 717 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 718 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 719 if (error != 0) { 720 aprint_error_dev(&sc->sc_dev, "could not load desc DMA map\n"); 721 goto fail; 722 } 723 724 memset(ring->desc, 0, count * RT2661_RX_DESC_SIZE); 725 ring->physaddr = ring->map->dm_segs->ds_addr; 726 727 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 728 M_NOWAIT); 729 if (ring->data == NULL) { 730 aprint_error_dev(&sc->sc_dev, "could not allocate soft data\n"); 731 error = ENOMEM; 732 goto fail; 733 } 734 735 /* 736 * Pre-allocate Rx buffers and populate Rx ring. 737 */ 738 memset(ring->data, 0, count * sizeof (struct rt2661_rx_data)); 739 for (i = 0; i < count; i++) { 740 desc = &sc->rxq.desc[i]; 741 data = &sc->rxq.data[i]; 742 743 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 744 0, BUS_DMA_NOWAIT, &data->map); 745 if (error != 0) { 746 aprint_error_dev(&sc->sc_dev, "could not create DMA map\n"); 747 goto fail; 748 } 749 750 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 751 if (data->m == NULL) { 752 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 753 error = ENOMEM; 754 goto fail; 755 } 756 757 MCLGET(data->m, M_DONTWAIT); 758 if (!(data->m->m_flags & M_EXT)) { 759 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 760 error = ENOMEM; 761 goto fail; 762 } 763 764 error = bus_dmamap_load(sc->sc_dmat, data->map, 765 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 766 if (error != 0) { 767 aprint_error_dev(&sc->sc_dev, "could not load rx buf DMA map"); 768 goto fail; 769 } 770 771 desc->flags = htole32(RT2661_RX_BUSY); 772 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 773 } 774 775 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 776 BUS_DMASYNC_PREWRITE); 777 778 return 0; 779 780 fail: rt2661_free_rx_ring(sc, ring); 781 return error; 782 } 783 784 static void 785 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 786 { 787 int i; 788 789 for (i = 0; i < ring->count; i++) 790 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 791 792 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 793 BUS_DMASYNC_PREWRITE); 794 795 ring->cur = ring->next = 0; 796 } 797 798 static void 799 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 800 { 801 struct rt2661_rx_data *data; 802 int i; 803 804 if (ring->desc != NULL) { 805 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 806 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 807 bus_dmamap_unload(sc->sc_dmat, ring->map); 808 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 809 ring->count * RT2661_RX_DESC_SIZE); 810 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 811 } 812 813 if (ring->data != NULL) { 814 for (i = 0; i < ring->count; i++) { 815 data = &ring->data[i]; 816 817 if (data->m != NULL) { 818 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 819 data->map->dm_mapsize, 820 BUS_DMASYNC_POSTREAD); 821 bus_dmamap_unload(sc->sc_dmat, data->map); 822 m_freem(data->m); 823 } 824 825 if (data->map != NULL) 826 bus_dmamap_destroy(sc->sc_dmat, data->map); 827 } 828 free(ring->data, M_DEVBUF); 829 } 830 } 831 832 static struct ieee80211_node * 833 rt2661_node_alloc(struct ieee80211_node_table *nt) 834 { 835 struct rt2661_node *rn; 836 837 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 838 M_NOWAIT | M_ZERO); 839 840 return (rn != NULL) ? &rn->ni : NULL; 841 } 842 843 static int 844 rt2661_media_change(struct ifnet *ifp) 845 { 846 int error; 847 848 error = ieee80211_media_change(ifp); 849 if (error != ENETRESET) 850 return error; 851 852 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 853 rt2661_init(ifp); 854 855 return 0; 856 } 857 858 /* 859 * This function is called periodically (every 200ms) during scanning to 860 * switch from one channel to another. 861 */ 862 static void 863 rt2661_next_scan(void *arg) 864 { 865 struct rt2661_softc *sc = arg; 866 struct ieee80211com *ic = &sc->sc_ic; 867 868 if (ic->ic_state == IEEE80211_S_SCAN) 869 ieee80211_next_scan(ic); 870 } 871 872 /* 873 * This function is called for each neighbor node. 874 */ 875 static void 876 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 877 { 878 struct rt2661_node *rn = (struct rt2661_node *)ni; 879 880 ieee80211_rssadapt_updatestats(&rn->rssadapt); 881 } 882 883 /* 884 * This function is called periodically (every 100ms) in RUN state to update 885 * the rate adaptation statistics. 886 */ 887 static void 888 rt2661_rssadapt_updatestats(void *arg) 889 { 890 struct rt2661_softc *sc = arg; 891 struct ieee80211com *ic = &sc->sc_ic; 892 893 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 894 895 callout_reset(&sc->rssadapt_ch, hz / 10, rt2661_rssadapt_updatestats, 896 sc); 897 } 898 899 static int 900 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 901 { 902 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 903 enum ieee80211_state ostate; 904 struct ieee80211_node *ni; 905 uint32_t tmp; 906 int error = 0; 907 908 ostate = ic->ic_state; 909 callout_stop(&sc->scan_ch); 910 911 switch (nstate) { 912 case IEEE80211_S_INIT: 913 callout_stop(&sc->rssadapt_ch); 914 915 if (ostate == IEEE80211_S_RUN) { 916 /* abort TSF synchronization */ 917 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 918 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 919 } 920 break; 921 922 case IEEE80211_S_SCAN: 923 rt2661_set_chan(sc, ic->ic_curchan); 924 callout_reset(&sc->scan_ch, hz / 5, rt2661_next_scan, sc); 925 break; 926 927 case IEEE80211_S_AUTH: 928 case IEEE80211_S_ASSOC: 929 rt2661_set_chan(sc, ic->ic_curchan); 930 break; 931 932 case IEEE80211_S_RUN: 933 rt2661_set_chan(sc, ic->ic_curchan); 934 935 ni = ic->ic_bss; 936 937 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 938 rt2661_enable_mrr(sc); 939 rt2661_set_txpreamble(sc); 940 rt2661_set_basicrates(sc, &ni->ni_rates); 941 rt2661_set_bssid(sc, ni->ni_bssid); 942 } 943 944 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 945 ic->ic_opmode == IEEE80211_M_IBSS) { 946 if ((error = rt2661_prepare_beacon(sc)) != 0) 947 break; 948 } 949 950 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 951 callout_reset(&sc->rssadapt_ch, hz / 10, 952 rt2661_rssadapt_updatestats, sc); 953 rt2661_enable_tsf_sync(sc); 954 } 955 break; 956 } 957 958 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 959 } 960 961 /* 962 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 963 * 93C66). 964 */ 965 static uint16_t 966 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 967 { 968 uint32_t tmp; 969 uint16_t val; 970 int n; 971 972 /* clock C once before the first command */ 973 RT2661_EEPROM_CTL(sc, 0); 974 975 RT2661_EEPROM_CTL(sc, RT2661_S); 976 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 977 RT2661_EEPROM_CTL(sc, RT2661_S); 978 979 /* write start bit (1) */ 980 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 981 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 982 983 /* write READ opcode (10) */ 984 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 985 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 986 RT2661_EEPROM_CTL(sc, RT2661_S); 987 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 988 989 /* write address (A5-A0 or A7-A0) */ 990 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 991 for (; n >= 0; n--) { 992 RT2661_EEPROM_CTL(sc, RT2661_S | 993 (((addr >> n) & 1) << RT2661_SHIFT_D)); 994 RT2661_EEPROM_CTL(sc, RT2661_S | 995 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 996 } 997 998 RT2661_EEPROM_CTL(sc, RT2661_S); 999 1000 /* read data Q15-Q0 */ 1001 val = 0; 1002 for (n = 15; n >= 0; n--) { 1003 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 1004 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 1005 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 1006 RT2661_EEPROM_CTL(sc, RT2661_S); 1007 } 1008 1009 RT2661_EEPROM_CTL(sc, 0); 1010 1011 /* clear Chip Select and clock C */ 1012 RT2661_EEPROM_CTL(sc, RT2661_S); 1013 RT2661_EEPROM_CTL(sc, 0); 1014 RT2661_EEPROM_CTL(sc, RT2661_C); 1015 1016 return val; 1017 } 1018 1019 static void 1020 rt2661_tx_intr(struct rt2661_softc *sc) 1021 { 1022 struct ieee80211com *ic = &sc->sc_ic; 1023 struct ifnet *ifp = &sc->sc_if; 1024 struct rt2661_tx_ring *txq; 1025 struct rt2661_tx_data *data; 1026 struct rt2661_node *rn; 1027 uint32_t val; 1028 int qid, retrycnt; 1029 1030 for (;;) { 1031 val = RAL_READ(sc, RT2661_STA_CSR4); 1032 if (!(val & RT2661_TX_STAT_VALID)) 1033 break; 1034 1035 /* retrieve the queue in which this frame was sent */ 1036 qid = RT2661_TX_QID(val); 1037 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 1038 1039 /* retrieve rate control algorithm context */ 1040 data = &txq->data[txq->stat]; 1041 rn = (struct rt2661_node *)data->ni; 1042 1043 /* if no frame has been sent, ignore */ 1044 if (rn == NULL) 1045 continue; 1046 1047 switch (RT2661_TX_RESULT(val)) { 1048 case RT2661_TX_SUCCESS: 1049 retrycnt = RT2661_TX_RETRYCNT(val); 1050 1051 DPRINTFN(10, ("data frame sent successfully after " 1052 "%d retries\n", retrycnt)); 1053 if (retrycnt == 0 && data->id.id_node != NULL) { 1054 ieee80211_rssadapt_raise_rate(ic, 1055 &rn->rssadapt, &data->id); 1056 } 1057 ifp->if_opackets++; 1058 break; 1059 1060 case RT2661_TX_RETRY_FAIL: 1061 DPRINTFN(9, ("sending data frame failed (too much " 1062 "retries)\n")); 1063 if (data->id.id_node != NULL) { 1064 ieee80211_rssadapt_lower_rate(ic, data->ni, 1065 &rn->rssadapt, &data->id); 1066 } 1067 ifp->if_oerrors++; 1068 break; 1069 1070 default: 1071 /* other failure */ 1072 aprint_error_dev(&sc->sc_dev, "sending data frame failed 0x%08x\n", val); 1073 ifp->if_oerrors++; 1074 } 1075 1076 ieee80211_free_node(data->ni); 1077 data->ni = NULL; 1078 1079 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 1080 1081 txq->queued--; 1082 if (++txq->stat >= txq->count) /* faster than % count */ 1083 txq->stat = 0; 1084 } 1085 1086 sc->sc_tx_timer = 0; 1087 ifp->if_flags &= ~IFF_OACTIVE; 1088 rt2661_start(ifp); 1089 } 1090 1091 static void 1092 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1093 { 1094 struct rt2661_tx_desc *desc; 1095 struct rt2661_tx_data *data; 1096 1097 for (;;) { 1098 desc = &txq->desc[txq->next]; 1099 data = &txq->data[txq->next]; 1100 1101 bus_dmamap_sync(sc->sc_dmat, txq->map, 1102 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1103 BUS_DMASYNC_POSTREAD); 1104 1105 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1106 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1107 break; 1108 1109 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1110 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1111 bus_dmamap_unload(sc->sc_dmat, data->map); 1112 m_freem(data->m); 1113 data->m = NULL; 1114 /* node reference is released in rt2661_tx_intr() */ 1115 1116 /* descriptor is no longer valid */ 1117 desc->flags &= ~htole32(RT2661_TX_VALID); 1118 1119 bus_dmamap_sync(sc->sc_dmat, txq->map, 1120 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1121 BUS_DMASYNC_PREWRITE); 1122 1123 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1124 1125 if (++txq->next >= txq->count) /* faster than % count */ 1126 txq->next = 0; 1127 } 1128 } 1129 1130 static void 1131 rt2661_rx_intr(struct rt2661_softc *sc) 1132 { 1133 struct ieee80211com *ic = &sc->sc_ic; 1134 struct ifnet *ifp = &sc->sc_if; 1135 struct rt2661_rx_desc *desc; 1136 struct rt2661_rx_data *data; 1137 struct rt2661_node *rn; 1138 struct ieee80211_frame *wh; 1139 struct ieee80211_node *ni; 1140 struct mbuf *mnew, *m; 1141 int error; 1142 1143 for (;;) { 1144 desc = &sc->rxq.desc[sc->rxq.cur]; 1145 data = &sc->rxq.data[sc->rxq.cur]; 1146 1147 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1148 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1149 BUS_DMASYNC_POSTREAD); 1150 1151 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1152 break; 1153 1154 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1155 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1156 /* 1157 * This should not happen since we did not request 1158 * to receive those frames when we filled TXRX_CSR0. 1159 */ 1160 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1161 le32toh(desc->flags))); 1162 ifp->if_ierrors++; 1163 goto skip; 1164 } 1165 1166 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1167 ifp->if_ierrors++; 1168 goto skip; 1169 } 1170 1171 /* 1172 * Try to allocate a new mbuf for this ring element and load it 1173 * before processing the current mbuf. If the ring element 1174 * cannot be loaded, drop the received packet and reuse the old 1175 * mbuf. In the unlikely case that the old mbuf can't be 1176 * reloaded either, explicitly panic. 1177 */ 1178 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1179 if (mnew == NULL) { 1180 ifp->if_ierrors++; 1181 goto skip; 1182 } 1183 1184 MCLGET(mnew, M_DONTWAIT); 1185 if (!(mnew->m_flags & M_EXT)) { 1186 m_freem(mnew); 1187 ifp->if_ierrors++; 1188 goto skip; 1189 } 1190 1191 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1192 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1193 bus_dmamap_unload(sc->sc_dmat, data->map); 1194 1195 error = bus_dmamap_load(sc->sc_dmat, data->map, 1196 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1197 if (error != 0) { 1198 m_freem(mnew); 1199 1200 /* try to reload the old mbuf */ 1201 error = bus_dmamap_load(sc->sc_dmat, data->map, 1202 mtod(data->m, void *), MCLBYTES, NULL, 1203 BUS_DMA_NOWAIT); 1204 if (error != 0) { 1205 /* very unlikely that it will fail... */ 1206 panic("%s: could not load old rx mbuf", 1207 device_xname(&sc->sc_dev)); 1208 } 1209 /* physical address may have changed */ 1210 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1211 ifp->if_ierrors++; 1212 goto skip; 1213 } 1214 1215 /* 1216 * New mbuf successfully loaded, update Rx ring and continue 1217 * processing. 1218 */ 1219 m = data->m; 1220 data->m = mnew; 1221 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1222 1223 /* finalize mbuf */ 1224 m->m_pkthdr.rcvif = ifp; 1225 m->m_pkthdr.len = m->m_len = 1226 (le32toh(desc->flags) >> 16) & 0xfff; 1227 1228 #if NBPFILTER > 0 1229 if (sc->sc_drvbpf != NULL) { 1230 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1231 uint32_t tsf_lo, tsf_hi; 1232 1233 /* get timestamp (low and high 32 bits) */ 1234 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1235 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1236 1237 tap->wr_tsf = 1238 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1239 tap->wr_flags = 0; 1240 tap->wr_rate = rt2661_rxrate(desc); 1241 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1242 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1243 tap->wr_antsignal = desc->rssi; 1244 1245 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1246 } 1247 #endif 1248 1249 wh = mtod(m, struct ieee80211_frame *); 1250 ni = ieee80211_find_rxnode(ic, 1251 (struct ieee80211_frame_min *)wh); 1252 1253 /* send the frame to the 802.11 layer */ 1254 ieee80211_input(ic, m, ni, desc->rssi, 0); 1255 1256 1257 /* give rssi to the rate adatation algorithm */ 1258 rn = (struct rt2661_node *)ni; 1259 ieee80211_rssadapt_input(ic, ni, &rn->rssadapt, 1260 rt2661_get_rssi(sc, desc->rssi)); 1261 1262 /* node is no longer needed */ 1263 ieee80211_free_node(ni); 1264 1265 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1266 1267 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1268 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1269 BUS_DMASYNC_PREWRITE); 1270 1271 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1272 1273 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1274 } 1275 1276 /* 1277 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 1278 * without calling if_start(). 1279 */ 1280 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 1281 rt2661_start(ifp); 1282 } 1283 1284 /* ARGSUSED */ 1285 static void 1286 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1287 { 1288 /* do nothing */ 1289 } 1290 1291 static void 1292 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1293 { 1294 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1295 1296 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1297 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1298 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1299 1300 /* send wakeup command to MCU */ 1301 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1302 } 1303 1304 static void 1305 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1306 { 1307 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1308 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1309 } 1310 1311 int 1312 rt2661_intr(void *arg) 1313 { 1314 struct rt2661_softc *sc = arg; 1315 struct ifnet *ifp = &sc->sc_if; 1316 uint32_t r1, r2; 1317 1318 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1319 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1320 if (r1 == 0 && r2 == 0) 1321 return 0; /* not for us */ 1322 1323 /* disable MAC and MCU interrupts */ 1324 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1325 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1326 1327 /* acknowledge interrupts */ 1328 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1329 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1330 1331 /* don't re-enable interrupts if we're shutting down */ 1332 if (!(ifp->if_flags & IFF_RUNNING)) 1333 return 0; 1334 1335 if (r1 & RT2661_MGT_DONE) 1336 rt2661_tx_dma_intr(sc, &sc->mgtq); 1337 1338 if (r1 & RT2661_RX_DONE) 1339 rt2661_rx_intr(sc); 1340 1341 if (r1 & RT2661_TX0_DMA_DONE) 1342 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1343 1344 if (r1 & RT2661_TX1_DMA_DONE) 1345 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1346 1347 if (r1 & RT2661_TX2_DMA_DONE) 1348 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1349 1350 if (r1 & RT2661_TX3_DMA_DONE) 1351 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1352 1353 if (r1 & RT2661_TX_DONE) 1354 rt2661_tx_intr(sc); 1355 1356 if (r2 & RT2661_MCU_CMD_DONE) 1357 rt2661_mcu_cmd_intr(sc); 1358 1359 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1360 rt2661_mcu_beacon_expire(sc); 1361 1362 if (r2 & RT2661_MCU_WAKEUP) 1363 rt2661_mcu_wakeup(sc); 1364 1365 /* re-enable MAC and MCU interrupts */ 1366 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1367 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1368 1369 return 1; 1370 } 1371 1372 /* quickly determine if a given rate is CCK or OFDM */ 1373 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1374 1375 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1376 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1377 1378 #define RAL_SIFS 10 /* us */ 1379 1380 /* 1381 * This function is only used by the Rx radiotap code. It returns the rate at 1382 * which a given frame was received. 1383 */ 1384 #if NBPFILTER > 0 1385 static uint8_t 1386 rt2661_rxrate(struct rt2661_rx_desc *desc) 1387 { 1388 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1389 /* reverse function of rt2661_plcp_signal */ 1390 switch (desc->rate & 0xf) { 1391 case 0xb: return 12; 1392 case 0xf: return 18; 1393 case 0xa: return 24; 1394 case 0xe: return 36; 1395 case 0x9: return 48; 1396 case 0xd: return 72; 1397 case 0x8: return 96; 1398 case 0xc: return 108; 1399 } 1400 } else { 1401 if (desc->rate == 10) 1402 return 2; 1403 if (desc->rate == 20) 1404 return 4; 1405 if (desc->rate == 55) 1406 return 11; 1407 if (desc->rate == 110) 1408 return 22; 1409 } 1410 return 2; /* should not get there */ 1411 } 1412 #endif 1413 1414 /* 1415 * Return the expected ack rate for a frame transmitted at rate `rate'. 1416 * XXX: this should depend on the destination node basic rate set. 1417 */ 1418 static int 1419 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1420 { 1421 switch (rate) { 1422 /* CCK rates */ 1423 case 2: 1424 return 2; 1425 case 4: 1426 case 11: 1427 case 22: 1428 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1429 1430 /* OFDM rates */ 1431 case 12: 1432 case 18: 1433 return 12; 1434 case 24: 1435 case 36: 1436 return 24; 1437 case 48: 1438 case 72: 1439 case 96: 1440 case 108: 1441 return 48; 1442 } 1443 1444 /* default to 1Mbps */ 1445 return 2; 1446 } 1447 1448 /* 1449 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1450 * The function automatically determines the operating mode depending on the 1451 * given rate. `flags' indicates whether short preamble is in use or not. 1452 */ 1453 static uint16_t 1454 rt2661_txtime(int len, int rate, uint32_t flags) 1455 { 1456 uint16_t txtime; 1457 1458 if (RAL_RATE_IS_OFDM(rate)) { 1459 /* IEEE Std 802.11a-1999, pp. 37 */ 1460 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1461 txtime = 16 + 4 + 4 * txtime + 6; 1462 } else { 1463 /* IEEE Std 802.11b-1999, pp. 28 */ 1464 txtime = (16 * len + rate - 1) / rate; 1465 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1466 txtime += 72 + 24; 1467 else 1468 txtime += 144 + 48; 1469 } 1470 return txtime; 1471 } 1472 1473 static uint8_t 1474 rt2661_plcp_signal(int rate) 1475 { 1476 switch (rate) { 1477 /* CCK rates (returned values are device-dependent) */ 1478 case 2: return 0x0; 1479 case 4: return 0x1; 1480 case 11: return 0x2; 1481 case 22: return 0x3; 1482 1483 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1484 case 12: return 0xb; 1485 case 18: return 0xf; 1486 case 24: return 0xa; 1487 case 36: return 0xe; 1488 case 48: return 0x9; 1489 case 72: return 0xd; 1490 case 96: return 0x8; 1491 case 108: return 0xc; 1492 1493 /* unsupported rates (should not get there) */ 1494 default: return 0xff; 1495 } 1496 } 1497 1498 static void 1499 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1500 uint32_t flags, uint16_t xflags, int len, int rate, 1501 const bus_dma_segment_t *segs, int nsegs, int ac) 1502 { 1503 struct ieee80211com *ic = &sc->sc_ic; 1504 uint16_t plcp_length; 1505 int i, remainder; 1506 1507 desc->flags = htole32(flags); 1508 desc->flags |= htole32(len << 16); 1509 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1510 1511 desc->xflags = htole16(xflags); 1512 desc->xflags |= htole16(nsegs << 13); 1513 1514 desc->wme = htole16( 1515 RT2661_QID(ac) | 1516 RT2661_AIFSN(2) | 1517 RT2661_LOGCWMIN(4) | 1518 RT2661_LOGCWMAX(10)); 1519 1520 /* 1521 * Remember in which queue this frame was sent. This field is driver 1522 * private data only. It will be made available by the NIC in STA_CSR4 1523 * on Tx interrupts. 1524 */ 1525 desc->qid = ac; 1526 1527 /* setup PLCP fields */ 1528 desc->plcp_signal = rt2661_plcp_signal(rate); 1529 desc->plcp_service = 4; 1530 1531 len += IEEE80211_CRC_LEN; 1532 if (RAL_RATE_IS_OFDM(rate)) { 1533 desc->flags |= htole32(RT2661_TX_OFDM); 1534 1535 plcp_length = len & 0xfff; 1536 desc->plcp_length_hi = plcp_length >> 6; 1537 desc->plcp_length_lo = plcp_length & 0x3f; 1538 } else { 1539 plcp_length = (16 * len + rate - 1) / rate; 1540 if (rate == 22) { 1541 remainder = (16 * len) % 22; 1542 if (remainder != 0 && remainder < 7) 1543 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1544 } 1545 desc->plcp_length_hi = plcp_length >> 8; 1546 desc->plcp_length_lo = plcp_length & 0xff; 1547 1548 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1549 desc->plcp_signal |= 0x08; 1550 } 1551 1552 /* RT2x61 supports scatter with up to 5 segments */ 1553 for (i = 0; i < nsegs; i++) { 1554 desc->addr[i] = htole32(segs[i].ds_addr); 1555 desc->len [i] = htole16(segs[i].ds_len); 1556 } 1557 } 1558 1559 static int 1560 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1561 struct ieee80211_node *ni) 1562 { 1563 struct ieee80211com *ic = &sc->sc_ic; 1564 struct rt2661_tx_desc *desc; 1565 struct rt2661_tx_data *data; 1566 struct ieee80211_frame *wh; 1567 struct ieee80211_key *k; 1568 uint16_t dur; 1569 uint32_t flags = 0; 1570 int rate, error; 1571 1572 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1573 data = &sc->mgtq.data[sc->mgtq.cur]; 1574 1575 /* send mgt frames at the lowest available rate */ 1576 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1577 1578 wh = mtod(m0, struct ieee80211_frame *); 1579 1580 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1581 k = ieee80211_crypto_encap(ic, ni, m0); 1582 if (k == NULL) { 1583 m_freem(m0); 1584 return ENOBUFS; 1585 } 1586 } 1587 1588 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1589 BUS_DMA_NOWAIT); 1590 if (error != 0) { 1591 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", 1592 error); 1593 m_freem(m0); 1594 return error; 1595 } 1596 1597 #if NBPFILTER > 0 1598 if (sc->sc_drvbpf != NULL) { 1599 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1600 1601 tap->wt_flags = 0; 1602 tap->wt_rate = rate; 1603 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1604 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1605 1606 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1607 } 1608 #endif 1609 1610 data->m = m0; 1611 data->ni = ni; 1612 1613 wh = mtod(m0, struct ieee80211_frame *); 1614 1615 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1616 flags |= RT2661_TX_NEED_ACK; 1617 1618 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1619 RAL_SIFS; 1620 *(uint16_t *)wh->i_dur = htole16(dur); 1621 1622 /* tell hardware to add timestamp in probe responses */ 1623 if ((wh->i_fc[0] & 1624 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1625 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1626 flags |= RT2661_TX_TIMESTAMP; 1627 } 1628 1629 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1630 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1631 RT2661_QID_MGT); 1632 1633 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1634 BUS_DMASYNC_PREWRITE); 1635 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1636 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1637 BUS_DMASYNC_PREWRITE); 1638 1639 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1640 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1641 1642 /* kick mgt */ 1643 sc->mgtq.queued++; 1644 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1645 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1646 1647 return 0; 1648 } 1649 1650 /* 1651 * Build a RTS control frame. 1652 */ 1653 static struct mbuf * 1654 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1655 uint16_t dur) 1656 { 1657 struct ieee80211_frame_rts *rts; 1658 struct mbuf *m; 1659 1660 MGETHDR(m, M_DONTWAIT, MT_DATA); 1661 if (m == NULL) { 1662 sc->sc_ic.ic_stats.is_tx_nobuf++; 1663 aprint_error_dev(&sc->sc_dev, "could not allocate RTS frame\n"); 1664 return NULL; 1665 } 1666 1667 rts = mtod(m, struct ieee80211_frame_rts *); 1668 1669 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1670 IEEE80211_FC0_SUBTYPE_RTS; 1671 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1672 *(uint16_t *)rts->i_dur = htole16(dur); 1673 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1674 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1675 1676 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1677 1678 return m; 1679 } 1680 1681 static int 1682 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1683 struct ieee80211_node *ni, int ac) 1684 { 1685 struct ieee80211com *ic = &sc->sc_ic; 1686 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1687 struct rt2661_tx_desc *desc; 1688 struct rt2661_tx_data *data; 1689 struct rt2661_node *rn; 1690 struct ieee80211_rateset *rs; 1691 struct ieee80211_frame *wh; 1692 struct ieee80211_key *k; 1693 struct mbuf *mnew; 1694 uint16_t dur; 1695 uint32_t flags = 0; 1696 int rate, error; 1697 1698 wh = mtod(m0, struct ieee80211_frame *); 1699 1700 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1701 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1702 rate = rs->rs_rates[ic->ic_fixed_rate]; 1703 } else { 1704 rs = &ni->ni_rates; 1705 rn = (struct rt2661_node *)ni; 1706 ni->ni_txrate = ieee80211_rssadapt_choose(&rn->rssadapt, rs, 1707 wh, m0->m_pkthdr.len, -1, NULL, 0); 1708 rate = rs->rs_rates[ni->ni_txrate]; 1709 } 1710 rate &= IEEE80211_RATE_VAL; 1711 1712 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1713 k = ieee80211_crypto_encap(ic, ni, m0); 1714 if (k == NULL) { 1715 m_freem(m0); 1716 return ENOBUFS; 1717 } 1718 1719 /* packet header may have moved, reset our local pointer */ 1720 wh = mtod(m0, struct ieee80211_frame *); 1721 } 1722 1723 /* 1724 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1725 * for directed frames only when the length of the MPDU is greater 1726 * than the length threshold indicated by [...]" ic_rtsthreshold. 1727 */ 1728 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1729 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1730 struct mbuf *m; 1731 int rtsrate, ackrate; 1732 1733 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1734 ackrate = rt2661_ack_rate(ic, rate); 1735 1736 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1737 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1738 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1739 3 * RAL_SIFS; 1740 1741 m = rt2661_get_rts(sc, wh, dur); 1742 1743 desc = &txq->desc[txq->cur]; 1744 data = &txq->data[txq->cur]; 1745 1746 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1747 BUS_DMA_NOWAIT); 1748 if (error != 0) { 1749 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", error); 1750 m_freem(m); 1751 m_freem(m0); 1752 return error; 1753 } 1754 1755 /* avoid multiple free() of the same node for each fragment */ 1756 ieee80211_ref_node(ni); 1757 1758 data->m = m; 1759 data->ni = ni; 1760 1761 /* RTS frames are not taken into account for rssadapt */ 1762 data->id.id_node = NULL; 1763 1764 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1765 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, 1766 data->map->dm_segs, data->map->dm_nsegs, ac); 1767 1768 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1769 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1770 bus_dmamap_sync(sc->sc_dmat, txq->map, 1771 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1772 BUS_DMASYNC_PREWRITE); 1773 1774 txq->queued++; 1775 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1776 1777 /* 1778 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1779 * asynchronous data frame shall be transmitted after the CTS 1780 * frame and a SIFS period. 1781 */ 1782 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1783 } 1784 1785 data = &txq->data[txq->cur]; 1786 desc = &txq->desc[txq->cur]; 1787 1788 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1789 BUS_DMA_NOWAIT); 1790 if (error != 0 && error != EFBIG) { 1791 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", 1792 error); 1793 m_freem(m0); 1794 return error; 1795 } 1796 if (error != 0) { 1797 /* too many fragments, linearize */ 1798 1799 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1800 if (mnew == NULL) { 1801 m_freem(m0); 1802 return ENOMEM; 1803 } 1804 1805 M_COPY_PKTHDR(mnew, m0); 1806 if (m0->m_pkthdr.len > MHLEN) { 1807 MCLGET(mnew, M_DONTWAIT); 1808 if (!(mnew->m_flags & M_EXT)) { 1809 m_freem(m0); 1810 m_freem(mnew); 1811 return ENOMEM; 1812 } 1813 } 1814 1815 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1816 m_freem(m0); 1817 mnew->m_len = mnew->m_pkthdr.len; 1818 m0 = mnew; 1819 1820 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1821 BUS_DMA_NOWAIT); 1822 if (error != 0) { 1823 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", error); 1824 m_freem(m0); 1825 return error; 1826 } 1827 1828 /* packet header have moved, reset our local pointer */ 1829 wh = mtod(m0, struct ieee80211_frame *); 1830 } 1831 1832 #if NBPFILTER > 0 1833 if (sc->sc_drvbpf != NULL) { 1834 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1835 1836 tap->wt_flags = 0; 1837 tap->wt_rate = rate; 1838 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1839 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1840 1841 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1842 } 1843 #endif 1844 1845 data->m = m0; 1846 data->ni = ni; 1847 1848 /* remember link conditions for rate adaptation algorithm */ 1849 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1850 data->id.id_len = m0->m_pkthdr.len; 1851 data->id.id_rateidx = ni->ni_txrate; 1852 data->id.id_node = ni; 1853 data->id.id_rssi = ni->ni_rssi; 1854 } else 1855 data->id.id_node = NULL; 1856 1857 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1858 flags |= RT2661_TX_NEED_ACK; 1859 1860 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1861 ic->ic_flags) + RAL_SIFS; 1862 *(uint16_t *)wh->i_dur = htole16(dur); 1863 } 1864 1865 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1866 data->map->dm_segs, data->map->dm_nsegs, ac); 1867 1868 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1869 BUS_DMASYNC_PREWRITE); 1870 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1871 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1872 1873 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1874 m0->m_pkthdr.len, txq->cur, rate)); 1875 1876 /* kick Tx */ 1877 txq->queued++; 1878 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1879 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1880 1881 return 0; 1882 } 1883 1884 static void 1885 rt2661_start(struct ifnet *ifp) 1886 { 1887 struct rt2661_softc *sc = ifp->if_softc; 1888 struct ieee80211com *ic = &sc->sc_ic; 1889 struct mbuf *m0; 1890 struct ether_header *eh; 1891 struct ieee80211_node *ni = NULL; 1892 int ac; 1893 1894 /* 1895 * net80211 may still try to send management frames even if the 1896 * IFF_RUNNING flag is not set... 1897 */ 1898 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1899 return; 1900 1901 for (;;) { 1902 IF_POLL(&ic->ic_mgtq, m0); 1903 if (m0 != NULL) { 1904 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1905 ifp->if_flags |= IFF_OACTIVE; 1906 break; 1907 } 1908 IF_DEQUEUE(&ic->ic_mgtq, m0); 1909 if (m0 == NULL) 1910 break; 1911 1912 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1913 m0->m_pkthdr.rcvif = NULL; 1914 #if NBPFILTER > 0 1915 if (ic->ic_rawbpf != NULL) 1916 bpf_mtap(ic->ic_rawbpf, m0); 1917 #endif 1918 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1919 break; 1920 1921 } else { 1922 if (ic->ic_state != IEEE80211_S_RUN) 1923 break; 1924 IFQ_DEQUEUE(&ifp->if_snd, m0); 1925 if (m0 == NULL) 1926 break; 1927 1928 if (m0->m_len < sizeof (struct ether_header) && 1929 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1930 continue; 1931 1932 eh = mtod(m0, struct ether_header *); 1933 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1934 if (ni == NULL) { 1935 m_freem(m0); 1936 ifp->if_oerrors++; 1937 continue; 1938 } 1939 1940 1941 /* classify mbuf so we can find which tx ring to use */ 1942 if (ieee80211_classify(ic, m0, ni) != 0) { 1943 m_freem(m0); 1944 ieee80211_free_node(ni); 1945 ifp->if_oerrors++; 1946 continue; 1947 } 1948 1949 /* no QoS encapsulation for EAPOL frames */ 1950 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 1951 M_WME_GETAC(m0) : WME_AC_BE; 1952 1953 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1954 /* there is no place left in this ring */ 1955 ifp->if_flags |= IFF_OACTIVE; 1956 break; 1957 } 1958 #if NBPFILTER > 0 1959 if (ifp->if_bpf != NULL) 1960 bpf_mtap(ifp->if_bpf, m0); 1961 #endif 1962 m0 = ieee80211_encap(ic, m0, ni); 1963 if (m0 == NULL) { 1964 ieee80211_free_node(ni); 1965 ifp->if_oerrors++; 1966 continue; 1967 } 1968 #if NBPFILTER > 0 1969 if (ic->ic_rawbpf != NULL) 1970 bpf_mtap(ic->ic_rawbpf, m0); 1971 #endif 1972 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1973 if (ni != NULL) 1974 ieee80211_free_node(ni); 1975 ifp->if_oerrors++; 1976 break; 1977 } 1978 } 1979 1980 sc->sc_tx_timer = 5; 1981 ifp->if_timer = 1; 1982 } 1983 } 1984 1985 static void 1986 rt2661_watchdog(struct ifnet *ifp) 1987 { 1988 struct rt2661_softc *sc = ifp->if_softc; 1989 1990 ifp->if_timer = 0; 1991 1992 if (sc->sc_tx_timer > 0) { 1993 if (--sc->sc_tx_timer == 0) { 1994 aprint_error_dev(&sc->sc_dev, "device timeout\n"); 1995 rt2661_init(ifp); 1996 ifp->if_oerrors++; 1997 return; 1998 } 1999 ifp->if_timer = 1; 2000 } 2001 2002 ieee80211_watchdog(&sc->sc_ic); 2003 } 2004 2005 /* 2006 * This function allows for fast channel switching in monitor mode (used by 2007 * kismet). In IBSS mode, we must explicitly reset the interface to 2008 * generate a new beacon frame. 2009 */ 2010 static int 2011 rt2661_reset(struct ifnet *ifp) 2012 { 2013 struct rt2661_softc *sc = ifp->if_softc; 2014 struct ieee80211com *ic = &sc->sc_ic; 2015 2016 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2017 return ENETRESET; 2018 2019 rt2661_set_chan(sc, ic->ic_curchan); 2020 2021 return 0; 2022 } 2023 2024 static int 2025 rt2661_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2026 { 2027 struct rt2661_softc *sc = ifp->if_softc; 2028 struct ieee80211com *ic = &sc->sc_ic; 2029 int s, error = 0; 2030 2031 s = splnet(); 2032 2033 switch (cmd) { 2034 case SIOCSIFFLAGS: 2035 if (ifp->if_flags & IFF_UP) { 2036 if (ifp->if_flags & IFF_RUNNING) 2037 rt2661_update_promisc(sc); 2038 else 2039 rt2661_init(ifp); 2040 } else { 2041 if (ifp->if_flags & IFF_RUNNING) 2042 rt2661_stop(ifp, 1); 2043 } 2044 break; 2045 2046 case SIOCADDMULTI: 2047 case SIOCDELMULTI: 2048 /* XXX no h/w multicast filter? --dyoung */ 2049 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2050 error = 0; 2051 break; 2052 2053 case SIOCS80211CHANNEL: 2054 /* 2055 * This allows for fast channel switching in monitor mode 2056 * (used by kismet). In IBSS mode, we must explicitly reset 2057 * the interface to generate a new beacon frame. 2058 */ 2059 error = ieee80211_ioctl(ic, cmd, data); 2060 if (error == ENETRESET && 2061 ic->ic_opmode == IEEE80211_M_MONITOR) { 2062 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2063 (IFF_UP | IFF_RUNNING)) 2064 rt2661_set_chan(sc, ic->ic_ibss_chan); 2065 error = 0; 2066 } 2067 break; 2068 2069 default: 2070 error = ieee80211_ioctl(ic, cmd, data); 2071 2072 } 2073 2074 if (error == ENETRESET) { 2075 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2076 (IFF_UP | IFF_RUNNING)) 2077 rt2661_init(ifp); 2078 error = 0; 2079 } 2080 2081 splx(s); 2082 2083 return error; 2084 } 2085 2086 static void 2087 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 2088 { 2089 uint32_t tmp; 2090 int ntries; 2091 2092 for (ntries = 0; ntries < 100; ntries++) { 2093 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2094 break; 2095 DELAY(1); 2096 } 2097 if (ntries == 100) { 2098 aprint_error_dev(&sc->sc_dev, "could not write to BBP\n"); 2099 return; 2100 } 2101 2102 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 2103 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 2104 2105 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 2106 } 2107 2108 static uint8_t 2109 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2110 { 2111 uint32_t val; 2112 int ntries; 2113 2114 for (ntries = 0; ntries < 100; ntries++) { 2115 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2116 break; 2117 DELAY(1); 2118 } 2119 if (ntries == 100) { 2120 aprint_error_dev(&sc->sc_dev, "could not read from BBP\n"); 2121 return 0; 2122 } 2123 2124 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2125 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2126 2127 for (ntries = 0; ntries < 100; ntries++) { 2128 val = RAL_READ(sc, RT2661_PHY_CSR3); 2129 if (!(val & RT2661_BBP_BUSY)) 2130 return val & 0xff; 2131 DELAY(1); 2132 } 2133 2134 aprint_error_dev(&sc->sc_dev, "could not read from BBP\n"); 2135 return 0; 2136 } 2137 2138 static void 2139 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2140 { 2141 uint32_t tmp; 2142 int ntries; 2143 2144 for (ntries = 0; ntries < 100; ntries++) { 2145 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2146 break; 2147 DELAY(1); 2148 } 2149 if (ntries == 100) { 2150 aprint_error_dev(&sc->sc_dev, "could not write to RF\n"); 2151 return; 2152 } 2153 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2154 (reg & 3); 2155 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2156 2157 /* remember last written value in sc */ 2158 sc->rf_regs[reg] = val; 2159 2160 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2161 } 2162 2163 static int 2164 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2165 { 2166 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2167 return EIO; /* there is already a command pending */ 2168 2169 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2170 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2171 2172 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2173 2174 return 0; 2175 } 2176 2177 static void 2178 rt2661_select_antenna(struct rt2661_softc *sc) 2179 { 2180 uint8_t bbp4, bbp77; 2181 uint32_t tmp; 2182 2183 bbp4 = rt2661_bbp_read(sc, 4); 2184 bbp77 = rt2661_bbp_read(sc, 77); 2185 2186 /* TBD */ 2187 2188 /* make sure Rx is disabled before switching antenna */ 2189 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2190 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2191 2192 rt2661_bbp_write(sc, 4, bbp4); 2193 rt2661_bbp_write(sc, 77, bbp77); 2194 2195 /* restore Rx filter */ 2196 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2197 } 2198 2199 /* 2200 * Enable multi-rate retries for frames sent at OFDM rates. 2201 * In 802.11b/g mode, allow fallback to CCK rates. 2202 */ 2203 static void 2204 rt2661_enable_mrr(struct rt2661_softc *sc) 2205 { 2206 struct ieee80211com *ic = &sc->sc_ic; 2207 uint32_t tmp; 2208 2209 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2210 2211 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2212 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2213 tmp |= RT2661_MRR_CCK_FALLBACK; 2214 tmp |= RT2661_MRR_ENABLED; 2215 2216 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2217 } 2218 2219 static void 2220 rt2661_set_txpreamble(struct rt2661_softc *sc) 2221 { 2222 uint32_t tmp; 2223 2224 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2225 2226 tmp &= ~RT2661_SHORT_PREAMBLE; 2227 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2228 tmp |= RT2661_SHORT_PREAMBLE; 2229 2230 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2231 } 2232 2233 static void 2234 rt2661_set_basicrates(struct rt2661_softc *sc, 2235 const struct ieee80211_rateset *rs) 2236 { 2237 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2238 uint32_t mask = 0; 2239 uint8_t rate; 2240 int i, j; 2241 2242 for (i = 0; i < rs->rs_nrates; i++) { 2243 rate = rs->rs_rates[i]; 2244 2245 if (!(rate & IEEE80211_RATE_BASIC)) 2246 continue; 2247 2248 /* 2249 * Find h/w rate index. We know it exists because the rate 2250 * set has already been negotiated. 2251 */ 2252 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++); 2253 2254 mask |= 1 << j; 2255 } 2256 2257 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2258 2259 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2260 #undef RV 2261 } 2262 2263 /* 2264 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2265 * driver. 2266 */ 2267 static void 2268 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2269 { 2270 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2271 uint32_t tmp; 2272 2273 /* update all BBP registers that depend on the band */ 2274 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2275 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2276 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2277 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2278 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2279 } 2280 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2281 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2282 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2283 } 2284 2285 rt2661_bbp_write(sc, 17, bbp17); 2286 rt2661_bbp_write(sc, 96, bbp96); 2287 rt2661_bbp_write(sc, 104, bbp104); 2288 2289 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2290 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2291 rt2661_bbp_write(sc, 75, 0x80); 2292 rt2661_bbp_write(sc, 86, 0x80); 2293 rt2661_bbp_write(sc, 88, 0x80); 2294 } 2295 2296 rt2661_bbp_write(sc, 35, bbp35); 2297 rt2661_bbp_write(sc, 97, bbp97); 2298 rt2661_bbp_write(sc, 98, bbp98); 2299 2300 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2301 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2302 if (IEEE80211_IS_CHAN_2GHZ(c)) 2303 tmp |= RT2661_PA_PE_2GHZ; 2304 else 2305 tmp |= RT2661_PA_PE_5GHZ; 2306 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2307 } 2308 2309 static void 2310 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2311 { 2312 struct ieee80211com *ic = &sc->sc_ic; 2313 const struct rfprog *rfprog; 2314 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2315 int8_t power; 2316 u_int i, chan; 2317 2318 chan = ieee80211_chan2ieee(ic, c); 2319 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2320 return; 2321 2322 /* select the appropriate RF settings based on what EEPROM says */ 2323 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2324 2325 /* find the settings for this channel (we know it exists) */ 2326 for (i = 0; rfprog[i].chan != chan; i++); 2327 2328 power = sc->txpow[i]; 2329 if (power < 0) { 2330 bbp94 += power; 2331 power = 0; 2332 } else if (power > 31) { 2333 bbp94 += power - 31; 2334 power = 31; 2335 } 2336 2337 /* 2338 * If we've yet to select a channel, or we are switching from the 2339 * 2GHz band to the 5GHz band or vice-versa, BBP registers need to 2340 * be reprogrammed. 2341 */ 2342 if (sc->sc_curchan == NULL || c->ic_flags != sc->sc_curchan->ic_flags) { 2343 rt2661_select_band(sc, c); 2344 rt2661_select_antenna(sc); 2345 } 2346 sc->sc_curchan = c; 2347 2348 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2349 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2350 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2351 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2352 2353 DELAY(200); 2354 2355 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2356 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2357 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2358 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2359 2360 DELAY(200); 2361 2362 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2363 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2364 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2365 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2366 2367 /* enable smart mode for MIMO-capable RFs */ 2368 bbp3 = rt2661_bbp_read(sc, 3); 2369 2370 bbp3 &= ~RT2661_SMART_MODE; 2371 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2372 bbp3 |= RT2661_SMART_MODE; 2373 2374 rt2661_bbp_write(sc, 3, bbp3); 2375 2376 if (bbp94 != RT2661_BBPR94_DEFAULT) 2377 rt2661_bbp_write(sc, 94, bbp94); 2378 2379 /* 5GHz radio needs a 1ms delay here */ 2380 if (IEEE80211_IS_CHAN_5GHZ(c)) 2381 DELAY(1000); 2382 } 2383 2384 static void 2385 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2386 { 2387 uint32_t tmp; 2388 2389 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2390 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2391 2392 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2393 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2394 } 2395 2396 static void 2397 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2398 { 2399 uint32_t tmp; 2400 2401 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2402 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2403 2404 tmp = addr[4] | addr[5] << 8; 2405 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2406 } 2407 2408 static void 2409 rt2661_update_promisc(struct rt2661_softc *sc) 2410 { 2411 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2412 uint32_t tmp; 2413 2414 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2415 2416 tmp &= ~RT2661_DROP_NOT_TO_ME; 2417 if (!(ifp->if_flags & IFF_PROMISC)) 2418 tmp |= RT2661_DROP_NOT_TO_ME; 2419 2420 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2421 2422 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2423 "entering" : "leaving")); 2424 } 2425 2426 #if 0 2427 /* 2428 * Update QoS (802.11e) settings for each h/w Tx ring. 2429 */ 2430 static int 2431 rt2661_wme_update(struct ieee80211com *ic) 2432 { 2433 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2434 const struct wmeParams *wmep; 2435 2436 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2437 2438 /* XXX: not sure about shifts. */ 2439 /* XXX: the reference driver plays with AC_VI settings too. */ 2440 2441 /* update TxOp */ 2442 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2443 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2444 wmep[WME_AC_BK].wmep_txopLimit); 2445 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2446 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2447 wmep[WME_AC_VO].wmep_txopLimit); 2448 2449 /* update CWmin */ 2450 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2451 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2452 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2453 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2454 wmep[WME_AC_VO].wmep_logcwmin); 2455 2456 /* update CWmax */ 2457 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2458 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2459 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2460 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2461 wmep[WME_AC_VO].wmep_logcwmax); 2462 2463 /* update Aifsn */ 2464 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2465 wmep[WME_AC_BE].wmep_aifsn << 12 | 2466 wmep[WME_AC_BK].wmep_aifsn << 8 | 2467 wmep[WME_AC_VI].wmep_aifsn << 4 | 2468 wmep[WME_AC_VO].wmep_aifsn); 2469 2470 return 0; 2471 } 2472 #endif 2473 2474 static void 2475 rt2661_update_slot(struct ifnet *ifp) 2476 { 2477 struct rt2661_softc *sc = ifp->if_softc; 2478 struct ieee80211com *ic = &sc->sc_ic; 2479 uint8_t slottime; 2480 uint32_t tmp; 2481 2482 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2483 2484 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2485 tmp = (tmp & ~0xff) | slottime; 2486 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2487 } 2488 2489 static const char * 2490 rt2661_get_rf(int rev) 2491 { 2492 switch (rev) { 2493 case RT2661_RF_5225: return "RT5225"; 2494 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2495 case RT2661_RF_2527: return "RT2527"; 2496 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2497 default: return "unknown"; 2498 } 2499 } 2500 2501 static void 2502 rt2661_read_eeprom(struct rt2661_softc *sc) 2503 { 2504 struct ieee80211com *ic = &sc->sc_ic; 2505 uint16_t val; 2506 int i; 2507 2508 /* read MAC address */ 2509 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2510 ic->ic_myaddr[0] = val & 0xff; 2511 ic->ic_myaddr[1] = val >> 8; 2512 2513 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2514 ic->ic_myaddr[2] = val & 0xff; 2515 ic->ic_myaddr[3] = val >> 8; 2516 2517 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2518 ic->ic_myaddr[4] = val & 0xff; 2519 ic->ic_myaddr[5] = val >> 8; 2520 2521 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2522 /* XXX: test if different from 0xffff? */ 2523 sc->rf_rev = (val >> 11) & 0x1f; 2524 sc->hw_radio = (val >> 10) & 0x1; 2525 sc->rx_ant = (val >> 4) & 0x3; 2526 sc->tx_ant = (val >> 2) & 0x3; 2527 sc->nb_ant = val & 0x3; 2528 2529 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2530 2531 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2532 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2533 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2534 2535 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2536 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2537 2538 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2539 if ((val & 0xff) != 0xff) 2540 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2541 2542 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2543 if ((val & 0xff) != 0xff) 2544 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2545 2546 /* adjust RSSI correction for external low-noise amplifier */ 2547 if (sc->ext_2ghz_lna) 2548 sc->rssi_2ghz_corr -= 14; 2549 if (sc->ext_5ghz_lna) 2550 sc->rssi_5ghz_corr -= 14; 2551 2552 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2553 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2554 2555 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2556 if ((val >> 8) != 0xff) 2557 sc->rfprog = (val >> 8) & 0x3; 2558 if ((val & 0xff) != 0xff) 2559 sc->rffreq = val & 0xff; 2560 2561 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2562 2563 /* read Tx power for all a/b/g channels */ 2564 for (i = 0; i < 19; i++) { 2565 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2566 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2567 DPRINTF(("Channel=%d Tx power=%d\n", 2568 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2569 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2570 DPRINTF(("Channel=%d Tx power=%d\n", 2571 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2572 } 2573 2574 /* read vendor-specific BBP values */ 2575 for (i = 0; i < 16; i++) { 2576 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2577 if (val == 0 || val == 0xffff) 2578 continue; /* skip invalid entries */ 2579 sc->bbp_prom[i].reg = val >> 8; 2580 sc->bbp_prom[i].val = val & 0xff; 2581 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2582 sc->bbp_prom[i].val)); 2583 } 2584 } 2585 2586 static int 2587 rt2661_bbp_init(struct rt2661_softc *sc) 2588 { 2589 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2590 int i, ntries; 2591 uint8_t val; 2592 2593 /* wait for BBP to be ready */ 2594 for (ntries = 0; ntries < 100; ntries++) { 2595 val = rt2661_bbp_read(sc, 0); 2596 if (val != 0 && val != 0xff) 2597 break; 2598 DELAY(100); 2599 } 2600 if (ntries == 100) { 2601 aprint_error_dev(&sc->sc_dev, "timeout waiting for BBP\n"); 2602 return EIO; 2603 } 2604 2605 /* initialize BBP registers to default values */ 2606 for (i = 0; i < N(rt2661_def_bbp); i++) { 2607 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2608 rt2661_def_bbp[i].val); 2609 } 2610 2611 /* write vendor-specific BBP values (from EEPROM) */ 2612 for (i = 0; i < 16; i++) { 2613 if (sc->bbp_prom[i].reg == 0) 2614 continue; 2615 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2616 } 2617 2618 return 0; 2619 #undef N 2620 } 2621 2622 static int 2623 rt2661_init(struct ifnet *ifp) 2624 { 2625 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2626 struct rt2661_softc *sc = ifp->if_softc; 2627 struct ieee80211com *ic = &sc->sc_ic; 2628 const char *name = NULL; /* make lint happy */ 2629 uint8_t *ucode; 2630 size_t size; 2631 uint32_t tmp, star[3]; 2632 int i, ntries; 2633 firmware_handle_t fh; 2634 2635 /* for CardBus, power on the socket */ 2636 if (!(sc->sc_flags & RT2661_ENABLED)) { 2637 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2638 aprint_error_dev(&sc->sc_dev, "could not enable device\n"); 2639 return EIO; 2640 } 2641 sc->sc_flags |= RT2661_ENABLED; 2642 } 2643 2644 rt2661_stop(ifp, 0); 2645 2646 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2647 switch (sc->sc_id) { 2648 case PCI_PRODUCT_RALINK_RT2561: 2649 name = "ral-rt2561"; 2650 break; 2651 case PCI_PRODUCT_RALINK_RT2561S: 2652 name = "ral-rt2561s"; 2653 break; 2654 case PCI_PRODUCT_RALINK_RT2661: 2655 name = "ral-rt2661"; 2656 break; 2657 } 2658 2659 if (firmware_open("ral", name, &fh) != 0) { 2660 aprint_error_dev(&sc->sc_dev, "could not open microcode %s\n", name); 2661 rt2661_stop(ifp, 1); 2662 return EIO; 2663 } 2664 2665 size = firmware_get_size(fh); 2666 if (!(ucode = firmware_malloc(size))) { 2667 aprint_error_dev(&sc->sc_dev, "could not alloc microcode memory\n"); 2668 firmware_close(fh); 2669 rt2661_stop(ifp, 1); 2670 return ENOMEM; 2671 } 2672 2673 if (firmware_read(fh, 0, ucode, size) != 0) { 2674 aprint_error_dev(&sc->sc_dev, "could not read microcode %s\n", name); 2675 firmware_free(ucode, 0); 2676 firmware_close(fh); 2677 rt2661_stop(ifp, 1); 2678 return EIO; 2679 } 2680 2681 if (rt2661_load_microcode(sc, ucode, size) != 0) { 2682 aprint_error_dev(&sc->sc_dev, "could not load 8051 microcode\n"); 2683 firmware_free(ucode, 0); 2684 firmware_close(fh); 2685 rt2661_stop(ifp, 1); 2686 return EIO; 2687 } 2688 2689 firmware_free(ucode, 0); 2690 firmware_close(fh); 2691 sc->sc_flags |= RT2661_FWLOADED; 2692 } 2693 2694 /* initialize Tx rings */ 2695 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2696 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2697 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2698 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2699 2700 /* initialize Mgt ring */ 2701 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2702 2703 /* initialize Rx ring */ 2704 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2705 2706 /* initialize Tx rings sizes */ 2707 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2708 RT2661_TX_RING_COUNT << 24 | 2709 RT2661_TX_RING_COUNT << 16 | 2710 RT2661_TX_RING_COUNT << 8 | 2711 RT2661_TX_RING_COUNT); 2712 2713 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2714 RT2661_TX_DESC_WSIZE << 16 | 2715 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2716 RT2661_MGT_RING_COUNT); 2717 2718 /* initialize Rx rings */ 2719 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2720 RT2661_RX_DESC_BACK << 16 | 2721 RT2661_RX_DESC_WSIZE << 8 | 2722 RT2661_RX_RING_COUNT); 2723 2724 /* XXX: some magic here */ 2725 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2726 2727 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2728 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2729 2730 /* load base address of Rx ring */ 2731 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2732 2733 /* initialize MAC registers to default values */ 2734 for (i = 0; i < N(rt2661_def_mac); i++) 2735 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2736 2737 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2738 rt2661_set_macaddr(sc, ic->ic_myaddr); 2739 2740 /* set host ready */ 2741 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2742 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2743 2744 /* wait for BBP/RF to wakeup */ 2745 for (ntries = 0; ntries < 1000; ntries++) { 2746 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2747 break; 2748 DELAY(1000); 2749 } 2750 if (ntries == 1000) { 2751 printf("timeout waiting for BBP/RF to wakeup\n"); 2752 rt2661_stop(ifp, 1); 2753 return EIO; 2754 } 2755 2756 if (rt2661_bbp_init(sc) != 0) { 2757 rt2661_stop(ifp, 1); 2758 return EIO; 2759 } 2760 2761 /* select default channel */ 2762 sc->sc_curchan = ic->ic_curchan; 2763 rt2661_select_band(sc, sc->sc_curchan); 2764 rt2661_select_antenna(sc); 2765 rt2661_set_chan(sc, sc->sc_curchan); 2766 2767 /* update Rx filter */ 2768 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2769 2770 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2771 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2772 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2773 RT2661_DROP_ACKCTS; 2774 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2775 tmp |= RT2661_DROP_TODS; 2776 if (!(ifp->if_flags & IFF_PROMISC)) 2777 tmp |= RT2661_DROP_NOT_TO_ME; 2778 } 2779 2780 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2781 2782 /* clear STA registers */ 2783 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, star, N(star)); 2784 2785 /* initialize ASIC */ 2786 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2787 2788 /* clear any pending interrupt */ 2789 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2790 2791 /* enable interrupts */ 2792 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2793 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2794 2795 /* kick Rx */ 2796 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2797 2798 ifp->if_flags &= ~IFF_OACTIVE; 2799 ifp->if_flags |= IFF_RUNNING; 2800 2801 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2802 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2803 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2804 } else 2805 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2806 2807 return 0; 2808 #undef N 2809 } 2810 2811 static void 2812 rt2661_stop(struct ifnet *ifp, int disable) 2813 { 2814 struct rt2661_softc *sc = ifp->if_softc; 2815 struct ieee80211com *ic = &sc->sc_ic; 2816 uint32_t tmp; 2817 2818 sc->sc_tx_timer = 0; 2819 ifp->if_timer = 0; 2820 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2821 2822 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2823 2824 /* abort Tx (for all 5 Tx rings) */ 2825 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2826 2827 /* disable Rx (value remains after reset!) */ 2828 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2829 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2830 2831 /* reset ASIC */ 2832 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2833 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2834 2835 /* disable interrupts */ 2836 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2837 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2838 2839 /* clear any pending interrupt */ 2840 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2841 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2842 2843 /* reset Tx and Rx rings */ 2844 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2845 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2846 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2847 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2848 rt2661_reset_tx_ring(sc, &sc->mgtq); 2849 rt2661_reset_rx_ring(sc, &sc->rxq); 2850 2851 /* for CardBus, power down the socket */ 2852 if (disable && sc->sc_disable != NULL) { 2853 if (sc->sc_flags & RT2661_ENABLED) { 2854 (*sc->sc_disable)(sc); 2855 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2856 } 2857 } 2858 } 2859 2860 static int 2861 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2862 { 2863 int ntries; 2864 2865 /* reset 8051 */ 2866 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2867 2868 /* cancel any pending Host to MCU command */ 2869 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2870 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2871 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2872 2873 /* write 8051's microcode */ 2874 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2875 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2876 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2877 2878 /* kick 8051's ass */ 2879 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2880 2881 /* wait for 8051 to initialize */ 2882 for (ntries = 0; ntries < 500; ntries++) { 2883 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2884 break; 2885 DELAY(100); 2886 } 2887 if (ntries == 500) { 2888 printf("timeout waiting for MCU to initialize\n"); 2889 return EIO; 2890 } 2891 return 0; 2892 } 2893 2894 #ifdef notyet 2895 /* 2896 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2897 * false CCA count. This function is called periodically (every seconds) when 2898 * in the RUN state. Values taken from the reference driver. 2899 */ 2900 static void 2901 rt2661_rx_tune(struct rt2661_softc *sc) 2902 { 2903 uint8_t bbp17; 2904 uint16_t cca; 2905 int lo, hi, dbm; 2906 2907 /* 2908 * Tuning range depends on operating band and on the presence of an 2909 * external low-noise amplifier. 2910 */ 2911 lo = 0x20; 2912 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2913 lo += 0x08; 2914 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2915 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2916 lo += 0x10; 2917 hi = lo + 0x20; 2918 2919 /* retrieve false CCA count since last call (clear on read) */ 2920 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2921 2922 if (dbm >= -35) { 2923 bbp17 = 0x60; 2924 } else if (dbm >= -58) { 2925 bbp17 = hi; 2926 } else if (dbm >= -66) { 2927 bbp17 = lo + 0x10; 2928 } else if (dbm >= -74) { 2929 bbp17 = lo + 0x08; 2930 } else { 2931 /* RSSI < -74dBm, tune using false CCA count */ 2932 2933 bbp17 = sc->bbp17; /* current value */ 2934 2935 hi -= 2 * (-74 - dbm); 2936 if (hi < lo) 2937 hi = lo; 2938 2939 if (bbp17 > hi) { 2940 bbp17 = hi; 2941 2942 } else if (cca > 512) { 2943 if (++bbp17 > hi) 2944 bbp17 = hi; 2945 } else if (cca < 100) { 2946 if (--bbp17 < lo) 2947 bbp17 = lo; 2948 } 2949 } 2950 2951 if (bbp17 != sc->bbp17) { 2952 rt2661_bbp_write(sc, 17, bbp17); 2953 sc->bbp17 = bbp17; 2954 } 2955 } 2956 2957 /* 2958 * Enter/Leave radar detection mode. 2959 * This is for 802.11h additional regulatory domains. 2960 */ 2961 static void 2962 rt2661_radar_start(struct rt2661_softc *sc) 2963 { 2964 uint32_t tmp; 2965 2966 /* disable Rx */ 2967 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2968 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2969 2970 rt2661_bbp_write(sc, 82, 0x20); 2971 rt2661_bbp_write(sc, 83, 0x00); 2972 rt2661_bbp_write(sc, 84, 0x40); 2973 2974 /* save current BBP registers values */ 2975 sc->bbp18 = rt2661_bbp_read(sc, 18); 2976 sc->bbp21 = rt2661_bbp_read(sc, 21); 2977 sc->bbp22 = rt2661_bbp_read(sc, 22); 2978 sc->bbp16 = rt2661_bbp_read(sc, 16); 2979 sc->bbp17 = rt2661_bbp_read(sc, 17); 2980 sc->bbp64 = rt2661_bbp_read(sc, 64); 2981 2982 rt2661_bbp_write(sc, 18, 0xff); 2983 rt2661_bbp_write(sc, 21, 0x3f); 2984 rt2661_bbp_write(sc, 22, 0x3f); 2985 rt2661_bbp_write(sc, 16, 0xbd); 2986 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2987 rt2661_bbp_write(sc, 64, 0x21); 2988 2989 /* restore Rx filter */ 2990 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2991 } 2992 2993 static int 2994 rt2661_radar_stop(struct rt2661_softc *sc) 2995 { 2996 uint8_t bbp66; 2997 2998 /* read radar detection result */ 2999 bbp66 = rt2661_bbp_read(sc, 66); 3000 3001 /* restore BBP registers values */ 3002 rt2661_bbp_write(sc, 16, sc->bbp16); 3003 rt2661_bbp_write(sc, 17, sc->bbp17); 3004 rt2661_bbp_write(sc, 18, sc->bbp18); 3005 rt2661_bbp_write(sc, 21, sc->bbp21); 3006 rt2661_bbp_write(sc, 22, sc->bbp22); 3007 rt2661_bbp_write(sc, 64, sc->bbp64); 3008 3009 return bbp66 == 1; 3010 } 3011 #endif 3012 3013 static int 3014 rt2661_prepare_beacon(struct rt2661_softc *sc) 3015 { 3016 struct ieee80211com *ic = &sc->sc_ic; 3017 struct rt2661_tx_desc desc; 3018 struct mbuf *m0; 3019 struct ieee80211_beacon_offsets bo; 3020 int rate; 3021 3022 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 3023 3024 if (m0 == NULL) { 3025 aprint_error_dev(&sc->sc_dev, "could not allocate beacon frame\n"); 3026 return ENOBUFS; 3027 } 3028 3029 /* send beacons at the lowest available rate */ 3030 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2; 3031 3032 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 3033 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 3034 3035 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 3036 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 3037 3038 /* copy beacon header and payload into NIC memory */ 3039 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 3040 mtod(m0, uint8_t *), m0->m_pkthdr.len); 3041 3042 m_freem(m0); 3043 3044 return 0; 3045 } 3046 3047 /* 3048 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 3049 * and HostAP operating modes. 3050 */ 3051 static void 3052 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 3053 { 3054 struct ieee80211com *ic = &sc->sc_ic; 3055 uint32_t tmp; 3056 3057 if (ic->ic_opmode != IEEE80211_M_STA) { 3058 /* 3059 * Change default 16ms TBTT adjustment to 8ms. 3060 * Must be done before enabling beacon generation. 3061 */ 3062 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 3063 } 3064 3065 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 3066 3067 /* set beacon interval (in 1/16ms unit) */ 3068 tmp |= ic->ic_bss->ni_intval * 16; 3069 3070 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 3071 if (ic->ic_opmode == IEEE80211_M_STA) 3072 tmp |= RT2661_TSF_MODE(1); 3073 else 3074 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 3075 3076 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 3077 } 3078 3079 /* 3080 * Retrieve the "Received Signal Strength Indicator" from the raw values 3081 * contained in Rx descriptors. The computation depends on which band the 3082 * frame was received. Correction values taken from the reference driver. 3083 */ 3084 static int 3085 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 3086 { 3087 int lna, agc, rssi; 3088 3089 lna = (raw >> 5) & 0x3; 3090 agc = raw & 0x1f; 3091 3092 rssi = 2 * agc; 3093 3094 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3095 rssi += sc->rssi_2ghz_corr; 3096 3097 if (lna == 1) 3098 rssi -= 64; 3099 else if (lna == 2) 3100 rssi -= 74; 3101 else if (lna == 3) 3102 rssi -= 90; 3103 } else { 3104 rssi += sc->rssi_5ghz_corr; 3105 3106 if (lna == 1) 3107 rssi -= 64; 3108 else if (lna == 2) 3109 rssi -= 86; 3110 else if (lna == 3) 3111 rssi -= 100; 3112 } 3113 return rssi; 3114 } 3115
Indexes created Thu Sep 25 08:09:54 GMT 2025