rt2661.c revision 1.32
1 /* $NetBSD: rt2661.c,v 1.32 2016/05/26 05:04:46 ozaki-r Exp $ */ 2 /* $OpenBSD: rt2661.c,v 1.17 2006/05/01 08:41:11 damien Exp $ */ 3 /* $FreeBSD: rt2560.c,v 1.5 2006/06/02 19:59:31 csjp Exp $ */ 4 5 /*- 6 * Copyright (c) 2006 7 * Damien Bergamini <damien.bergamini (at) free.fr> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2661.c,v 1.32 2016/05/26 05:04:46 ozaki-r Exp $"); 29 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/callout.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 60 #include <net80211/ieee80211_var.h> 61 #include <net80211/ieee80211_amrr.h> 62 #include <net80211/ieee80211_radiotap.h> 63 64 #include <dev/ic/rt2661reg.h> 65 #include <dev/ic/rt2661var.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/firmload.h> 72 73 #ifdef RAL_DEBUG 74 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 75 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 76 int rt2661_debug = 0; 77 #else 78 #define DPRINTF(x) 79 #define DPRINTFN(n, x) 80 #endif 81 82 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *, int); 84 static void rt2661_reset_tx_ring(struct rt2661_softc *, 85 struct rt2661_tx_ring *); 86 static void rt2661_free_tx_ring(struct rt2661_softc *, 87 struct rt2661_tx_ring *); 88 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *, int); 90 static void rt2661_reset_rx_ring(struct rt2661_softc *, 91 struct rt2661_rx_ring *); 92 static void rt2661_free_rx_ring(struct rt2661_softc *, 93 struct rt2661_rx_ring *); 94 static struct ieee80211_node * 95 rt2661_node_alloc(struct ieee80211_node_table *); 96 static int rt2661_media_change(struct ifnet *); 97 static void rt2661_next_scan(void *); 98 static void rt2661_iter_func(void *, struct ieee80211_node *); 99 static void rt2661_updatestats(void *); 100 static void rt2661_newassoc(struct ieee80211_node *, int); 101 static int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 102 int); 103 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 104 static void rt2661_tx_intr(struct rt2661_softc *); 105 static void rt2661_tx_dma_intr(struct rt2661_softc *, 106 struct rt2661_tx_ring *); 107 static void rt2661_rx_intr(struct rt2661_softc *); 108 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 109 static void rt2661_mcu_wakeup(struct rt2661_softc *); 110 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 111 int rt2661_intr(void *); 112 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 113 static int rt2661_ack_rate(struct ieee80211com *, int); 114 static uint16_t rt2661_txtime(int, int, uint32_t); 115 static uint8_t rt2661_plcp_signal(int); 116 static void rt2661_setup_tx_desc(struct rt2661_softc *, 117 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 118 const bus_dma_segment_t *, int, int); 119 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 120 struct ieee80211_node *); 121 static struct mbuf * 122 rt2661_get_rts(struct rt2661_softc *, 123 struct ieee80211_frame *, uint16_t); 124 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 125 struct ieee80211_node *, int); 126 static void rt2661_start(struct ifnet *); 127 static void rt2661_watchdog(struct ifnet *); 128 static int rt2661_reset(struct ifnet *); 129 static int rt2661_ioctl(struct ifnet *, u_long, void *); 130 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 131 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 132 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 133 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 134 static void rt2661_select_antenna(struct rt2661_softc *); 135 static void rt2661_enable_mrr(struct rt2661_softc *); 136 static void rt2661_set_txpreamble(struct rt2661_softc *); 137 static void rt2661_set_basicrates(struct rt2661_softc *, 138 const struct ieee80211_rateset *); 139 static void rt2661_select_band(struct rt2661_softc *, 140 struct ieee80211_channel *); 141 static void rt2661_set_chan(struct rt2661_softc *, 142 struct ieee80211_channel *); 143 static void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 144 static void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 145 static void rt2661_update_promisc(struct rt2661_softc *); 146 #if 0 147 static int rt2661_wme_update(struct ieee80211com *); 148 #endif 149 150 static void rt2661_updateslot(struct ifnet *); 151 static void rt2661_set_slottime(struct rt2661_softc *); 152 static const char * 153 rt2661_get_rf(int); 154 static void rt2661_read_eeprom(struct rt2661_softc *); 155 static int rt2661_bbp_init(struct rt2661_softc *); 156 static int rt2661_init(struct ifnet *); 157 static void rt2661_stop(struct ifnet *, int); 158 static int rt2661_load_microcode(struct rt2661_softc *, const uint8_t *, 159 int); 160 static void rt2661_rx_tune(struct rt2661_softc *); 161 #ifdef notyet 162 static void rt2661_radar_start(struct rt2661_softc *); 163 static int rt2661_radar_stop(struct rt2661_softc *); 164 #endif 165 static int rt2661_prepare_beacon(struct rt2661_softc *); 166 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 167 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 168 169 /* 170 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 171 */ 172 static const struct ieee80211_rateset rt2661_rateset_11a = 173 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 174 175 static const struct ieee80211_rateset rt2661_rateset_11b = 176 { 4, { 2, 4, 11, 22 } }; 177 178 static const struct ieee80211_rateset rt2661_rateset_11g = 179 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 180 181 static const struct { 182 uint32_t reg; 183 uint32_t val; 184 } rt2661_def_mac[] = { 185 RT2661_DEF_MAC 186 }; 187 188 static const struct { 189 uint8_t reg; 190 uint8_t val; 191 } rt2661_def_bbp[] = { 192 RT2661_DEF_BBP 193 }; 194 195 static const struct rfprog { 196 uint8_t chan; 197 uint32_t r1, r2, r3, r4; 198 } rt2661_rf5225_1[] = { 199 RT2661_RF5225_1 200 }, rt2661_rf5225_2[] = { 201 RT2661_RF5225_2 202 }; 203 204 int 205 rt2661_attach(void *xsc, int id) 206 { 207 struct rt2661_softc *sc = xsc; 208 struct ieee80211com *ic = &sc->sc_ic; 209 struct ifnet *ifp = &sc->sc_if; 210 uint32_t val; 211 int error, i, ntries; 212 213 sc->sc_id = id; 214 215 sc->amrr.amrr_min_success_threshold = 1; 216 sc->amrr.amrr_max_success_threshold = 15; 217 callout_init(&sc->scan_ch, 0); 218 callout_init(&sc->amrr_ch, 0); 219 220 /* wait for NIC to initialize */ 221 for (ntries = 0; ntries < 1000; ntries++) { 222 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 223 break; 224 DELAY(1000); 225 } 226 if (ntries == 1000) { 227 aprint_error_dev(sc->sc_dev, "timeout waiting for NIC to initialize\n"); 228 return EIO; 229 } 230 231 /* retrieve RF rev. no and various other things from EEPROM */ 232 rt2661_read_eeprom(sc); 233 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 234 ether_sprintf(ic->ic_myaddr)); 235 236 aprint_normal_dev(sc->sc_dev, "MAC/BBP RT%X, RF %s\n", val, 237 rt2661_get_rf(sc->rf_rev)); 238 239 /* 240 * Allocate Tx and Rx rings. 241 */ 242 error = rt2661_alloc_tx_ring(sc, &sc->txq[0], RT2661_TX_RING_COUNT); 243 if (error != 0) { 244 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 0\n"); 245 goto fail1; 246 } 247 248 error = rt2661_alloc_tx_ring(sc, &sc->txq[1], RT2661_TX_RING_COUNT); 249 if (error != 0) { 250 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 1\n"); 251 goto fail2; 252 } 253 254 error = rt2661_alloc_tx_ring(sc, &sc->txq[2], RT2661_TX_RING_COUNT); 255 if (error != 0) { 256 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 2\n"); 257 goto fail3; 258 } 259 260 error = rt2661_alloc_tx_ring(sc, &sc->txq[3], RT2661_TX_RING_COUNT); 261 if (error != 0) { 262 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 3\n"); 263 goto fail4; 264 } 265 266 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 267 if (error != 0) { 268 aprint_error_dev(sc->sc_dev, "could not allocate Mgt ring\n"); 269 goto fail5; 270 } 271 272 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 273 if (error != 0) { 274 aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n"); 275 goto fail6; 276 } 277 278 ifp->if_softc = sc; 279 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 280 ifp->if_init = rt2661_init; 281 ifp->if_stop = rt2661_stop; 282 ifp->if_ioctl = rt2661_ioctl; 283 ifp->if_start = rt2661_start; 284 ifp->if_watchdog = rt2661_watchdog; 285 IFQ_SET_READY(&ifp->if_snd); 286 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 287 288 ic->ic_ifp = ifp; 289 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 290 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 291 ic->ic_state = IEEE80211_S_INIT; 292 293 /* set device capabilities */ 294 ic->ic_caps = 295 IEEE80211_C_IBSS | /* IBSS mode supported */ 296 IEEE80211_C_MONITOR | /* monitor mode supported */ 297 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 298 IEEE80211_C_TXPMGT | /* tx power management */ 299 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 300 IEEE80211_C_SHSLOT | /* short slot time supported */ 301 IEEE80211_C_WPA; /* 802.11i */ 302 303 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 304 /* set supported .11a rates */ 305 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 306 307 /* set supported .11a channels */ 308 for (i = 36; i <= 64; i += 4) { 309 ic->ic_channels[i].ic_freq = 310 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 311 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 312 } 313 for (i = 100; i <= 140; i += 4) { 314 ic->ic_channels[i].ic_freq = 315 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 316 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 317 } 318 for (i = 149; i <= 165; i += 4) { 319 ic->ic_channels[i].ic_freq = 320 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 321 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 322 } 323 } 324 325 /* set supported .11b and .11g rates */ 326 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 327 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 328 329 /* set supported .11b and .11g channels (1 through 14) */ 330 for (i = 1; i <= 14; i++) { 331 ic->ic_channels[i].ic_freq = 332 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 333 ic->ic_channels[i].ic_flags = 334 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 335 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 336 } 337 338 if_attach(ifp); 339 ieee80211_ifattach(ic); 340 ic->ic_node_alloc = rt2661_node_alloc; 341 ic->ic_newassoc = rt2661_newassoc; 342 ic->ic_updateslot = rt2661_updateslot; 343 ic->ic_reset = rt2661_reset; 344 345 /* override state transition machine */ 346 sc->sc_newstate = ic->ic_newstate; 347 ic->ic_newstate = rt2661_newstate; 348 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 349 350 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 351 sizeof(struct ieee80211_frame) + sizeof(sc->sc_txtap), 352 &sc->sc_drvbpf); 353 354 sc->sc_rxtap_len = roundup(sizeof(sc->sc_rxtap), sizeof(u_int32_t)); 355 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 356 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 357 358 sc->sc_txtap_len = roundup(sizeof(sc->sc_txtap), sizeof(u_int32_t)); 359 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 360 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 361 362 ieee80211_announce(ic); 363 364 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 365 pmf_class_network_register(sc->sc_dev, ifp); 366 else 367 aprint_error_dev(sc->sc_dev, 368 "couldn't establish power handler\n"); 369 370 return 0; 371 372 fail6: rt2661_free_tx_ring(sc, &sc->mgtq); 373 fail5: rt2661_free_tx_ring(sc, &sc->txq[3]); 374 fail4: rt2661_free_tx_ring(sc, &sc->txq[2]); 375 fail3: rt2661_free_tx_ring(sc, &sc->txq[1]); 376 fail2: rt2661_free_tx_ring(sc, &sc->txq[0]); 377 fail1: return ENXIO; 378 } 379 380 int 381 rt2661_detach(void *xsc) 382 { 383 struct rt2661_softc *sc = xsc; 384 struct ifnet *ifp = &sc->sc_if; 385 386 callout_stop(&sc->scan_ch); 387 callout_stop(&sc->amrr_ch); 388 389 pmf_device_deregister(sc->sc_dev); 390 391 ieee80211_ifdetach(&sc->sc_ic); 392 if_detach(ifp); 393 394 rt2661_free_tx_ring(sc, &sc->txq[0]); 395 rt2661_free_tx_ring(sc, &sc->txq[1]); 396 rt2661_free_tx_ring(sc, &sc->txq[2]); 397 rt2661_free_tx_ring(sc, &sc->txq[3]); 398 rt2661_free_tx_ring(sc, &sc->mgtq); 399 rt2661_free_rx_ring(sc, &sc->rxq); 400 401 return 0; 402 } 403 404 static int 405 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 406 int count) 407 { 408 int i, nsegs, error; 409 410 ring->count = count; 411 ring->queued = 0; 412 ring->cur = ring->next = ring->stat = 0; 413 414 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 415 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 416 if (error != 0) { 417 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 418 goto fail; 419 } 420 421 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 422 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 423 if (error != 0) { 424 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 425 goto fail; 426 } 427 428 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 429 count * RT2661_TX_DESC_SIZE, (void **)&ring->desc, 430 BUS_DMA_NOWAIT); 431 if (error != 0) { 432 aprint_error_dev(sc->sc_dev, "could not map desc DMA memory\n"); 433 goto fail; 434 } 435 436 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 437 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 438 if (error != 0) { 439 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 440 goto fail; 441 } 442 443 memset(ring->desc, 0, count * RT2661_TX_DESC_SIZE); 444 ring->physaddr = ring->map->dm_segs->ds_addr; 445 446 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 447 M_NOWAIT); 448 if (ring->data == NULL) { 449 aprint_error_dev(sc->sc_dev, "could not allocate soft data\n"); 450 error = ENOMEM; 451 goto fail; 452 } 453 454 memset(ring->data, 0, count * sizeof (struct rt2661_tx_data)); 455 for (i = 0; i < count; i++) { 456 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 457 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 458 &ring->data[i].map); 459 if (error != 0) { 460 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 461 goto fail; 462 } 463 } 464 465 return 0; 466 467 fail: rt2661_free_tx_ring(sc, ring); 468 return error; 469 } 470 471 static void 472 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 473 { 474 struct rt2661_tx_desc *desc; 475 struct rt2661_tx_data *data; 476 int i; 477 478 for (i = 0; i < ring->count; i++) { 479 desc = &ring->desc[i]; 480 data = &ring->data[i]; 481 482 if (data->m != NULL) { 483 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 484 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 485 bus_dmamap_unload(sc->sc_dmat, data->map); 486 m_freem(data->m); 487 data->m = NULL; 488 } 489 490 if (data->ni != NULL) { 491 ieee80211_free_node(data->ni); 492 data->ni = NULL; 493 } 494 495 desc->flags = 0; 496 } 497 498 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 499 BUS_DMASYNC_PREWRITE); 500 501 ring->queued = 0; 502 ring->cur = ring->next = ring->stat = 0; 503 } 504 505 506 static void 507 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 508 { 509 struct rt2661_tx_data *data; 510 int i; 511 512 if (ring->desc != NULL) { 513 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 514 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 515 bus_dmamap_unload(sc->sc_dmat, ring->map); 516 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 517 ring->count * RT2661_TX_DESC_SIZE); 518 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 519 } 520 521 if (ring->data != NULL) { 522 for (i = 0; i < ring->count; i++) { 523 data = &ring->data[i]; 524 525 if (data->m != NULL) { 526 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 527 data->map->dm_mapsize, 528 BUS_DMASYNC_POSTWRITE); 529 bus_dmamap_unload(sc->sc_dmat, data->map); 530 m_freem(data->m); 531 } 532 533 if (data->ni != NULL) 534 ieee80211_free_node(data->ni); 535 536 if (data->map != NULL) 537 bus_dmamap_destroy(sc->sc_dmat, data->map); 538 } 539 free(ring->data, M_DEVBUF); 540 } 541 } 542 543 static int 544 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 545 int count) 546 { 547 struct rt2661_rx_desc *desc; 548 struct rt2661_rx_data *data; 549 int i, nsegs, error; 550 551 ring->count = count; 552 ring->cur = ring->next = 0; 553 554 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 555 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 556 if (error != 0) { 557 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 558 goto fail; 559 } 560 561 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 562 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 563 if (error != 0) { 564 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 565 goto fail; 566 } 567 568 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 569 count * RT2661_RX_DESC_SIZE, (void **)&ring->desc, 570 BUS_DMA_NOWAIT); 571 if (error != 0) { 572 aprint_error_dev(sc->sc_dev, "could not map desc DMA memory\n"); 573 goto fail; 574 } 575 576 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 577 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 578 if (error != 0) { 579 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 580 goto fail; 581 } 582 583 memset(ring->desc, 0, count * RT2661_RX_DESC_SIZE); 584 ring->physaddr = ring->map->dm_segs->ds_addr; 585 586 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 587 M_NOWAIT); 588 if (ring->data == NULL) { 589 aprint_error_dev(sc->sc_dev, "could not allocate soft data\n"); 590 error = ENOMEM; 591 goto fail; 592 } 593 594 /* 595 * Pre-allocate Rx buffers and populate Rx ring. 596 */ 597 memset(ring->data, 0, count * sizeof (struct rt2661_rx_data)); 598 for (i = 0; i < count; i++) { 599 desc = &sc->rxq.desc[i]; 600 data = &sc->rxq.data[i]; 601 602 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 603 0, BUS_DMA_NOWAIT, &data->map); 604 if (error != 0) { 605 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 606 goto fail; 607 } 608 609 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 610 if (data->m == NULL) { 611 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 612 error = ENOMEM; 613 goto fail; 614 } 615 616 MCLGET(data->m, M_DONTWAIT); 617 if (!(data->m->m_flags & M_EXT)) { 618 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 619 error = ENOMEM; 620 goto fail; 621 } 622 623 error = bus_dmamap_load(sc->sc_dmat, data->map, 624 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 625 if (error != 0) { 626 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map"); 627 goto fail; 628 } 629 630 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 631 desc->flags = htole32(RT2661_RX_BUSY); 632 } 633 634 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 635 BUS_DMASYNC_PREWRITE); 636 637 return 0; 638 639 fail: rt2661_free_rx_ring(sc, ring); 640 return error; 641 } 642 643 static void 644 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 645 { 646 int i; 647 648 for (i = 0; i < ring->count; i++) 649 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 650 651 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 652 BUS_DMASYNC_PREWRITE); 653 654 ring->cur = ring->next = 0; 655 } 656 657 static void 658 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 659 { 660 struct rt2661_rx_data *data; 661 int i; 662 663 if (ring->desc != NULL) { 664 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 665 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 666 bus_dmamap_unload(sc->sc_dmat, ring->map); 667 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 668 ring->count * RT2661_RX_DESC_SIZE); 669 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 670 } 671 672 if (ring->data != NULL) { 673 for (i = 0; i < ring->count; i++) { 674 data = &ring->data[i]; 675 676 if (data->m != NULL) { 677 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 678 data->map->dm_mapsize, 679 BUS_DMASYNC_POSTREAD); 680 bus_dmamap_unload(sc->sc_dmat, data->map); 681 m_freem(data->m); 682 } 683 684 if (data->map != NULL) 685 bus_dmamap_destroy(sc->sc_dmat, data->map); 686 } 687 free(ring->data, M_DEVBUF); 688 } 689 } 690 691 static struct ieee80211_node * 692 rt2661_node_alloc(struct ieee80211_node_table *nt) 693 { 694 struct rt2661_node *rn; 695 696 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 697 M_NOWAIT | M_ZERO); 698 699 return (rn != NULL) ? &rn->ni : NULL; 700 } 701 702 static int 703 rt2661_media_change(struct ifnet *ifp) 704 { 705 int error; 706 707 error = ieee80211_media_change(ifp); 708 if (error != ENETRESET) 709 return error; 710 711 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 712 rt2661_init(ifp); 713 714 return 0; 715 } 716 717 /* 718 * This function is called periodically (every 200ms) during scanning to 719 * switch from one channel to another. 720 */ 721 static void 722 rt2661_next_scan(void *arg) 723 { 724 struct rt2661_softc *sc = arg; 725 struct ieee80211com *ic = &sc->sc_ic; 726 int s; 727 728 s = splnet(); 729 if (ic->ic_state == IEEE80211_S_SCAN) 730 ieee80211_next_scan(ic); 731 splx(s); 732 } 733 734 /* 735 * This function is called for each neighbor node. 736 */ 737 static void 738 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 739 { 740 struct rt2661_softc *sc = arg; 741 struct rt2661_node *rn = (struct rt2661_node *)ni; 742 743 ieee80211_amrr_choose(&sc->amrr, ni, &rn->amn); 744 } 745 746 /* 747 * This function is called periodically (every 500ms) in RUN state to update 748 * various settings like rate control statistics or Rx sensitivity. 749 */ 750 static void 751 rt2661_updatestats(void *arg) 752 { 753 struct rt2661_softc *sc = arg; 754 struct ieee80211com *ic = &sc->sc_ic; 755 int s; 756 757 s = splnet(); 758 if (ic->ic_opmode == IEEE80211_M_STA) 759 rt2661_iter_func(sc, ic->ic_bss); 760 else 761 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 762 763 /* update rx sensitivity every 1 sec */ 764 if (++sc->ncalls & 1) 765 rt2661_rx_tune(sc); 766 splx(s); 767 768 callout_reset(&sc->amrr_ch, hz / 2, rt2661_updatestats, sc); 769 } 770 771 static void 772 rt2661_newassoc(struct ieee80211_node *ni, int isnew) 773 { 774 struct rt2661_softc *sc = ni->ni_ic->ic_ifp->if_softc; 775 int i; 776 777 ieee80211_amrr_node_init(&sc->amrr, &((struct rt2661_node *)ni)->amn); 778 779 /* set rate to some reasonable initial value */ 780 for (i = ni->ni_rates.rs_nrates - 1; 781 i > 0 && (ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL) > 72; 782 i--); 783 ni->ni_txrate = i; 784 } 785 786 static int 787 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 788 { 789 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 790 enum ieee80211_state ostate; 791 struct ieee80211_node *ni; 792 uint32_t tmp; 793 794 ostate = ic->ic_state; 795 callout_stop(&sc->scan_ch); 796 797 switch (nstate) { 798 case IEEE80211_S_INIT: 799 callout_stop(&sc->amrr_ch); 800 801 if (ostate == IEEE80211_S_RUN) { 802 /* abort TSF synchronization */ 803 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 804 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 805 } 806 break; 807 808 case IEEE80211_S_SCAN: 809 rt2661_set_chan(sc, ic->ic_curchan); 810 callout_reset(&sc->scan_ch, hz / 5, rt2661_next_scan, sc); 811 break; 812 813 case IEEE80211_S_AUTH: 814 case IEEE80211_S_ASSOC: 815 rt2661_set_chan(sc, ic->ic_curchan); 816 break; 817 818 case IEEE80211_S_RUN: 819 rt2661_set_chan(sc, ic->ic_curchan); 820 821 ni = ic->ic_bss; 822 823 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 824 rt2661_set_slottime(sc); 825 rt2661_enable_mrr(sc); 826 rt2661_set_txpreamble(sc); 827 rt2661_set_basicrates(sc, &ni->ni_rates); 828 rt2661_set_bssid(sc, ni->ni_bssid); 829 } 830 831 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 832 ic->ic_opmode == IEEE80211_M_IBSS) 833 rt2661_prepare_beacon(sc); 834 835 if (ic->ic_opmode == IEEE80211_M_STA) { 836 /* fake a join to init the tx rate */ 837 rt2661_newassoc(ni, 1); 838 } 839 840 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 841 sc->ncalls = 0; 842 sc->avg_rssi = -95; /* reset EMA */ 843 callout_reset(&sc->amrr_ch, hz / 2, 844 rt2661_updatestats, sc); 845 rt2661_enable_tsf_sync(sc); 846 } 847 break; 848 } 849 850 return sc->sc_newstate(ic, nstate, arg); 851 } 852 853 /* 854 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 855 * 93C66). 856 */ 857 static uint16_t 858 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 859 { 860 uint32_t tmp; 861 uint16_t val; 862 int n; 863 864 /* clock C once before the first command */ 865 RT2661_EEPROM_CTL(sc, 0); 866 867 RT2661_EEPROM_CTL(sc, RT2661_S); 868 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 869 RT2661_EEPROM_CTL(sc, RT2661_S); 870 871 /* write start bit (1) */ 872 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 873 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 874 875 /* write READ opcode (10) */ 876 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 877 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 878 RT2661_EEPROM_CTL(sc, RT2661_S); 879 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 880 881 /* write address (A5-A0 or A7-A0) */ 882 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 883 for (; n >= 0; n--) { 884 RT2661_EEPROM_CTL(sc, RT2661_S | 885 (((addr >> n) & 1) << RT2661_SHIFT_D)); 886 RT2661_EEPROM_CTL(sc, RT2661_S | 887 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 888 } 889 890 RT2661_EEPROM_CTL(sc, RT2661_S); 891 892 /* read data Q15-Q0 */ 893 val = 0; 894 for (n = 15; n >= 0; n--) { 895 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 896 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 897 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 898 RT2661_EEPROM_CTL(sc, RT2661_S); 899 } 900 901 RT2661_EEPROM_CTL(sc, 0); 902 903 /* clear Chip Select and clock C */ 904 RT2661_EEPROM_CTL(sc, RT2661_S); 905 RT2661_EEPROM_CTL(sc, 0); 906 RT2661_EEPROM_CTL(sc, RT2661_C); 907 908 return val; 909 } 910 911 static void 912 rt2661_tx_intr(struct rt2661_softc *sc) 913 { 914 struct ifnet *ifp = &sc->sc_if; 915 struct rt2661_tx_ring *txq; 916 struct rt2661_tx_data *data; 917 struct rt2661_node *rn; 918 uint32_t val; 919 int qid, retrycnt; 920 921 for (;;) { 922 val = RAL_READ(sc, RT2661_STA_CSR4); 923 if (!(val & RT2661_TX_STAT_VALID)) 924 break; 925 926 /* retrieve the queue in which this frame was sent */ 927 qid = RT2661_TX_QID(val); 928 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 929 930 /* retrieve rate control algorithm context */ 931 data = &txq->data[txq->stat]; 932 rn = (struct rt2661_node *)data->ni; 933 934 /* if no frame has been sent, ignore */ 935 if (rn == NULL) 936 continue; 937 938 switch (RT2661_TX_RESULT(val)) { 939 case RT2661_TX_SUCCESS: 940 retrycnt = RT2661_TX_RETRYCNT(val); 941 942 DPRINTFN(10, ("data frame sent successfully after " 943 "%d retries\n", retrycnt)); 944 rn->amn.amn_txcnt++; 945 if (retrycnt > 0) 946 rn->amn.amn_retrycnt++; 947 ifp->if_opackets++; 948 break; 949 950 case RT2661_TX_RETRY_FAIL: 951 DPRINTFN(9, ("sending data frame failed (too much " 952 "retries)\n")); 953 rn->amn.amn_txcnt++; 954 rn->amn.amn_retrycnt++; 955 ifp->if_oerrors++; 956 break; 957 958 default: 959 /* other failure */ 960 aprint_error_dev(sc->sc_dev, "sending data frame failed 0x%08x\n", val); 961 ifp->if_oerrors++; 962 } 963 964 ieee80211_free_node(data->ni); 965 data->ni = NULL; 966 967 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 968 969 txq->queued--; 970 if (++txq->stat >= txq->count) /* faster than % count */ 971 txq->stat = 0; 972 } 973 974 sc->sc_tx_timer = 0; 975 ifp->if_flags &= ~IFF_OACTIVE; 976 rt2661_start(ifp); 977 } 978 979 static void 980 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 981 { 982 struct rt2661_tx_desc *desc; 983 struct rt2661_tx_data *data; 984 985 for (;;) { 986 desc = &txq->desc[txq->next]; 987 data = &txq->data[txq->next]; 988 989 bus_dmamap_sync(sc->sc_dmat, txq->map, 990 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 991 BUS_DMASYNC_POSTREAD); 992 993 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 994 !(le32toh(desc->flags) & RT2661_TX_VALID)) 995 break; 996 997 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 998 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 999 bus_dmamap_unload(sc->sc_dmat, data->map); 1000 m_freem(data->m); 1001 data->m = NULL; 1002 /* node reference is released in rt2661_tx_intr() */ 1003 1004 /* descriptor is no longer valid */ 1005 desc->flags &= ~htole32(RT2661_TX_VALID); 1006 1007 bus_dmamap_sync(sc->sc_dmat, txq->map, 1008 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1009 BUS_DMASYNC_PREWRITE); 1010 1011 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1012 1013 if (++txq->next >= txq->count) /* faster than % count */ 1014 txq->next = 0; 1015 } 1016 } 1017 1018 static void 1019 rt2661_rx_intr(struct rt2661_softc *sc) 1020 { 1021 struct ieee80211com *ic = &sc->sc_ic; 1022 struct ifnet *ifp = &sc->sc_if; 1023 struct rt2661_rx_desc *desc; 1024 struct rt2661_rx_data *data; 1025 struct ieee80211_frame *wh; 1026 struct ieee80211_node *ni; 1027 struct mbuf *mnew, *m; 1028 int error, rssi; 1029 1030 for (;;) { 1031 desc = &sc->rxq.desc[sc->rxq.cur]; 1032 data = &sc->rxq.data[sc->rxq.cur]; 1033 1034 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1035 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1036 BUS_DMASYNC_POSTREAD); 1037 1038 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1039 break; 1040 1041 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1042 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1043 /* 1044 * This should not happen since we did not request 1045 * to receive those frames when we filled TXRX_CSR0. 1046 */ 1047 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1048 le32toh(desc->flags))); 1049 ifp->if_ierrors++; 1050 goto skip; 1051 } 1052 1053 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1054 ifp->if_ierrors++; 1055 goto skip; 1056 } 1057 1058 /* 1059 * Try to allocate a new mbuf for this ring element and load it 1060 * before processing the current mbuf. If the ring element 1061 * cannot be loaded, drop the received packet and reuse the old 1062 * mbuf. In the unlikely case that the old mbuf can't be 1063 * reloaded either, explicitly panic. 1064 */ 1065 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1066 if (mnew == NULL) { 1067 ifp->if_ierrors++; 1068 goto skip; 1069 } 1070 1071 MCLGET(mnew, M_DONTWAIT); 1072 if (!(mnew->m_flags & M_EXT)) { 1073 m_freem(mnew); 1074 ifp->if_ierrors++; 1075 goto skip; 1076 } 1077 1078 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1079 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1080 bus_dmamap_unload(sc->sc_dmat, data->map); 1081 1082 error = bus_dmamap_load(sc->sc_dmat, data->map, 1083 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1084 if (error != 0) { 1085 m_freem(mnew); 1086 1087 /* try to reload the old mbuf */ 1088 error = bus_dmamap_load(sc->sc_dmat, data->map, 1089 mtod(data->m, void *), MCLBYTES, NULL, 1090 BUS_DMA_NOWAIT); 1091 if (error != 0) { 1092 /* very unlikely that it will fail... */ 1093 panic("%s: could not load old rx mbuf", 1094 device_xname(sc->sc_dev)); 1095 } 1096 /* physical address may have changed */ 1097 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1098 ifp->if_ierrors++; 1099 goto skip; 1100 } 1101 1102 /* 1103 * New mbuf successfully loaded, update Rx ring and continue 1104 * processing. 1105 */ 1106 m = data->m; 1107 data->m = mnew; 1108 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1109 1110 /* finalize mbuf */ 1111 m->m_pkthdr.rcvif = ifp; 1112 m->m_pkthdr.len = m->m_len = 1113 (le32toh(desc->flags) >> 16) & 0xfff; 1114 1115 if (sc->sc_drvbpf != NULL) { 1116 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1117 uint32_t tsf_lo, tsf_hi; 1118 1119 /* get timestamp (low and high 32 bits) */ 1120 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1121 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1122 1123 tap->wr_tsf = 1124 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1125 tap->wr_flags = 0; 1126 tap->wr_rate = rt2661_rxrate(desc); 1127 tap->wr_chan_freq = htole16(sc->sc_curchan->ic_freq); 1128 tap->wr_chan_flags = htole16(sc->sc_curchan->ic_flags); 1129 tap->wr_antsignal = desc->rssi; 1130 1131 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1132 } 1133 1134 wh = mtod(m, struct ieee80211_frame *); 1135 ni = ieee80211_find_rxnode(ic, 1136 (struct ieee80211_frame_min *)wh); 1137 1138 /* send the frame to the 802.11 layer */ 1139 ieee80211_input(ic, m, ni, desc->rssi, 0); 1140 1141 /*- 1142 * Keep track of the average RSSI using an Exponential Moving 1143 * Average (EMA) of 8 Wilder's days: 1144 * avg = (1 / N) x rssi + ((N - 1) / N) x avg 1145 */ 1146 rssi = rt2661_get_rssi(sc, desc->rssi); 1147 sc->avg_rssi = (rssi + 7 * sc->avg_rssi) / 8; 1148 1149 /* node is no longer needed */ 1150 ieee80211_free_node(ni); 1151 1152 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1153 1154 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1155 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1156 BUS_DMASYNC_PREWRITE); 1157 1158 DPRINTFN(16, ("rx intr idx=%u\n", sc->rxq.cur)); 1159 1160 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1161 } 1162 1163 /* 1164 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 1165 * without calling if_start(). 1166 */ 1167 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 1168 rt2661_start(ifp); 1169 } 1170 1171 /* 1172 * This function is called in HostAP or IBSS modes when it's time to send a 1173 * new beacon (every ni_intval milliseconds). 1174 */ 1175 static void 1176 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1177 { 1178 struct ieee80211com *ic = &sc->sc_ic; 1179 1180 if (sc->sc_flags & RT2661_UPDATE_SLOT) { 1181 sc->sc_flags &= ~RT2661_UPDATE_SLOT; 1182 sc->sc_flags |= RT2661_SET_SLOTTIME; 1183 } else if (sc->sc_flags & RT2661_SET_SLOTTIME) { 1184 sc->sc_flags &= ~RT2661_SET_SLOTTIME; 1185 rt2661_set_slottime(sc); 1186 } 1187 1188 if (ic->ic_curmode == IEEE80211_MODE_11G) { 1189 /* update ERP Information Element */ 1190 RAL_WRITE_1(sc, sc->erp_csr, ic->ic_bss->ni_erp); 1191 RAL_RW_BARRIER_1(sc, sc->erp_csr); 1192 } 1193 1194 DPRINTFN(15, ("beacon expired\n")); 1195 } 1196 1197 static void 1198 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1199 { 1200 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1201 1202 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1203 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1204 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1205 1206 /* send wakeup command to MCU */ 1207 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1208 } 1209 1210 static void 1211 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1212 { 1213 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1214 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1215 } 1216 1217 int 1218 rt2661_intr(void *arg) 1219 { 1220 struct rt2661_softc *sc = arg; 1221 struct ifnet *ifp = &sc->sc_if; 1222 uint32_t r1, r2; 1223 int rv = 0; 1224 1225 /* don't re-enable interrupts if we're shutting down */ 1226 if (!(ifp->if_flags & IFF_RUNNING)) { 1227 /* disable MAC and MCU interrupts */ 1228 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1229 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1230 return 0; 1231 } 1232 1233 for (;;) { 1234 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1235 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1236 1237 if ((r1 & RT2661_INT_CSR_ALL) == 0 && 1238 (r2 & RT2661_MCU_INT_ALL) == 0) 1239 break; 1240 1241 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1242 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1243 1244 rv = 1; 1245 1246 if (r1 & RT2661_MGT_DONE) 1247 rt2661_tx_dma_intr(sc, &sc->mgtq); 1248 1249 if (r1 & RT2661_RX_DONE) 1250 rt2661_rx_intr(sc); 1251 1252 if (r1 & RT2661_TX0_DMA_DONE) 1253 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1254 1255 if (r1 & RT2661_TX1_DMA_DONE) 1256 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1257 1258 if (r1 & RT2661_TX2_DMA_DONE) 1259 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1260 1261 if (r1 & RT2661_TX3_DMA_DONE) 1262 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1263 1264 if (r1 & RT2661_TX_DONE) 1265 rt2661_tx_intr(sc); 1266 1267 if (r2 & RT2661_MCU_CMD_DONE) 1268 rt2661_mcu_cmd_intr(sc); 1269 1270 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1271 rt2661_mcu_beacon_expire(sc); 1272 1273 if (r2 & RT2661_MCU_WAKEUP) 1274 rt2661_mcu_wakeup(sc); 1275 } 1276 1277 return rv; 1278 } 1279 1280 /* quickly determine if a given rate is CCK or OFDM */ 1281 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1282 1283 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1284 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1285 1286 /* 1287 * This function is only used by the Rx radiotap code. It returns the rate at 1288 * which a given frame was received. 1289 */ 1290 static uint8_t 1291 rt2661_rxrate(struct rt2661_rx_desc *desc) 1292 { 1293 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1294 /* reverse function of rt2661_plcp_signal */ 1295 switch (desc->rate & 0xf) { 1296 case 0xb: return 12; 1297 case 0xf: return 18; 1298 case 0xa: return 24; 1299 case 0xe: return 36; 1300 case 0x9: return 48; 1301 case 0xd: return 72; 1302 case 0x8: return 96; 1303 case 0xc: return 108; 1304 } 1305 } else { 1306 if (desc->rate == 10) 1307 return 2; 1308 if (desc->rate == 20) 1309 return 4; 1310 if (desc->rate == 55) 1311 return 11; 1312 if (desc->rate == 110) 1313 return 22; 1314 } 1315 return 2; /* should not get there */ 1316 } 1317 1318 /* 1319 * Return the expected ack rate for a frame transmitted at rate `rate'. 1320 * XXX: this should depend on the destination node basic rate set. 1321 */ 1322 static int 1323 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1324 { 1325 switch (rate) { 1326 /* CCK rates */ 1327 case 2: 1328 return 2; 1329 case 4: 1330 case 11: 1331 case 22: 1332 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1333 1334 /* OFDM rates */ 1335 case 12: 1336 case 18: 1337 return 12; 1338 case 24: 1339 case 36: 1340 return 24; 1341 case 48: 1342 case 72: 1343 case 96: 1344 case 108: 1345 return 48; 1346 } 1347 1348 /* default to 1Mbps */ 1349 return 2; 1350 } 1351 1352 /* 1353 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1354 * The function automatically determines the operating mode depending on the 1355 * given rate. `flags' indicates whether short preamble is in use or not. 1356 */ 1357 static uint16_t 1358 rt2661_txtime(int len, int rate, uint32_t flags) 1359 { 1360 uint16_t txtime; 1361 1362 if (RAL_RATE_IS_OFDM(rate)) { 1363 /* IEEE Std 802.11g-2003, pp. 44 */ 1364 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1365 txtime = 16 + 4 + 4 * txtime + 6; 1366 } else { 1367 /* IEEE Std 802.11b-1999, pp. 28 */ 1368 txtime = (16 * len + rate - 1) / rate; 1369 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1370 txtime += 72 + 24; 1371 else 1372 txtime += 144 + 48; 1373 } 1374 return txtime; 1375 } 1376 1377 static uint8_t 1378 rt2661_plcp_signal(int rate) 1379 { 1380 switch (rate) { 1381 /* CCK rates (returned values are device-dependent) */ 1382 case 2: return 0x0; 1383 case 4: return 0x1; 1384 case 11: return 0x2; 1385 case 22: return 0x3; 1386 1387 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1388 case 12: return 0xb; 1389 case 18: return 0xf; 1390 case 24: return 0xa; 1391 case 36: return 0xe; 1392 case 48: return 0x9; 1393 case 72: return 0xd; 1394 case 96: return 0x8; 1395 case 108: return 0xc; 1396 1397 /* unsupported rates (should not get there) */ 1398 default: return 0xff; 1399 } 1400 } 1401 1402 static void 1403 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1404 uint32_t flags, uint16_t xflags, int len, int rate, 1405 const bus_dma_segment_t *segs, int nsegs, int ac) 1406 { 1407 struct ieee80211com *ic = &sc->sc_ic; 1408 uint16_t plcp_length; 1409 int i, remainder; 1410 1411 desc->flags = htole32(flags); 1412 desc->flags |= htole32(len << 16); 1413 1414 desc->xflags = htole16(xflags); 1415 desc->xflags |= htole16(nsegs << 13); 1416 1417 desc->wme = htole16( 1418 RT2661_QID(ac) | 1419 RT2661_AIFSN(2) | 1420 RT2661_LOGCWMIN(4) | 1421 RT2661_LOGCWMAX(10)); 1422 1423 /* 1424 * Remember in which queue this frame was sent. This field is driver 1425 * private data only. It will be made available by the NIC in STA_CSR4 1426 * on Tx interrupts. 1427 */ 1428 desc->qid = ac; 1429 1430 /* setup PLCP fields */ 1431 desc->plcp_signal = rt2661_plcp_signal(rate); 1432 desc->plcp_service = 4; 1433 1434 len += IEEE80211_CRC_LEN; 1435 if (RAL_RATE_IS_OFDM(rate)) { 1436 desc->flags |= htole32(RT2661_TX_OFDM); 1437 1438 plcp_length = len & 0xfff; 1439 desc->plcp_length_hi = plcp_length >> 6; 1440 desc->plcp_length_lo = plcp_length & 0x3f; 1441 } else { 1442 plcp_length = (16 * len + rate - 1) / rate; 1443 if (rate == 22) { 1444 remainder = (16 * len) % 22; 1445 if (remainder != 0 && remainder < 7) 1446 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1447 } 1448 desc->plcp_length_hi = plcp_length >> 8; 1449 desc->plcp_length_lo = plcp_length & 0xff; 1450 1451 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1452 desc->plcp_signal |= 0x08; 1453 } 1454 1455 /* RT2x61 supports scatter with up to 5 segments */ 1456 for (i = 0; i < nsegs; i++) { 1457 desc->addr[i] = htole32(segs[i].ds_addr); 1458 desc->len [i] = htole16(segs[i].ds_len); 1459 } 1460 1461 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1462 } 1463 1464 static int 1465 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1466 struct ieee80211_node *ni) 1467 { 1468 struct ieee80211com *ic = &sc->sc_ic; 1469 struct rt2661_tx_desc *desc; 1470 struct rt2661_tx_data *data; 1471 struct ieee80211_frame *wh; 1472 uint16_t dur; 1473 uint32_t flags = 0; 1474 int rate, error; 1475 1476 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1477 data = &sc->mgtq.data[sc->mgtq.cur]; 1478 1479 /* send mgt frames at the lowest available rate */ 1480 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1481 1482 wh = mtod(m0, struct ieee80211_frame *); 1483 1484 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1485 if (ieee80211_crypto_encap(ic, ni, m0) == NULL) { 1486 m_freem(m0); 1487 return ENOBUFS; 1488 } 1489 1490 /* packet header may have moved, reset our local pointer */ 1491 wh = mtod(m0, struct ieee80211_frame *); 1492 } 1493 1494 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1495 BUS_DMA_NOWAIT); 1496 if (error != 0) { 1497 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1498 error); 1499 m_freem(m0); 1500 return error; 1501 } 1502 1503 if (sc->sc_drvbpf != NULL) { 1504 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1505 1506 tap->wt_flags = 0; 1507 tap->wt_rate = rate; 1508 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1509 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1510 1511 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1512 } 1513 1514 data->m = m0; 1515 data->ni = ni; 1516 1517 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1518 flags |= RT2661_TX_NEED_ACK; 1519 1520 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1521 sc->sifs; 1522 *(uint16_t *)wh->i_dur = htole16(dur); 1523 1524 /* tell hardware to set timestamp in probe responses */ 1525 if ((wh->i_fc[0] & 1526 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1527 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1528 flags |= RT2661_TX_TIMESTAMP; 1529 } 1530 1531 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1532 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1533 RT2661_QID_MGT); 1534 1535 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1536 BUS_DMASYNC_PREWRITE); 1537 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1538 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1539 BUS_DMASYNC_PREWRITE); 1540 1541 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1542 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1543 1544 /* kick mgt */ 1545 sc->mgtq.queued++; 1546 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1547 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1548 1549 return 0; 1550 } 1551 1552 /* 1553 * Build a RTS control frame. 1554 */ 1555 static struct mbuf * 1556 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1557 uint16_t dur) 1558 { 1559 struct ieee80211_frame_rts *rts; 1560 struct mbuf *m; 1561 1562 MGETHDR(m, M_DONTWAIT, MT_DATA); 1563 if (m == NULL) { 1564 sc->sc_ic.ic_stats.is_tx_nobuf++; 1565 aprint_error_dev(sc->sc_dev, "could not allocate RTS frame\n"); 1566 return NULL; 1567 } 1568 1569 rts = mtod(m, struct ieee80211_frame_rts *); 1570 1571 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1572 IEEE80211_FC0_SUBTYPE_RTS; 1573 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1574 *(uint16_t *)rts->i_dur = htole16(dur); 1575 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1576 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1577 1578 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1579 1580 return m; 1581 } 1582 1583 static int 1584 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1585 struct ieee80211_node *ni, int ac) 1586 { 1587 struct ieee80211com *ic = &sc->sc_ic; 1588 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1589 struct rt2661_tx_desc *desc; 1590 struct rt2661_tx_data *data; 1591 struct ieee80211_frame *wh; 1592 struct ieee80211_key *k; 1593 struct mbuf *mnew; 1594 uint16_t dur; 1595 uint32_t flags = 0; 1596 int rate, useprot, error, tid; 1597 1598 wh = mtod(m0, struct ieee80211_frame *); 1599 1600 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1601 rate = ic->ic_sup_rates[ic->ic_curmode]. 1602 rs_rates[ic->ic_fixed_rate]; 1603 } else 1604 rate = ni->ni_rates.rs_rates[ni->ni_txrate]; 1605 rate &= IEEE80211_RATE_VAL; 1606 if (rate == 0) 1607 rate = 2; /* XXX should not happen */ 1608 1609 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1610 k = ieee80211_crypto_encap(ic, ni, m0); 1611 if (k == NULL) { 1612 m_freem(m0); 1613 return ENOBUFS; 1614 } 1615 1616 /* packet header may have moved, reset our local pointer */ 1617 wh = mtod(m0, struct ieee80211_frame *); 1618 } 1619 1620 /* 1621 * Packet Bursting: backoff after ppb=8 frames to give other STAs a 1622 * chance to contend for the wireless medium. 1623 */ 1624 tid = WME_AC_TO_TID(M_WME_GETAC(m0)); 1625 if (ic->ic_opmode == IEEE80211_M_STA && (ni->ni_txseqs[tid] & 7)) 1626 flags |= RT2661_TX_IFS_SIFS; 1627 1628 /* 1629 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1630 * for directed frames only when the length of the MPDU is greater 1631 * than the length threshold indicated by" ic_rtsthreshold. 1632 * 1633 * IEEE Std 802.11-2003g, pp 13: "ERP STAs shall use protection 1634 * mechanism (such as RTS/CTS or CTS-to-self) for ERP-OFDM MPDUs of 1635 * type Data or an MMPDU". 1636 */ 1637 useprot = !IEEE80211_IS_MULTICAST(wh->i_addr1) && 1638 (m0->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1639 ((ic->ic_flags & IEEE80211_F_USEPROT) && RAL_RATE_IS_OFDM(rate))); 1640 if (useprot) { 1641 struct mbuf *m; 1642 int rtsrate, ackrate; 1643 1644 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1645 ackrate = rt2661_ack_rate(ic, rate); 1646 1647 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1648 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1649 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1650 3 * sc->sifs; 1651 1652 m = rt2661_get_rts(sc, wh, dur); 1653 if (m == NULL) { 1654 aprint_error_dev(sc->sc_dev, "could not allocate RTS " 1655 "frame\n"); 1656 m_freem(m0); 1657 return ENOBUFS; 1658 } 1659 1660 desc = &txq->desc[txq->cur]; 1661 data = &txq->data[txq->cur]; 1662 1663 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1664 BUS_DMA_NOWAIT); 1665 if (error != 0) { 1666 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1667 m_freem(m); 1668 m_freem(m0); 1669 return error; 1670 } 1671 1672 /* avoid multiple free() of the same node for each fragment */ 1673 ieee80211_ref_node(ni); 1674 1675 data->m = m; 1676 data->ni = ni; 1677 1678 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1679 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, 1680 data->map->dm_segs, data->map->dm_nsegs, ac); 1681 1682 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1683 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1684 bus_dmamap_sync(sc->sc_dmat, txq->map, 1685 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1686 BUS_DMASYNC_PREWRITE); 1687 1688 txq->queued++; 1689 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1690 1691 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS_SIFS; 1692 } 1693 1694 data = &txq->data[txq->cur]; 1695 desc = &txq->desc[txq->cur]; 1696 1697 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1698 BUS_DMA_NOWAIT); 1699 if (error != 0 && error != EFBIG) { 1700 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1701 error); 1702 m_freem(m0); 1703 return error; 1704 } 1705 if (error != 0) { 1706 /* too many fragments, linearize */ 1707 1708 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1709 if (mnew == NULL) { 1710 m_freem(m0); 1711 return ENOMEM; 1712 } 1713 1714 M_COPY_PKTHDR(mnew, m0); 1715 if (m0->m_pkthdr.len > MHLEN) { 1716 MCLGET(mnew, M_DONTWAIT); 1717 if (!(mnew->m_flags & M_EXT)) { 1718 m_freem(m0); 1719 m_freem(mnew); 1720 return ENOMEM; 1721 } 1722 } 1723 1724 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1725 m_freem(m0); 1726 mnew->m_len = mnew->m_pkthdr.len; 1727 m0 = mnew; 1728 1729 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1730 BUS_DMA_NOWAIT); 1731 if (error != 0) { 1732 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1733 m_freem(m0); 1734 return error; 1735 } 1736 1737 /* packet header have moved, reset our local pointer */ 1738 wh = mtod(m0, struct ieee80211_frame *); 1739 } 1740 1741 if (sc->sc_drvbpf != NULL) { 1742 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1743 1744 tap->wt_flags = 0; 1745 tap->wt_rate = rate; 1746 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1747 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1748 1749 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1750 } 1751 1752 data->m = m0; 1753 data->ni = ni; 1754 1755 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1756 flags |= RT2661_TX_NEED_ACK; 1757 1758 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1759 ic->ic_flags) + sc->sifs; 1760 *(uint16_t *)wh->i_dur = htole16(dur); 1761 } 1762 1763 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1764 data->map->dm_segs, data->map->dm_nsegs, ac); 1765 1766 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1767 BUS_DMASYNC_PREWRITE); 1768 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1769 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1770 1771 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1772 m0->m_pkthdr.len, txq->cur, rate)); 1773 1774 /* kick Tx */ 1775 txq->queued++; 1776 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1777 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1778 1779 return 0; 1780 } 1781 1782 static void 1783 rt2661_start(struct ifnet *ifp) 1784 { 1785 struct rt2661_softc *sc = ifp->if_softc; 1786 struct ieee80211com *ic = &sc->sc_ic; 1787 struct mbuf *m0; 1788 struct ether_header *eh; 1789 struct ieee80211_node *ni = NULL; 1790 1791 /* 1792 * net80211 may still try to send management frames even if the 1793 * IFF_RUNNING flag is not set... 1794 */ 1795 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1796 return; 1797 1798 for (;;) { 1799 IF_POLL(&ic->ic_mgtq, m0); 1800 if (m0 != NULL) { 1801 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1802 ifp->if_flags |= IFF_OACTIVE; 1803 break; 1804 } 1805 IF_DEQUEUE(&ic->ic_mgtq, m0); 1806 if (m0 == NULL) 1807 break; 1808 1809 ni = M_GETCTX(m0, struct ieee80211_node *); 1810 M_CLEARCTX(m0); 1811 bpf_mtap3(ic->ic_rawbpf, m0); 1812 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1813 break; 1814 1815 } else { 1816 IF_POLL(&ifp->if_snd, m0); 1817 if (m0 == NULL || ic->ic_state != IEEE80211_S_RUN) 1818 break; 1819 1820 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1821 /* there is no place left in this ring */ 1822 ifp->if_flags |= IFF_OACTIVE; 1823 break; 1824 } 1825 1826 IFQ_DEQUEUE(&ifp->if_snd, m0); 1827 1828 if (m0->m_len < sizeof (struct ether_header) && 1829 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1830 continue; 1831 1832 eh = mtod(m0, struct ether_header *); 1833 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1834 if (ni == NULL) { 1835 m_freem(m0); 1836 ifp->if_oerrors++; 1837 continue; 1838 } 1839 1840 bpf_mtap3(ifp->if_bpf, m0); 1841 m0 = ieee80211_encap(ic, m0, ni); 1842 if (m0 == NULL) { 1843 ieee80211_free_node(ni); 1844 ifp->if_oerrors++; 1845 continue; 1846 } 1847 bpf_mtap3(ic->ic_rawbpf, m0); 1848 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1849 if (ni != NULL) 1850 ieee80211_free_node(ni); 1851 ifp->if_oerrors++; 1852 break; 1853 } 1854 } 1855 1856 sc->sc_tx_timer = 5; 1857 ifp->if_timer = 1; 1858 } 1859 } 1860 1861 static void 1862 rt2661_watchdog(struct ifnet *ifp) 1863 { 1864 struct rt2661_softc *sc = ifp->if_softc; 1865 1866 ifp->if_timer = 0; 1867 1868 if (sc->sc_tx_timer > 0) { 1869 if (--sc->sc_tx_timer == 0) { 1870 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1871 rt2661_init(ifp); 1872 ifp->if_oerrors++; 1873 return; 1874 } 1875 ifp->if_timer = 1; 1876 } 1877 1878 ieee80211_watchdog(&sc->sc_ic); 1879 } 1880 1881 /* 1882 * This function allows for fast channel switching in monitor mode (used by 1883 * kismet). In IBSS mode, we must explicitly reset the interface to 1884 * generate a new beacon frame. 1885 */ 1886 static int 1887 rt2661_reset(struct ifnet *ifp) 1888 { 1889 struct rt2661_softc *sc = ifp->if_softc; 1890 struct ieee80211com *ic = &sc->sc_ic; 1891 1892 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1893 return ENETRESET; 1894 1895 rt2661_set_chan(sc, ic->ic_curchan); 1896 1897 return 0; 1898 } 1899 1900 static int 1901 rt2661_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1902 { 1903 struct rt2661_softc *sc = ifp->if_softc; 1904 struct ieee80211com *ic = &sc->sc_ic; 1905 int s, error = 0; 1906 1907 s = splnet(); 1908 1909 switch (cmd) { 1910 case SIOCSIFFLAGS: 1911 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1912 break; 1913 if (ifp->if_flags & IFF_UP) { 1914 if (ifp->if_flags & IFF_RUNNING) 1915 rt2661_update_promisc(sc); 1916 else 1917 rt2661_init(ifp); 1918 } else { 1919 if (ifp->if_flags & IFF_RUNNING) 1920 rt2661_stop(ifp, 1); 1921 } 1922 break; 1923 1924 case SIOCADDMULTI: 1925 case SIOCDELMULTI: 1926 /* XXX no h/w multicast filter? --dyoung */ 1927 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 1928 error = 0; 1929 break; 1930 1931 case SIOCS80211CHANNEL: 1932 /* 1933 * This allows for fast channel switching in monitor mode 1934 * (used by kismet). In IBSS mode, we must explicitly reset 1935 * the interface to generate a new beacon frame. 1936 */ 1937 error = ieee80211_ioctl(ic, cmd, data); 1938 if (error == ENETRESET && 1939 ic->ic_opmode == IEEE80211_M_MONITOR) { 1940 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1941 (IFF_UP | IFF_RUNNING)) 1942 rt2661_set_chan(sc, ic->ic_ibss_chan); 1943 error = 0; 1944 } 1945 break; 1946 1947 default: 1948 error = ieee80211_ioctl(ic, cmd, data); 1949 1950 } 1951 1952 if (error == ENETRESET) { 1953 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1954 (IFF_UP | IFF_RUNNING)) 1955 rt2661_init(ifp); 1956 error = 0; 1957 } 1958 1959 splx(s); 1960 1961 return error; 1962 } 1963 1964 static void 1965 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1966 { 1967 uint32_t tmp; 1968 int ntries; 1969 1970 for (ntries = 0; ntries < 100; ntries++) { 1971 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1972 break; 1973 DELAY(1); 1974 } 1975 if (ntries == 100) { 1976 aprint_error_dev(sc->sc_dev, "could not write to BBP\n"); 1977 return; 1978 } 1979 1980 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1981 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1982 1983 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 1984 } 1985 1986 static uint8_t 1987 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1988 { 1989 uint32_t val; 1990 int ntries; 1991 1992 for (ntries = 0; ntries < 100; ntries++) { 1993 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1994 break; 1995 DELAY(1); 1996 } 1997 if (ntries == 100) { 1998 aprint_error_dev(sc->sc_dev, "could not read from BBP\n"); 1999 return 0; 2000 } 2001 2002 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2003 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2004 2005 for (ntries = 0; ntries < 100; ntries++) { 2006 val = RAL_READ(sc, RT2661_PHY_CSR3); 2007 if (!(val & RT2661_BBP_BUSY)) 2008 return val & 0xff; 2009 DELAY(1); 2010 } 2011 2012 aprint_error_dev(sc->sc_dev, "could not read from BBP\n"); 2013 return 0; 2014 } 2015 2016 static void 2017 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2018 { 2019 uint32_t tmp; 2020 int ntries; 2021 2022 for (ntries = 0; ntries < 100; ntries++) { 2023 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2024 break; 2025 DELAY(1); 2026 } 2027 if (ntries == 100) { 2028 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2029 return; 2030 } 2031 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2032 (reg & 3); 2033 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2034 2035 /* remember last written value in sc */ 2036 sc->rf_regs[reg] = val; 2037 2038 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2039 } 2040 2041 static int 2042 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2043 { 2044 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2045 return EIO; /* there is already a command pending */ 2046 2047 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2048 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2049 2050 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2051 2052 return 0; 2053 } 2054 2055 static void 2056 rt2661_select_antenna(struct rt2661_softc *sc) 2057 { 2058 uint8_t bbp4, bbp77; 2059 uint32_t tmp; 2060 2061 bbp4 = rt2661_bbp_read(sc, 4); 2062 bbp77 = rt2661_bbp_read(sc, 77); 2063 2064 /* TBD */ 2065 2066 /* make sure Rx is disabled before switching antenna */ 2067 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2068 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2069 2070 rt2661_bbp_write(sc, 4, bbp4); 2071 rt2661_bbp_write(sc, 77, bbp77); 2072 2073 /* restore Rx filter */ 2074 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2075 } 2076 2077 /* 2078 * Enable multi-rate retries for frames sent at OFDM rates. 2079 * In 802.11b/g mode, allow fallback to CCK rates. 2080 */ 2081 static void 2082 rt2661_enable_mrr(struct rt2661_softc *sc) 2083 { 2084 struct ieee80211com *ic = &sc->sc_ic; 2085 uint32_t tmp; 2086 2087 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2088 2089 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2090 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2091 tmp |= RT2661_MRR_CCK_FALLBACK; 2092 tmp |= RT2661_MRR_ENABLED; 2093 2094 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2095 } 2096 2097 static void 2098 rt2661_set_txpreamble(struct rt2661_softc *sc) 2099 { 2100 uint32_t tmp; 2101 2102 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2103 2104 tmp &= ~RT2661_SHORT_PREAMBLE; 2105 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2106 tmp |= RT2661_SHORT_PREAMBLE; 2107 2108 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2109 } 2110 2111 static void 2112 rt2661_set_basicrates(struct rt2661_softc *sc, 2113 const struct ieee80211_rateset *rs) 2114 { 2115 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2116 uint32_t mask = 0; 2117 uint8_t rate; 2118 int i, j; 2119 2120 for (i = 0; i < rs->rs_nrates; i++) { 2121 rate = rs->rs_rates[i]; 2122 2123 if (!(rate & IEEE80211_RATE_BASIC)) 2124 continue; 2125 2126 /* 2127 * Find h/w rate index. We know it exists because the rate 2128 * set has already been negotiated. 2129 */ 2130 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++); 2131 2132 mask |= 1 << j; 2133 } 2134 2135 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2136 2137 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2138 #undef RV 2139 } 2140 2141 /* 2142 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2143 * driver. 2144 */ 2145 static void 2146 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2147 { 2148 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2149 uint32_t tmp; 2150 2151 /* update all BBP registers that depend on the band */ 2152 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2153 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2154 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2155 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2156 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2157 } 2158 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2159 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2160 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2161 } 2162 2163 sc->bbp17 = bbp17; 2164 rt2661_bbp_write(sc, 17, bbp17); 2165 rt2661_bbp_write(sc, 96, bbp96); 2166 rt2661_bbp_write(sc, 104, bbp104); 2167 2168 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2169 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2170 rt2661_bbp_write(sc, 75, 0x80); 2171 rt2661_bbp_write(sc, 86, 0x80); 2172 rt2661_bbp_write(sc, 88, 0x80); 2173 } 2174 2175 rt2661_bbp_write(sc, 35, bbp35); 2176 rt2661_bbp_write(sc, 97, bbp97); 2177 rt2661_bbp_write(sc, 98, bbp98); 2178 2179 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2180 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2181 if (IEEE80211_IS_CHAN_2GHZ(c)) 2182 tmp |= RT2661_PA_PE_2GHZ; 2183 else 2184 tmp |= RT2661_PA_PE_5GHZ; 2185 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2186 2187 /* 802.11a uses a 16 microseconds short interframe space */ 2188 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10; 2189 } 2190 2191 static void 2192 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2193 { 2194 struct ieee80211com *ic = &sc->sc_ic; 2195 const struct rfprog *rfprog; 2196 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2197 int8_t power; 2198 u_int i, chan; 2199 2200 chan = ieee80211_chan2ieee(ic, c); 2201 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2202 return; 2203 2204 /* select the appropriate RF settings based on what EEPROM says */ 2205 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2206 2207 /* find the settings for this channel (we know it exists) */ 2208 for (i = 0; rfprog[i].chan != chan; i++); 2209 2210 power = sc->txpow[i]; 2211 if (power < 0) { 2212 bbp94 += power; 2213 power = 0; 2214 } else if (power > 31) { 2215 bbp94 += power - 31; 2216 power = 31; 2217 } 2218 2219 /* 2220 * If we've yet to select a channel, or we are switching from the 2221 * 2GHz band to the 5GHz band or vice-versa, BBP registers need to 2222 * be reprogrammed. 2223 */ 2224 if (sc->sc_curchan == NULL || c->ic_flags != sc->sc_curchan->ic_flags) { 2225 rt2661_select_band(sc, c); 2226 rt2661_select_antenna(sc); 2227 } 2228 sc->sc_curchan = c; 2229 2230 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2231 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2232 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2233 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2234 2235 DELAY(200); 2236 2237 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2238 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2239 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2240 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2241 2242 DELAY(200); 2243 2244 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2245 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2246 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2247 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2248 2249 /* enable smart mode for MIMO-capable RFs */ 2250 bbp3 = rt2661_bbp_read(sc, 3); 2251 2252 bbp3 &= ~RT2661_SMART_MODE; 2253 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2254 bbp3 |= RT2661_SMART_MODE; 2255 2256 rt2661_bbp_write(sc, 3, bbp3); 2257 2258 if (bbp94 != RT2661_BBPR94_DEFAULT) 2259 rt2661_bbp_write(sc, 94, bbp94); 2260 2261 /* 5GHz radio needs a 1ms delay here */ 2262 if (IEEE80211_IS_CHAN_5GHZ(c)) 2263 DELAY(1000); 2264 } 2265 2266 static void 2267 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2268 { 2269 uint32_t tmp; 2270 2271 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2272 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2273 2274 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2275 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2276 } 2277 2278 static void 2279 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2280 { 2281 uint32_t tmp; 2282 2283 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2284 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2285 2286 tmp = addr[4] | addr[5] << 8 | 0xff << 16; 2287 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2288 } 2289 2290 static void 2291 rt2661_update_promisc(struct rt2661_softc *sc) 2292 { 2293 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2294 uint32_t tmp; 2295 2296 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2297 2298 tmp &= ~RT2661_DROP_NOT_TO_ME; 2299 if (!(ifp->if_flags & IFF_PROMISC)) 2300 tmp |= RT2661_DROP_NOT_TO_ME; 2301 2302 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2303 2304 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2305 "entering" : "leaving")); 2306 } 2307 2308 #if 0 2309 /* 2310 * Update QoS (802.11e) settings for each h/w Tx ring. 2311 */ 2312 static int 2313 rt2661_wme_update(struct ieee80211com *ic) 2314 { 2315 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2316 const struct wmeParams *wmep; 2317 2318 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2319 2320 /* XXX: not sure about shifts. */ 2321 /* XXX: the reference driver plays with AC_VI settings too. */ 2322 2323 /* update TxOp */ 2324 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2325 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2326 wmep[WME_AC_BK].wmep_txopLimit); 2327 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2328 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2329 wmep[WME_AC_VO].wmep_txopLimit); 2330 2331 /* update CWmin */ 2332 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2333 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2334 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2335 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2336 wmep[WME_AC_VO].wmep_logcwmin); 2337 2338 /* update CWmax */ 2339 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2340 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2341 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2342 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2343 wmep[WME_AC_VO].wmep_logcwmax); 2344 2345 /* update Aifsn */ 2346 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2347 wmep[WME_AC_BE].wmep_aifsn << 12 | 2348 wmep[WME_AC_BK].wmep_aifsn << 8 | 2349 wmep[WME_AC_VI].wmep_aifsn << 4 | 2350 wmep[WME_AC_VO].wmep_aifsn); 2351 2352 return 0; 2353 } 2354 #endif 2355 2356 static void 2357 rt2661_updateslot(struct ifnet *ifp) 2358 { 2359 struct rt2661_softc *sc = ifp->if_softc; 2360 struct ieee80211com *ic = &sc->sc_ic; 2361 2362 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2363 /* 2364 * In HostAP mode, we defer setting of new slot time until 2365 * updated ERP Information Element has propagated to all 2366 * associated STAs. 2367 */ 2368 sc->sc_flags |= RT2661_UPDATE_SLOT; 2369 } else 2370 rt2661_set_slottime(sc); 2371 } 2372 2373 static void 2374 rt2661_set_slottime(struct rt2661_softc *sc) 2375 { 2376 struct ieee80211com *ic = &sc->sc_ic; 2377 uint8_t slottime; 2378 uint32_t tmp; 2379 2380 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2381 2382 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2383 tmp = (tmp & ~0xff) | slottime; 2384 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2385 2386 DPRINTF(("setting slot time to %uus\n", slottime)); 2387 } 2388 2389 static const char * 2390 rt2661_get_rf(int rev) 2391 { 2392 switch (rev) { 2393 case RT2661_RF_5225: return "RT5225"; 2394 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2395 case RT2661_RF_2527: return "RT2527"; 2396 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2397 default: return "unknown"; 2398 } 2399 } 2400 2401 static void 2402 rt2661_read_eeprom(struct rt2661_softc *sc) 2403 { 2404 struct ieee80211com *ic = &sc->sc_ic; 2405 uint16_t val; 2406 int i; 2407 2408 /* read MAC address */ 2409 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2410 ic->ic_myaddr[0] = val & 0xff; 2411 ic->ic_myaddr[1] = val >> 8; 2412 2413 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2414 ic->ic_myaddr[2] = val & 0xff; 2415 ic->ic_myaddr[3] = val >> 8; 2416 2417 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2418 ic->ic_myaddr[4] = val & 0xff; 2419 ic->ic_myaddr[5] = val >> 8; 2420 2421 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2422 /* XXX: test if different from 0xffff? */ 2423 sc->rf_rev = (val >> 11) & 0x1f; 2424 sc->hw_radio = (val >> 10) & 0x1; 2425 sc->rx_ant = (val >> 4) & 0x3; 2426 sc->tx_ant = (val >> 2) & 0x3; 2427 sc->nb_ant = val & 0x3; 2428 2429 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2430 2431 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2432 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2433 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2434 2435 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2436 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2437 2438 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2439 if ((val & 0xff) != 0xff) 2440 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2441 2442 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2443 if ((val & 0xff) != 0xff) 2444 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2445 2446 /* adjust RSSI correction for external low-noise amplifier */ 2447 if (sc->ext_2ghz_lna) 2448 sc->rssi_2ghz_corr -= 14; 2449 if (sc->ext_5ghz_lna) 2450 sc->rssi_5ghz_corr -= 14; 2451 2452 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2453 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2454 2455 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2456 if ((val >> 8) != 0xff) 2457 sc->rfprog = (val >> 8) & 0x3; 2458 if ((val & 0xff) != 0xff) 2459 sc->rffreq = val & 0xff; 2460 2461 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2462 2463 /* read Tx power for all a/b/g channels */ 2464 for (i = 0; i < 19; i++) { 2465 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2466 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2467 DPRINTF(("Channel=%d Tx power=%d\n", 2468 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2469 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2470 DPRINTF(("Channel=%d Tx power=%d\n", 2471 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2472 } 2473 2474 /* read vendor-specific BBP values */ 2475 for (i = 0; i < 16; i++) { 2476 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2477 if (val == 0 || val == 0xffff) 2478 continue; /* skip invalid entries */ 2479 sc->bbp_prom[i].reg = val >> 8; 2480 sc->bbp_prom[i].val = val & 0xff; 2481 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2482 sc->bbp_prom[i].val)); 2483 } 2484 } 2485 2486 static int 2487 rt2661_bbp_init(struct rt2661_softc *sc) 2488 { 2489 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2490 int i, ntries; 2491 uint8_t val; 2492 2493 /* wait for BBP to be ready */ 2494 for (ntries = 0; ntries < 100; ntries++) { 2495 val = rt2661_bbp_read(sc, 0); 2496 if (val != 0 && val != 0xff) 2497 break; 2498 DELAY(100); 2499 } 2500 if (ntries == 100) { 2501 aprint_error_dev(sc->sc_dev, "timeout waiting for BBP\n"); 2502 return EIO; 2503 } 2504 2505 /* initialize BBP registers to default values */ 2506 for (i = 0; i < N(rt2661_def_bbp); i++) { 2507 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2508 rt2661_def_bbp[i].val); 2509 } 2510 2511 /* write vendor-specific BBP values (from EEPROM) */ 2512 for (i = 0; i < 16; i++) { 2513 if (sc->bbp_prom[i].reg == 0) 2514 continue; 2515 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2516 } 2517 2518 return 0; 2519 #undef N 2520 } 2521 2522 static int 2523 rt2661_init(struct ifnet *ifp) 2524 { 2525 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2526 struct rt2661_softc *sc = ifp->if_softc; 2527 struct ieee80211com *ic = &sc->sc_ic; 2528 const char *name = NULL; /* make lint happy */ 2529 uint8_t *ucode; 2530 size_t size; 2531 uint32_t tmp, star[3]; 2532 int i, ntries; 2533 firmware_handle_t fh; 2534 2535 /* for CardBus, power on the socket */ 2536 if (!(sc->sc_flags & RT2661_ENABLED)) { 2537 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2538 aprint_error_dev(sc->sc_dev, "could not enable device\n"); 2539 return EIO; 2540 } 2541 sc->sc_flags |= RT2661_ENABLED; 2542 } 2543 2544 rt2661_stop(ifp, 0); 2545 2546 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2547 switch (sc->sc_id) { 2548 case PCI_PRODUCT_RALINK_RT2561: 2549 name = "ral-rt2561"; 2550 break; 2551 case PCI_PRODUCT_RALINK_RT2561S: 2552 name = "ral-rt2561s"; 2553 break; 2554 case PCI_PRODUCT_RALINK_RT2661: 2555 name = "ral-rt2661"; 2556 break; 2557 } 2558 2559 if (firmware_open("ral", name, &fh) != 0) { 2560 aprint_error_dev(sc->sc_dev, "could not open microcode %s\n", name); 2561 rt2661_stop(ifp, 1); 2562 return EIO; 2563 } 2564 2565 size = firmware_get_size(fh); 2566 if (!(ucode = firmware_malloc(size))) { 2567 aprint_error_dev(sc->sc_dev, "could not alloc microcode memory\n"); 2568 firmware_close(fh); 2569 rt2661_stop(ifp, 1); 2570 return ENOMEM; 2571 } 2572 2573 if (firmware_read(fh, 0, ucode, size) != 0) { 2574 aprint_error_dev(sc->sc_dev, "could not read microcode %s\n", name); 2575 firmware_free(ucode, size); 2576 firmware_close(fh); 2577 rt2661_stop(ifp, 1); 2578 return EIO; 2579 } 2580 2581 if (rt2661_load_microcode(sc, ucode, size) != 0) { 2582 aprint_error_dev(sc->sc_dev, "could not load 8051 microcode\n"); 2583 firmware_free(ucode, size); 2584 firmware_close(fh); 2585 rt2661_stop(ifp, 1); 2586 return EIO; 2587 } 2588 2589 firmware_free(ucode, size); 2590 firmware_close(fh); 2591 sc->sc_flags |= RT2661_FWLOADED; 2592 } 2593 2594 /* initialize Tx rings */ 2595 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2596 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2597 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2598 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2599 2600 /* initialize Mgt ring */ 2601 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2602 2603 /* initialize Rx ring */ 2604 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2605 2606 /* initialize Tx rings sizes */ 2607 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2608 RT2661_TX_RING_COUNT << 24 | 2609 RT2661_TX_RING_COUNT << 16 | 2610 RT2661_TX_RING_COUNT << 8 | 2611 RT2661_TX_RING_COUNT); 2612 2613 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2614 RT2661_TX_DESC_WSIZE << 16 | 2615 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2616 RT2661_MGT_RING_COUNT); 2617 2618 /* initialize Rx rings */ 2619 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2620 RT2661_RX_DESC_BACK << 16 | 2621 RT2661_RX_DESC_WSIZE << 8 | 2622 RT2661_RX_RING_COUNT); 2623 2624 /* XXX: some magic here */ 2625 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2626 2627 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2628 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2629 2630 /* load base address of Rx ring */ 2631 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2632 2633 /* initialize MAC registers to default values */ 2634 for (i = 0; i < N(rt2661_def_mac); i++) 2635 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2636 2637 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2638 rt2661_set_macaddr(sc, ic->ic_myaddr); 2639 2640 /* set host ready */ 2641 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2642 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2643 2644 /* wait for BBP/RF to wakeup */ 2645 for (ntries = 0; ntries < 1000; ntries++) { 2646 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2647 break; 2648 DELAY(1000); 2649 } 2650 if (ntries == 1000) { 2651 printf("timeout waiting for BBP/RF to wakeup\n"); 2652 rt2661_stop(ifp, 1); 2653 return EIO; 2654 } 2655 2656 if (rt2661_bbp_init(sc) != 0) { 2657 rt2661_stop(ifp, 1); 2658 return EIO; 2659 } 2660 2661 /* select default channel */ 2662 sc->sc_curchan = ic->ic_curchan; 2663 rt2661_select_band(sc, sc->sc_curchan); 2664 rt2661_select_antenna(sc); 2665 rt2661_set_chan(sc, sc->sc_curchan); 2666 2667 /* update Rx filter */ 2668 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2669 2670 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2671 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2672 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2673 RT2661_DROP_ACKCTS; 2674 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2675 tmp |= RT2661_DROP_TODS; 2676 if (!(ifp->if_flags & IFF_PROMISC)) 2677 tmp |= RT2661_DROP_NOT_TO_ME; 2678 } 2679 2680 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2681 2682 /* clear STA registers */ 2683 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, star, N(star)); 2684 2685 /* initialize ASIC */ 2686 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2687 2688 /* clear any pending interrupt */ 2689 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2690 2691 /* enable interrupts */ 2692 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2693 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2694 2695 /* kick Rx */ 2696 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2697 2698 ifp->if_flags &= ~IFF_OACTIVE; 2699 ifp->if_flags |= IFF_RUNNING; 2700 2701 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2702 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2703 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2704 } else 2705 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2706 2707 return 0; 2708 #undef N 2709 } 2710 2711 static void 2712 rt2661_stop(struct ifnet *ifp, int disable) 2713 { 2714 struct rt2661_softc *sc = ifp->if_softc; 2715 struct ieee80211com *ic = &sc->sc_ic; 2716 uint32_t tmp; 2717 2718 sc->sc_tx_timer = 0; 2719 ifp->if_timer = 0; 2720 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2721 2722 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2723 2724 /* abort Tx (for all 5 Tx rings) */ 2725 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2726 2727 /* disable Rx (value remains after reset!) */ 2728 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2729 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2730 2731 /* reset ASIC */ 2732 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2733 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2734 2735 /* disable interrupts */ 2736 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2737 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2738 2739 /* clear any pending interrupt */ 2740 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2741 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2742 2743 /* reset Tx and Rx rings */ 2744 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2745 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2746 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2747 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2748 rt2661_reset_tx_ring(sc, &sc->mgtq); 2749 rt2661_reset_rx_ring(sc, &sc->rxq); 2750 2751 /* for CardBus, power down the socket */ 2752 if (disable && sc->sc_disable != NULL) { 2753 if (sc->sc_flags & RT2661_ENABLED) { 2754 (*sc->sc_disable)(sc); 2755 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2756 } 2757 } 2758 } 2759 2760 static int 2761 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2762 { 2763 int ntries; 2764 2765 /* reset 8051 */ 2766 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2767 2768 /* cancel any pending Host to MCU command */ 2769 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2770 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2771 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2772 2773 /* write 8051's microcode */ 2774 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2775 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2776 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2777 2778 /* kick 8051's ass */ 2779 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2780 2781 /* wait for 8051 to initialize */ 2782 for (ntries = 0; ntries < 500; ntries++) { 2783 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2784 break; 2785 DELAY(100); 2786 } 2787 if (ntries == 500) { 2788 printf("timeout waiting for MCU to initialize\n"); 2789 return EIO; 2790 } 2791 return 0; 2792 } 2793 2794 /* 2795 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2796 * false CCA count. This function is called periodically (every seconds) when 2797 * in the RUN state. Values taken from the reference driver. 2798 */ 2799 static void 2800 rt2661_rx_tune(struct rt2661_softc *sc) 2801 { 2802 uint8_t bbp17; 2803 uint16_t cca; 2804 int lo, hi, dbm; 2805 2806 /* 2807 * Tuning range depends on operating band and on the presence of an 2808 * external low-noise amplifier. 2809 */ 2810 lo = 0x20; 2811 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2812 lo += 0x08; 2813 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2814 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2815 lo += 0x10; 2816 hi = lo + 0x20; 2817 2818 dbm = sc->avg_rssi; 2819 /* retrieve false CCA count since last call (clear on read) */ 2820 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2821 2822 DPRINTFN(2, ("RSSI=%ddBm false CCA=%d\n", dbm, cca)); 2823 2824 if (dbm < -74) { 2825 /* very bad RSSI, tune using false CCA count */ 2826 bbp17 = sc->bbp17; /* current value */ 2827 2828 hi -= 2 * (-74 - dbm); 2829 if (hi < lo) 2830 hi = lo; 2831 2832 if (bbp17 > hi) 2833 bbp17 = hi; 2834 else if (cca > 512) 2835 bbp17 = min(bbp17 + 1, hi); 2836 else if (cca < 100) 2837 bbp17 = max(bbp17 - 1, lo); 2838 2839 } else if (dbm < -66) { 2840 bbp17 = lo + 0x08; 2841 } else if (dbm < -58) { 2842 bbp17 = lo + 0x10; 2843 } else if (dbm < -35) { 2844 bbp17 = hi; 2845 } else { /* very good RSSI >= -35dBm */ 2846 bbp17 = 0x60; /* very low sensitivity */ 2847 } 2848 2849 if (bbp17 != sc->bbp17) { 2850 DPRINTF(("BBP17 %x->%x\n", sc->bbp17, bbp17)); 2851 rt2661_bbp_write(sc, 17, bbp17); 2852 sc->bbp17 = bbp17; 2853 } 2854 } 2855 2856 #ifdef notyet 2857 /* 2858 * Enter/Leave radar detection mode. 2859 * This is for 802.11h additional regulatory domains. 2860 */ 2861 static void 2862 rt2661_radar_start(struct rt2661_softc *sc) 2863 { 2864 uint32_t tmp; 2865 2866 /* disable Rx */ 2867 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2868 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2869 2870 rt2661_bbp_write(sc, 82, 0x20); 2871 rt2661_bbp_write(sc, 83, 0x00); 2872 rt2661_bbp_write(sc, 84, 0x40); 2873 2874 /* save current BBP registers values */ 2875 sc->bbp18 = rt2661_bbp_read(sc, 18); 2876 sc->bbp21 = rt2661_bbp_read(sc, 21); 2877 sc->bbp22 = rt2661_bbp_read(sc, 22); 2878 sc->bbp16 = rt2661_bbp_read(sc, 16); 2879 sc->bbp17 = rt2661_bbp_read(sc, 17); 2880 sc->bbp64 = rt2661_bbp_read(sc, 64); 2881 2882 rt2661_bbp_write(sc, 18, 0xff); 2883 rt2661_bbp_write(sc, 21, 0x3f); 2884 rt2661_bbp_write(sc, 22, 0x3f); 2885 rt2661_bbp_write(sc, 16, 0xbd); 2886 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2887 rt2661_bbp_write(sc, 64, 0x21); 2888 2889 /* restore Rx filter */ 2890 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2891 } 2892 2893 static int 2894 rt2661_radar_stop(struct rt2661_softc *sc) 2895 { 2896 uint8_t bbp66; 2897 2898 /* read radar detection result */ 2899 bbp66 = rt2661_bbp_read(sc, 66); 2900 2901 /* restore BBP registers values */ 2902 rt2661_bbp_write(sc, 16, sc->bbp16); 2903 rt2661_bbp_write(sc, 17, sc->bbp17); 2904 rt2661_bbp_write(sc, 18, sc->bbp18); 2905 rt2661_bbp_write(sc, 21, sc->bbp21); 2906 rt2661_bbp_write(sc, 22, sc->bbp22); 2907 rt2661_bbp_write(sc, 64, sc->bbp64); 2908 2909 return bbp66 == 1; 2910 } 2911 #endif 2912 2913 static int 2914 rt2661_prepare_beacon(struct rt2661_softc *sc) 2915 { 2916 struct ieee80211com *ic = &sc->sc_ic; 2917 struct ieee80211_node *ni = ic->ic_bss; 2918 struct rt2661_tx_desc desc; 2919 struct mbuf *m0; 2920 struct ieee80211_beacon_offsets bo; 2921 int rate; 2922 2923 m0 = ieee80211_beacon_alloc(ic, ni, &bo); 2924 if (m0 == NULL) { 2925 aprint_error_dev(sc->sc_dev, "could not allocate beacon frame\n"); 2926 return ENOBUFS; 2927 } 2928 2929 /* send beacons at the lowest available rate */ 2930 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 2931 2932 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2933 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2934 2935 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2936 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2937 2938 /* copy beacon header and payload into NIC memory */ 2939 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2940 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2941 2942 m_freem(m0); 2943 2944 /* 2945 * Store offset of ERP Information Element so that we can update it 2946 * dynamically when the slot time changes. 2947 * XXX: this is ugly since it depends on how net80211 builds beacon 2948 * frames but ieee80211_beacon_alloc() doesn't store offsets for us. 2949 */ 2950 if (ic->ic_curmode == IEEE80211_MODE_11G) { 2951 sc->erp_csr = 2952 RT2661_HW_BEACON_BASE0 + 24 + 2953 sizeof (struct ieee80211_frame) + 2954 8 + 2 + 2 + 2 + ni->ni_esslen + 2955 2 + min(ni->ni_rates.rs_nrates, IEEE80211_RATE_SIZE) + 2956 2 + 1 + 2957 ((ic->ic_opmode == IEEE80211_M_IBSS) ? 4 : 6) + 2958 2; 2959 } 2960 2961 return 0; 2962 } 2963 2964 /* 2965 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2966 * and HostAP operating modes. 2967 */ 2968 static void 2969 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2970 { 2971 struct ieee80211com *ic = &sc->sc_ic; 2972 uint32_t tmp; 2973 2974 if (ic->ic_opmode != IEEE80211_M_STA) { 2975 /* 2976 * Change default 16ms TBTT adjustment to 8ms. 2977 * Must be done before enabling beacon generation. 2978 */ 2979 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2980 } 2981 2982 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2983 2984 /* set beacon interval (in 1/16ms unit) */ 2985 tmp |= ic->ic_bss->ni_intval * 16; 2986 2987 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2988 if (ic->ic_opmode == IEEE80211_M_STA) 2989 tmp |= RT2661_TSF_MODE(1); 2990 else 2991 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2992 2993 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2994 } 2995 2996 /* 2997 * Retrieve the "Received Signal Strength Indicator" from the raw values 2998 * contained in Rx descriptors. The computation depends on which band the 2999 * frame was received. Correction values taken from the reference driver. 3000 */ 3001 static int 3002 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 3003 { 3004 int lna, agc, rssi; 3005 3006 lna = (raw >> 5) & 0x3; 3007 agc = raw & 0x1f; 3008 3009 rssi = 2 * agc; 3010 3011 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3012 rssi += sc->rssi_2ghz_corr; 3013 3014 if (lna == 1) 3015 rssi -= 64; 3016 else if (lna == 2) 3017 rssi -= 74; 3018 else if (lna == 3) 3019 rssi -= 90; 3020 } else { 3021 rssi += sc->rssi_5ghz_corr; 3022 3023 if (lna == 1) 3024 rssi -= 64; 3025 else if (lna == 2) 3026 rssi -= 86; 3027 else if (lna == 3) 3028 rssi -= 100; 3029 } 3030 return rssi; 3031 } 3032
Indexes created Tue Sep 23 14:10:03 GMT 2025