rt2661.c revision 1.34
1 /* $NetBSD: rt2661.c,v 1.34 2017/02/02 10:05:35 nonaka Exp $ */ 2 /* $OpenBSD: rt2661.c,v 1.17 2006/05/01 08:41:11 damien Exp $ */ 3 /* $FreeBSD: rt2560.c,v 1.5 2006/06/02 19:59:31 csjp Exp $ */ 4 5 /*- 6 * Copyright (c) 2006 7 * Damien Bergamini <damien.bergamini (at) free.fr> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2661.c,v 1.34 2017/02/02 10:05:35 nonaka Exp $"); 29 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/callout.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 60 #include <net80211/ieee80211_var.h> 61 #include <net80211/ieee80211_amrr.h> 62 #include <net80211/ieee80211_radiotap.h> 63 64 #include <dev/ic/rt2661reg.h> 65 #include <dev/ic/rt2661var.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/firmload.h> 72 73 #ifdef RAL_DEBUG 74 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 75 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 76 int rt2661_debug = 0; 77 #else 78 #define DPRINTF(x) 79 #define DPRINTFN(n, x) 80 #endif 81 82 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *, int); 84 static void rt2661_reset_tx_ring(struct rt2661_softc *, 85 struct rt2661_tx_ring *); 86 static void rt2661_free_tx_ring(struct rt2661_softc *, 87 struct rt2661_tx_ring *); 88 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *, int); 90 static void rt2661_reset_rx_ring(struct rt2661_softc *, 91 struct rt2661_rx_ring *); 92 static void rt2661_free_rx_ring(struct rt2661_softc *, 93 struct rt2661_rx_ring *); 94 static struct ieee80211_node * 95 rt2661_node_alloc(struct ieee80211_node_table *); 96 static int rt2661_media_change(struct ifnet *); 97 static void rt2661_next_scan(void *); 98 static void rt2661_iter_func(void *, struct ieee80211_node *); 99 static void rt2661_updatestats(void *); 100 static void rt2661_newassoc(struct ieee80211_node *, int); 101 static int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 102 int); 103 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 104 static void rt2661_tx_intr(struct rt2661_softc *); 105 static void rt2661_tx_dma_intr(struct rt2661_softc *, 106 struct rt2661_tx_ring *); 107 static void rt2661_rx_intr(struct rt2661_softc *); 108 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 109 static void rt2661_mcu_wakeup(struct rt2661_softc *); 110 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 111 int rt2661_intr(void *); 112 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 113 static int rt2661_ack_rate(struct ieee80211com *, int); 114 static uint16_t rt2661_txtime(int, int, uint32_t); 115 static uint8_t rt2661_plcp_signal(int); 116 static void rt2661_setup_tx_desc(struct rt2661_softc *, 117 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 118 const bus_dma_segment_t *, int, int); 119 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 120 struct ieee80211_node *); 121 static struct mbuf * 122 rt2661_get_rts(struct rt2661_softc *, 123 struct ieee80211_frame *, uint16_t); 124 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 125 struct ieee80211_node *, int); 126 static void rt2661_start(struct ifnet *); 127 static void rt2661_watchdog(struct ifnet *); 128 static int rt2661_reset(struct ifnet *); 129 static int rt2661_ioctl(struct ifnet *, u_long, void *); 130 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 131 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 132 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 133 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 134 static void rt2661_select_antenna(struct rt2661_softc *); 135 static void rt2661_enable_mrr(struct rt2661_softc *); 136 static void rt2661_set_txpreamble(struct rt2661_softc *); 137 static void rt2661_set_basicrates(struct rt2661_softc *, 138 const struct ieee80211_rateset *); 139 static void rt2661_select_band(struct rt2661_softc *, 140 struct ieee80211_channel *); 141 static void rt2661_set_chan(struct rt2661_softc *, 142 struct ieee80211_channel *); 143 static void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 144 static void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 145 static void rt2661_update_promisc(struct rt2661_softc *); 146 #if 0 147 static int rt2661_wme_update(struct ieee80211com *); 148 #endif 149 150 static void rt2661_updateslot(struct ifnet *); 151 static void rt2661_set_slottime(struct rt2661_softc *); 152 static const char * 153 rt2661_get_rf(int); 154 static void rt2661_read_eeprom(struct rt2661_softc *); 155 static int rt2661_bbp_init(struct rt2661_softc *); 156 static int rt2661_init(struct ifnet *); 157 static void rt2661_stop(struct ifnet *, int); 158 static int rt2661_load_microcode(struct rt2661_softc *, const uint8_t *, 159 int); 160 static void rt2661_rx_tune(struct rt2661_softc *); 161 #ifdef notyet 162 static void rt2661_radar_start(struct rt2661_softc *); 163 static int rt2661_radar_stop(struct rt2661_softc *); 164 #endif 165 static int rt2661_prepare_beacon(struct rt2661_softc *); 166 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 167 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 168 static void rt2661_softintr(void *); 169 170 /* 171 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 172 */ 173 static const struct ieee80211_rateset rt2661_rateset_11a = 174 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 175 176 static const struct ieee80211_rateset rt2661_rateset_11b = 177 { 4, { 2, 4, 11, 22 } }; 178 179 static const struct ieee80211_rateset rt2661_rateset_11g = 180 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 181 182 static const struct { 183 uint32_t reg; 184 uint32_t val; 185 } rt2661_def_mac[] = { 186 RT2661_DEF_MAC 187 }; 188 189 static const struct { 190 uint8_t reg; 191 uint8_t val; 192 } rt2661_def_bbp[] = { 193 RT2661_DEF_BBP 194 }; 195 196 static const struct rfprog { 197 uint8_t chan; 198 uint32_t r1, r2, r3, r4; 199 } rt2661_rf5225_1[] = { 200 RT2661_RF5225_1 201 }, rt2661_rf5225_2[] = { 202 RT2661_RF5225_2 203 }; 204 205 int 206 rt2661_attach(void *xsc, int id) 207 { 208 struct rt2661_softc *sc = xsc; 209 struct ieee80211com *ic = &sc->sc_ic; 210 struct ifnet *ifp = &sc->sc_if; 211 uint32_t val; 212 int error, i, ntries; 213 214 sc->sc_id = id; 215 216 sc->amrr.amrr_min_success_threshold = 1; 217 sc->amrr.amrr_max_success_threshold = 15; 218 callout_init(&sc->scan_ch, 0); 219 callout_init(&sc->amrr_ch, 0); 220 221 /* wait for NIC to initialize */ 222 for (ntries = 0; ntries < 1000; ntries++) { 223 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 224 break; 225 DELAY(1000); 226 } 227 if (ntries == 1000) { 228 aprint_error_dev(sc->sc_dev, "timeout waiting for NIC to initialize\n"); 229 return EIO; 230 } 231 232 /* retrieve RF rev. no and various other things from EEPROM */ 233 rt2661_read_eeprom(sc); 234 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 235 ether_sprintf(ic->ic_myaddr)); 236 237 aprint_normal_dev(sc->sc_dev, "MAC/BBP RT%X, RF %s\n", val, 238 rt2661_get_rf(sc->rf_rev)); 239 240 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rt2661_softintr, sc); 241 if (sc->sc_soft_ih == NULL) { 242 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 243 goto fail0; 244 } 245 246 /* 247 * Allocate Tx and Rx rings. 248 */ 249 error = rt2661_alloc_tx_ring(sc, &sc->txq[0], RT2661_TX_RING_COUNT); 250 if (error != 0) { 251 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 0\n"); 252 goto fail1; 253 } 254 255 error = rt2661_alloc_tx_ring(sc, &sc->txq[1], RT2661_TX_RING_COUNT); 256 if (error != 0) { 257 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 1\n"); 258 goto fail2; 259 } 260 261 error = rt2661_alloc_tx_ring(sc, &sc->txq[2], RT2661_TX_RING_COUNT); 262 if (error != 0) { 263 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 2\n"); 264 goto fail3; 265 } 266 267 error = rt2661_alloc_tx_ring(sc, &sc->txq[3], RT2661_TX_RING_COUNT); 268 if (error != 0) { 269 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 3\n"); 270 goto fail4; 271 } 272 273 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 274 if (error != 0) { 275 aprint_error_dev(sc->sc_dev, "could not allocate Mgt ring\n"); 276 goto fail5; 277 } 278 279 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 280 if (error != 0) { 281 aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n"); 282 goto fail6; 283 } 284 285 ifp->if_softc = sc; 286 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 287 ifp->if_init = rt2661_init; 288 ifp->if_stop = rt2661_stop; 289 ifp->if_ioctl = rt2661_ioctl; 290 ifp->if_start = rt2661_start; 291 ifp->if_watchdog = rt2661_watchdog; 292 IFQ_SET_READY(&ifp->if_snd); 293 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 294 295 ic->ic_ifp = ifp; 296 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 297 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 298 ic->ic_state = IEEE80211_S_INIT; 299 300 /* set device capabilities */ 301 ic->ic_caps = 302 IEEE80211_C_IBSS | /* IBSS mode supported */ 303 IEEE80211_C_MONITOR | /* monitor mode supported */ 304 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 305 IEEE80211_C_TXPMGT | /* tx power management */ 306 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 307 IEEE80211_C_SHSLOT | /* short slot time supported */ 308 IEEE80211_C_WPA; /* 802.11i */ 309 310 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 311 /* set supported .11a rates */ 312 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 313 314 /* set supported .11a channels */ 315 for (i = 36; i <= 64; i += 4) { 316 ic->ic_channels[i].ic_freq = 317 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 318 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 319 } 320 for (i = 100; i <= 140; i += 4) { 321 ic->ic_channels[i].ic_freq = 322 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 323 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 324 } 325 for (i = 149; i <= 165; i += 4) { 326 ic->ic_channels[i].ic_freq = 327 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 328 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 329 } 330 } 331 332 /* set supported .11b and .11g rates */ 333 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 334 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 335 336 /* set supported .11b and .11g channels (1 through 14) */ 337 for (i = 1; i <= 14; i++) { 338 ic->ic_channels[i].ic_freq = 339 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 340 ic->ic_channels[i].ic_flags = 341 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 342 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 343 } 344 345 if_initialize(ifp); 346 ieee80211_ifattach(ic); 347 /* Use common softint-based if_input */ 348 ifp->if_percpuq = if_percpuq_create(ifp); 349 if_register(ifp); 350 351 ic->ic_node_alloc = rt2661_node_alloc; 352 ic->ic_newassoc = rt2661_newassoc; 353 ic->ic_updateslot = rt2661_updateslot; 354 ic->ic_reset = rt2661_reset; 355 356 /* override state transition machine */ 357 sc->sc_newstate = ic->ic_newstate; 358 ic->ic_newstate = rt2661_newstate; 359 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 360 361 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 362 sizeof(struct ieee80211_frame) + sizeof(sc->sc_txtap), 363 &sc->sc_drvbpf); 364 365 sc->sc_rxtap_len = roundup(sizeof(sc->sc_rxtap), sizeof(u_int32_t)); 366 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 367 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 368 369 sc->sc_txtap_len = roundup(sizeof(sc->sc_txtap), sizeof(u_int32_t)); 370 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 371 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 372 373 ieee80211_announce(ic); 374 375 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 376 pmf_class_network_register(sc->sc_dev, ifp); 377 else 378 aprint_error_dev(sc->sc_dev, 379 "couldn't establish power handler\n"); 380 381 return 0; 382 383 fail6: rt2661_free_tx_ring(sc, &sc->mgtq); 384 fail5: rt2661_free_tx_ring(sc, &sc->txq[3]); 385 fail4: rt2661_free_tx_ring(sc, &sc->txq[2]); 386 fail3: rt2661_free_tx_ring(sc, &sc->txq[1]); 387 fail2: rt2661_free_tx_ring(sc, &sc->txq[0]); 388 fail1: softint_disestablish(sc->sc_soft_ih); 389 sc->sc_soft_ih = NULL; 390 fail0: return ENXIO; 391 } 392 393 int 394 rt2661_detach(void *xsc) 395 { 396 struct rt2661_softc *sc = xsc; 397 struct ifnet *ifp = &sc->sc_if; 398 399 callout_stop(&sc->scan_ch); 400 callout_stop(&sc->amrr_ch); 401 402 pmf_device_deregister(sc->sc_dev); 403 404 ieee80211_ifdetach(&sc->sc_ic); 405 if_detach(ifp); 406 407 rt2661_free_tx_ring(sc, &sc->txq[0]); 408 rt2661_free_tx_ring(sc, &sc->txq[1]); 409 rt2661_free_tx_ring(sc, &sc->txq[2]); 410 rt2661_free_tx_ring(sc, &sc->txq[3]); 411 rt2661_free_tx_ring(sc, &sc->mgtq); 412 rt2661_free_rx_ring(sc, &sc->rxq); 413 414 if (sc->sc_soft_ih != NULL) { 415 softint_disestablish(sc->sc_soft_ih); 416 sc->sc_soft_ih = NULL; 417 } 418 419 return 0; 420 } 421 422 static int 423 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 424 int count) 425 { 426 int i, nsegs, error; 427 428 ring->count = count; 429 ring->queued = 0; 430 ring->cur = ring->next = ring->stat = 0; 431 432 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 433 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 434 if (error != 0) { 435 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 436 goto fail; 437 } 438 439 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 440 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 441 if (error != 0) { 442 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 443 goto fail; 444 } 445 446 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 447 count * RT2661_TX_DESC_SIZE, (void **)&ring->desc, 448 BUS_DMA_NOWAIT); 449 if (error != 0) { 450 aprint_error_dev(sc->sc_dev, "could not map desc DMA memory\n"); 451 goto fail; 452 } 453 454 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 455 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 456 if (error != 0) { 457 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 458 goto fail; 459 } 460 461 memset(ring->desc, 0, count * RT2661_TX_DESC_SIZE); 462 ring->physaddr = ring->map->dm_segs->ds_addr; 463 464 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 465 M_NOWAIT); 466 if (ring->data == NULL) { 467 aprint_error_dev(sc->sc_dev, "could not allocate soft data\n"); 468 error = ENOMEM; 469 goto fail; 470 } 471 472 memset(ring->data, 0, count * sizeof (struct rt2661_tx_data)); 473 for (i = 0; i < count; i++) { 474 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 475 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 476 &ring->data[i].map); 477 if (error != 0) { 478 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 479 goto fail; 480 } 481 } 482 483 return 0; 484 485 fail: rt2661_free_tx_ring(sc, ring); 486 return error; 487 } 488 489 static void 490 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 491 { 492 struct rt2661_tx_desc *desc; 493 struct rt2661_tx_data *data; 494 int i; 495 496 for (i = 0; i < ring->count; i++) { 497 desc = &ring->desc[i]; 498 data = &ring->data[i]; 499 500 if (data->m != NULL) { 501 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 502 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 503 bus_dmamap_unload(sc->sc_dmat, data->map); 504 m_freem(data->m); 505 data->m = NULL; 506 } 507 508 if (data->ni != NULL) { 509 ieee80211_free_node(data->ni); 510 data->ni = NULL; 511 } 512 513 desc->flags = 0; 514 } 515 516 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 517 BUS_DMASYNC_PREWRITE); 518 519 ring->queued = 0; 520 ring->cur = ring->next = ring->stat = 0; 521 } 522 523 524 static void 525 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 526 { 527 struct rt2661_tx_data *data; 528 int i; 529 530 if (ring->desc != NULL) { 531 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 532 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 533 bus_dmamap_unload(sc->sc_dmat, ring->map); 534 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 535 ring->count * RT2661_TX_DESC_SIZE); 536 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 537 } 538 539 if (ring->data != NULL) { 540 for (i = 0; i < ring->count; i++) { 541 data = &ring->data[i]; 542 543 if (data->m != NULL) { 544 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 545 data->map->dm_mapsize, 546 BUS_DMASYNC_POSTWRITE); 547 bus_dmamap_unload(sc->sc_dmat, data->map); 548 m_freem(data->m); 549 } 550 551 if (data->ni != NULL) 552 ieee80211_free_node(data->ni); 553 554 if (data->map != NULL) 555 bus_dmamap_destroy(sc->sc_dmat, data->map); 556 } 557 free(ring->data, M_DEVBUF); 558 } 559 } 560 561 static int 562 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 563 int count) 564 { 565 struct rt2661_rx_desc *desc; 566 struct rt2661_rx_data *data; 567 int i, nsegs, error; 568 569 ring->count = count; 570 ring->cur = ring->next = 0; 571 572 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 573 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 574 if (error != 0) { 575 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 576 goto fail; 577 } 578 579 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 580 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 581 if (error != 0) { 582 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 583 goto fail; 584 } 585 586 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 587 count * RT2661_RX_DESC_SIZE, (void **)&ring->desc, 588 BUS_DMA_NOWAIT); 589 if (error != 0) { 590 aprint_error_dev(sc->sc_dev, "could not map desc DMA memory\n"); 591 goto fail; 592 } 593 594 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 595 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 596 if (error != 0) { 597 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 598 goto fail; 599 } 600 601 memset(ring->desc, 0, count * RT2661_RX_DESC_SIZE); 602 ring->physaddr = ring->map->dm_segs->ds_addr; 603 604 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 605 M_NOWAIT); 606 if (ring->data == NULL) { 607 aprint_error_dev(sc->sc_dev, "could not allocate soft data\n"); 608 error = ENOMEM; 609 goto fail; 610 } 611 612 /* 613 * Pre-allocate Rx buffers and populate Rx ring. 614 */ 615 memset(ring->data, 0, count * sizeof (struct rt2661_rx_data)); 616 for (i = 0; i < count; i++) { 617 desc = &sc->rxq.desc[i]; 618 data = &sc->rxq.data[i]; 619 620 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 621 0, BUS_DMA_NOWAIT, &data->map); 622 if (error != 0) { 623 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 624 goto fail; 625 } 626 627 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 628 if (data->m == NULL) { 629 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 630 error = ENOMEM; 631 goto fail; 632 } 633 634 MCLGET(data->m, M_DONTWAIT); 635 if (!(data->m->m_flags & M_EXT)) { 636 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 637 error = ENOMEM; 638 goto fail; 639 } 640 641 error = bus_dmamap_load(sc->sc_dmat, data->map, 642 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 643 if (error != 0) { 644 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map"); 645 goto fail; 646 } 647 648 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 649 desc->flags = htole32(RT2661_RX_BUSY); 650 } 651 652 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 653 BUS_DMASYNC_PREWRITE); 654 655 return 0; 656 657 fail: rt2661_free_rx_ring(sc, ring); 658 return error; 659 } 660 661 static void 662 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 663 { 664 int i; 665 666 for (i = 0; i < ring->count; i++) 667 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 668 669 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 670 BUS_DMASYNC_PREWRITE); 671 672 ring->cur = ring->next = 0; 673 } 674 675 static void 676 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 677 { 678 struct rt2661_rx_data *data; 679 int i; 680 681 if (ring->desc != NULL) { 682 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 683 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 684 bus_dmamap_unload(sc->sc_dmat, ring->map); 685 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 686 ring->count * RT2661_RX_DESC_SIZE); 687 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 688 } 689 690 if (ring->data != NULL) { 691 for (i = 0; i < ring->count; i++) { 692 data = &ring->data[i]; 693 694 if (data->m != NULL) { 695 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 696 data->map->dm_mapsize, 697 BUS_DMASYNC_POSTREAD); 698 bus_dmamap_unload(sc->sc_dmat, data->map); 699 m_freem(data->m); 700 } 701 702 if (data->map != NULL) 703 bus_dmamap_destroy(sc->sc_dmat, data->map); 704 } 705 free(ring->data, M_DEVBUF); 706 } 707 } 708 709 static struct ieee80211_node * 710 rt2661_node_alloc(struct ieee80211_node_table *nt) 711 { 712 struct rt2661_node *rn; 713 714 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 715 M_NOWAIT | M_ZERO); 716 717 return (rn != NULL) ? &rn->ni : NULL; 718 } 719 720 static int 721 rt2661_media_change(struct ifnet *ifp) 722 { 723 int error; 724 725 error = ieee80211_media_change(ifp); 726 if (error != ENETRESET) 727 return error; 728 729 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 730 rt2661_init(ifp); 731 732 return 0; 733 } 734 735 /* 736 * This function is called periodically (every 200ms) during scanning to 737 * switch from one channel to another. 738 */ 739 static void 740 rt2661_next_scan(void *arg) 741 { 742 struct rt2661_softc *sc = arg; 743 struct ieee80211com *ic = &sc->sc_ic; 744 int s; 745 746 s = splnet(); 747 if (ic->ic_state == IEEE80211_S_SCAN) 748 ieee80211_next_scan(ic); 749 splx(s); 750 } 751 752 /* 753 * This function is called for each neighbor node. 754 */ 755 static void 756 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 757 { 758 struct rt2661_softc *sc = arg; 759 struct rt2661_node *rn = (struct rt2661_node *)ni; 760 761 ieee80211_amrr_choose(&sc->amrr, ni, &rn->amn); 762 } 763 764 /* 765 * This function is called periodically (every 500ms) in RUN state to update 766 * various settings like rate control statistics or Rx sensitivity. 767 */ 768 static void 769 rt2661_updatestats(void *arg) 770 { 771 struct rt2661_softc *sc = arg; 772 struct ieee80211com *ic = &sc->sc_ic; 773 int s; 774 775 s = splnet(); 776 if (ic->ic_opmode == IEEE80211_M_STA) 777 rt2661_iter_func(sc, ic->ic_bss); 778 else 779 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 780 781 /* update rx sensitivity every 1 sec */ 782 if (++sc->ncalls & 1) 783 rt2661_rx_tune(sc); 784 splx(s); 785 786 callout_reset(&sc->amrr_ch, hz / 2, rt2661_updatestats, sc); 787 } 788 789 static void 790 rt2661_newassoc(struct ieee80211_node *ni, int isnew) 791 { 792 struct rt2661_softc *sc = ni->ni_ic->ic_ifp->if_softc; 793 int i; 794 795 ieee80211_amrr_node_init(&sc->amrr, &((struct rt2661_node *)ni)->amn); 796 797 /* set rate to some reasonable initial value */ 798 for (i = ni->ni_rates.rs_nrates - 1; 799 i > 0 && (ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL) > 72; 800 i--); 801 ni->ni_txrate = i; 802 } 803 804 static int 805 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 806 { 807 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 808 enum ieee80211_state ostate; 809 struct ieee80211_node *ni; 810 uint32_t tmp; 811 812 ostate = ic->ic_state; 813 callout_stop(&sc->scan_ch); 814 815 switch (nstate) { 816 case IEEE80211_S_INIT: 817 callout_stop(&sc->amrr_ch); 818 819 if (ostate == IEEE80211_S_RUN) { 820 /* abort TSF synchronization */ 821 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 822 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 823 } 824 break; 825 826 case IEEE80211_S_SCAN: 827 rt2661_set_chan(sc, ic->ic_curchan); 828 callout_reset(&sc->scan_ch, hz / 5, rt2661_next_scan, sc); 829 break; 830 831 case IEEE80211_S_AUTH: 832 case IEEE80211_S_ASSOC: 833 rt2661_set_chan(sc, ic->ic_curchan); 834 break; 835 836 case IEEE80211_S_RUN: 837 rt2661_set_chan(sc, ic->ic_curchan); 838 839 ni = ic->ic_bss; 840 841 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 842 rt2661_set_slottime(sc); 843 rt2661_enable_mrr(sc); 844 rt2661_set_txpreamble(sc); 845 rt2661_set_basicrates(sc, &ni->ni_rates); 846 rt2661_set_bssid(sc, ni->ni_bssid); 847 } 848 849 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 850 ic->ic_opmode == IEEE80211_M_IBSS) 851 rt2661_prepare_beacon(sc); 852 853 if (ic->ic_opmode == IEEE80211_M_STA) { 854 /* fake a join to init the tx rate */ 855 rt2661_newassoc(ni, 1); 856 } 857 858 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 859 sc->ncalls = 0; 860 sc->avg_rssi = -95; /* reset EMA */ 861 callout_reset(&sc->amrr_ch, hz / 2, 862 rt2661_updatestats, sc); 863 rt2661_enable_tsf_sync(sc); 864 } 865 break; 866 } 867 868 return sc->sc_newstate(ic, nstate, arg); 869 } 870 871 /* 872 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 873 * 93C66). 874 */ 875 static uint16_t 876 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 877 { 878 uint32_t tmp; 879 uint16_t val; 880 int n; 881 882 /* clock C once before the first command */ 883 RT2661_EEPROM_CTL(sc, 0); 884 885 RT2661_EEPROM_CTL(sc, RT2661_S); 886 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 887 RT2661_EEPROM_CTL(sc, RT2661_S); 888 889 /* write start bit (1) */ 890 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 891 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 892 893 /* write READ opcode (10) */ 894 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 895 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 896 RT2661_EEPROM_CTL(sc, RT2661_S); 897 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 898 899 /* write address (A5-A0 or A7-A0) */ 900 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 901 for (; n >= 0; n--) { 902 RT2661_EEPROM_CTL(sc, RT2661_S | 903 (((addr >> n) & 1) << RT2661_SHIFT_D)); 904 RT2661_EEPROM_CTL(sc, RT2661_S | 905 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 906 } 907 908 RT2661_EEPROM_CTL(sc, RT2661_S); 909 910 /* read data Q15-Q0 */ 911 val = 0; 912 for (n = 15; n >= 0; n--) { 913 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 914 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 915 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 916 RT2661_EEPROM_CTL(sc, RT2661_S); 917 } 918 919 RT2661_EEPROM_CTL(sc, 0); 920 921 /* clear Chip Select and clock C */ 922 RT2661_EEPROM_CTL(sc, RT2661_S); 923 RT2661_EEPROM_CTL(sc, 0); 924 RT2661_EEPROM_CTL(sc, RT2661_C); 925 926 return val; 927 } 928 929 static void 930 rt2661_tx_intr(struct rt2661_softc *sc) 931 { 932 struct ifnet *ifp = &sc->sc_if; 933 struct rt2661_tx_ring *txq; 934 struct rt2661_tx_data *data; 935 struct rt2661_node *rn; 936 uint32_t val; 937 int qid, retrycnt, s; 938 939 s = splnet(); 940 941 for (;;) { 942 val = RAL_READ(sc, RT2661_STA_CSR4); 943 if (!(val & RT2661_TX_STAT_VALID)) 944 break; 945 946 /* retrieve the queue in which this frame was sent */ 947 qid = RT2661_TX_QID(val); 948 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 949 950 /* retrieve rate control algorithm context */ 951 data = &txq->data[txq->stat]; 952 rn = (struct rt2661_node *)data->ni; 953 954 /* if no frame has been sent, ignore */ 955 if (rn == NULL) 956 continue; 957 958 switch (RT2661_TX_RESULT(val)) { 959 case RT2661_TX_SUCCESS: 960 retrycnt = RT2661_TX_RETRYCNT(val); 961 962 DPRINTFN(10, ("data frame sent successfully after " 963 "%d retries\n", retrycnt)); 964 rn->amn.amn_txcnt++; 965 if (retrycnt > 0) 966 rn->amn.amn_retrycnt++; 967 ifp->if_opackets++; 968 break; 969 970 case RT2661_TX_RETRY_FAIL: 971 DPRINTFN(9, ("sending data frame failed (too much " 972 "retries)\n")); 973 rn->amn.amn_txcnt++; 974 rn->amn.amn_retrycnt++; 975 ifp->if_oerrors++; 976 break; 977 978 default: 979 /* other failure */ 980 aprint_error_dev(sc->sc_dev, "sending data frame failed 0x%08x\n", val); 981 ifp->if_oerrors++; 982 } 983 984 ieee80211_free_node(data->ni); 985 data->ni = NULL; 986 987 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 988 989 txq->queued--; 990 if (++txq->stat >= txq->count) /* faster than % count */ 991 txq->stat = 0; 992 } 993 994 sc->sc_tx_timer = 0; 995 ifp->if_flags &= ~IFF_OACTIVE; 996 rt2661_start(ifp); 997 998 splx(s); 999 } 1000 1001 static void 1002 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1003 { 1004 struct rt2661_tx_desc *desc; 1005 struct rt2661_tx_data *data; 1006 1007 for (;;) { 1008 desc = &txq->desc[txq->next]; 1009 data = &txq->data[txq->next]; 1010 1011 bus_dmamap_sync(sc->sc_dmat, txq->map, 1012 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1013 BUS_DMASYNC_POSTREAD); 1014 1015 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1016 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1017 break; 1018 1019 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1020 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1021 bus_dmamap_unload(sc->sc_dmat, data->map); 1022 m_freem(data->m); 1023 data->m = NULL; 1024 /* node reference is released in rt2661_tx_intr() */ 1025 1026 /* descriptor is no longer valid */ 1027 desc->flags &= ~htole32(RT2661_TX_VALID); 1028 1029 bus_dmamap_sync(sc->sc_dmat, txq->map, 1030 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1031 BUS_DMASYNC_PREWRITE); 1032 1033 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1034 1035 if (++txq->next >= txq->count) /* faster than % count */ 1036 txq->next = 0; 1037 } 1038 } 1039 1040 static void 1041 rt2661_rx_intr(struct rt2661_softc *sc) 1042 { 1043 struct ieee80211com *ic = &sc->sc_ic; 1044 struct ifnet *ifp = &sc->sc_if; 1045 struct rt2661_rx_desc *desc; 1046 struct rt2661_rx_data *data; 1047 struct ieee80211_frame *wh; 1048 struct ieee80211_node *ni; 1049 struct mbuf *mnew, *m; 1050 int error, rssi, s; 1051 1052 for (;;) { 1053 desc = &sc->rxq.desc[sc->rxq.cur]; 1054 data = &sc->rxq.data[sc->rxq.cur]; 1055 1056 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1057 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1058 BUS_DMASYNC_POSTREAD); 1059 1060 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1061 break; 1062 1063 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1064 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1065 /* 1066 * This should not happen since we did not request 1067 * to receive those frames when we filled TXRX_CSR0. 1068 */ 1069 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1070 le32toh(desc->flags))); 1071 ifp->if_ierrors++; 1072 goto skip; 1073 } 1074 1075 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1076 ifp->if_ierrors++; 1077 goto skip; 1078 } 1079 1080 /* 1081 * Try to allocate a new mbuf for this ring element and load it 1082 * before processing the current mbuf. If the ring element 1083 * cannot be loaded, drop the received packet and reuse the old 1084 * mbuf. In the unlikely case that the old mbuf can't be 1085 * reloaded either, explicitly panic. 1086 */ 1087 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1088 if (mnew == NULL) { 1089 ifp->if_ierrors++; 1090 goto skip; 1091 } 1092 1093 MCLGET(mnew, M_DONTWAIT); 1094 if (!(mnew->m_flags & M_EXT)) { 1095 m_freem(mnew); 1096 ifp->if_ierrors++; 1097 goto skip; 1098 } 1099 1100 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1101 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1102 bus_dmamap_unload(sc->sc_dmat, data->map); 1103 1104 error = bus_dmamap_load(sc->sc_dmat, data->map, 1105 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1106 if (error != 0) { 1107 m_freem(mnew); 1108 1109 /* try to reload the old mbuf */ 1110 error = bus_dmamap_load(sc->sc_dmat, data->map, 1111 mtod(data->m, void *), MCLBYTES, NULL, 1112 BUS_DMA_NOWAIT); 1113 if (error != 0) { 1114 /* very unlikely that it will fail... */ 1115 panic("%s: could not load old rx mbuf", 1116 device_xname(sc->sc_dev)); 1117 } 1118 /* physical address may have changed */ 1119 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1120 ifp->if_ierrors++; 1121 goto skip; 1122 } 1123 1124 /* 1125 * New mbuf successfully loaded, update Rx ring and continue 1126 * processing. 1127 */ 1128 m = data->m; 1129 data->m = mnew; 1130 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1131 1132 /* finalize mbuf */ 1133 m_set_rcvif(m, ifp); 1134 m->m_pkthdr.len = m->m_len = 1135 (le32toh(desc->flags) >> 16) & 0xfff; 1136 1137 s = splnet(); 1138 1139 if (sc->sc_drvbpf != NULL) { 1140 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1141 uint32_t tsf_lo, tsf_hi; 1142 1143 /* get timestamp (low and high 32 bits) */ 1144 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1145 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1146 1147 tap->wr_tsf = 1148 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1149 tap->wr_flags = 0; 1150 tap->wr_rate = rt2661_rxrate(desc); 1151 tap->wr_chan_freq = htole16(sc->sc_curchan->ic_freq); 1152 tap->wr_chan_flags = htole16(sc->sc_curchan->ic_flags); 1153 tap->wr_antsignal = desc->rssi; 1154 1155 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1156 } 1157 1158 wh = mtod(m, struct ieee80211_frame *); 1159 ni = ieee80211_find_rxnode(ic, 1160 (struct ieee80211_frame_min *)wh); 1161 1162 /* send the frame to the 802.11 layer */ 1163 ieee80211_input(ic, m, ni, desc->rssi, 0); 1164 1165 /*- 1166 * Keep track of the average RSSI using an Exponential Moving 1167 * Average (EMA) of 8 Wilder's days: 1168 * avg = (1 / N) x rssi + ((N - 1) / N) x avg 1169 */ 1170 rssi = rt2661_get_rssi(sc, desc->rssi); 1171 sc->avg_rssi = (rssi + 7 * sc->avg_rssi) / 8; 1172 1173 /* node is no longer needed */ 1174 ieee80211_free_node(ni); 1175 1176 splx(s); 1177 1178 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1179 1180 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1181 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1182 BUS_DMASYNC_PREWRITE); 1183 1184 DPRINTFN(16, ("rx intr idx=%u\n", sc->rxq.cur)); 1185 1186 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1187 } 1188 1189 /* 1190 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 1191 * without calling if_start(). 1192 */ 1193 s = splnet(); 1194 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 1195 rt2661_start(ifp); 1196 splx(s); 1197 } 1198 1199 /* 1200 * This function is called in HostAP or IBSS modes when it's time to send a 1201 * new beacon (every ni_intval milliseconds). 1202 */ 1203 static void 1204 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1205 { 1206 struct ieee80211com *ic = &sc->sc_ic; 1207 1208 if (sc->sc_flags & RT2661_UPDATE_SLOT) { 1209 sc->sc_flags &= ~RT2661_UPDATE_SLOT; 1210 sc->sc_flags |= RT2661_SET_SLOTTIME; 1211 } else if (sc->sc_flags & RT2661_SET_SLOTTIME) { 1212 sc->sc_flags &= ~RT2661_SET_SLOTTIME; 1213 rt2661_set_slottime(sc); 1214 } 1215 1216 if (ic->ic_curmode == IEEE80211_MODE_11G) { 1217 /* update ERP Information Element */ 1218 RAL_WRITE_1(sc, sc->erp_csr, ic->ic_bss->ni_erp); 1219 RAL_RW_BARRIER_1(sc, sc->erp_csr); 1220 } 1221 1222 DPRINTFN(15, ("beacon expired\n")); 1223 } 1224 1225 static void 1226 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1227 { 1228 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1229 1230 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1231 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1232 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1233 1234 /* send wakeup command to MCU */ 1235 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1236 } 1237 1238 static void 1239 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1240 { 1241 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1242 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1243 } 1244 1245 int 1246 rt2661_intr(void *arg) 1247 { 1248 struct rt2661_softc *sc = arg; 1249 struct ifnet *ifp = &sc->sc_if; 1250 uint32_t r1, r2; 1251 1252 /* don't re-enable interrupts if we're shutting down */ 1253 if (!(ifp->if_flags & IFF_RUNNING)) { 1254 /* disable MAC and MCU interrupts */ 1255 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1256 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1257 return 0; 1258 } 1259 1260 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1261 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1262 1263 if ((r1 & RT2661_INT_CSR_ALL) == 0 && (r2 & RT2661_MCU_INT_ALL) == 0) 1264 return 0; 1265 1266 /* disable interrupts */ 1267 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1268 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1269 1270 softint_schedule(sc->sc_soft_ih); 1271 return 1; 1272 } 1273 1274 static void 1275 rt2661_softintr(void *arg) 1276 { 1277 struct rt2661_softc *sc = arg; 1278 uint32_t r1, r2; 1279 1280 for (;;) { 1281 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1282 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1283 1284 if ((r1 & RT2661_INT_CSR_ALL) == 0 && 1285 (r2 & RT2661_MCU_INT_ALL) == 0) 1286 break; 1287 1288 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1289 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1290 1291 if (r1 & RT2661_MGT_DONE) 1292 rt2661_tx_dma_intr(sc, &sc->mgtq); 1293 1294 if (r1 & RT2661_RX_DONE) 1295 rt2661_rx_intr(sc); 1296 1297 if (r1 & RT2661_TX0_DMA_DONE) 1298 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1299 1300 if (r1 & RT2661_TX1_DMA_DONE) 1301 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1302 1303 if (r1 & RT2661_TX2_DMA_DONE) 1304 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1305 1306 if (r1 & RT2661_TX3_DMA_DONE) 1307 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1308 1309 if (r1 & RT2661_TX_DONE) 1310 rt2661_tx_intr(sc); 1311 1312 if (r2 & RT2661_MCU_CMD_DONE) 1313 rt2661_mcu_cmd_intr(sc); 1314 1315 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1316 rt2661_mcu_beacon_expire(sc); 1317 1318 if (r2 & RT2661_MCU_WAKEUP) 1319 rt2661_mcu_wakeup(sc); 1320 } 1321 1322 /* enable interrupts */ 1323 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1324 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1325 } 1326 1327 /* quickly determine if a given rate is CCK or OFDM */ 1328 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1329 1330 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1331 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1332 1333 /* 1334 * This function is only used by the Rx radiotap code. It returns the rate at 1335 * which a given frame was received. 1336 */ 1337 static uint8_t 1338 rt2661_rxrate(struct rt2661_rx_desc *desc) 1339 { 1340 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1341 /* reverse function of rt2661_plcp_signal */ 1342 switch (desc->rate & 0xf) { 1343 case 0xb: return 12; 1344 case 0xf: return 18; 1345 case 0xa: return 24; 1346 case 0xe: return 36; 1347 case 0x9: return 48; 1348 case 0xd: return 72; 1349 case 0x8: return 96; 1350 case 0xc: return 108; 1351 } 1352 } else { 1353 if (desc->rate == 10) 1354 return 2; 1355 if (desc->rate == 20) 1356 return 4; 1357 if (desc->rate == 55) 1358 return 11; 1359 if (desc->rate == 110) 1360 return 22; 1361 } 1362 return 2; /* should not get there */ 1363 } 1364 1365 /* 1366 * Return the expected ack rate for a frame transmitted at rate `rate'. 1367 * XXX: this should depend on the destination node basic rate set. 1368 */ 1369 static int 1370 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1371 { 1372 switch (rate) { 1373 /* CCK rates */ 1374 case 2: 1375 return 2; 1376 case 4: 1377 case 11: 1378 case 22: 1379 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1380 1381 /* OFDM rates */ 1382 case 12: 1383 case 18: 1384 return 12; 1385 case 24: 1386 case 36: 1387 return 24; 1388 case 48: 1389 case 72: 1390 case 96: 1391 case 108: 1392 return 48; 1393 } 1394 1395 /* default to 1Mbps */ 1396 return 2; 1397 } 1398 1399 /* 1400 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1401 * The function automatically determines the operating mode depending on the 1402 * given rate. `flags' indicates whether short preamble is in use or not. 1403 */ 1404 static uint16_t 1405 rt2661_txtime(int len, int rate, uint32_t flags) 1406 { 1407 uint16_t txtime; 1408 1409 if (RAL_RATE_IS_OFDM(rate)) { 1410 /* IEEE Std 802.11g-2003, pp. 44 */ 1411 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1412 txtime = 16 + 4 + 4 * txtime + 6; 1413 } else { 1414 /* IEEE Std 802.11b-1999, pp. 28 */ 1415 txtime = (16 * len + rate - 1) / rate; 1416 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1417 txtime += 72 + 24; 1418 else 1419 txtime += 144 + 48; 1420 } 1421 return txtime; 1422 } 1423 1424 static uint8_t 1425 rt2661_plcp_signal(int rate) 1426 { 1427 switch (rate) { 1428 /* CCK rates (returned values are device-dependent) */ 1429 case 2: return 0x0; 1430 case 4: return 0x1; 1431 case 11: return 0x2; 1432 case 22: return 0x3; 1433 1434 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1435 case 12: return 0xb; 1436 case 18: return 0xf; 1437 case 24: return 0xa; 1438 case 36: return 0xe; 1439 case 48: return 0x9; 1440 case 72: return 0xd; 1441 case 96: return 0x8; 1442 case 108: return 0xc; 1443 1444 /* unsupported rates (should not get there) */ 1445 default: return 0xff; 1446 } 1447 } 1448 1449 static void 1450 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1451 uint32_t flags, uint16_t xflags, int len, int rate, 1452 const bus_dma_segment_t *segs, int nsegs, int ac) 1453 { 1454 struct ieee80211com *ic = &sc->sc_ic; 1455 uint16_t plcp_length; 1456 int i, remainder; 1457 1458 desc->flags = htole32(flags); 1459 desc->flags |= htole32(len << 16); 1460 1461 desc->xflags = htole16(xflags); 1462 desc->xflags |= htole16(nsegs << 13); 1463 1464 desc->wme = htole16( 1465 RT2661_QID(ac) | 1466 RT2661_AIFSN(2) | 1467 RT2661_LOGCWMIN(4) | 1468 RT2661_LOGCWMAX(10)); 1469 1470 /* 1471 * Remember in which queue this frame was sent. This field is driver 1472 * private data only. It will be made available by the NIC in STA_CSR4 1473 * on Tx interrupts. 1474 */ 1475 desc->qid = ac; 1476 1477 /* setup PLCP fields */ 1478 desc->plcp_signal = rt2661_plcp_signal(rate); 1479 desc->plcp_service = 4; 1480 1481 len += IEEE80211_CRC_LEN; 1482 if (RAL_RATE_IS_OFDM(rate)) { 1483 desc->flags |= htole32(RT2661_TX_OFDM); 1484 1485 plcp_length = len & 0xfff; 1486 desc->plcp_length_hi = plcp_length >> 6; 1487 desc->plcp_length_lo = plcp_length & 0x3f; 1488 } else { 1489 plcp_length = (16 * len + rate - 1) / rate; 1490 if (rate == 22) { 1491 remainder = (16 * len) % 22; 1492 if (remainder != 0 && remainder < 7) 1493 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1494 } 1495 desc->plcp_length_hi = plcp_length >> 8; 1496 desc->plcp_length_lo = plcp_length & 0xff; 1497 1498 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1499 desc->plcp_signal |= 0x08; 1500 } 1501 1502 /* RT2x61 supports scatter with up to 5 segments */ 1503 for (i = 0; i < nsegs; i++) { 1504 desc->addr[i] = htole32(segs[i].ds_addr); 1505 desc->len [i] = htole16(segs[i].ds_len); 1506 } 1507 1508 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1509 } 1510 1511 static int 1512 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1513 struct ieee80211_node *ni) 1514 { 1515 struct ieee80211com *ic = &sc->sc_ic; 1516 struct rt2661_tx_desc *desc; 1517 struct rt2661_tx_data *data; 1518 struct ieee80211_frame *wh; 1519 uint16_t dur; 1520 uint32_t flags = 0; 1521 int rate, error; 1522 1523 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1524 data = &sc->mgtq.data[sc->mgtq.cur]; 1525 1526 /* send mgt frames at the lowest available rate */ 1527 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1528 1529 wh = mtod(m0, struct ieee80211_frame *); 1530 1531 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1532 if (ieee80211_crypto_encap(ic, ni, m0) == NULL) { 1533 m_freem(m0); 1534 return ENOBUFS; 1535 } 1536 1537 /* packet header may have moved, reset our local pointer */ 1538 wh = mtod(m0, struct ieee80211_frame *); 1539 } 1540 1541 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1542 BUS_DMA_NOWAIT); 1543 if (error != 0) { 1544 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1545 error); 1546 m_freem(m0); 1547 return error; 1548 } 1549 1550 if (sc->sc_drvbpf != NULL) { 1551 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1552 1553 tap->wt_flags = 0; 1554 tap->wt_rate = rate; 1555 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1556 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1557 1558 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1559 } 1560 1561 data->m = m0; 1562 data->ni = ni; 1563 1564 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1565 flags |= RT2661_TX_NEED_ACK; 1566 1567 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1568 sc->sifs; 1569 *(uint16_t *)wh->i_dur = htole16(dur); 1570 1571 /* tell hardware to set timestamp in probe responses */ 1572 if ((wh->i_fc[0] & 1573 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1574 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1575 flags |= RT2661_TX_TIMESTAMP; 1576 } 1577 1578 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1579 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1580 RT2661_QID_MGT); 1581 1582 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1583 BUS_DMASYNC_PREWRITE); 1584 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1585 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1586 BUS_DMASYNC_PREWRITE); 1587 1588 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1589 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1590 1591 /* kick mgt */ 1592 sc->mgtq.queued++; 1593 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1594 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1595 1596 return 0; 1597 } 1598 1599 /* 1600 * Build a RTS control frame. 1601 */ 1602 static struct mbuf * 1603 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1604 uint16_t dur) 1605 { 1606 struct ieee80211_frame_rts *rts; 1607 struct mbuf *m; 1608 1609 MGETHDR(m, M_DONTWAIT, MT_DATA); 1610 if (m == NULL) { 1611 sc->sc_ic.ic_stats.is_tx_nobuf++; 1612 aprint_error_dev(sc->sc_dev, "could not allocate RTS frame\n"); 1613 return NULL; 1614 } 1615 1616 rts = mtod(m, struct ieee80211_frame_rts *); 1617 1618 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1619 IEEE80211_FC0_SUBTYPE_RTS; 1620 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1621 *(uint16_t *)rts->i_dur = htole16(dur); 1622 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1623 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1624 1625 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1626 1627 return m; 1628 } 1629 1630 static int 1631 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1632 struct ieee80211_node *ni, int ac) 1633 { 1634 struct ieee80211com *ic = &sc->sc_ic; 1635 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1636 struct rt2661_tx_desc *desc; 1637 struct rt2661_tx_data *data; 1638 struct ieee80211_frame *wh; 1639 struct ieee80211_key *k; 1640 struct mbuf *mnew; 1641 uint16_t dur; 1642 uint32_t flags = 0; 1643 int rate, useprot, error, tid; 1644 1645 wh = mtod(m0, struct ieee80211_frame *); 1646 1647 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1648 rate = ic->ic_sup_rates[ic->ic_curmode]. 1649 rs_rates[ic->ic_fixed_rate]; 1650 } else 1651 rate = ni->ni_rates.rs_rates[ni->ni_txrate]; 1652 rate &= IEEE80211_RATE_VAL; 1653 if (rate == 0) 1654 rate = 2; /* XXX should not happen */ 1655 1656 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1657 k = ieee80211_crypto_encap(ic, ni, m0); 1658 if (k == NULL) { 1659 m_freem(m0); 1660 return ENOBUFS; 1661 } 1662 1663 /* packet header may have moved, reset our local pointer */ 1664 wh = mtod(m0, struct ieee80211_frame *); 1665 } 1666 1667 /* 1668 * Packet Bursting: backoff after ppb=8 frames to give other STAs a 1669 * chance to contend for the wireless medium. 1670 */ 1671 tid = WME_AC_TO_TID(M_WME_GETAC(m0)); 1672 if (ic->ic_opmode == IEEE80211_M_STA && (ni->ni_txseqs[tid] & 7)) 1673 flags |= RT2661_TX_IFS_SIFS; 1674 1675 /* 1676 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1677 * for directed frames only when the length of the MPDU is greater 1678 * than the length threshold indicated by" ic_rtsthreshold. 1679 * 1680 * IEEE Std 802.11-2003g, pp 13: "ERP STAs shall use protection 1681 * mechanism (such as RTS/CTS or CTS-to-self) for ERP-OFDM MPDUs of 1682 * type Data or an MMPDU". 1683 */ 1684 useprot = !IEEE80211_IS_MULTICAST(wh->i_addr1) && 1685 (m0->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1686 ((ic->ic_flags & IEEE80211_F_USEPROT) && RAL_RATE_IS_OFDM(rate))); 1687 if (useprot) { 1688 struct mbuf *m; 1689 int rtsrate, ackrate; 1690 1691 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1692 ackrate = rt2661_ack_rate(ic, rate); 1693 1694 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1695 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1696 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1697 3 * sc->sifs; 1698 1699 m = rt2661_get_rts(sc, wh, dur); 1700 if (m == NULL) { 1701 aprint_error_dev(sc->sc_dev, "could not allocate RTS " 1702 "frame\n"); 1703 m_freem(m0); 1704 return ENOBUFS; 1705 } 1706 1707 desc = &txq->desc[txq->cur]; 1708 data = &txq->data[txq->cur]; 1709 1710 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1711 BUS_DMA_NOWAIT); 1712 if (error != 0) { 1713 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1714 m_freem(m); 1715 m_freem(m0); 1716 return error; 1717 } 1718 1719 /* avoid multiple free() of the same node for each fragment */ 1720 ieee80211_ref_node(ni); 1721 1722 data->m = m; 1723 data->ni = ni; 1724 1725 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1726 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, 1727 data->map->dm_segs, data->map->dm_nsegs, ac); 1728 1729 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1730 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1731 bus_dmamap_sync(sc->sc_dmat, txq->map, 1732 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1733 BUS_DMASYNC_PREWRITE); 1734 1735 txq->queued++; 1736 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1737 1738 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS_SIFS; 1739 } 1740 1741 data = &txq->data[txq->cur]; 1742 desc = &txq->desc[txq->cur]; 1743 1744 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1745 BUS_DMA_NOWAIT); 1746 if (error != 0 && error != EFBIG) { 1747 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1748 error); 1749 m_freem(m0); 1750 return error; 1751 } 1752 if (error != 0) { 1753 /* too many fragments, linearize */ 1754 1755 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1756 if (mnew == NULL) { 1757 m_freem(m0); 1758 return ENOMEM; 1759 } 1760 1761 M_COPY_PKTHDR(mnew, m0); 1762 if (m0->m_pkthdr.len > MHLEN) { 1763 MCLGET(mnew, M_DONTWAIT); 1764 if (!(mnew->m_flags & M_EXT)) { 1765 m_freem(m0); 1766 m_freem(mnew); 1767 return ENOMEM; 1768 } 1769 } 1770 1771 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1772 m_freem(m0); 1773 mnew->m_len = mnew->m_pkthdr.len; 1774 m0 = mnew; 1775 1776 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1777 BUS_DMA_NOWAIT); 1778 if (error != 0) { 1779 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1780 m_freem(m0); 1781 return error; 1782 } 1783 1784 /* packet header have moved, reset our local pointer */ 1785 wh = mtod(m0, struct ieee80211_frame *); 1786 } 1787 1788 if (sc->sc_drvbpf != NULL) { 1789 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1790 1791 tap->wt_flags = 0; 1792 tap->wt_rate = rate; 1793 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1794 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1795 1796 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1797 } 1798 1799 data->m = m0; 1800 data->ni = ni; 1801 1802 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1803 flags |= RT2661_TX_NEED_ACK; 1804 1805 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1806 ic->ic_flags) + sc->sifs; 1807 *(uint16_t *)wh->i_dur = htole16(dur); 1808 } 1809 1810 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1811 data->map->dm_segs, data->map->dm_nsegs, ac); 1812 1813 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1814 BUS_DMASYNC_PREWRITE); 1815 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1816 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1817 1818 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1819 m0->m_pkthdr.len, txq->cur, rate)); 1820 1821 /* kick Tx */ 1822 txq->queued++; 1823 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1824 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1825 1826 return 0; 1827 } 1828 1829 static void 1830 rt2661_start(struct ifnet *ifp) 1831 { 1832 struct rt2661_softc *sc = ifp->if_softc; 1833 struct ieee80211com *ic = &sc->sc_ic; 1834 struct mbuf *m0; 1835 struct ether_header *eh; 1836 struct ieee80211_node *ni = NULL; 1837 1838 /* 1839 * net80211 may still try to send management frames even if the 1840 * IFF_RUNNING flag is not set... 1841 */ 1842 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1843 return; 1844 1845 for (;;) { 1846 IF_POLL(&ic->ic_mgtq, m0); 1847 if (m0 != NULL) { 1848 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1849 ifp->if_flags |= IFF_OACTIVE; 1850 break; 1851 } 1852 IF_DEQUEUE(&ic->ic_mgtq, m0); 1853 if (m0 == NULL) 1854 break; 1855 1856 ni = M_GETCTX(m0, struct ieee80211_node *); 1857 M_CLEARCTX(m0); 1858 bpf_mtap3(ic->ic_rawbpf, m0); 1859 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1860 break; 1861 1862 } else { 1863 IF_POLL(&ifp->if_snd, m0); 1864 if (m0 == NULL || ic->ic_state != IEEE80211_S_RUN) 1865 break; 1866 1867 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1868 /* there is no place left in this ring */ 1869 ifp->if_flags |= IFF_OACTIVE; 1870 break; 1871 } 1872 1873 IFQ_DEQUEUE(&ifp->if_snd, m0); 1874 1875 if (m0->m_len < sizeof (struct ether_header) && 1876 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1877 continue; 1878 1879 eh = mtod(m0, struct ether_header *); 1880 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1881 if (ni == NULL) { 1882 m_freem(m0); 1883 ifp->if_oerrors++; 1884 continue; 1885 } 1886 1887 bpf_mtap3(ifp->if_bpf, m0); 1888 m0 = ieee80211_encap(ic, m0, ni); 1889 if (m0 == NULL) { 1890 ieee80211_free_node(ni); 1891 ifp->if_oerrors++; 1892 continue; 1893 } 1894 bpf_mtap3(ic->ic_rawbpf, m0); 1895 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1896 if (ni != NULL) 1897 ieee80211_free_node(ni); 1898 ifp->if_oerrors++; 1899 break; 1900 } 1901 } 1902 1903 sc->sc_tx_timer = 5; 1904 ifp->if_timer = 1; 1905 } 1906 } 1907 1908 static void 1909 rt2661_watchdog(struct ifnet *ifp) 1910 { 1911 struct rt2661_softc *sc = ifp->if_softc; 1912 1913 ifp->if_timer = 0; 1914 1915 if (sc->sc_tx_timer > 0) { 1916 if (--sc->sc_tx_timer == 0) { 1917 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1918 rt2661_init(ifp); 1919 ifp->if_oerrors++; 1920 return; 1921 } 1922 ifp->if_timer = 1; 1923 } 1924 1925 ieee80211_watchdog(&sc->sc_ic); 1926 } 1927 1928 /* 1929 * This function allows for fast channel switching in monitor mode (used by 1930 * kismet). In IBSS mode, we must explicitly reset the interface to 1931 * generate a new beacon frame. 1932 */ 1933 static int 1934 rt2661_reset(struct ifnet *ifp) 1935 { 1936 struct rt2661_softc *sc = ifp->if_softc; 1937 struct ieee80211com *ic = &sc->sc_ic; 1938 1939 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1940 return ENETRESET; 1941 1942 rt2661_set_chan(sc, ic->ic_curchan); 1943 1944 return 0; 1945 } 1946 1947 static int 1948 rt2661_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1949 { 1950 struct rt2661_softc *sc = ifp->if_softc; 1951 struct ieee80211com *ic = &sc->sc_ic; 1952 int s, error = 0; 1953 1954 s = splnet(); 1955 1956 switch (cmd) { 1957 case SIOCSIFFLAGS: 1958 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1959 break; 1960 if (ifp->if_flags & IFF_UP) { 1961 if (ifp->if_flags & IFF_RUNNING) 1962 rt2661_update_promisc(sc); 1963 else 1964 rt2661_init(ifp); 1965 } else { 1966 if (ifp->if_flags & IFF_RUNNING) 1967 rt2661_stop(ifp, 1); 1968 } 1969 break; 1970 1971 case SIOCADDMULTI: 1972 case SIOCDELMULTI: 1973 /* XXX no h/w multicast filter? --dyoung */ 1974 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 1975 error = 0; 1976 break; 1977 1978 case SIOCS80211CHANNEL: 1979 /* 1980 * This allows for fast channel switching in monitor mode 1981 * (used by kismet). In IBSS mode, we must explicitly reset 1982 * the interface to generate a new beacon frame. 1983 */ 1984 error = ieee80211_ioctl(ic, cmd, data); 1985 if (error == ENETRESET && 1986 ic->ic_opmode == IEEE80211_M_MONITOR) { 1987 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1988 (IFF_UP | IFF_RUNNING)) 1989 rt2661_set_chan(sc, ic->ic_ibss_chan); 1990 error = 0; 1991 } 1992 break; 1993 1994 default: 1995 error = ieee80211_ioctl(ic, cmd, data); 1996 1997 } 1998 1999 if (error == ENETRESET) { 2000 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2001 (IFF_UP | IFF_RUNNING)) 2002 rt2661_init(ifp); 2003 error = 0; 2004 } 2005 2006 splx(s); 2007 2008 return error; 2009 } 2010 2011 static void 2012 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 2013 { 2014 uint32_t tmp; 2015 int ntries; 2016 2017 for (ntries = 0; ntries < 100; ntries++) { 2018 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2019 break; 2020 DELAY(1); 2021 } 2022 if (ntries == 100) { 2023 aprint_error_dev(sc->sc_dev, "could not write to BBP\n"); 2024 return; 2025 } 2026 2027 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 2028 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 2029 2030 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 2031 } 2032 2033 static uint8_t 2034 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2035 { 2036 uint32_t val; 2037 int ntries; 2038 2039 for (ntries = 0; ntries < 100; ntries++) { 2040 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2041 break; 2042 DELAY(1); 2043 } 2044 if (ntries == 100) { 2045 aprint_error_dev(sc->sc_dev, "could not read from BBP\n"); 2046 return 0; 2047 } 2048 2049 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2050 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2051 2052 for (ntries = 0; ntries < 100; ntries++) { 2053 val = RAL_READ(sc, RT2661_PHY_CSR3); 2054 if (!(val & RT2661_BBP_BUSY)) 2055 return val & 0xff; 2056 DELAY(1); 2057 } 2058 2059 aprint_error_dev(sc->sc_dev, "could not read from BBP\n"); 2060 return 0; 2061 } 2062 2063 static void 2064 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2065 { 2066 uint32_t tmp; 2067 int ntries; 2068 2069 for (ntries = 0; ntries < 100; ntries++) { 2070 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2071 break; 2072 DELAY(1); 2073 } 2074 if (ntries == 100) { 2075 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2076 return; 2077 } 2078 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2079 (reg & 3); 2080 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2081 2082 /* remember last written value in sc */ 2083 sc->rf_regs[reg] = val; 2084 2085 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2086 } 2087 2088 static int 2089 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2090 { 2091 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2092 return EIO; /* there is already a command pending */ 2093 2094 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2095 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2096 2097 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2098 2099 return 0; 2100 } 2101 2102 static void 2103 rt2661_select_antenna(struct rt2661_softc *sc) 2104 { 2105 uint8_t bbp4, bbp77; 2106 uint32_t tmp; 2107 2108 bbp4 = rt2661_bbp_read(sc, 4); 2109 bbp77 = rt2661_bbp_read(sc, 77); 2110 2111 /* TBD */ 2112 2113 /* make sure Rx is disabled before switching antenna */ 2114 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2115 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2116 2117 rt2661_bbp_write(sc, 4, bbp4); 2118 rt2661_bbp_write(sc, 77, bbp77); 2119 2120 /* restore Rx filter */ 2121 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2122 } 2123 2124 /* 2125 * Enable multi-rate retries for frames sent at OFDM rates. 2126 * In 802.11b/g mode, allow fallback to CCK rates. 2127 */ 2128 static void 2129 rt2661_enable_mrr(struct rt2661_softc *sc) 2130 { 2131 struct ieee80211com *ic = &sc->sc_ic; 2132 uint32_t tmp; 2133 2134 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2135 2136 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2137 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2138 tmp |= RT2661_MRR_CCK_FALLBACK; 2139 tmp |= RT2661_MRR_ENABLED; 2140 2141 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2142 } 2143 2144 static void 2145 rt2661_set_txpreamble(struct rt2661_softc *sc) 2146 { 2147 uint32_t tmp; 2148 2149 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2150 2151 tmp &= ~RT2661_SHORT_PREAMBLE; 2152 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2153 tmp |= RT2661_SHORT_PREAMBLE; 2154 2155 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2156 } 2157 2158 static void 2159 rt2661_set_basicrates(struct rt2661_softc *sc, 2160 const struct ieee80211_rateset *rs) 2161 { 2162 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2163 uint32_t mask = 0; 2164 uint8_t rate; 2165 int i, j; 2166 2167 for (i = 0; i < rs->rs_nrates; i++) { 2168 rate = rs->rs_rates[i]; 2169 2170 if (!(rate & IEEE80211_RATE_BASIC)) 2171 continue; 2172 2173 /* 2174 * Find h/w rate index. We know it exists because the rate 2175 * set has already been negotiated. 2176 */ 2177 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++); 2178 2179 mask |= 1 << j; 2180 } 2181 2182 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2183 2184 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2185 #undef RV 2186 } 2187 2188 /* 2189 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2190 * driver. 2191 */ 2192 static void 2193 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2194 { 2195 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2196 uint32_t tmp; 2197 2198 /* update all BBP registers that depend on the band */ 2199 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2200 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2201 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2202 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2203 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2204 } 2205 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2206 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2207 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2208 } 2209 2210 sc->bbp17 = bbp17; 2211 rt2661_bbp_write(sc, 17, bbp17); 2212 rt2661_bbp_write(sc, 96, bbp96); 2213 rt2661_bbp_write(sc, 104, bbp104); 2214 2215 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2216 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2217 rt2661_bbp_write(sc, 75, 0x80); 2218 rt2661_bbp_write(sc, 86, 0x80); 2219 rt2661_bbp_write(sc, 88, 0x80); 2220 } 2221 2222 rt2661_bbp_write(sc, 35, bbp35); 2223 rt2661_bbp_write(sc, 97, bbp97); 2224 rt2661_bbp_write(sc, 98, bbp98); 2225 2226 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2227 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2228 if (IEEE80211_IS_CHAN_2GHZ(c)) 2229 tmp |= RT2661_PA_PE_2GHZ; 2230 else 2231 tmp |= RT2661_PA_PE_5GHZ; 2232 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2233 2234 /* 802.11a uses a 16 microseconds short interframe space */ 2235 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10; 2236 } 2237 2238 static void 2239 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2240 { 2241 struct ieee80211com *ic = &sc->sc_ic; 2242 const struct rfprog *rfprog; 2243 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2244 int8_t power; 2245 u_int i, chan; 2246 2247 chan = ieee80211_chan2ieee(ic, c); 2248 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2249 return; 2250 2251 /* select the appropriate RF settings based on what EEPROM says */ 2252 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2253 2254 /* find the settings for this channel (we know it exists) */ 2255 for (i = 0; rfprog[i].chan != chan; i++); 2256 2257 power = sc->txpow[i]; 2258 if (power < 0) { 2259 bbp94 += power; 2260 power = 0; 2261 } else if (power > 31) { 2262 bbp94 += power - 31; 2263 power = 31; 2264 } 2265 2266 /* 2267 * If we've yet to select a channel, or we are switching from the 2268 * 2GHz band to the 5GHz band or vice-versa, BBP registers need to 2269 * be reprogrammed. 2270 */ 2271 if (sc->sc_curchan == NULL || c->ic_flags != sc->sc_curchan->ic_flags) { 2272 rt2661_select_band(sc, c); 2273 rt2661_select_antenna(sc); 2274 } 2275 sc->sc_curchan = c; 2276 2277 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2278 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2279 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2280 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2281 2282 DELAY(200); 2283 2284 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2285 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2286 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2287 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2288 2289 DELAY(200); 2290 2291 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2292 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2293 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2294 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2295 2296 /* enable smart mode for MIMO-capable RFs */ 2297 bbp3 = rt2661_bbp_read(sc, 3); 2298 2299 bbp3 &= ~RT2661_SMART_MODE; 2300 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2301 bbp3 |= RT2661_SMART_MODE; 2302 2303 rt2661_bbp_write(sc, 3, bbp3); 2304 2305 if (bbp94 != RT2661_BBPR94_DEFAULT) 2306 rt2661_bbp_write(sc, 94, bbp94); 2307 2308 /* 5GHz radio needs a 1ms delay here */ 2309 if (IEEE80211_IS_CHAN_5GHZ(c)) 2310 DELAY(1000); 2311 } 2312 2313 static void 2314 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2315 { 2316 uint32_t tmp; 2317 2318 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2319 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2320 2321 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2322 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2323 } 2324 2325 static void 2326 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2327 { 2328 uint32_t tmp; 2329 2330 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2331 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2332 2333 tmp = addr[4] | addr[5] << 8 | 0xff << 16; 2334 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2335 } 2336 2337 static void 2338 rt2661_update_promisc(struct rt2661_softc *sc) 2339 { 2340 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2341 uint32_t tmp; 2342 2343 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2344 2345 tmp &= ~RT2661_DROP_NOT_TO_ME; 2346 if (!(ifp->if_flags & IFF_PROMISC)) 2347 tmp |= RT2661_DROP_NOT_TO_ME; 2348 2349 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2350 2351 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2352 "entering" : "leaving")); 2353 } 2354 2355 #if 0 2356 /* 2357 * Update QoS (802.11e) settings for each h/w Tx ring. 2358 */ 2359 static int 2360 rt2661_wme_update(struct ieee80211com *ic) 2361 { 2362 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2363 const struct wmeParams *wmep; 2364 2365 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2366 2367 /* XXX: not sure about shifts. */ 2368 /* XXX: the reference driver plays with AC_VI settings too. */ 2369 2370 /* update TxOp */ 2371 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2372 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2373 wmep[WME_AC_BK].wmep_txopLimit); 2374 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2375 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2376 wmep[WME_AC_VO].wmep_txopLimit); 2377 2378 /* update CWmin */ 2379 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2380 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2381 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2382 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2383 wmep[WME_AC_VO].wmep_logcwmin); 2384 2385 /* update CWmax */ 2386 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2387 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2388 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2389 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2390 wmep[WME_AC_VO].wmep_logcwmax); 2391 2392 /* update Aifsn */ 2393 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2394 wmep[WME_AC_BE].wmep_aifsn << 12 | 2395 wmep[WME_AC_BK].wmep_aifsn << 8 | 2396 wmep[WME_AC_VI].wmep_aifsn << 4 | 2397 wmep[WME_AC_VO].wmep_aifsn); 2398 2399 return 0; 2400 } 2401 #endif 2402 2403 static void 2404 rt2661_updateslot(struct ifnet *ifp) 2405 { 2406 struct rt2661_softc *sc = ifp->if_softc; 2407 struct ieee80211com *ic = &sc->sc_ic; 2408 2409 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2410 /* 2411 * In HostAP mode, we defer setting of new slot time until 2412 * updated ERP Information Element has propagated to all 2413 * associated STAs. 2414 */ 2415 sc->sc_flags |= RT2661_UPDATE_SLOT; 2416 } else 2417 rt2661_set_slottime(sc); 2418 } 2419 2420 static void 2421 rt2661_set_slottime(struct rt2661_softc *sc) 2422 { 2423 struct ieee80211com *ic = &sc->sc_ic; 2424 uint8_t slottime; 2425 uint32_t tmp; 2426 2427 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2428 2429 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2430 tmp = (tmp & ~0xff) | slottime; 2431 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2432 2433 DPRINTF(("setting slot time to %uus\n", slottime)); 2434 } 2435 2436 static const char * 2437 rt2661_get_rf(int rev) 2438 { 2439 switch (rev) { 2440 case RT2661_RF_5225: return "RT5225"; 2441 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2442 case RT2661_RF_2527: return "RT2527"; 2443 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2444 default: return "unknown"; 2445 } 2446 } 2447 2448 static void 2449 rt2661_read_eeprom(struct rt2661_softc *sc) 2450 { 2451 struct ieee80211com *ic = &sc->sc_ic; 2452 uint16_t val; 2453 int i; 2454 2455 /* read MAC address */ 2456 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2457 ic->ic_myaddr[0] = val & 0xff; 2458 ic->ic_myaddr[1] = val >> 8; 2459 2460 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2461 ic->ic_myaddr[2] = val & 0xff; 2462 ic->ic_myaddr[3] = val >> 8; 2463 2464 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2465 ic->ic_myaddr[4] = val & 0xff; 2466 ic->ic_myaddr[5] = val >> 8; 2467 2468 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2469 /* XXX: test if different from 0xffff? */ 2470 sc->rf_rev = (val >> 11) & 0x1f; 2471 sc->hw_radio = (val >> 10) & 0x1; 2472 sc->rx_ant = (val >> 4) & 0x3; 2473 sc->tx_ant = (val >> 2) & 0x3; 2474 sc->nb_ant = val & 0x3; 2475 2476 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2477 2478 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2479 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2480 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2481 2482 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2483 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2484 2485 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2486 if ((val & 0xff) != 0xff) 2487 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2488 2489 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2490 if ((val & 0xff) != 0xff) 2491 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2492 2493 /* adjust RSSI correction for external low-noise amplifier */ 2494 if (sc->ext_2ghz_lna) 2495 sc->rssi_2ghz_corr -= 14; 2496 if (sc->ext_5ghz_lna) 2497 sc->rssi_5ghz_corr -= 14; 2498 2499 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2500 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2501 2502 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2503 if ((val >> 8) != 0xff) 2504 sc->rfprog = (val >> 8) & 0x3; 2505 if ((val & 0xff) != 0xff) 2506 sc->rffreq = val & 0xff; 2507 2508 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2509 2510 /* read Tx power for all a/b/g channels */ 2511 for (i = 0; i < 19; i++) { 2512 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2513 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2514 DPRINTF(("Channel=%d Tx power=%d\n", 2515 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2516 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2517 DPRINTF(("Channel=%d Tx power=%d\n", 2518 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2519 } 2520 2521 /* read vendor-specific BBP values */ 2522 for (i = 0; i < 16; i++) { 2523 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2524 if (val == 0 || val == 0xffff) 2525 continue; /* skip invalid entries */ 2526 sc->bbp_prom[i].reg = val >> 8; 2527 sc->bbp_prom[i].val = val & 0xff; 2528 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2529 sc->bbp_prom[i].val)); 2530 } 2531 } 2532 2533 static int 2534 rt2661_bbp_init(struct rt2661_softc *sc) 2535 { 2536 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2537 int i, ntries; 2538 uint8_t val; 2539 2540 /* wait for BBP to be ready */ 2541 for (ntries = 0; ntries < 100; ntries++) { 2542 val = rt2661_bbp_read(sc, 0); 2543 if (val != 0 && val != 0xff) 2544 break; 2545 DELAY(100); 2546 } 2547 if (ntries == 100) { 2548 aprint_error_dev(sc->sc_dev, "timeout waiting for BBP\n"); 2549 return EIO; 2550 } 2551 2552 /* initialize BBP registers to default values */ 2553 for (i = 0; i < N(rt2661_def_bbp); i++) { 2554 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2555 rt2661_def_bbp[i].val); 2556 } 2557 2558 /* write vendor-specific BBP values (from EEPROM) */ 2559 for (i = 0; i < 16; i++) { 2560 if (sc->bbp_prom[i].reg == 0) 2561 continue; 2562 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2563 } 2564 2565 return 0; 2566 #undef N 2567 } 2568 2569 static int 2570 rt2661_init(struct ifnet *ifp) 2571 { 2572 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2573 struct rt2661_softc *sc = ifp->if_softc; 2574 struct ieee80211com *ic = &sc->sc_ic; 2575 const char *name = NULL; /* make lint happy */ 2576 uint8_t *ucode; 2577 size_t size; 2578 uint32_t tmp, star[3]; 2579 int i, ntries; 2580 firmware_handle_t fh; 2581 2582 /* for CardBus, power on the socket */ 2583 if (!(sc->sc_flags & RT2661_ENABLED)) { 2584 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2585 aprint_error_dev(sc->sc_dev, "could not enable device\n"); 2586 return EIO; 2587 } 2588 sc->sc_flags |= RT2661_ENABLED; 2589 } 2590 2591 rt2661_stop(ifp, 0); 2592 2593 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2594 switch (sc->sc_id) { 2595 case PCI_PRODUCT_RALINK_RT2561: 2596 name = "ral-rt2561"; 2597 break; 2598 case PCI_PRODUCT_RALINK_RT2561S: 2599 name = "ral-rt2561s"; 2600 break; 2601 case PCI_PRODUCT_RALINK_RT2661: 2602 name = "ral-rt2661"; 2603 break; 2604 } 2605 2606 if (firmware_open("ral", name, &fh) != 0) { 2607 aprint_error_dev(sc->sc_dev, "could not open microcode %s\n", name); 2608 rt2661_stop(ifp, 1); 2609 return EIO; 2610 } 2611 2612 size = firmware_get_size(fh); 2613 if (!(ucode = firmware_malloc(size))) { 2614 aprint_error_dev(sc->sc_dev, "could not alloc microcode memory\n"); 2615 firmware_close(fh); 2616 rt2661_stop(ifp, 1); 2617 return ENOMEM; 2618 } 2619 2620 if (firmware_read(fh, 0, ucode, size) != 0) { 2621 aprint_error_dev(sc->sc_dev, "could not read microcode %s\n", name); 2622 firmware_free(ucode, size); 2623 firmware_close(fh); 2624 rt2661_stop(ifp, 1); 2625 return EIO; 2626 } 2627 2628 if (rt2661_load_microcode(sc, ucode, size) != 0) { 2629 aprint_error_dev(sc->sc_dev, "could not load 8051 microcode\n"); 2630 firmware_free(ucode, size); 2631 firmware_close(fh); 2632 rt2661_stop(ifp, 1); 2633 return EIO; 2634 } 2635 2636 firmware_free(ucode, size); 2637 firmware_close(fh); 2638 sc->sc_flags |= RT2661_FWLOADED; 2639 } 2640 2641 /* initialize Tx rings */ 2642 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2643 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2644 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2645 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2646 2647 /* initialize Mgt ring */ 2648 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2649 2650 /* initialize Rx ring */ 2651 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2652 2653 /* initialize Tx rings sizes */ 2654 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2655 RT2661_TX_RING_COUNT << 24 | 2656 RT2661_TX_RING_COUNT << 16 | 2657 RT2661_TX_RING_COUNT << 8 | 2658 RT2661_TX_RING_COUNT); 2659 2660 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2661 RT2661_TX_DESC_WSIZE << 16 | 2662 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2663 RT2661_MGT_RING_COUNT); 2664 2665 /* initialize Rx rings */ 2666 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2667 RT2661_RX_DESC_BACK << 16 | 2668 RT2661_RX_DESC_WSIZE << 8 | 2669 RT2661_RX_RING_COUNT); 2670 2671 /* XXX: some magic here */ 2672 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2673 2674 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2675 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2676 2677 /* load base address of Rx ring */ 2678 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2679 2680 /* initialize MAC registers to default values */ 2681 for (i = 0; i < N(rt2661_def_mac); i++) 2682 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2683 2684 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2685 rt2661_set_macaddr(sc, ic->ic_myaddr); 2686 2687 /* set host ready */ 2688 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2689 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2690 2691 /* wait for BBP/RF to wakeup */ 2692 for (ntries = 0; ntries < 1000; ntries++) { 2693 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2694 break; 2695 DELAY(1000); 2696 } 2697 if (ntries == 1000) { 2698 printf("timeout waiting for BBP/RF to wakeup\n"); 2699 rt2661_stop(ifp, 1); 2700 return EIO; 2701 } 2702 2703 if (rt2661_bbp_init(sc) != 0) { 2704 rt2661_stop(ifp, 1); 2705 return EIO; 2706 } 2707 2708 /* select default channel */ 2709 sc->sc_curchan = ic->ic_curchan; 2710 rt2661_select_band(sc, sc->sc_curchan); 2711 rt2661_select_antenna(sc); 2712 rt2661_set_chan(sc, sc->sc_curchan); 2713 2714 /* update Rx filter */ 2715 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2716 2717 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2718 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2719 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2720 RT2661_DROP_ACKCTS; 2721 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2722 tmp |= RT2661_DROP_TODS; 2723 if (!(ifp->if_flags & IFF_PROMISC)) 2724 tmp |= RT2661_DROP_NOT_TO_ME; 2725 } 2726 2727 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2728 2729 /* clear STA registers */ 2730 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, star, N(star)); 2731 2732 /* initialize ASIC */ 2733 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2734 2735 /* clear any pending interrupt */ 2736 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2737 2738 /* enable interrupts */ 2739 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2740 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2741 2742 /* kick Rx */ 2743 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2744 2745 ifp->if_flags &= ~IFF_OACTIVE; 2746 ifp->if_flags |= IFF_RUNNING; 2747 2748 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2749 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2750 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2751 } else 2752 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2753 2754 return 0; 2755 #undef N 2756 } 2757 2758 static void 2759 rt2661_stop(struct ifnet *ifp, int disable) 2760 { 2761 struct rt2661_softc *sc = ifp->if_softc; 2762 struct ieee80211com *ic = &sc->sc_ic; 2763 uint32_t tmp; 2764 2765 sc->sc_tx_timer = 0; 2766 ifp->if_timer = 0; 2767 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2768 2769 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2770 2771 /* abort Tx (for all 5 Tx rings) */ 2772 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2773 2774 /* disable Rx (value remains after reset!) */ 2775 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2776 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2777 2778 /* reset ASIC */ 2779 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2780 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2781 2782 /* disable interrupts */ 2783 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2784 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2785 2786 /* clear any pending interrupt */ 2787 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2788 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2789 2790 /* reset Tx and Rx rings */ 2791 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2792 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2793 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2794 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2795 rt2661_reset_tx_ring(sc, &sc->mgtq); 2796 rt2661_reset_rx_ring(sc, &sc->rxq); 2797 2798 /* for CardBus, power down the socket */ 2799 if (disable && sc->sc_disable != NULL) { 2800 if (sc->sc_flags & RT2661_ENABLED) { 2801 (*sc->sc_disable)(sc); 2802 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2803 } 2804 } 2805 } 2806 2807 static int 2808 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2809 { 2810 int ntries; 2811 2812 /* reset 8051 */ 2813 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2814 2815 /* cancel any pending Host to MCU command */ 2816 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2817 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2818 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2819 2820 /* write 8051's microcode */ 2821 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2822 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2823 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2824 2825 /* kick 8051's ass */ 2826 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2827 2828 /* wait for 8051 to initialize */ 2829 for (ntries = 0; ntries < 500; ntries++) { 2830 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2831 break; 2832 DELAY(100); 2833 } 2834 if (ntries == 500) { 2835 printf("timeout waiting for MCU to initialize\n"); 2836 return EIO; 2837 } 2838 return 0; 2839 } 2840 2841 /* 2842 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2843 * false CCA count. This function is called periodically (every seconds) when 2844 * in the RUN state. Values taken from the reference driver. 2845 */ 2846 static void 2847 rt2661_rx_tune(struct rt2661_softc *sc) 2848 { 2849 uint8_t bbp17; 2850 uint16_t cca; 2851 int lo, hi, dbm; 2852 2853 /* 2854 * Tuning range depends on operating band and on the presence of an 2855 * external low-noise amplifier. 2856 */ 2857 lo = 0x20; 2858 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2859 lo += 0x08; 2860 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2861 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2862 lo += 0x10; 2863 hi = lo + 0x20; 2864 2865 dbm = sc->avg_rssi; 2866 /* retrieve false CCA count since last call (clear on read) */ 2867 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2868 2869 DPRINTFN(2, ("RSSI=%ddBm false CCA=%d\n", dbm, cca)); 2870 2871 if (dbm < -74) { 2872 /* very bad RSSI, tune using false CCA count */ 2873 bbp17 = sc->bbp17; /* current value */ 2874 2875 hi -= 2 * (-74 - dbm); 2876 if (hi < lo) 2877 hi = lo; 2878 2879 if (bbp17 > hi) 2880 bbp17 = hi; 2881 else if (cca > 512) 2882 bbp17 = min(bbp17 + 1, hi); 2883 else if (cca < 100) 2884 bbp17 = max(bbp17 - 1, lo); 2885 2886 } else if (dbm < -66) { 2887 bbp17 = lo + 0x08; 2888 } else if (dbm < -58) { 2889 bbp17 = lo + 0x10; 2890 } else if (dbm < -35) { 2891 bbp17 = hi; 2892 } else { /* very good RSSI >= -35dBm */ 2893 bbp17 = 0x60; /* very low sensitivity */ 2894 } 2895 2896 if (bbp17 != sc->bbp17) { 2897 DPRINTF(("BBP17 %x->%x\n", sc->bbp17, bbp17)); 2898 rt2661_bbp_write(sc, 17, bbp17); 2899 sc->bbp17 = bbp17; 2900 } 2901 } 2902 2903 #ifdef notyet 2904 /* 2905 * Enter/Leave radar detection mode. 2906 * This is for 802.11h additional regulatory domains. 2907 */ 2908 static void 2909 rt2661_radar_start(struct rt2661_softc *sc) 2910 { 2911 uint32_t tmp; 2912 2913 /* disable Rx */ 2914 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2915 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2916 2917 rt2661_bbp_write(sc, 82, 0x20); 2918 rt2661_bbp_write(sc, 83, 0x00); 2919 rt2661_bbp_write(sc, 84, 0x40); 2920 2921 /* save current BBP registers values */ 2922 sc->bbp18 = rt2661_bbp_read(sc, 18); 2923 sc->bbp21 = rt2661_bbp_read(sc, 21); 2924 sc->bbp22 = rt2661_bbp_read(sc, 22); 2925 sc->bbp16 = rt2661_bbp_read(sc, 16); 2926 sc->bbp17 = rt2661_bbp_read(sc, 17); 2927 sc->bbp64 = rt2661_bbp_read(sc, 64); 2928 2929 rt2661_bbp_write(sc, 18, 0xff); 2930 rt2661_bbp_write(sc, 21, 0x3f); 2931 rt2661_bbp_write(sc, 22, 0x3f); 2932 rt2661_bbp_write(sc, 16, 0xbd); 2933 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2934 rt2661_bbp_write(sc, 64, 0x21); 2935 2936 /* restore Rx filter */ 2937 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2938 } 2939 2940 static int 2941 rt2661_radar_stop(struct rt2661_softc *sc) 2942 { 2943 uint8_t bbp66; 2944 2945 /* read radar detection result */ 2946 bbp66 = rt2661_bbp_read(sc, 66); 2947 2948 /* restore BBP registers values */ 2949 rt2661_bbp_write(sc, 16, sc->bbp16); 2950 rt2661_bbp_write(sc, 17, sc->bbp17); 2951 rt2661_bbp_write(sc, 18, sc->bbp18); 2952 rt2661_bbp_write(sc, 21, sc->bbp21); 2953 rt2661_bbp_write(sc, 22, sc->bbp22); 2954 rt2661_bbp_write(sc, 64, sc->bbp64); 2955 2956 return bbp66 == 1; 2957 } 2958 #endif 2959 2960 static int 2961 rt2661_prepare_beacon(struct rt2661_softc *sc) 2962 { 2963 struct ieee80211com *ic = &sc->sc_ic; 2964 struct ieee80211_node *ni = ic->ic_bss; 2965 struct rt2661_tx_desc desc; 2966 struct mbuf *m0; 2967 struct ieee80211_beacon_offsets bo; 2968 int rate; 2969 2970 m0 = ieee80211_beacon_alloc(ic, ni, &bo); 2971 if (m0 == NULL) { 2972 aprint_error_dev(sc->sc_dev, "could not allocate beacon frame\n"); 2973 return ENOBUFS; 2974 } 2975 2976 /* send beacons at the lowest available rate */ 2977 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 2978 2979 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2980 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2981 2982 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2983 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2984 2985 /* copy beacon header and payload into NIC memory */ 2986 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2987 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2988 2989 m_freem(m0); 2990 2991 /* 2992 * Store offset of ERP Information Element so that we can update it 2993 * dynamically when the slot time changes. 2994 * XXX: this is ugly since it depends on how net80211 builds beacon 2995 * frames but ieee80211_beacon_alloc() doesn't store offsets for us. 2996 */ 2997 if (ic->ic_curmode == IEEE80211_MODE_11G) { 2998 sc->erp_csr = 2999 RT2661_HW_BEACON_BASE0 + 24 + 3000 sizeof (struct ieee80211_frame) + 3001 8 + 2 + 2 + 2 + ni->ni_esslen + 3002 2 + min(ni->ni_rates.rs_nrates, IEEE80211_RATE_SIZE) + 3003 2 + 1 + 3004 ((ic->ic_opmode == IEEE80211_M_IBSS) ? 4 : 6) + 3005 2; 3006 } 3007 3008 return 0; 3009 } 3010 3011 /* 3012 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 3013 * and HostAP operating modes. 3014 */ 3015 static void 3016 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 3017 { 3018 struct ieee80211com *ic = &sc->sc_ic; 3019 uint32_t tmp; 3020 3021 if (ic->ic_opmode != IEEE80211_M_STA) { 3022 /* 3023 * Change default 16ms TBTT adjustment to 8ms. 3024 * Must be done before enabling beacon generation. 3025 */ 3026 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 3027 } 3028 3029 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 3030 3031 /* set beacon interval (in 1/16ms unit) */ 3032 tmp |= ic->ic_bss->ni_intval * 16; 3033 3034 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 3035 if (ic->ic_opmode == IEEE80211_M_STA) 3036 tmp |= RT2661_TSF_MODE(1); 3037 else 3038 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 3039 3040 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 3041 } 3042 3043 /* 3044 * Retrieve the "Received Signal Strength Indicator" from the raw values 3045 * contained in Rx descriptors. The computation depends on which band the 3046 * frame was received. Correction values taken from the reference driver. 3047 */ 3048 static int 3049 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 3050 { 3051 int lna, agc, rssi; 3052 3053 lna = (raw >> 5) & 0x3; 3054 agc = raw & 0x1f; 3055 3056 rssi = 2 * agc; 3057 3058 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3059 rssi += sc->rssi_2ghz_corr; 3060 3061 if (lna == 1) 3062 rssi -= 64; 3063 else if (lna == 2) 3064 rssi -= 74; 3065 else if (lna == 3) 3066 rssi -= 90; 3067 } else { 3068 rssi += sc->rssi_5ghz_corr; 3069 3070 if (lna == 1) 3071 rssi -= 64; 3072 else if (lna == 2) 3073 rssi -= 86; 3074 else if (lna == 3) 3075 rssi -= 100; 3076 } 3077 return rssi; 3078 } 3079
Indexes created Fri Sep 26 20:09:58 GMT 2025