rt2661.c revision 1.37
1 /* $NetBSD: rt2661.c,v 1.37 2018/05/01 16:18:13 maya Exp $ */ 2 /* $OpenBSD: rt2661.c,v 1.17 2006/05/01 08:41:11 damien Exp $ */ 3 /* $FreeBSD: rt2560.c,v 1.5 2006/06/02 19:59:31 csjp Exp $ */ 4 5 /*- 6 * Copyright (c) 2006 7 * Damien Bergamini <damien.bergamini (at) free.fr> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2661.c,v 1.37 2018/05/01 16:18:13 maya Exp $"); 29 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/callout.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 60 #include <net80211/ieee80211_var.h> 61 #include <net80211/ieee80211_amrr.h> 62 #include <net80211/ieee80211_radiotap.h> 63 64 #include <dev/ic/rt2661reg.h> 65 #include <dev/ic/rt2661var.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/firmload.h> 72 73 #ifdef RAL_DEBUG 74 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 75 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 76 int rt2661_debug = 0; 77 #else 78 #define DPRINTF(x) 79 #define DPRINTFN(n, x) 80 #endif 81 82 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *, int); 84 static void rt2661_reset_tx_ring(struct rt2661_softc *, 85 struct rt2661_tx_ring *); 86 static void rt2661_free_tx_ring(struct rt2661_softc *, 87 struct rt2661_tx_ring *); 88 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *, int); 90 static void rt2661_reset_rx_ring(struct rt2661_softc *, 91 struct rt2661_rx_ring *); 92 static void rt2661_free_rx_ring(struct rt2661_softc *, 93 struct rt2661_rx_ring *); 94 static struct ieee80211_node * 95 rt2661_node_alloc(struct ieee80211_node_table *); 96 static int rt2661_media_change(struct ifnet *); 97 static void rt2661_next_scan(void *); 98 static void rt2661_iter_func(void *, struct ieee80211_node *); 99 static void rt2661_updatestats(void *); 100 static void rt2661_newassoc(struct ieee80211_node *, int); 101 static int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 102 int); 103 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 104 static void rt2661_tx_intr(struct rt2661_softc *); 105 static void rt2661_tx_dma_intr(struct rt2661_softc *, 106 struct rt2661_tx_ring *); 107 static void rt2661_rx_intr(struct rt2661_softc *); 108 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 109 static void rt2661_mcu_wakeup(struct rt2661_softc *); 110 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 111 int rt2661_intr(void *); 112 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 113 static int rt2661_ack_rate(struct ieee80211com *, int); 114 static uint16_t rt2661_txtime(int, int, uint32_t); 115 static uint8_t rt2661_plcp_signal(int); 116 static void rt2661_setup_tx_desc(struct rt2661_softc *, 117 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 118 const bus_dma_segment_t *, int, int); 119 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 120 struct ieee80211_node *); 121 static struct mbuf * 122 rt2661_get_rts(struct rt2661_softc *, 123 struct ieee80211_frame *, uint16_t); 124 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 125 struct ieee80211_node *, int); 126 static void rt2661_start(struct ifnet *); 127 static void rt2661_watchdog(struct ifnet *); 128 static int rt2661_reset(struct ifnet *); 129 static int rt2661_ioctl(struct ifnet *, u_long, void *); 130 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 131 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 132 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 133 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 134 static void rt2661_select_antenna(struct rt2661_softc *); 135 static void rt2661_enable_mrr(struct rt2661_softc *); 136 static void rt2661_set_txpreamble(struct rt2661_softc *); 137 static void rt2661_set_basicrates(struct rt2661_softc *, 138 const struct ieee80211_rateset *); 139 static void rt2661_select_band(struct rt2661_softc *, 140 struct ieee80211_channel *); 141 static void rt2661_set_chan(struct rt2661_softc *, 142 struct ieee80211_channel *); 143 static void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 144 static void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 145 static void rt2661_update_promisc(struct rt2661_softc *); 146 #if 0 147 static int rt2661_wme_update(struct ieee80211com *); 148 #endif 149 150 static void rt2661_updateslot(struct ifnet *); 151 static void rt2661_set_slottime(struct rt2661_softc *); 152 static const char * 153 rt2661_get_rf(int); 154 static void rt2661_read_eeprom(struct rt2661_softc *); 155 static int rt2661_bbp_init(struct rt2661_softc *); 156 static int rt2661_init(struct ifnet *); 157 static void rt2661_stop(struct ifnet *, int); 158 static int rt2661_load_microcode(struct rt2661_softc *, const uint8_t *, 159 int); 160 static void rt2661_rx_tune(struct rt2661_softc *); 161 #ifdef notyet 162 static void rt2661_radar_start(struct rt2661_softc *); 163 static int rt2661_radar_stop(struct rt2661_softc *); 164 #endif 165 static int rt2661_prepare_beacon(struct rt2661_softc *); 166 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 167 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 168 static void rt2661_softintr(void *); 169 170 static const struct { 171 uint32_t reg; 172 uint32_t val; 173 } rt2661_def_mac[] = { 174 RT2661_DEF_MAC 175 }; 176 177 static const struct { 178 uint8_t reg; 179 uint8_t val; 180 } rt2661_def_bbp[] = { 181 RT2661_DEF_BBP 182 }; 183 184 static const struct rfprog { 185 uint8_t chan; 186 uint32_t r1, r2, r3, r4; 187 } rt2661_rf5225_1[] = { 188 RT2661_RF5225_1 189 }, rt2661_rf5225_2[] = { 190 RT2661_RF5225_2 191 }; 192 193 int 194 rt2661_attach(void *xsc, int id) 195 { 196 struct rt2661_softc *sc = xsc; 197 struct ieee80211com *ic = &sc->sc_ic; 198 struct ifnet *ifp = &sc->sc_if; 199 uint32_t val; 200 int error, i, ntries; 201 202 sc->sc_id = id; 203 204 sc->amrr.amrr_min_success_threshold = 1; 205 sc->amrr.amrr_max_success_threshold = 15; 206 callout_init(&sc->scan_ch, 0); 207 callout_init(&sc->amrr_ch, 0); 208 209 /* wait for NIC to initialize */ 210 for (ntries = 0; ntries < 1000; ntries++) { 211 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 212 break; 213 DELAY(1000); 214 } 215 if (ntries == 1000) { 216 aprint_error_dev(sc->sc_dev, "timeout waiting for NIC to initialize\n"); 217 return EIO; 218 } 219 220 /* retrieve RF rev. no and various other things from EEPROM */ 221 rt2661_read_eeprom(sc); 222 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 223 ether_sprintf(ic->ic_myaddr)); 224 225 aprint_normal_dev(sc->sc_dev, "MAC/BBP RT%X, RF %s\n", val, 226 rt2661_get_rf(sc->rf_rev)); 227 228 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rt2661_softintr, sc); 229 if (sc->sc_soft_ih == NULL) { 230 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 231 goto fail0; 232 } 233 234 /* 235 * Allocate Tx and Rx rings. 236 */ 237 error = rt2661_alloc_tx_ring(sc, &sc->txq[0], RT2661_TX_RING_COUNT); 238 if (error != 0) { 239 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 0\n"); 240 goto fail1; 241 } 242 243 error = rt2661_alloc_tx_ring(sc, &sc->txq[1], RT2661_TX_RING_COUNT); 244 if (error != 0) { 245 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 1\n"); 246 goto fail2; 247 } 248 249 error = rt2661_alloc_tx_ring(sc, &sc->txq[2], RT2661_TX_RING_COUNT); 250 if (error != 0) { 251 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 2\n"); 252 goto fail3; 253 } 254 255 error = rt2661_alloc_tx_ring(sc, &sc->txq[3], RT2661_TX_RING_COUNT); 256 if (error != 0) { 257 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 3\n"); 258 goto fail4; 259 } 260 261 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 262 if (error != 0) { 263 aprint_error_dev(sc->sc_dev, "could not allocate Mgt ring\n"); 264 goto fail5; 265 } 266 267 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 268 if (error != 0) { 269 aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n"); 270 goto fail6; 271 } 272 273 ifp->if_softc = sc; 274 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 275 ifp->if_init = rt2661_init; 276 ifp->if_stop = rt2661_stop; 277 ifp->if_ioctl = rt2661_ioctl; 278 ifp->if_start = rt2661_start; 279 ifp->if_watchdog = rt2661_watchdog; 280 IFQ_SET_READY(&ifp->if_snd); 281 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 282 283 ic->ic_ifp = ifp; 284 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 285 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 286 ic->ic_state = IEEE80211_S_INIT; 287 288 /* set device capabilities */ 289 ic->ic_caps = 290 IEEE80211_C_IBSS | /* IBSS mode supported */ 291 IEEE80211_C_MONITOR | /* monitor mode supported */ 292 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 293 IEEE80211_C_TXPMGT | /* tx power management */ 294 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 295 IEEE80211_C_SHSLOT | /* short slot time supported */ 296 IEEE80211_C_WPA; /* 802.11i */ 297 298 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 299 /* set supported .11a rates */ 300 ic->ic_sup_rates[IEEE80211_MODE_11A] = ieee80211_std_rateset_11a; 301 302 /* set supported .11a channels */ 303 for (i = 36; i <= 64; i += 4) { 304 ic->ic_channels[i].ic_freq = 305 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 306 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 307 } 308 for (i = 100; i <= 140; i += 4) { 309 ic->ic_channels[i].ic_freq = 310 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 311 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 312 } 313 for (i = 149; i <= 165; i += 4) { 314 ic->ic_channels[i].ic_freq = 315 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 316 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 317 } 318 } 319 320 /* set supported .11b and .11g rates */ 321 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 322 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 323 324 /* set supported .11b and .11g channels (1 through 14) */ 325 for (i = 1; i <= 14; i++) { 326 ic->ic_channels[i].ic_freq = 327 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 328 ic->ic_channels[i].ic_flags = 329 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 330 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 331 } 332 333 error = if_initialize(ifp); 334 if (error != 0) { 335 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 336 error); 337 goto fail7; 338 } 339 ieee80211_ifattach(ic); 340 /* Use common softint-based if_input */ 341 ifp->if_percpuq = if_percpuq_create(ifp); 342 if_register(ifp); 343 344 ic->ic_node_alloc = rt2661_node_alloc; 345 ic->ic_newassoc = rt2661_newassoc; 346 ic->ic_updateslot = rt2661_updateslot; 347 ic->ic_reset = rt2661_reset; 348 349 /* override state transition machine */ 350 sc->sc_newstate = ic->ic_newstate; 351 ic->ic_newstate = rt2661_newstate; 352 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 353 354 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 355 sizeof(struct ieee80211_frame) + sizeof(sc->sc_txtap), 356 &sc->sc_drvbpf); 357 358 sc->sc_rxtap_len = roundup(sizeof(sc->sc_rxtap), sizeof(u_int32_t)); 359 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 360 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 361 362 sc->sc_txtap_len = roundup(sizeof(sc->sc_txtap), sizeof(u_int32_t)); 363 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 364 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 365 366 ieee80211_announce(ic); 367 368 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 369 pmf_class_network_register(sc->sc_dev, ifp); 370 else 371 aprint_error_dev(sc->sc_dev, 372 "couldn't establish power handler\n"); 373 374 return 0; 375 376 fail7: rt2661_free_rx_ring(sc, &sc->rxq); 377 fail6: rt2661_free_tx_ring(sc, &sc->mgtq); 378 fail5: rt2661_free_tx_ring(sc, &sc->txq[3]); 379 fail4: rt2661_free_tx_ring(sc, &sc->txq[2]); 380 fail3: rt2661_free_tx_ring(sc, &sc->txq[1]); 381 fail2: rt2661_free_tx_ring(sc, &sc->txq[0]); 382 fail1: softint_disestablish(sc->sc_soft_ih); 383 sc->sc_soft_ih = NULL; 384 fail0: return ENXIO; 385 } 386 387 int 388 rt2661_detach(void *xsc) 389 { 390 struct rt2661_softc *sc = xsc; 391 struct ifnet *ifp = &sc->sc_if; 392 393 callout_stop(&sc->scan_ch); 394 callout_stop(&sc->amrr_ch); 395 396 pmf_device_deregister(sc->sc_dev); 397 398 ieee80211_ifdetach(&sc->sc_ic); 399 if_detach(ifp); 400 401 rt2661_free_tx_ring(sc, &sc->txq[0]); 402 rt2661_free_tx_ring(sc, &sc->txq[1]); 403 rt2661_free_tx_ring(sc, &sc->txq[2]); 404 rt2661_free_tx_ring(sc, &sc->txq[3]); 405 rt2661_free_tx_ring(sc, &sc->mgtq); 406 rt2661_free_rx_ring(sc, &sc->rxq); 407 408 if (sc->sc_soft_ih != NULL) { 409 softint_disestablish(sc->sc_soft_ih); 410 sc->sc_soft_ih = NULL; 411 } 412 413 return 0; 414 } 415 416 static int 417 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 418 int count) 419 { 420 int i, nsegs, error; 421 422 ring->count = count; 423 ring->queued = 0; 424 ring->cur = ring->next = ring->stat = 0; 425 426 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 427 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 428 if (error != 0) { 429 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 430 goto fail; 431 } 432 433 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 434 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 435 if (error != 0) { 436 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 437 goto fail; 438 } 439 440 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 441 count * RT2661_TX_DESC_SIZE, (void **)&ring->desc, 442 BUS_DMA_NOWAIT); 443 if (error != 0) { 444 aprint_error_dev(sc->sc_dev, "could not map desc DMA memory\n"); 445 goto fail; 446 } 447 448 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 449 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 450 if (error != 0) { 451 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 452 goto fail; 453 } 454 455 memset(ring->desc, 0, count * RT2661_TX_DESC_SIZE); 456 ring->physaddr = ring->map->dm_segs->ds_addr; 457 458 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 459 M_NOWAIT); 460 if (ring->data == NULL) { 461 aprint_error_dev(sc->sc_dev, "could not allocate soft data\n"); 462 error = ENOMEM; 463 goto fail; 464 } 465 466 memset(ring->data, 0, count * sizeof (struct rt2661_tx_data)); 467 for (i = 0; i < count; i++) { 468 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 469 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 470 &ring->data[i].map); 471 if (error != 0) { 472 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 473 goto fail; 474 } 475 } 476 477 return 0; 478 479 fail: rt2661_free_tx_ring(sc, ring); 480 return error; 481 } 482 483 static void 484 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 485 { 486 struct rt2661_tx_desc *desc; 487 struct rt2661_tx_data *data; 488 int i; 489 490 for (i = 0; i < ring->count; i++) { 491 desc = &ring->desc[i]; 492 data = &ring->data[i]; 493 494 if (data->m != NULL) { 495 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 496 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 497 bus_dmamap_unload(sc->sc_dmat, data->map); 498 m_freem(data->m); 499 data->m = NULL; 500 } 501 502 if (data->ni != NULL) { 503 ieee80211_free_node(data->ni); 504 data->ni = NULL; 505 } 506 507 desc->flags = 0; 508 } 509 510 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 511 BUS_DMASYNC_PREWRITE); 512 513 ring->queued = 0; 514 ring->cur = ring->next = ring->stat = 0; 515 } 516 517 518 static void 519 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 520 { 521 struct rt2661_tx_data *data; 522 int i; 523 524 if (ring->desc != NULL) { 525 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 526 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 527 bus_dmamap_unload(sc->sc_dmat, ring->map); 528 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 529 ring->count * RT2661_TX_DESC_SIZE); 530 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 531 } 532 533 if (ring->data != NULL) { 534 for (i = 0; i < ring->count; i++) { 535 data = &ring->data[i]; 536 537 if (data->m != NULL) { 538 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 539 data->map->dm_mapsize, 540 BUS_DMASYNC_POSTWRITE); 541 bus_dmamap_unload(sc->sc_dmat, data->map); 542 m_freem(data->m); 543 } 544 545 if (data->ni != NULL) 546 ieee80211_free_node(data->ni); 547 548 if (data->map != NULL) 549 bus_dmamap_destroy(sc->sc_dmat, data->map); 550 } 551 free(ring->data, M_DEVBUF); 552 } 553 } 554 555 static int 556 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 557 int count) 558 { 559 struct rt2661_rx_desc *desc; 560 struct rt2661_rx_data *data; 561 int i, nsegs, error; 562 563 ring->count = count; 564 ring->cur = ring->next = 0; 565 566 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 567 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 568 if (error != 0) { 569 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 570 goto fail; 571 } 572 573 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 574 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 575 if (error != 0) { 576 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 577 goto fail; 578 } 579 580 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 581 count * RT2661_RX_DESC_SIZE, (void **)&ring->desc, 582 BUS_DMA_NOWAIT); 583 if (error != 0) { 584 aprint_error_dev(sc->sc_dev, "could not map desc DMA memory\n"); 585 goto fail; 586 } 587 588 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 589 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 590 if (error != 0) { 591 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 592 goto fail; 593 } 594 595 memset(ring->desc, 0, count * RT2661_RX_DESC_SIZE); 596 ring->physaddr = ring->map->dm_segs->ds_addr; 597 598 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 599 M_NOWAIT); 600 if (ring->data == NULL) { 601 aprint_error_dev(sc->sc_dev, "could not allocate soft data\n"); 602 error = ENOMEM; 603 goto fail; 604 } 605 606 /* 607 * Pre-allocate Rx buffers and populate Rx ring. 608 */ 609 memset(ring->data, 0, count * sizeof (struct rt2661_rx_data)); 610 for (i = 0; i < count; i++) { 611 desc = &sc->rxq.desc[i]; 612 data = &sc->rxq.data[i]; 613 614 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 615 0, BUS_DMA_NOWAIT, &data->map); 616 if (error != 0) { 617 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 618 goto fail; 619 } 620 621 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 622 if (data->m == NULL) { 623 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 624 error = ENOMEM; 625 goto fail; 626 } 627 628 MCLGET(data->m, M_DONTWAIT); 629 if (!(data->m->m_flags & M_EXT)) { 630 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 631 error = ENOMEM; 632 goto fail; 633 } 634 635 error = bus_dmamap_load(sc->sc_dmat, data->map, 636 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 637 if (error != 0) { 638 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map"); 639 goto fail; 640 } 641 642 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 643 desc->flags = htole32(RT2661_RX_BUSY); 644 } 645 646 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 647 BUS_DMASYNC_PREWRITE); 648 649 return 0; 650 651 fail: rt2661_free_rx_ring(sc, ring); 652 return error; 653 } 654 655 static void 656 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 657 { 658 int i; 659 660 for (i = 0; i < ring->count; i++) 661 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 662 663 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 664 BUS_DMASYNC_PREWRITE); 665 666 ring->cur = ring->next = 0; 667 } 668 669 static void 670 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 671 { 672 struct rt2661_rx_data *data; 673 int i; 674 675 if (ring->desc != NULL) { 676 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 677 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 678 bus_dmamap_unload(sc->sc_dmat, ring->map); 679 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 680 ring->count * RT2661_RX_DESC_SIZE); 681 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 682 } 683 684 if (ring->data != NULL) { 685 for (i = 0; i < ring->count; i++) { 686 data = &ring->data[i]; 687 688 if (data->m != NULL) { 689 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 690 data->map->dm_mapsize, 691 BUS_DMASYNC_POSTREAD); 692 bus_dmamap_unload(sc->sc_dmat, data->map); 693 m_freem(data->m); 694 } 695 696 if (data->map != NULL) 697 bus_dmamap_destroy(sc->sc_dmat, data->map); 698 } 699 free(ring->data, M_DEVBUF); 700 } 701 } 702 703 static struct ieee80211_node * 704 rt2661_node_alloc(struct ieee80211_node_table *nt) 705 { 706 struct rt2661_node *rn; 707 708 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 709 M_NOWAIT | M_ZERO); 710 711 return (rn != NULL) ? &rn->ni : NULL; 712 } 713 714 static int 715 rt2661_media_change(struct ifnet *ifp) 716 { 717 int error; 718 719 error = ieee80211_media_change(ifp); 720 if (error != ENETRESET) 721 return error; 722 723 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 724 rt2661_init(ifp); 725 726 return 0; 727 } 728 729 /* 730 * This function is called periodically (every 200ms) during scanning to 731 * switch from one channel to another. 732 */ 733 static void 734 rt2661_next_scan(void *arg) 735 { 736 struct rt2661_softc *sc = arg; 737 struct ieee80211com *ic = &sc->sc_ic; 738 int s; 739 740 s = splnet(); 741 if (ic->ic_state == IEEE80211_S_SCAN) 742 ieee80211_next_scan(ic); 743 splx(s); 744 } 745 746 /* 747 * This function is called for each neighbor node. 748 */ 749 static void 750 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 751 { 752 struct rt2661_softc *sc = arg; 753 struct rt2661_node *rn = (struct rt2661_node *)ni; 754 755 ieee80211_amrr_choose(&sc->amrr, ni, &rn->amn); 756 } 757 758 /* 759 * This function is called periodically (every 500ms) in RUN state to update 760 * various settings like rate control statistics or Rx sensitivity. 761 */ 762 static void 763 rt2661_updatestats(void *arg) 764 { 765 struct rt2661_softc *sc = arg; 766 struct ieee80211com *ic = &sc->sc_ic; 767 int s; 768 769 s = splnet(); 770 if (ic->ic_opmode == IEEE80211_M_STA) 771 rt2661_iter_func(sc, ic->ic_bss); 772 else 773 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 774 775 /* update rx sensitivity every 1 sec */ 776 if (++sc->ncalls & 1) 777 rt2661_rx_tune(sc); 778 splx(s); 779 780 callout_reset(&sc->amrr_ch, hz / 2, rt2661_updatestats, sc); 781 } 782 783 static void 784 rt2661_newassoc(struct ieee80211_node *ni, int isnew) 785 { 786 struct rt2661_softc *sc = ni->ni_ic->ic_ifp->if_softc; 787 int i; 788 789 ieee80211_amrr_node_init(&sc->amrr, &((struct rt2661_node *)ni)->amn); 790 791 /* set rate to some reasonable initial value */ 792 for (i = ni->ni_rates.rs_nrates - 1; 793 i > 0 && (ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL) > 72; 794 i--); 795 ni->ni_txrate = i; 796 } 797 798 static int 799 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 800 { 801 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 802 enum ieee80211_state ostate; 803 struct ieee80211_node *ni; 804 uint32_t tmp; 805 806 ostate = ic->ic_state; 807 callout_stop(&sc->scan_ch); 808 809 switch (nstate) { 810 case IEEE80211_S_INIT: 811 callout_stop(&sc->amrr_ch); 812 813 if (ostate == IEEE80211_S_RUN) { 814 /* abort TSF synchronization */ 815 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 816 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 817 } 818 break; 819 820 case IEEE80211_S_SCAN: 821 rt2661_set_chan(sc, ic->ic_curchan); 822 callout_reset(&sc->scan_ch, hz / 5, rt2661_next_scan, sc); 823 break; 824 825 case IEEE80211_S_AUTH: 826 case IEEE80211_S_ASSOC: 827 rt2661_set_chan(sc, ic->ic_curchan); 828 break; 829 830 case IEEE80211_S_RUN: 831 rt2661_set_chan(sc, ic->ic_curchan); 832 833 ni = ic->ic_bss; 834 835 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 836 rt2661_set_slottime(sc); 837 rt2661_enable_mrr(sc); 838 rt2661_set_txpreamble(sc); 839 rt2661_set_basicrates(sc, &ni->ni_rates); 840 rt2661_set_bssid(sc, ni->ni_bssid); 841 } 842 843 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 844 ic->ic_opmode == IEEE80211_M_IBSS) 845 rt2661_prepare_beacon(sc); 846 847 if (ic->ic_opmode == IEEE80211_M_STA) { 848 /* fake a join to init the tx rate */ 849 rt2661_newassoc(ni, 1); 850 } 851 852 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 853 sc->ncalls = 0; 854 sc->avg_rssi = -95; /* reset EMA */ 855 callout_reset(&sc->amrr_ch, hz / 2, 856 rt2661_updatestats, sc); 857 rt2661_enable_tsf_sync(sc); 858 } 859 break; 860 } 861 862 return sc->sc_newstate(ic, nstate, arg); 863 } 864 865 /* 866 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 867 * 93C66). 868 */ 869 static uint16_t 870 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 871 { 872 uint32_t tmp; 873 uint16_t val; 874 int n; 875 876 /* clock C once before the first command */ 877 RT2661_EEPROM_CTL(sc, 0); 878 879 RT2661_EEPROM_CTL(sc, RT2661_S); 880 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 881 RT2661_EEPROM_CTL(sc, RT2661_S); 882 883 /* write start bit (1) */ 884 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 885 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 886 887 /* write READ opcode (10) */ 888 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 889 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 890 RT2661_EEPROM_CTL(sc, RT2661_S); 891 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 892 893 /* write address (A5-A0 or A7-A0) */ 894 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 895 for (; n >= 0; n--) { 896 RT2661_EEPROM_CTL(sc, RT2661_S | 897 (((addr >> n) & 1) << RT2661_SHIFT_D)); 898 RT2661_EEPROM_CTL(sc, RT2661_S | 899 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 900 } 901 902 RT2661_EEPROM_CTL(sc, RT2661_S); 903 904 /* read data Q15-Q0 */ 905 val = 0; 906 for (n = 15; n >= 0; n--) { 907 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 908 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 909 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 910 RT2661_EEPROM_CTL(sc, RT2661_S); 911 } 912 913 RT2661_EEPROM_CTL(sc, 0); 914 915 /* clear Chip Select and clock C */ 916 RT2661_EEPROM_CTL(sc, RT2661_S); 917 RT2661_EEPROM_CTL(sc, 0); 918 RT2661_EEPROM_CTL(sc, RT2661_C); 919 920 return val; 921 } 922 923 static void 924 rt2661_tx_intr(struct rt2661_softc *sc) 925 { 926 struct ifnet *ifp = &sc->sc_if; 927 struct rt2661_tx_ring *txq; 928 struct rt2661_tx_data *data; 929 struct rt2661_node *rn; 930 uint32_t val; 931 int qid, retrycnt, s; 932 933 s = splnet(); 934 935 for (;;) { 936 val = RAL_READ(sc, RT2661_STA_CSR4); 937 if (!(val & RT2661_TX_STAT_VALID)) 938 break; 939 940 /* retrieve the queue in which this frame was sent */ 941 qid = RT2661_TX_QID(val); 942 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 943 944 /* retrieve rate control algorithm context */ 945 data = &txq->data[txq->stat]; 946 rn = (struct rt2661_node *)data->ni; 947 948 /* if no frame has been sent, ignore */ 949 if (rn == NULL) 950 continue; 951 952 switch (RT2661_TX_RESULT(val)) { 953 case RT2661_TX_SUCCESS: 954 retrycnt = RT2661_TX_RETRYCNT(val); 955 956 DPRINTFN(10, ("data frame sent successfully after " 957 "%d retries\n", retrycnt)); 958 rn->amn.amn_txcnt++; 959 if (retrycnt > 0) 960 rn->amn.amn_retrycnt++; 961 ifp->if_opackets++; 962 break; 963 964 case RT2661_TX_RETRY_FAIL: 965 DPRINTFN(9, ("sending data frame failed (too much " 966 "retries)\n")); 967 rn->amn.amn_txcnt++; 968 rn->amn.amn_retrycnt++; 969 ifp->if_oerrors++; 970 break; 971 972 default: 973 /* other failure */ 974 aprint_error_dev(sc->sc_dev, "sending data frame failed 0x%08x\n", val); 975 ifp->if_oerrors++; 976 } 977 978 ieee80211_free_node(data->ni); 979 data->ni = NULL; 980 981 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 982 983 txq->queued--; 984 if (++txq->stat >= txq->count) /* faster than % count */ 985 txq->stat = 0; 986 } 987 988 sc->sc_tx_timer = 0; 989 ifp->if_flags &= ~IFF_OACTIVE; 990 rt2661_start(ifp); /* in softint */ 991 992 splx(s); 993 } 994 995 static void 996 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 997 { 998 struct rt2661_tx_desc *desc; 999 struct rt2661_tx_data *data; 1000 1001 for (;;) { 1002 desc = &txq->desc[txq->next]; 1003 data = &txq->data[txq->next]; 1004 1005 bus_dmamap_sync(sc->sc_dmat, txq->map, 1006 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1007 BUS_DMASYNC_POSTREAD); 1008 1009 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1010 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1011 break; 1012 1013 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1014 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1015 bus_dmamap_unload(sc->sc_dmat, data->map); 1016 m_freem(data->m); 1017 data->m = NULL; 1018 /* node reference is released in rt2661_tx_intr() */ 1019 1020 /* descriptor is no longer valid */ 1021 desc->flags &= ~htole32(RT2661_TX_VALID); 1022 1023 bus_dmamap_sync(sc->sc_dmat, txq->map, 1024 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1025 BUS_DMASYNC_PREWRITE); 1026 1027 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1028 1029 if (++txq->next >= txq->count) /* faster than % count */ 1030 txq->next = 0; 1031 } 1032 } 1033 1034 static void 1035 rt2661_rx_intr(struct rt2661_softc *sc) 1036 { 1037 struct ieee80211com *ic = &sc->sc_ic; 1038 struct ifnet *ifp = &sc->sc_if; 1039 struct rt2661_rx_desc *desc; 1040 struct rt2661_rx_data *data; 1041 struct ieee80211_frame *wh; 1042 struct ieee80211_node *ni; 1043 struct mbuf *mnew, *m; 1044 int error, rssi, s; 1045 1046 for (;;) { 1047 desc = &sc->rxq.desc[sc->rxq.cur]; 1048 data = &sc->rxq.data[sc->rxq.cur]; 1049 1050 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1051 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1052 BUS_DMASYNC_POSTREAD); 1053 1054 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1055 break; 1056 1057 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1058 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1059 /* 1060 * This should not happen since we did not request 1061 * to receive those frames when we filled TXRX_CSR0. 1062 */ 1063 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1064 le32toh(desc->flags))); 1065 ifp->if_ierrors++; 1066 goto skip; 1067 } 1068 1069 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1070 ifp->if_ierrors++; 1071 goto skip; 1072 } 1073 1074 /* 1075 * Try to allocate a new mbuf for this ring element and load it 1076 * before processing the current mbuf. If the ring element 1077 * cannot be loaded, drop the received packet and reuse the old 1078 * mbuf. In the unlikely case that the old mbuf can't be 1079 * reloaded either, explicitly panic. 1080 */ 1081 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1082 if (mnew == NULL) { 1083 ifp->if_ierrors++; 1084 goto skip; 1085 } 1086 1087 MCLGET(mnew, M_DONTWAIT); 1088 if (!(mnew->m_flags & M_EXT)) { 1089 m_freem(mnew); 1090 ifp->if_ierrors++; 1091 goto skip; 1092 } 1093 1094 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1095 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1096 bus_dmamap_unload(sc->sc_dmat, data->map); 1097 1098 error = bus_dmamap_load(sc->sc_dmat, data->map, 1099 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1100 if (error != 0) { 1101 m_freem(mnew); 1102 1103 /* try to reload the old mbuf */ 1104 error = bus_dmamap_load(sc->sc_dmat, data->map, 1105 mtod(data->m, void *), MCLBYTES, NULL, 1106 BUS_DMA_NOWAIT); 1107 if (error != 0) { 1108 /* very unlikely that it will fail... */ 1109 panic("%s: could not load old rx mbuf", 1110 device_xname(sc->sc_dev)); 1111 } 1112 /* physical address may have changed */ 1113 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1114 ifp->if_ierrors++; 1115 goto skip; 1116 } 1117 1118 /* 1119 * New mbuf successfully loaded, update Rx ring and continue 1120 * processing. 1121 */ 1122 m = data->m; 1123 data->m = mnew; 1124 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1125 1126 /* finalize mbuf */ 1127 m_set_rcvif(m, ifp); 1128 m->m_pkthdr.len = m->m_len = 1129 (le32toh(desc->flags) >> 16) & 0xfff; 1130 1131 s = splnet(); 1132 1133 if (sc->sc_drvbpf != NULL) { 1134 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1135 uint32_t tsf_lo, tsf_hi; 1136 1137 /* get timestamp (low and high 32 bits) */ 1138 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1139 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1140 1141 tap->wr_tsf = 1142 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1143 tap->wr_flags = 0; 1144 tap->wr_rate = rt2661_rxrate(desc); 1145 tap->wr_chan_freq = htole16(sc->sc_curchan->ic_freq); 1146 tap->wr_chan_flags = htole16(sc->sc_curchan->ic_flags); 1147 tap->wr_antsignal = desc->rssi; 1148 1149 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1150 } 1151 1152 wh = mtod(m, struct ieee80211_frame *); 1153 ni = ieee80211_find_rxnode(ic, 1154 (struct ieee80211_frame_min *)wh); 1155 1156 /* send the frame to the 802.11 layer */ 1157 ieee80211_input(ic, m, ni, desc->rssi, 0); 1158 1159 /*- 1160 * Keep track of the average RSSI using an Exponential Moving 1161 * Average (EMA) of 8 Wilder's days: 1162 * avg = (1 / N) x rssi + ((N - 1) / N) x avg 1163 */ 1164 rssi = rt2661_get_rssi(sc, desc->rssi); 1165 sc->avg_rssi = (rssi + 7 * sc->avg_rssi) / 8; 1166 1167 /* node is no longer needed */ 1168 ieee80211_free_node(ni); 1169 1170 splx(s); 1171 1172 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1173 1174 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1175 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1176 BUS_DMASYNC_PREWRITE); 1177 1178 DPRINTFN(16, ("rx intr idx=%u\n", sc->rxq.cur)); 1179 1180 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1181 } 1182 1183 /* 1184 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 1185 * without calling if_start(). 1186 */ 1187 s = splnet(); 1188 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 1189 rt2661_start(ifp); 1190 splx(s); 1191 } 1192 1193 /* 1194 * This function is called in HostAP or IBSS modes when it's time to send a 1195 * new beacon (every ni_intval milliseconds). 1196 */ 1197 static void 1198 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1199 { 1200 struct ieee80211com *ic = &sc->sc_ic; 1201 1202 if (sc->sc_flags & RT2661_UPDATE_SLOT) { 1203 sc->sc_flags &= ~RT2661_UPDATE_SLOT; 1204 sc->sc_flags |= RT2661_SET_SLOTTIME; 1205 } else if (sc->sc_flags & RT2661_SET_SLOTTIME) { 1206 sc->sc_flags &= ~RT2661_SET_SLOTTIME; 1207 rt2661_set_slottime(sc); 1208 } 1209 1210 if (ic->ic_curmode == IEEE80211_MODE_11G) { 1211 /* update ERP Information Element */ 1212 RAL_WRITE_1(sc, sc->erp_csr, ic->ic_bss->ni_erp); 1213 RAL_RW_BARRIER_1(sc, sc->erp_csr); 1214 } 1215 1216 DPRINTFN(15, ("beacon expired\n")); 1217 } 1218 1219 static void 1220 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1221 { 1222 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1223 1224 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1225 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1226 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1227 1228 /* send wakeup command to MCU */ 1229 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1230 } 1231 1232 static void 1233 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1234 { 1235 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1236 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1237 } 1238 1239 int 1240 rt2661_intr(void *arg) 1241 { 1242 struct rt2661_softc *sc = arg; 1243 struct ifnet *ifp = &sc->sc_if; 1244 uint32_t r1, r2; 1245 1246 /* don't re-enable interrupts if we're shutting down */ 1247 if (!(ifp->if_flags & IFF_RUNNING)) { 1248 /* disable MAC and MCU interrupts */ 1249 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1250 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1251 return 0; 1252 } 1253 1254 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1255 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1256 1257 if ((r1 & RT2661_INT_CSR_ALL) == 0 && (r2 & RT2661_MCU_INT_ALL) == 0) 1258 return 0; 1259 1260 /* disable interrupts */ 1261 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1262 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1263 1264 softint_schedule(sc->sc_soft_ih); 1265 return 1; 1266 } 1267 1268 static void 1269 rt2661_softintr(void *arg) 1270 { 1271 struct rt2661_softc *sc = arg; 1272 uint32_t r1, r2; 1273 1274 for (;;) { 1275 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1276 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1277 1278 if ((r1 & RT2661_INT_CSR_ALL) == 0 && 1279 (r2 & RT2661_MCU_INT_ALL) == 0) 1280 break; 1281 1282 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1283 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1284 1285 if (r1 & RT2661_MGT_DONE) 1286 rt2661_tx_dma_intr(sc, &sc->mgtq); 1287 1288 if (r1 & RT2661_RX_DONE) 1289 rt2661_rx_intr(sc); 1290 1291 if (r1 & RT2661_TX0_DMA_DONE) 1292 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1293 1294 if (r1 & RT2661_TX1_DMA_DONE) 1295 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1296 1297 if (r1 & RT2661_TX2_DMA_DONE) 1298 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1299 1300 if (r1 & RT2661_TX3_DMA_DONE) 1301 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1302 1303 if (r1 & RT2661_TX_DONE) 1304 rt2661_tx_intr(sc); 1305 1306 if (r2 & RT2661_MCU_CMD_DONE) 1307 rt2661_mcu_cmd_intr(sc); 1308 1309 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1310 rt2661_mcu_beacon_expire(sc); 1311 1312 if (r2 & RT2661_MCU_WAKEUP) 1313 rt2661_mcu_wakeup(sc); 1314 } 1315 1316 /* enable interrupts */ 1317 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1318 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1319 } 1320 1321 /* quickly determine if a given rate is CCK or OFDM */ 1322 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1323 1324 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1325 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1326 1327 /* 1328 * This function is only used by the Rx radiotap code. It returns the rate at 1329 * which a given frame was received. 1330 */ 1331 static uint8_t 1332 rt2661_rxrate(struct rt2661_rx_desc *desc) 1333 { 1334 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1335 /* reverse function of rt2661_plcp_signal */ 1336 switch (desc->rate & 0xf) { 1337 case 0xb: return 12; 1338 case 0xf: return 18; 1339 case 0xa: return 24; 1340 case 0xe: return 36; 1341 case 0x9: return 48; 1342 case 0xd: return 72; 1343 case 0x8: return 96; 1344 case 0xc: return 108; 1345 } 1346 } else { 1347 if (desc->rate == 10) 1348 return 2; 1349 if (desc->rate == 20) 1350 return 4; 1351 if (desc->rate == 55) 1352 return 11; 1353 if (desc->rate == 110) 1354 return 22; 1355 } 1356 return 2; /* should not get there */ 1357 } 1358 1359 /* 1360 * Return the expected ack rate for a frame transmitted at rate `rate'. 1361 * XXX: this should depend on the destination node basic rate set. 1362 */ 1363 static int 1364 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1365 { 1366 switch (rate) { 1367 /* CCK rates */ 1368 case 2: 1369 return 2; 1370 case 4: 1371 case 11: 1372 case 22: 1373 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1374 1375 /* OFDM rates */ 1376 case 12: 1377 case 18: 1378 return 12; 1379 case 24: 1380 case 36: 1381 return 24; 1382 case 48: 1383 case 72: 1384 case 96: 1385 case 108: 1386 return 48; 1387 } 1388 1389 /* default to 1Mbps */ 1390 return 2; 1391 } 1392 1393 /* 1394 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1395 * The function automatically determines the operating mode depending on the 1396 * given rate. `flags' indicates whether short preamble is in use or not. 1397 */ 1398 static uint16_t 1399 rt2661_txtime(int len, int rate, uint32_t flags) 1400 { 1401 uint16_t txtime; 1402 1403 if (RAL_RATE_IS_OFDM(rate)) { 1404 /* IEEE Std 802.11g-2003, pp. 44 */ 1405 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1406 txtime = 16 + 4 + 4 * txtime + 6; 1407 } else { 1408 /* IEEE Std 802.11b-1999, pp. 28 */ 1409 txtime = (16 * len + rate - 1) / rate; 1410 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1411 txtime += 72 + 24; 1412 else 1413 txtime += 144 + 48; 1414 } 1415 return txtime; 1416 } 1417 1418 static uint8_t 1419 rt2661_plcp_signal(int rate) 1420 { 1421 switch (rate) { 1422 /* CCK rates (returned values are device-dependent) */ 1423 case 2: return 0x0; 1424 case 4: return 0x1; 1425 case 11: return 0x2; 1426 case 22: return 0x3; 1427 1428 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1429 case 12: return 0xb; 1430 case 18: return 0xf; 1431 case 24: return 0xa; 1432 case 36: return 0xe; 1433 case 48: return 0x9; 1434 case 72: return 0xd; 1435 case 96: return 0x8; 1436 case 108: return 0xc; 1437 1438 /* unsupported rates (should not get there) */ 1439 default: return 0xff; 1440 } 1441 } 1442 1443 static void 1444 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1445 uint32_t flags, uint16_t xflags, int len, int rate, 1446 const bus_dma_segment_t *segs, int nsegs, int ac) 1447 { 1448 struct ieee80211com *ic = &sc->sc_ic; 1449 uint16_t plcp_length; 1450 int i, remainder; 1451 1452 desc->flags = htole32(flags); 1453 desc->flags |= htole32(len << 16); 1454 1455 desc->xflags = htole16(xflags); 1456 desc->xflags |= htole16(nsegs << 13); 1457 1458 desc->wme = htole16( 1459 RT2661_QID(ac) | 1460 RT2661_AIFSN(2) | 1461 RT2661_LOGCWMIN(4) | 1462 RT2661_LOGCWMAX(10)); 1463 1464 /* 1465 * Remember in which queue this frame was sent. This field is driver 1466 * private data only. It will be made available by the NIC in STA_CSR4 1467 * on Tx interrupts. 1468 */ 1469 desc->qid = ac; 1470 1471 /* setup PLCP fields */ 1472 desc->plcp_signal = rt2661_plcp_signal(rate); 1473 desc->plcp_service = 4; 1474 1475 len += IEEE80211_CRC_LEN; 1476 if (RAL_RATE_IS_OFDM(rate)) { 1477 desc->flags |= htole32(RT2661_TX_OFDM); 1478 1479 plcp_length = len & 0xfff; 1480 desc->plcp_length_hi = plcp_length >> 6; 1481 desc->plcp_length_lo = plcp_length & 0x3f; 1482 } else { 1483 plcp_length = (16 * len + rate - 1) / rate; 1484 if (rate == 22) { 1485 remainder = (16 * len) % 22; 1486 if (remainder != 0 && remainder < 7) 1487 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1488 } 1489 desc->plcp_length_hi = plcp_length >> 8; 1490 desc->plcp_length_lo = plcp_length & 0xff; 1491 1492 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1493 desc->plcp_signal |= 0x08; 1494 } 1495 1496 /* RT2x61 supports scatter with up to 5 segments */ 1497 for (i = 0; i < nsegs; i++) { 1498 desc->addr[i] = htole32(segs[i].ds_addr); 1499 desc->len [i] = htole16(segs[i].ds_len); 1500 } 1501 1502 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1503 } 1504 1505 static int 1506 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1507 struct ieee80211_node *ni) 1508 { 1509 struct ieee80211com *ic = &sc->sc_ic; 1510 struct rt2661_tx_desc *desc; 1511 struct rt2661_tx_data *data; 1512 struct ieee80211_frame *wh; 1513 uint16_t dur; 1514 uint32_t flags = 0; 1515 int rate, error; 1516 1517 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1518 data = &sc->mgtq.data[sc->mgtq.cur]; 1519 1520 /* send mgt frames at the lowest available rate */ 1521 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1522 1523 wh = mtod(m0, struct ieee80211_frame *); 1524 1525 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1526 if (ieee80211_crypto_encap(ic, ni, m0) == NULL) { 1527 m_freem(m0); 1528 return ENOBUFS; 1529 } 1530 1531 /* packet header may have moved, reset our local pointer */ 1532 wh = mtod(m0, struct ieee80211_frame *); 1533 } 1534 1535 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1536 BUS_DMA_NOWAIT); 1537 if (error != 0) { 1538 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1539 error); 1540 m_freem(m0); 1541 return error; 1542 } 1543 1544 if (sc->sc_drvbpf != NULL) { 1545 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1546 1547 tap->wt_flags = 0; 1548 tap->wt_rate = rate; 1549 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1550 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1551 1552 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1553 } 1554 1555 data->m = m0; 1556 data->ni = ni; 1557 1558 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1559 flags |= RT2661_TX_NEED_ACK; 1560 1561 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1562 sc->sifs; 1563 *(uint16_t *)wh->i_dur = htole16(dur); 1564 1565 /* tell hardware to set timestamp in probe responses */ 1566 if ((wh->i_fc[0] & 1567 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1568 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1569 flags |= RT2661_TX_TIMESTAMP; 1570 } 1571 1572 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1573 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1574 RT2661_QID_MGT); 1575 1576 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1577 BUS_DMASYNC_PREWRITE); 1578 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1579 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1580 BUS_DMASYNC_PREWRITE); 1581 1582 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1583 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1584 1585 /* kick mgt */ 1586 sc->mgtq.queued++; 1587 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1588 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1589 1590 return 0; 1591 } 1592 1593 /* 1594 * Build a RTS control frame. 1595 */ 1596 static struct mbuf * 1597 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1598 uint16_t dur) 1599 { 1600 struct ieee80211_frame_rts *rts; 1601 struct mbuf *m; 1602 1603 MGETHDR(m, M_DONTWAIT, MT_DATA); 1604 if (m == NULL) { 1605 sc->sc_ic.ic_stats.is_tx_nobuf++; 1606 aprint_error_dev(sc->sc_dev, "could not allocate RTS frame\n"); 1607 return NULL; 1608 } 1609 1610 rts = mtod(m, struct ieee80211_frame_rts *); 1611 1612 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1613 IEEE80211_FC0_SUBTYPE_RTS; 1614 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1615 *(uint16_t *)rts->i_dur = htole16(dur); 1616 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1617 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1618 1619 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1620 1621 return m; 1622 } 1623 1624 static int 1625 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1626 struct ieee80211_node *ni, int ac) 1627 { 1628 struct ieee80211com *ic = &sc->sc_ic; 1629 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1630 struct rt2661_tx_desc *desc; 1631 struct rt2661_tx_data *data; 1632 struct ieee80211_frame *wh; 1633 struct ieee80211_key *k; 1634 struct mbuf *mnew; 1635 uint16_t dur; 1636 uint32_t flags = 0; 1637 int rate, useprot, error, tid; 1638 1639 wh = mtod(m0, struct ieee80211_frame *); 1640 1641 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1642 rate = ic->ic_sup_rates[ic->ic_curmode]. 1643 rs_rates[ic->ic_fixed_rate]; 1644 } else 1645 rate = ni->ni_rates.rs_rates[ni->ni_txrate]; 1646 rate &= IEEE80211_RATE_VAL; 1647 if (rate == 0) 1648 rate = 2; /* XXX should not happen */ 1649 1650 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1651 k = ieee80211_crypto_encap(ic, ni, m0); 1652 if (k == NULL) { 1653 m_freem(m0); 1654 return ENOBUFS; 1655 } 1656 1657 /* packet header may have moved, reset our local pointer */ 1658 wh = mtod(m0, struct ieee80211_frame *); 1659 } 1660 1661 /* 1662 * Packet Bursting: backoff after ppb=8 frames to give other STAs a 1663 * chance to contend for the wireless medium. 1664 */ 1665 tid = WME_AC_TO_TID(M_WME_GETAC(m0)); 1666 if (ic->ic_opmode == IEEE80211_M_STA && (ni->ni_txseqs[tid] & 7)) 1667 flags |= RT2661_TX_IFS_SIFS; 1668 1669 /* 1670 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1671 * for directed frames only when the length of the MPDU is greater 1672 * than the length threshold indicated by" ic_rtsthreshold. 1673 * 1674 * IEEE Std 802.11-2003g, pp 13: "ERP STAs shall use protection 1675 * mechanism (such as RTS/CTS or CTS-to-self) for ERP-OFDM MPDUs of 1676 * type Data or an MMPDU". 1677 */ 1678 useprot = !IEEE80211_IS_MULTICAST(wh->i_addr1) && 1679 (m0->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1680 ((ic->ic_flags & IEEE80211_F_USEPROT) && RAL_RATE_IS_OFDM(rate))); 1681 if (useprot) { 1682 struct mbuf *m; 1683 int rtsrate, ackrate; 1684 1685 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1686 ackrate = rt2661_ack_rate(ic, rate); 1687 1688 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1689 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1690 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1691 3 * sc->sifs; 1692 1693 m = rt2661_get_rts(sc, wh, dur); 1694 if (m == NULL) { 1695 aprint_error_dev(sc->sc_dev, "could not allocate RTS " 1696 "frame\n"); 1697 m_freem(m0); 1698 return ENOBUFS; 1699 } 1700 1701 desc = &txq->desc[txq->cur]; 1702 data = &txq->data[txq->cur]; 1703 1704 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1705 BUS_DMA_NOWAIT); 1706 if (error != 0) { 1707 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1708 m_freem(m); 1709 m_freem(m0); 1710 return error; 1711 } 1712 1713 /* avoid multiple free() of the same node for each fragment */ 1714 ieee80211_ref_node(ni); 1715 1716 data->m = m; 1717 data->ni = ni; 1718 1719 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1720 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, 1721 data->map->dm_segs, data->map->dm_nsegs, ac); 1722 1723 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1724 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1725 bus_dmamap_sync(sc->sc_dmat, txq->map, 1726 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1727 BUS_DMASYNC_PREWRITE); 1728 1729 txq->queued++; 1730 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1731 1732 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS_SIFS; 1733 } 1734 1735 data = &txq->data[txq->cur]; 1736 desc = &txq->desc[txq->cur]; 1737 1738 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1739 BUS_DMA_NOWAIT); 1740 if (error != 0 && error != EFBIG) { 1741 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1742 error); 1743 m_freem(m0); 1744 return error; 1745 } 1746 if (error != 0) { 1747 /* too many fragments, linearize */ 1748 1749 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1750 if (mnew == NULL) { 1751 m_freem(m0); 1752 return ENOMEM; 1753 } 1754 1755 M_COPY_PKTHDR(mnew, m0); 1756 if (m0->m_pkthdr.len > MHLEN) { 1757 MCLGET(mnew, M_DONTWAIT); 1758 if (!(mnew->m_flags & M_EXT)) { 1759 m_freem(m0); 1760 m_freem(mnew); 1761 return ENOMEM; 1762 } 1763 } 1764 1765 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1766 m_freem(m0); 1767 mnew->m_len = mnew->m_pkthdr.len; 1768 m0 = mnew; 1769 1770 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1771 BUS_DMA_NOWAIT); 1772 if (error != 0) { 1773 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1774 m_freem(m0); 1775 return error; 1776 } 1777 1778 /* packet header have moved, reset our local pointer */ 1779 wh = mtod(m0, struct ieee80211_frame *); 1780 } 1781 1782 if (sc->sc_drvbpf != NULL) { 1783 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1784 1785 tap->wt_flags = 0; 1786 tap->wt_rate = rate; 1787 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1788 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1789 1790 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1791 } 1792 1793 data->m = m0; 1794 data->ni = ni; 1795 1796 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1797 flags |= RT2661_TX_NEED_ACK; 1798 1799 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1800 ic->ic_flags) + sc->sifs; 1801 *(uint16_t *)wh->i_dur = htole16(dur); 1802 } 1803 1804 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1805 data->map->dm_segs, data->map->dm_nsegs, ac); 1806 1807 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1808 BUS_DMASYNC_PREWRITE); 1809 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1810 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1811 1812 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1813 m0->m_pkthdr.len, txq->cur, rate)); 1814 1815 /* kick Tx */ 1816 txq->queued++; 1817 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1818 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1819 1820 return 0; 1821 } 1822 1823 static void 1824 rt2661_start(struct ifnet *ifp) 1825 { 1826 struct rt2661_softc *sc = ifp->if_softc; 1827 struct ieee80211com *ic = &sc->sc_ic; 1828 struct mbuf *m0; 1829 struct ether_header *eh; 1830 struct ieee80211_node *ni = NULL; 1831 1832 /* 1833 * net80211 may still try to send management frames even if the 1834 * IFF_RUNNING flag is not set... 1835 */ 1836 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1837 return; 1838 1839 for (;;) { 1840 IF_POLL(&ic->ic_mgtq, m0); 1841 if (m0 != NULL) { 1842 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1843 ifp->if_flags |= IFF_OACTIVE; 1844 break; 1845 } 1846 IF_DEQUEUE(&ic->ic_mgtq, m0); 1847 if (m0 == NULL) 1848 break; 1849 1850 ni = M_GETCTX(m0, struct ieee80211_node *); 1851 M_CLEARCTX(m0); 1852 bpf_mtap3(ic->ic_rawbpf, m0); 1853 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1854 break; 1855 1856 } else { 1857 IF_POLL(&ifp->if_snd, m0); 1858 if (m0 == NULL || ic->ic_state != IEEE80211_S_RUN) 1859 break; 1860 1861 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1862 /* there is no place left in this ring */ 1863 ifp->if_flags |= IFF_OACTIVE; 1864 break; 1865 } 1866 1867 IFQ_DEQUEUE(&ifp->if_snd, m0); 1868 1869 if (m0->m_len < sizeof (struct ether_header) && 1870 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1871 continue; 1872 1873 eh = mtod(m0, struct ether_header *); 1874 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1875 if (ni == NULL) { 1876 m_freem(m0); 1877 ifp->if_oerrors++; 1878 continue; 1879 } 1880 1881 bpf_mtap3(ifp->if_bpf, m0); 1882 m0 = ieee80211_encap(ic, m0, ni); 1883 if (m0 == NULL) { 1884 ieee80211_free_node(ni); 1885 ifp->if_oerrors++; 1886 continue; 1887 } 1888 bpf_mtap3(ic->ic_rawbpf, m0); 1889 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1890 if (ni != NULL) 1891 ieee80211_free_node(ni); 1892 ifp->if_oerrors++; 1893 break; 1894 } 1895 } 1896 1897 sc->sc_tx_timer = 5; 1898 ifp->if_timer = 1; 1899 } 1900 } 1901 1902 static void 1903 rt2661_watchdog(struct ifnet *ifp) 1904 { 1905 struct rt2661_softc *sc = ifp->if_softc; 1906 1907 ifp->if_timer = 0; 1908 1909 if (sc->sc_tx_timer > 0) { 1910 if (--sc->sc_tx_timer == 0) { 1911 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1912 rt2661_init(ifp); 1913 ifp->if_oerrors++; 1914 return; 1915 } 1916 ifp->if_timer = 1; 1917 } 1918 1919 ieee80211_watchdog(&sc->sc_ic); 1920 } 1921 1922 /* 1923 * This function allows for fast channel switching in monitor mode (used by 1924 * kismet). In IBSS mode, we must explicitly reset the interface to 1925 * generate a new beacon frame. 1926 */ 1927 static int 1928 rt2661_reset(struct ifnet *ifp) 1929 { 1930 struct rt2661_softc *sc = ifp->if_softc; 1931 struct ieee80211com *ic = &sc->sc_ic; 1932 1933 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1934 return ENETRESET; 1935 1936 rt2661_set_chan(sc, ic->ic_curchan); 1937 1938 return 0; 1939 } 1940 1941 static int 1942 rt2661_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1943 { 1944 struct rt2661_softc *sc = ifp->if_softc; 1945 struct ieee80211com *ic = &sc->sc_ic; 1946 int s, error = 0; 1947 1948 s = splnet(); 1949 1950 switch (cmd) { 1951 case SIOCSIFFLAGS: 1952 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1953 break; 1954 if (ifp->if_flags & IFF_UP) { 1955 if (ifp->if_flags & IFF_RUNNING) 1956 rt2661_update_promisc(sc); 1957 else 1958 rt2661_init(ifp); 1959 } else { 1960 if (ifp->if_flags & IFF_RUNNING) 1961 rt2661_stop(ifp, 1); 1962 } 1963 break; 1964 1965 case SIOCADDMULTI: 1966 case SIOCDELMULTI: 1967 /* XXX no h/w multicast filter? --dyoung */ 1968 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 1969 error = 0; 1970 break; 1971 1972 case SIOCS80211CHANNEL: 1973 /* 1974 * This allows for fast channel switching in monitor mode 1975 * (used by kismet). In IBSS mode, we must explicitly reset 1976 * the interface to generate a new beacon frame. 1977 */ 1978 error = ieee80211_ioctl(ic, cmd, data); 1979 if (error == ENETRESET && 1980 ic->ic_opmode == IEEE80211_M_MONITOR) { 1981 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1982 (IFF_UP | IFF_RUNNING)) 1983 rt2661_set_chan(sc, ic->ic_ibss_chan); 1984 error = 0; 1985 } 1986 break; 1987 1988 default: 1989 error = ieee80211_ioctl(ic, cmd, data); 1990 1991 } 1992 1993 if (error == ENETRESET) { 1994 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1995 (IFF_UP | IFF_RUNNING)) 1996 rt2661_init(ifp); 1997 error = 0; 1998 } 1999 2000 splx(s); 2001 2002 return error; 2003 } 2004 2005 static void 2006 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 2007 { 2008 uint32_t tmp; 2009 int ntries; 2010 2011 for (ntries = 0; ntries < 100; ntries++) { 2012 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2013 break; 2014 DELAY(1); 2015 } 2016 if (ntries == 100) { 2017 aprint_error_dev(sc->sc_dev, "could not write to BBP\n"); 2018 return; 2019 } 2020 2021 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 2022 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 2023 2024 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 2025 } 2026 2027 static uint8_t 2028 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2029 { 2030 uint32_t val; 2031 int ntries; 2032 2033 for (ntries = 0; ntries < 100; ntries++) { 2034 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2035 break; 2036 DELAY(1); 2037 } 2038 if (ntries == 100) { 2039 aprint_error_dev(sc->sc_dev, "could not read from BBP\n"); 2040 return 0; 2041 } 2042 2043 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2044 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2045 2046 for (ntries = 0; ntries < 100; ntries++) { 2047 val = RAL_READ(sc, RT2661_PHY_CSR3); 2048 if (!(val & RT2661_BBP_BUSY)) 2049 return val & 0xff; 2050 DELAY(1); 2051 } 2052 2053 aprint_error_dev(sc->sc_dev, "could not read from BBP\n"); 2054 return 0; 2055 } 2056 2057 static void 2058 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2059 { 2060 uint32_t tmp; 2061 int ntries; 2062 2063 for (ntries = 0; ntries < 100; ntries++) { 2064 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2065 break; 2066 DELAY(1); 2067 } 2068 if (ntries == 100) { 2069 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2070 return; 2071 } 2072 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2073 (reg & 3); 2074 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2075 2076 /* remember last written value in sc */ 2077 sc->rf_regs[reg] = val; 2078 2079 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2080 } 2081 2082 static int 2083 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2084 { 2085 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2086 return EIO; /* there is already a command pending */ 2087 2088 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2089 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2090 2091 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2092 2093 return 0; 2094 } 2095 2096 static void 2097 rt2661_select_antenna(struct rt2661_softc *sc) 2098 { 2099 uint8_t bbp4, bbp77; 2100 uint32_t tmp; 2101 2102 bbp4 = rt2661_bbp_read(sc, 4); 2103 bbp77 = rt2661_bbp_read(sc, 77); 2104 2105 /* TBD */ 2106 2107 /* make sure Rx is disabled before switching antenna */ 2108 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2109 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2110 2111 rt2661_bbp_write(sc, 4, bbp4); 2112 rt2661_bbp_write(sc, 77, bbp77); 2113 2114 /* restore Rx filter */ 2115 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2116 } 2117 2118 /* 2119 * Enable multi-rate retries for frames sent at OFDM rates. 2120 * In 802.11b/g mode, allow fallback to CCK rates. 2121 */ 2122 static void 2123 rt2661_enable_mrr(struct rt2661_softc *sc) 2124 { 2125 struct ieee80211com *ic = &sc->sc_ic; 2126 uint32_t tmp; 2127 2128 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2129 2130 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2131 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2132 tmp |= RT2661_MRR_CCK_FALLBACK; 2133 tmp |= RT2661_MRR_ENABLED; 2134 2135 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2136 } 2137 2138 static void 2139 rt2661_set_txpreamble(struct rt2661_softc *sc) 2140 { 2141 uint32_t tmp; 2142 2143 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2144 2145 tmp &= ~RT2661_SHORT_PREAMBLE; 2146 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2147 tmp |= RT2661_SHORT_PREAMBLE; 2148 2149 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2150 } 2151 2152 static void 2153 rt2661_set_basicrates(struct rt2661_softc *sc, 2154 const struct ieee80211_rateset *rs) 2155 { 2156 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2157 uint32_t mask = 0; 2158 uint8_t rate; 2159 int i, j; 2160 2161 for (i = 0; i < rs->rs_nrates; i++) { 2162 rate = rs->rs_rates[i]; 2163 2164 if (!(rate & IEEE80211_RATE_BASIC)) 2165 continue; 2166 2167 /* 2168 * Find h/w rate index. We know it exists because the rate 2169 * set has already been negotiated. 2170 */ 2171 for (j = 0; ieee80211_std_rateset_11g.rs_rates[j] != RV(rate); j++); 2172 2173 mask |= 1 << j; 2174 } 2175 2176 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2177 2178 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2179 #undef RV 2180 } 2181 2182 /* 2183 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2184 * driver. 2185 */ 2186 static void 2187 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2188 { 2189 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2190 uint32_t tmp; 2191 2192 /* update all BBP registers that depend on the band */ 2193 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2194 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2195 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2196 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2197 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2198 } 2199 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2200 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2201 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2202 } 2203 2204 sc->bbp17 = bbp17; 2205 rt2661_bbp_write(sc, 17, bbp17); 2206 rt2661_bbp_write(sc, 96, bbp96); 2207 rt2661_bbp_write(sc, 104, bbp104); 2208 2209 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2210 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2211 rt2661_bbp_write(sc, 75, 0x80); 2212 rt2661_bbp_write(sc, 86, 0x80); 2213 rt2661_bbp_write(sc, 88, 0x80); 2214 } 2215 2216 rt2661_bbp_write(sc, 35, bbp35); 2217 rt2661_bbp_write(sc, 97, bbp97); 2218 rt2661_bbp_write(sc, 98, bbp98); 2219 2220 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2221 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2222 if (IEEE80211_IS_CHAN_2GHZ(c)) 2223 tmp |= RT2661_PA_PE_2GHZ; 2224 else 2225 tmp |= RT2661_PA_PE_5GHZ; 2226 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2227 2228 /* 802.11a uses a 16 microseconds short interframe space */ 2229 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10; 2230 } 2231 2232 static void 2233 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2234 { 2235 struct ieee80211com *ic = &sc->sc_ic; 2236 const struct rfprog *rfprog; 2237 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2238 int8_t power; 2239 u_int i, chan; 2240 2241 chan = ieee80211_chan2ieee(ic, c); 2242 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2243 return; 2244 2245 /* select the appropriate RF settings based on what EEPROM says */ 2246 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2247 2248 /* find the settings for this channel (we know it exists) */ 2249 for (i = 0; rfprog[i].chan != chan; i++); 2250 2251 power = sc->txpow[i]; 2252 if (power < 0) { 2253 bbp94 += power; 2254 power = 0; 2255 } else if (power > 31) { 2256 bbp94 += power - 31; 2257 power = 31; 2258 } 2259 2260 /* 2261 * If we've yet to select a channel, or we are switching from the 2262 * 2GHz band to the 5GHz band or vice-versa, BBP registers need to 2263 * be reprogrammed. 2264 */ 2265 if (sc->sc_curchan == NULL || c->ic_flags != sc->sc_curchan->ic_flags) { 2266 rt2661_select_band(sc, c); 2267 rt2661_select_antenna(sc); 2268 } 2269 sc->sc_curchan = c; 2270 2271 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2272 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2273 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2274 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2275 2276 DELAY(200); 2277 2278 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2279 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2280 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2281 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2282 2283 DELAY(200); 2284 2285 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2286 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2287 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2288 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2289 2290 /* enable smart mode for MIMO-capable RFs */ 2291 bbp3 = rt2661_bbp_read(sc, 3); 2292 2293 bbp3 &= ~RT2661_SMART_MODE; 2294 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2295 bbp3 |= RT2661_SMART_MODE; 2296 2297 rt2661_bbp_write(sc, 3, bbp3); 2298 2299 if (bbp94 != RT2661_BBPR94_DEFAULT) 2300 rt2661_bbp_write(sc, 94, bbp94); 2301 2302 /* 5GHz radio needs a 1ms delay here */ 2303 if (IEEE80211_IS_CHAN_5GHZ(c)) 2304 DELAY(1000); 2305 } 2306 2307 static void 2308 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2309 { 2310 uint32_t tmp; 2311 2312 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2313 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2314 2315 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2316 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2317 } 2318 2319 static void 2320 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2321 { 2322 uint32_t tmp; 2323 2324 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2325 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2326 2327 tmp = addr[4] | addr[5] << 8 | 0xff << 16; 2328 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2329 } 2330 2331 static void 2332 rt2661_update_promisc(struct rt2661_softc *sc) 2333 { 2334 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2335 uint32_t tmp; 2336 2337 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2338 2339 tmp &= ~RT2661_DROP_NOT_TO_ME; 2340 if (!(ifp->if_flags & IFF_PROMISC)) 2341 tmp |= RT2661_DROP_NOT_TO_ME; 2342 2343 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2344 2345 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2346 "entering" : "leaving")); 2347 } 2348 2349 #if 0 2350 /* 2351 * Update QoS (802.11e) settings for each h/w Tx ring. 2352 */ 2353 static int 2354 rt2661_wme_update(struct ieee80211com *ic) 2355 { 2356 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2357 const struct wmeParams *wmep; 2358 2359 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2360 2361 /* XXX: not sure about shifts. */ 2362 /* XXX: the reference driver plays with AC_VI settings too. */ 2363 2364 /* update TxOp */ 2365 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2366 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2367 wmep[WME_AC_BK].wmep_txopLimit); 2368 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2369 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2370 wmep[WME_AC_VO].wmep_txopLimit); 2371 2372 /* update CWmin */ 2373 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2374 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2375 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2376 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2377 wmep[WME_AC_VO].wmep_logcwmin); 2378 2379 /* update CWmax */ 2380 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2381 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2382 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2383 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2384 wmep[WME_AC_VO].wmep_logcwmax); 2385 2386 /* update Aifsn */ 2387 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2388 wmep[WME_AC_BE].wmep_aifsn << 12 | 2389 wmep[WME_AC_BK].wmep_aifsn << 8 | 2390 wmep[WME_AC_VI].wmep_aifsn << 4 | 2391 wmep[WME_AC_VO].wmep_aifsn); 2392 2393 return 0; 2394 } 2395 #endif 2396 2397 static void 2398 rt2661_updateslot(struct ifnet *ifp) 2399 { 2400 struct rt2661_softc *sc = ifp->if_softc; 2401 struct ieee80211com *ic = &sc->sc_ic; 2402 2403 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2404 /* 2405 * In HostAP mode, we defer setting of new slot time until 2406 * updated ERP Information Element has propagated to all 2407 * associated STAs. 2408 */ 2409 sc->sc_flags |= RT2661_UPDATE_SLOT; 2410 } else 2411 rt2661_set_slottime(sc); 2412 } 2413 2414 static void 2415 rt2661_set_slottime(struct rt2661_softc *sc) 2416 { 2417 struct ieee80211com *ic = &sc->sc_ic; 2418 uint8_t slottime; 2419 uint32_t tmp; 2420 2421 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2422 2423 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2424 tmp = (tmp & ~0xff) | slottime; 2425 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2426 2427 DPRINTF(("setting slot time to %uus\n", slottime)); 2428 } 2429 2430 static const char * 2431 rt2661_get_rf(int rev) 2432 { 2433 switch (rev) { 2434 case RT2661_RF_5225: return "RT5225"; 2435 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2436 case RT2661_RF_2527: return "RT2527"; 2437 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2438 default: return "unknown"; 2439 } 2440 } 2441 2442 static void 2443 rt2661_read_eeprom(struct rt2661_softc *sc) 2444 { 2445 struct ieee80211com *ic = &sc->sc_ic; 2446 uint16_t val; 2447 int i; 2448 2449 /* read MAC address */ 2450 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2451 ic->ic_myaddr[0] = val & 0xff; 2452 ic->ic_myaddr[1] = val >> 8; 2453 2454 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2455 ic->ic_myaddr[2] = val & 0xff; 2456 ic->ic_myaddr[3] = val >> 8; 2457 2458 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2459 ic->ic_myaddr[4] = val & 0xff; 2460 ic->ic_myaddr[5] = val >> 8; 2461 2462 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2463 /* XXX: test if different from 0xffff? */ 2464 sc->rf_rev = (val >> 11) & 0x1f; 2465 sc->hw_radio = (val >> 10) & 0x1; 2466 sc->rx_ant = (val >> 4) & 0x3; 2467 sc->tx_ant = (val >> 2) & 0x3; 2468 sc->nb_ant = val & 0x3; 2469 2470 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2471 2472 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2473 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2474 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2475 2476 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2477 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2478 2479 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2480 if ((val & 0xff) != 0xff) 2481 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2482 2483 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2484 if ((val & 0xff) != 0xff) 2485 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2486 2487 /* adjust RSSI correction for external low-noise amplifier */ 2488 if (sc->ext_2ghz_lna) 2489 sc->rssi_2ghz_corr -= 14; 2490 if (sc->ext_5ghz_lna) 2491 sc->rssi_5ghz_corr -= 14; 2492 2493 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2494 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2495 2496 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2497 if ((val >> 8) != 0xff) 2498 sc->rfprog = (val >> 8) & 0x3; 2499 if ((val & 0xff) != 0xff) 2500 sc->rffreq = val & 0xff; 2501 2502 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2503 2504 /* read Tx power for all a/b/g channels */ 2505 for (i = 0; i < 19; i++) { 2506 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2507 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2508 DPRINTF(("Channel=%d Tx power=%d\n", 2509 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2510 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2511 DPRINTF(("Channel=%d Tx power=%d\n", 2512 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2513 } 2514 2515 /* read vendor-specific BBP values */ 2516 for (i = 0; i < 16; i++) { 2517 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2518 if (val == 0 || val == 0xffff) 2519 continue; /* skip invalid entries */ 2520 sc->bbp_prom[i].reg = val >> 8; 2521 sc->bbp_prom[i].val = val & 0xff; 2522 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2523 sc->bbp_prom[i].val)); 2524 } 2525 } 2526 2527 static int 2528 rt2661_bbp_init(struct rt2661_softc *sc) 2529 { 2530 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2531 int i, ntries; 2532 uint8_t val; 2533 2534 /* wait for BBP to be ready */ 2535 for (ntries = 0; ntries < 100; ntries++) { 2536 val = rt2661_bbp_read(sc, 0); 2537 if (val != 0 && val != 0xff) 2538 break; 2539 DELAY(100); 2540 } 2541 if (ntries == 100) { 2542 aprint_error_dev(sc->sc_dev, "timeout waiting for BBP\n"); 2543 return EIO; 2544 } 2545 2546 /* initialize BBP registers to default values */ 2547 for (i = 0; i < N(rt2661_def_bbp); i++) { 2548 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2549 rt2661_def_bbp[i].val); 2550 } 2551 2552 /* write vendor-specific BBP values (from EEPROM) */ 2553 for (i = 0; i < 16; i++) { 2554 if (sc->bbp_prom[i].reg == 0) 2555 continue; 2556 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2557 } 2558 2559 return 0; 2560 #undef N 2561 } 2562 2563 static int 2564 rt2661_init(struct ifnet *ifp) 2565 { 2566 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2567 struct rt2661_softc *sc = ifp->if_softc; 2568 struct ieee80211com *ic = &sc->sc_ic; 2569 const char *name = NULL; /* make lint happy */ 2570 uint8_t *ucode; 2571 size_t size; 2572 uint32_t tmp, star[3]; 2573 int i, ntries; 2574 firmware_handle_t fh; 2575 2576 /* for CardBus, power on the socket */ 2577 if (!(sc->sc_flags & RT2661_ENABLED)) { 2578 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2579 aprint_error_dev(sc->sc_dev, "could not enable device\n"); 2580 return EIO; 2581 } 2582 sc->sc_flags |= RT2661_ENABLED; 2583 } 2584 2585 rt2661_stop(ifp, 0); 2586 2587 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2588 switch (sc->sc_id) { 2589 case PCI_PRODUCT_RALINK_RT2561: 2590 name = "ral-rt2561"; 2591 break; 2592 case PCI_PRODUCT_RALINK_RT2561S: 2593 name = "ral-rt2561s"; 2594 break; 2595 case PCI_PRODUCT_RALINK_RT2661: 2596 name = "ral-rt2661"; 2597 break; 2598 } 2599 2600 if (firmware_open("ral", name, &fh) != 0) { 2601 aprint_error_dev(sc->sc_dev, "could not open microcode %s\n", name); 2602 rt2661_stop(ifp, 1); 2603 return EIO; 2604 } 2605 2606 size = firmware_get_size(fh); 2607 if (!(ucode = firmware_malloc(size))) { 2608 aprint_error_dev(sc->sc_dev, "could not alloc microcode memory\n"); 2609 firmware_close(fh); 2610 rt2661_stop(ifp, 1); 2611 return ENOMEM; 2612 } 2613 2614 if (firmware_read(fh, 0, ucode, size) != 0) { 2615 aprint_error_dev(sc->sc_dev, "could not read microcode %s\n", name); 2616 firmware_free(ucode, size); 2617 firmware_close(fh); 2618 rt2661_stop(ifp, 1); 2619 return EIO; 2620 } 2621 2622 if (rt2661_load_microcode(sc, ucode, size) != 0) { 2623 aprint_error_dev(sc->sc_dev, "could not load 8051 microcode\n"); 2624 firmware_free(ucode, size); 2625 firmware_close(fh); 2626 rt2661_stop(ifp, 1); 2627 return EIO; 2628 } 2629 2630 firmware_free(ucode, size); 2631 firmware_close(fh); 2632 sc->sc_flags |= RT2661_FWLOADED; 2633 } 2634 2635 /* initialize Tx rings */ 2636 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2637 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2638 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2639 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2640 2641 /* initialize Mgt ring */ 2642 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2643 2644 /* initialize Rx ring */ 2645 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2646 2647 /* initialize Tx rings sizes */ 2648 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2649 RT2661_TX_RING_COUNT << 24 | 2650 RT2661_TX_RING_COUNT << 16 | 2651 RT2661_TX_RING_COUNT << 8 | 2652 RT2661_TX_RING_COUNT); 2653 2654 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2655 RT2661_TX_DESC_WSIZE << 16 | 2656 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2657 RT2661_MGT_RING_COUNT); 2658 2659 /* initialize Rx rings */ 2660 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2661 RT2661_RX_DESC_BACK << 16 | 2662 RT2661_RX_DESC_WSIZE << 8 | 2663 RT2661_RX_RING_COUNT); 2664 2665 /* XXX: some magic here */ 2666 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2667 2668 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2669 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2670 2671 /* load base address of Rx ring */ 2672 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2673 2674 /* initialize MAC registers to default values */ 2675 for (i = 0; i < N(rt2661_def_mac); i++) 2676 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2677 2678 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2679 rt2661_set_macaddr(sc, ic->ic_myaddr); 2680 2681 /* set host ready */ 2682 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2683 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2684 2685 /* wait for BBP/RF to wakeup */ 2686 for (ntries = 0; ntries < 1000; ntries++) { 2687 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2688 break; 2689 DELAY(1000); 2690 } 2691 if (ntries == 1000) { 2692 printf("timeout waiting for BBP/RF to wakeup\n"); 2693 rt2661_stop(ifp, 1); 2694 return EIO; 2695 } 2696 2697 if (rt2661_bbp_init(sc) != 0) { 2698 rt2661_stop(ifp, 1); 2699 return EIO; 2700 } 2701 2702 /* select default channel */ 2703 sc->sc_curchan = ic->ic_curchan; 2704 rt2661_select_band(sc, sc->sc_curchan); 2705 rt2661_select_antenna(sc); 2706 rt2661_set_chan(sc, sc->sc_curchan); 2707 2708 /* update Rx filter */ 2709 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2710 2711 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2712 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2713 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2714 RT2661_DROP_ACKCTS; 2715 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2716 tmp |= RT2661_DROP_TODS; 2717 if (!(ifp->if_flags & IFF_PROMISC)) 2718 tmp |= RT2661_DROP_NOT_TO_ME; 2719 } 2720 2721 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2722 2723 /* clear STA registers */ 2724 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, star, N(star)); 2725 2726 /* initialize ASIC */ 2727 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2728 2729 /* clear any pending interrupt */ 2730 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2731 2732 /* enable interrupts */ 2733 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2734 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2735 2736 /* kick Rx */ 2737 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2738 2739 ifp->if_flags &= ~IFF_OACTIVE; 2740 ifp->if_flags |= IFF_RUNNING; 2741 2742 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2743 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2744 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2745 } else 2746 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2747 2748 return 0; 2749 #undef N 2750 } 2751 2752 static void 2753 rt2661_stop(struct ifnet *ifp, int disable) 2754 { 2755 struct rt2661_softc *sc = ifp->if_softc; 2756 struct ieee80211com *ic = &sc->sc_ic; 2757 uint32_t tmp; 2758 2759 sc->sc_tx_timer = 0; 2760 ifp->if_timer = 0; 2761 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2762 2763 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2764 2765 /* abort Tx (for all 5 Tx rings) */ 2766 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2767 2768 /* disable Rx (value remains after reset!) */ 2769 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2770 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2771 2772 /* reset ASIC */ 2773 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2774 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2775 2776 /* disable interrupts */ 2777 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2778 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2779 2780 /* clear any pending interrupt */ 2781 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2782 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2783 2784 /* reset Tx and Rx rings */ 2785 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2786 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2787 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2788 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2789 rt2661_reset_tx_ring(sc, &sc->mgtq); 2790 rt2661_reset_rx_ring(sc, &sc->rxq); 2791 2792 /* for CardBus, power down the socket */ 2793 if (disable && sc->sc_disable != NULL) { 2794 if (sc->sc_flags & RT2661_ENABLED) { 2795 (*sc->sc_disable)(sc); 2796 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2797 } 2798 } 2799 } 2800 2801 static int 2802 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2803 { 2804 int ntries; 2805 2806 /* reset 8051 */ 2807 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2808 2809 /* cancel any pending Host to MCU command */ 2810 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2811 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2812 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2813 2814 /* write 8051's microcode */ 2815 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2816 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2817 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2818 2819 /* kick 8051's ass */ 2820 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2821 2822 /* wait for 8051 to initialize */ 2823 for (ntries = 0; ntries < 500; ntries++) { 2824 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2825 break; 2826 DELAY(100); 2827 } 2828 if (ntries == 500) { 2829 printf("timeout waiting for MCU to initialize\n"); 2830 return EIO; 2831 } 2832 return 0; 2833 } 2834 2835 /* 2836 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2837 * false CCA count. This function is called periodically (every seconds) when 2838 * in the RUN state. Values taken from the reference driver. 2839 */ 2840 static void 2841 rt2661_rx_tune(struct rt2661_softc *sc) 2842 { 2843 uint8_t bbp17; 2844 uint16_t cca; 2845 int lo, hi, dbm; 2846 2847 /* 2848 * Tuning range depends on operating band and on the presence of an 2849 * external low-noise amplifier. 2850 */ 2851 lo = 0x20; 2852 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2853 lo += 0x08; 2854 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2855 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2856 lo += 0x10; 2857 hi = lo + 0x20; 2858 2859 dbm = sc->avg_rssi; 2860 /* retrieve false CCA count since last call (clear on read) */ 2861 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2862 2863 DPRINTFN(2, ("RSSI=%ddBm false CCA=%d\n", dbm, cca)); 2864 2865 if (dbm < -74) { 2866 /* very bad RSSI, tune using false CCA count */ 2867 bbp17 = sc->bbp17; /* current value */ 2868 2869 hi -= 2 * (-74 - dbm); 2870 if (hi < lo) 2871 hi = lo; 2872 2873 if (bbp17 > hi) 2874 bbp17 = hi; 2875 else if (cca > 512) 2876 bbp17 = min(bbp17 + 1, hi); 2877 else if (cca < 100) 2878 bbp17 = max(bbp17 - 1, lo); 2879 2880 } else if (dbm < -66) { 2881 bbp17 = lo + 0x08; 2882 } else if (dbm < -58) { 2883 bbp17 = lo + 0x10; 2884 } else if (dbm < -35) { 2885 bbp17 = hi; 2886 } else { /* very good RSSI >= -35dBm */ 2887 bbp17 = 0x60; /* very low sensitivity */ 2888 } 2889 2890 if (bbp17 != sc->bbp17) { 2891 DPRINTF(("BBP17 %x->%x\n", sc->bbp17, bbp17)); 2892 rt2661_bbp_write(sc, 17, bbp17); 2893 sc->bbp17 = bbp17; 2894 } 2895 } 2896 2897 #ifdef notyet 2898 /* 2899 * Enter/Leave radar detection mode. 2900 * This is for 802.11h additional regulatory domains. 2901 */ 2902 static void 2903 rt2661_radar_start(struct rt2661_softc *sc) 2904 { 2905 uint32_t tmp; 2906 2907 /* disable Rx */ 2908 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2909 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2910 2911 rt2661_bbp_write(sc, 82, 0x20); 2912 rt2661_bbp_write(sc, 83, 0x00); 2913 rt2661_bbp_write(sc, 84, 0x40); 2914 2915 /* save current BBP registers values */ 2916 sc->bbp18 = rt2661_bbp_read(sc, 18); 2917 sc->bbp21 = rt2661_bbp_read(sc, 21); 2918 sc->bbp22 = rt2661_bbp_read(sc, 22); 2919 sc->bbp16 = rt2661_bbp_read(sc, 16); 2920 sc->bbp17 = rt2661_bbp_read(sc, 17); 2921 sc->bbp64 = rt2661_bbp_read(sc, 64); 2922 2923 rt2661_bbp_write(sc, 18, 0xff); 2924 rt2661_bbp_write(sc, 21, 0x3f); 2925 rt2661_bbp_write(sc, 22, 0x3f); 2926 rt2661_bbp_write(sc, 16, 0xbd); 2927 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2928 rt2661_bbp_write(sc, 64, 0x21); 2929 2930 /* restore Rx filter */ 2931 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2932 } 2933 2934 static int 2935 rt2661_radar_stop(struct rt2661_softc *sc) 2936 { 2937 uint8_t bbp66; 2938 2939 /* read radar detection result */ 2940 bbp66 = rt2661_bbp_read(sc, 66); 2941 2942 /* restore BBP registers values */ 2943 rt2661_bbp_write(sc, 16, sc->bbp16); 2944 rt2661_bbp_write(sc, 17, sc->bbp17); 2945 rt2661_bbp_write(sc, 18, sc->bbp18); 2946 rt2661_bbp_write(sc, 21, sc->bbp21); 2947 rt2661_bbp_write(sc, 22, sc->bbp22); 2948 rt2661_bbp_write(sc, 64, sc->bbp64); 2949 2950 return bbp66 == 1; 2951 } 2952 #endif 2953 2954 static int 2955 rt2661_prepare_beacon(struct rt2661_softc *sc) 2956 { 2957 struct ieee80211com *ic = &sc->sc_ic; 2958 struct ieee80211_node *ni = ic->ic_bss; 2959 struct rt2661_tx_desc desc; 2960 struct mbuf *m0; 2961 struct ieee80211_beacon_offsets bo; 2962 int rate; 2963 2964 m0 = ieee80211_beacon_alloc(ic, ni, &bo); 2965 if (m0 == NULL) { 2966 aprint_error_dev(sc->sc_dev, "could not allocate beacon frame\n"); 2967 return ENOBUFS; 2968 } 2969 2970 /* send beacons at the lowest available rate */ 2971 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 2972 2973 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2974 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2975 2976 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2977 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2978 2979 /* copy beacon header and payload into NIC memory */ 2980 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2981 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2982 2983 m_freem(m0); 2984 2985 /* 2986 * Store offset of ERP Information Element so that we can update it 2987 * dynamically when the slot time changes. 2988 * XXX: this is ugly since it depends on how net80211 builds beacon 2989 * frames but ieee80211_beacon_alloc() doesn't store offsets for us. 2990 */ 2991 if (ic->ic_curmode == IEEE80211_MODE_11G) { 2992 sc->erp_csr = 2993 RT2661_HW_BEACON_BASE0 + 24 + 2994 sizeof (struct ieee80211_frame) + 2995 8 + 2 + 2 + 2 + ni->ni_esslen + 2996 2 + min(ni->ni_rates.rs_nrates, IEEE80211_RATE_SIZE) + 2997 2 + 1 + 2998 ((ic->ic_opmode == IEEE80211_M_IBSS) ? 4 : 6) + 2999 2; 3000 } 3001 3002 return 0; 3003 } 3004 3005 /* 3006 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 3007 * and HostAP operating modes. 3008 */ 3009 static void 3010 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 3011 { 3012 struct ieee80211com *ic = &sc->sc_ic; 3013 uint32_t tmp; 3014 3015 if (ic->ic_opmode != IEEE80211_M_STA) { 3016 /* 3017 * Change default 16ms TBTT adjustment to 8ms. 3018 * Must be done before enabling beacon generation. 3019 */ 3020 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 3021 } 3022 3023 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 3024 3025 /* set beacon interval (in 1/16ms unit) */ 3026 tmp |= ic->ic_bss->ni_intval * 16; 3027 3028 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 3029 if (ic->ic_opmode == IEEE80211_M_STA) 3030 tmp |= RT2661_TSF_MODE(1); 3031 else 3032 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 3033 3034 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 3035 } 3036 3037 /* 3038 * Retrieve the "Received Signal Strength Indicator" from the raw values 3039 * contained in Rx descriptors. The computation depends on which band the 3040 * frame was received. Correction values taken from the reference driver. 3041 */ 3042 static int 3043 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 3044 { 3045 int lna, agc, rssi; 3046 3047 lna = (raw >> 5) & 0x3; 3048 agc = raw & 0x1f; 3049 3050 rssi = 2 * agc; 3051 3052 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3053 rssi += sc->rssi_2ghz_corr; 3054 3055 if (lna == 1) 3056 rssi -= 64; 3057 else if (lna == 2) 3058 rssi -= 74; 3059 else if (lna == 3) 3060 rssi -= 90; 3061 } else { 3062 rssi += sc->rssi_5ghz_corr; 3063 3064 if (lna == 1) 3065 rssi -= 64; 3066 else if (lna == 2) 3067 rssi -= 86; 3068 else if (lna == 3) 3069 rssi -= 100; 3070 } 3071 return rssi; 3072 } 3073
Indexes created Tue Sep 23 07:09:52 GMT 2025