rt2661.c revision 1.39
1 /* $NetBSD: rt2661.c,v 1.39 2018/06/26 06:48:00 msaitoh Exp $ */ 2 /* $OpenBSD: rt2661.c,v 1.17 2006/05/01 08:41:11 damien Exp $ */ 3 /* $FreeBSD: rt2560.c,v 1.5 2006/06/02 19:59:31 csjp Exp $ */ 4 5 /*- 6 * Copyright (c) 2006 7 * Damien Bergamini <damien.bergamini (at) free.fr> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2661.c,v 1.39 2018/06/26 06:48:00 msaitoh Exp $"); 29 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/callout.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 60 #include <net80211/ieee80211_var.h> 61 #include <net80211/ieee80211_amrr.h> 62 #include <net80211/ieee80211_radiotap.h> 63 64 #include <dev/ic/rt2661reg.h> 65 #include <dev/ic/rt2661var.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/firmload.h> 72 73 #ifdef RAL_DEBUG 74 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 75 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 76 int rt2661_debug = 0; 77 #else 78 #define DPRINTF(x) 79 #define DPRINTFN(n, x) 80 #endif 81 82 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *, int); 84 static void rt2661_reset_tx_ring(struct rt2661_softc *, 85 struct rt2661_tx_ring *); 86 static void rt2661_free_tx_ring(struct rt2661_softc *, 87 struct rt2661_tx_ring *); 88 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *, int); 90 static void rt2661_reset_rx_ring(struct rt2661_softc *, 91 struct rt2661_rx_ring *); 92 static void rt2661_free_rx_ring(struct rt2661_softc *, 93 struct rt2661_rx_ring *); 94 static struct ieee80211_node * 95 rt2661_node_alloc(struct ieee80211_node_table *); 96 static int rt2661_media_change(struct ifnet *); 97 static void rt2661_next_scan(void *); 98 static void rt2661_iter_func(void *, struct ieee80211_node *); 99 static void rt2661_updatestats(void *); 100 static void rt2661_newassoc(struct ieee80211_node *, int); 101 static int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 102 int); 103 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 104 static void rt2661_tx_intr(struct rt2661_softc *); 105 static void rt2661_tx_dma_intr(struct rt2661_softc *, 106 struct rt2661_tx_ring *); 107 static void rt2661_rx_intr(struct rt2661_softc *); 108 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 109 static void rt2661_mcu_wakeup(struct rt2661_softc *); 110 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 111 int rt2661_intr(void *); 112 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 113 static int rt2661_ack_rate(struct ieee80211com *, int); 114 static uint16_t rt2661_txtime(int, int, uint32_t); 115 static uint8_t rt2661_plcp_signal(int); 116 static void rt2661_setup_tx_desc(struct rt2661_softc *, 117 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 118 const bus_dma_segment_t *, int, int); 119 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 120 struct ieee80211_node *); 121 static struct mbuf * 122 rt2661_get_rts(struct rt2661_softc *, 123 struct ieee80211_frame *, uint16_t); 124 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 125 struct ieee80211_node *, int); 126 static void rt2661_start(struct ifnet *); 127 static void rt2661_watchdog(struct ifnet *); 128 static int rt2661_reset(struct ifnet *); 129 static int rt2661_ioctl(struct ifnet *, u_long, void *); 130 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 131 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 132 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 133 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 134 static void rt2661_select_antenna(struct rt2661_softc *); 135 static void rt2661_enable_mrr(struct rt2661_softc *); 136 static void rt2661_set_txpreamble(struct rt2661_softc *); 137 static void rt2661_set_basicrates(struct rt2661_softc *, 138 const struct ieee80211_rateset *); 139 static void rt2661_select_band(struct rt2661_softc *, 140 struct ieee80211_channel *); 141 static void rt2661_set_chan(struct rt2661_softc *, 142 struct ieee80211_channel *); 143 static void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 144 static void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 145 static void rt2661_update_promisc(struct rt2661_softc *); 146 #if 0 147 static int rt2661_wme_update(struct ieee80211com *); 148 #endif 149 150 static void rt2661_updateslot(struct ifnet *); 151 static void rt2661_set_slottime(struct rt2661_softc *); 152 static const char * 153 rt2661_get_rf(int); 154 static void rt2661_read_eeprom(struct rt2661_softc *); 155 static int rt2661_bbp_init(struct rt2661_softc *); 156 static int rt2661_init(struct ifnet *); 157 static void rt2661_stop(struct ifnet *, int); 158 static int rt2661_load_microcode(struct rt2661_softc *, const uint8_t *, 159 int); 160 static void rt2661_rx_tune(struct rt2661_softc *); 161 #ifdef notyet 162 static void rt2661_radar_start(struct rt2661_softc *); 163 static int rt2661_radar_stop(struct rt2661_softc *); 164 #endif 165 static int rt2661_prepare_beacon(struct rt2661_softc *); 166 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 167 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 168 static void rt2661_softintr(void *); 169 170 static const struct { 171 uint32_t reg; 172 uint32_t val; 173 } rt2661_def_mac[] = { 174 RT2661_DEF_MAC 175 }; 176 177 static const struct { 178 uint8_t reg; 179 uint8_t val; 180 } rt2661_def_bbp[] = { 181 RT2661_DEF_BBP 182 }; 183 184 static const struct rfprog { 185 uint8_t chan; 186 uint32_t r1, r2, r3, r4; 187 } rt2661_rf5225_1[] = { 188 RT2661_RF5225_1 189 }, rt2661_rf5225_2[] = { 190 RT2661_RF5225_2 191 }; 192 193 int 194 rt2661_attach(void *xsc, int id) 195 { 196 struct rt2661_softc *sc = xsc; 197 struct ieee80211com *ic = &sc->sc_ic; 198 struct ifnet *ifp = &sc->sc_if; 199 uint32_t val; 200 int error, i, ntries; 201 202 sc->sc_id = id; 203 204 sc->amrr.amrr_min_success_threshold = 1; 205 sc->amrr.amrr_max_success_threshold = 15; 206 callout_init(&sc->scan_ch, 0); 207 callout_init(&sc->amrr_ch, 0); 208 209 /* wait for NIC to initialize */ 210 for (ntries = 0; ntries < 1000; ntries++) { 211 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 212 break; 213 DELAY(1000); 214 } 215 if (ntries == 1000) { 216 aprint_error_dev(sc->sc_dev, "timeout waiting for NIC to initialize\n"); 217 return EIO; 218 } 219 220 /* retrieve RF rev. no and various other things from EEPROM */ 221 rt2661_read_eeprom(sc); 222 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 223 ether_sprintf(ic->ic_myaddr)); 224 225 aprint_normal_dev(sc->sc_dev, "MAC/BBP RT%X, RF %s\n", val, 226 rt2661_get_rf(sc->rf_rev)); 227 228 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rt2661_softintr, sc); 229 if (sc->sc_soft_ih == NULL) { 230 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 231 goto fail0; 232 } 233 234 /* 235 * Allocate Tx and Rx rings. 236 */ 237 error = rt2661_alloc_tx_ring(sc, &sc->txq[0], RT2661_TX_RING_COUNT); 238 if (error != 0) { 239 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 0\n"); 240 goto fail1; 241 } 242 243 error = rt2661_alloc_tx_ring(sc, &sc->txq[1], RT2661_TX_RING_COUNT); 244 if (error != 0) { 245 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 1\n"); 246 goto fail2; 247 } 248 249 error = rt2661_alloc_tx_ring(sc, &sc->txq[2], RT2661_TX_RING_COUNT); 250 if (error != 0) { 251 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 2\n"); 252 goto fail3; 253 } 254 255 error = rt2661_alloc_tx_ring(sc, &sc->txq[3], RT2661_TX_RING_COUNT); 256 if (error != 0) { 257 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 3\n"); 258 goto fail4; 259 } 260 261 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 262 if (error != 0) { 263 aprint_error_dev(sc->sc_dev, "could not allocate Mgt ring\n"); 264 goto fail5; 265 } 266 267 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 268 if (error != 0) { 269 aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n"); 270 goto fail6; 271 } 272 273 ifp->if_softc = sc; 274 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 275 ifp->if_init = rt2661_init; 276 ifp->if_stop = rt2661_stop; 277 ifp->if_ioctl = rt2661_ioctl; 278 ifp->if_start = rt2661_start; 279 ifp->if_watchdog = rt2661_watchdog; 280 IFQ_SET_READY(&ifp->if_snd); 281 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 282 283 ic->ic_ifp = ifp; 284 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 285 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 286 ic->ic_state = IEEE80211_S_INIT; 287 288 /* set device capabilities */ 289 ic->ic_caps = 290 IEEE80211_C_IBSS | /* IBSS mode supported */ 291 IEEE80211_C_MONITOR | /* monitor mode supported */ 292 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 293 IEEE80211_C_TXPMGT | /* tx power management */ 294 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 295 IEEE80211_C_SHSLOT | /* short slot time supported */ 296 IEEE80211_C_WPA; /* 802.11i */ 297 298 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 299 /* set supported .11a rates */ 300 ic->ic_sup_rates[IEEE80211_MODE_11A] = ieee80211_std_rateset_11a; 301 302 /* set supported .11a channels */ 303 for (i = 36; i <= 64; i += 4) { 304 ic->ic_channels[i].ic_freq = 305 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 306 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 307 } 308 for (i = 100; i <= 140; i += 4) { 309 ic->ic_channels[i].ic_freq = 310 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 311 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 312 } 313 for (i = 149; i <= 165; i += 4) { 314 ic->ic_channels[i].ic_freq = 315 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 316 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 317 } 318 } 319 320 /* set supported .11b and .11g rates */ 321 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 322 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 323 324 /* set supported .11b and .11g channels (1 through 14) */ 325 for (i = 1; i <= 14; i++) { 326 ic->ic_channels[i].ic_freq = 327 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 328 ic->ic_channels[i].ic_flags = 329 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 330 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 331 } 332 333 error = if_initialize(ifp); 334 if (error != 0) { 335 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 336 error); 337 goto fail7; 338 } 339 ieee80211_ifattach(ic); 340 /* Use common softint-based if_input */ 341 ifp->if_percpuq = if_percpuq_create(ifp); 342 if_register(ifp); 343 344 ic->ic_node_alloc = rt2661_node_alloc; 345 ic->ic_newassoc = rt2661_newassoc; 346 ic->ic_updateslot = rt2661_updateslot; 347 ic->ic_reset = rt2661_reset; 348 349 /* override state transition machine */ 350 sc->sc_newstate = ic->ic_newstate; 351 ic->ic_newstate = rt2661_newstate; 352 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 353 354 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 355 sizeof(struct ieee80211_frame) + sizeof(sc->sc_txtap), 356 &sc->sc_drvbpf); 357 358 sc->sc_rxtap_len = roundup(sizeof(sc->sc_rxtap), sizeof(u_int32_t)); 359 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 360 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 361 362 sc->sc_txtap_len = roundup(sizeof(sc->sc_txtap), sizeof(u_int32_t)); 363 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 364 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 365 366 ieee80211_announce(ic); 367 368 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 369 pmf_class_network_register(sc->sc_dev, ifp); 370 else 371 aprint_error_dev(sc->sc_dev, 372 "couldn't establish power handler\n"); 373 374 return 0; 375 376 fail7: rt2661_free_rx_ring(sc, &sc->rxq); 377 fail6: rt2661_free_tx_ring(sc, &sc->mgtq); 378 fail5: rt2661_free_tx_ring(sc, &sc->txq[3]); 379 fail4: rt2661_free_tx_ring(sc, &sc->txq[2]); 380 fail3: rt2661_free_tx_ring(sc, &sc->txq[1]); 381 fail2: rt2661_free_tx_ring(sc, &sc->txq[0]); 382 fail1: softint_disestablish(sc->sc_soft_ih); 383 sc->sc_soft_ih = NULL; 384 fail0: return ENXIO; 385 } 386 387 int 388 rt2661_detach(void *xsc) 389 { 390 struct rt2661_softc *sc = xsc; 391 struct ifnet *ifp = &sc->sc_if; 392 393 callout_stop(&sc->scan_ch); 394 callout_stop(&sc->amrr_ch); 395 396 pmf_device_deregister(sc->sc_dev); 397 398 ieee80211_ifdetach(&sc->sc_ic); 399 if_detach(ifp); 400 401 rt2661_free_tx_ring(sc, &sc->txq[0]); 402 rt2661_free_tx_ring(sc, &sc->txq[1]); 403 rt2661_free_tx_ring(sc, &sc->txq[2]); 404 rt2661_free_tx_ring(sc, &sc->txq[3]); 405 rt2661_free_tx_ring(sc, &sc->mgtq); 406 rt2661_free_rx_ring(sc, &sc->rxq); 407 408 if (sc->sc_soft_ih != NULL) { 409 softint_disestablish(sc->sc_soft_ih); 410 sc->sc_soft_ih = NULL; 411 } 412 413 return 0; 414 } 415 416 static int 417 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 418 int count) 419 { 420 int i, nsegs, error; 421 422 ring->count = count; 423 ring->queued = 0; 424 ring->cur = ring->next = ring->stat = 0; 425 426 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 427 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 428 if (error != 0) { 429 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 430 goto fail; 431 } 432 433 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 434 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 435 if (error != 0) { 436 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 437 goto fail; 438 } 439 440 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 441 count * RT2661_TX_DESC_SIZE, (void **)&ring->desc, 442 BUS_DMA_NOWAIT); 443 if (error != 0) { 444 aprint_error_dev(sc->sc_dev, "could not map desc DMA memory\n"); 445 goto fail; 446 } 447 448 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 449 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 450 if (error != 0) { 451 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 452 goto fail; 453 } 454 455 memset(ring->desc, 0, count * RT2661_TX_DESC_SIZE); 456 ring->physaddr = ring->map->dm_segs->ds_addr; 457 458 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 459 M_NOWAIT); 460 if (ring->data == NULL) { 461 aprint_error_dev(sc->sc_dev, "could not allocate soft data\n"); 462 error = ENOMEM; 463 goto fail; 464 } 465 466 memset(ring->data, 0, count * sizeof (struct rt2661_tx_data)); 467 for (i = 0; i < count; i++) { 468 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 469 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 470 &ring->data[i].map); 471 if (error != 0) { 472 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 473 goto fail; 474 } 475 } 476 477 return 0; 478 479 fail: rt2661_free_tx_ring(sc, ring); 480 return error; 481 } 482 483 static void 484 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 485 { 486 struct rt2661_tx_desc *desc; 487 struct rt2661_tx_data *data; 488 int i; 489 490 for (i = 0; i < ring->count; i++) { 491 desc = &ring->desc[i]; 492 data = &ring->data[i]; 493 494 if (data->m != NULL) { 495 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 496 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 497 bus_dmamap_unload(sc->sc_dmat, data->map); 498 m_freem(data->m); 499 data->m = NULL; 500 } 501 502 if (data->ni != NULL) { 503 ieee80211_free_node(data->ni); 504 data->ni = NULL; 505 } 506 507 desc->flags = 0; 508 } 509 510 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 511 BUS_DMASYNC_PREWRITE); 512 513 ring->queued = 0; 514 ring->cur = ring->next = ring->stat = 0; 515 } 516 517 518 static void 519 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 520 { 521 struct rt2661_tx_data *data; 522 int i; 523 524 if (ring->desc != NULL) { 525 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 526 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 527 bus_dmamap_unload(sc->sc_dmat, ring->map); 528 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 529 ring->count * RT2661_TX_DESC_SIZE); 530 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 531 } 532 533 if (ring->data != NULL) { 534 for (i = 0; i < ring->count; i++) { 535 data = &ring->data[i]; 536 537 if (data->m != NULL) { 538 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 539 data->map->dm_mapsize, 540 BUS_DMASYNC_POSTWRITE); 541 bus_dmamap_unload(sc->sc_dmat, data->map); 542 m_freem(data->m); 543 } 544 545 if (data->ni != NULL) 546 ieee80211_free_node(data->ni); 547 548 if (data->map != NULL) 549 bus_dmamap_destroy(sc->sc_dmat, data->map); 550 } 551 free(ring->data, M_DEVBUF); 552 } 553 } 554 555 static int 556 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 557 int count) 558 { 559 struct rt2661_rx_desc *desc; 560 struct rt2661_rx_data *data; 561 int i, nsegs, error; 562 563 ring->count = count; 564 ring->cur = ring->next = 0; 565 566 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 567 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 568 if (error != 0) { 569 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 570 goto fail; 571 } 572 573 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 574 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 575 if (error != 0) { 576 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 577 goto fail; 578 } 579 580 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 581 count * RT2661_RX_DESC_SIZE, (void **)&ring->desc, 582 BUS_DMA_NOWAIT); 583 if (error != 0) { 584 aprint_error_dev(sc->sc_dev, "could not map desc DMA memory\n"); 585 goto fail; 586 } 587 588 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 589 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 590 if (error != 0) { 591 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 592 goto fail; 593 } 594 595 memset(ring->desc, 0, count * RT2661_RX_DESC_SIZE); 596 ring->physaddr = ring->map->dm_segs->ds_addr; 597 598 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 599 M_NOWAIT); 600 if (ring->data == NULL) { 601 aprint_error_dev(sc->sc_dev, "could not allocate soft data\n"); 602 error = ENOMEM; 603 goto fail; 604 } 605 606 /* 607 * Pre-allocate Rx buffers and populate Rx ring. 608 */ 609 memset(ring->data, 0, count * sizeof (struct rt2661_rx_data)); 610 for (i = 0; i < count; i++) { 611 desc = &sc->rxq.desc[i]; 612 data = &sc->rxq.data[i]; 613 614 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 615 0, BUS_DMA_NOWAIT, &data->map); 616 if (error != 0) { 617 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 618 goto fail; 619 } 620 621 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 622 if (data->m == NULL) { 623 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 624 error = ENOMEM; 625 goto fail; 626 } 627 628 MCLGET(data->m, M_DONTWAIT); 629 if (!(data->m->m_flags & M_EXT)) { 630 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 631 error = ENOMEM; 632 goto fail; 633 } 634 635 error = bus_dmamap_load(sc->sc_dmat, data->map, 636 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 637 if (error != 0) { 638 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map"); 639 goto fail; 640 } 641 642 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 643 desc->flags = htole32(RT2661_RX_BUSY); 644 } 645 646 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 647 BUS_DMASYNC_PREWRITE); 648 649 return 0; 650 651 fail: rt2661_free_rx_ring(sc, ring); 652 return error; 653 } 654 655 static void 656 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 657 { 658 int i; 659 660 for (i = 0; i < ring->count; i++) 661 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 662 663 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 664 BUS_DMASYNC_PREWRITE); 665 666 ring->cur = ring->next = 0; 667 } 668 669 static void 670 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 671 { 672 struct rt2661_rx_data *data; 673 int i; 674 675 if (ring->desc != NULL) { 676 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 677 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 678 bus_dmamap_unload(sc->sc_dmat, ring->map); 679 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 680 ring->count * RT2661_RX_DESC_SIZE); 681 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 682 } 683 684 if (ring->data != NULL) { 685 for (i = 0; i < ring->count; i++) { 686 data = &ring->data[i]; 687 688 if (data->m != NULL) { 689 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 690 data->map->dm_mapsize, 691 BUS_DMASYNC_POSTREAD); 692 bus_dmamap_unload(sc->sc_dmat, data->map); 693 m_freem(data->m); 694 } 695 696 if (data->map != NULL) 697 bus_dmamap_destroy(sc->sc_dmat, data->map); 698 } 699 free(ring->data, M_DEVBUF); 700 } 701 } 702 703 static struct ieee80211_node * 704 rt2661_node_alloc(struct ieee80211_node_table *nt) 705 { 706 struct rt2661_node *rn; 707 708 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 709 M_NOWAIT | M_ZERO); 710 711 return (rn != NULL) ? &rn->ni : NULL; 712 } 713 714 static int 715 rt2661_media_change(struct ifnet *ifp) 716 { 717 int error; 718 719 error = ieee80211_media_change(ifp); 720 if (error != ENETRESET) 721 return error; 722 723 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 724 rt2661_init(ifp); 725 726 return 0; 727 } 728 729 /* 730 * This function is called periodically (every 200ms) during scanning to 731 * switch from one channel to another. 732 */ 733 static void 734 rt2661_next_scan(void *arg) 735 { 736 struct rt2661_softc *sc = arg; 737 struct ieee80211com *ic = &sc->sc_ic; 738 int s; 739 740 s = splnet(); 741 if (ic->ic_state == IEEE80211_S_SCAN) 742 ieee80211_next_scan(ic); 743 splx(s); 744 } 745 746 /* 747 * This function is called for each neighbor node. 748 */ 749 static void 750 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 751 { 752 struct rt2661_softc *sc = arg; 753 struct rt2661_node *rn = (struct rt2661_node *)ni; 754 755 ieee80211_amrr_choose(&sc->amrr, ni, &rn->amn); 756 } 757 758 /* 759 * This function is called periodically (every 500ms) in RUN state to update 760 * various settings like rate control statistics or Rx sensitivity. 761 */ 762 static void 763 rt2661_updatestats(void *arg) 764 { 765 struct rt2661_softc *sc = arg; 766 struct ieee80211com *ic = &sc->sc_ic; 767 int s; 768 769 s = splnet(); 770 if (ic->ic_opmode == IEEE80211_M_STA) 771 rt2661_iter_func(sc, ic->ic_bss); 772 else 773 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 774 775 /* update rx sensitivity every 1 sec */ 776 if (++sc->ncalls & 1) 777 rt2661_rx_tune(sc); 778 splx(s); 779 780 callout_reset(&sc->amrr_ch, hz / 2, rt2661_updatestats, sc); 781 } 782 783 static void 784 rt2661_newassoc(struct ieee80211_node *ni, int isnew) 785 { 786 struct rt2661_softc *sc = ni->ni_ic->ic_ifp->if_softc; 787 int i; 788 789 ieee80211_amrr_node_init(&sc->amrr, &((struct rt2661_node *)ni)->amn); 790 791 /* set rate to some reasonable initial value */ 792 for (i = ni->ni_rates.rs_nrates - 1; 793 i > 0 && (ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL) > 72; 794 i--); 795 ni->ni_txrate = i; 796 } 797 798 static int 799 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 800 { 801 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 802 enum ieee80211_state ostate; 803 struct ieee80211_node *ni; 804 uint32_t tmp; 805 806 ostate = ic->ic_state; 807 callout_stop(&sc->scan_ch); 808 809 switch (nstate) { 810 case IEEE80211_S_INIT: 811 callout_stop(&sc->amrr_ch); 812 813 if (ostate == IEEE80211_S_RUN) { 814 /* abort TSF synchronization */ 815 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 816 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 817 } 818 break; 819 820 case IEEE80211_S_SCAN: 821 rt2661_set_chan(sc, ic->ic_curchan); 822 callout_reset(&sc->scan_ch, hz / 5, rt2661_next_scan, sc); 823 break; 824 825 case IEEE80211_S_AUTH: 826 case IEEE80211_S_ASSOC: 827 rt2661_set_chan(sc, ic->ic_curchan); 828 break; 829 830 case IEEE80211_S_RUN: 831 rt2661_set_chan(sc, ic->ic_curchan); 832 833 ni = ic->ic_bss; 834 835 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 836 rt2661_set_slottime(sc); 837 rt2661_enable_mrr(sc); 838 rt2661_set_txpreamble(sc); 839 rt2661_set_basicrates(sc, &ni->ni_rates); 840 rt2661_set_bssid(sc, ni->ni_bssid); 841 } 842 843 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 844 ic->ic_opmode == IEEE80211_M_IBSS) 845 rt2661_prepare_beacon(sc); 846 847 if (ic->ic_opmode == IEEE80211_M_STA) { 848 /* fake a join to init the tx rate */ 849 rt2661_newassoc(ni, 1); 850 } 851 852 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 853 sc->ncalls = 0; 854 sc->avg_rssi = -95; /* reset EMA */ 855 callout_reset(&sc->amrr_ch, hz / 2, 856 rt2661_updatestats, sc); 857 rt2661_enable_tsf_sync(sc); 858 } 859 break; 860 } 861 862 return sc->sc_newstate(ic, nstate, arg); 863 } 864 865 /* 866 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 867 * 93C66). 868 */ 869 static uint16_t 870 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 871 { 872 uint32_t tmp; 873 uint16_t val; 874 int n; 875 876 /* clock C once before the first command */ 877 RT2661_EEPROM_CTL(sc, 0); 878 879 RT2661_EEPROM_CTL(sc, RT2661_S); 880 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 881 RT2661_EEPROM_CTL(sc, RT2661_S); 882 883 /* write start bit (1) */ 884 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 885 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 886 887 /* write READ opcode (10) */ 888 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 889 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 890 RT2661_EEPROM_CTL(sc, RT2661_S); 891 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 892 893 /* write address (A5-A0 or A7-A0) */ 894 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 895 for (; n >= 0; n--) { 896 RT2661_EEPROM_CTL(sc, RT2661_S | 897 (((addr >> n) & 1) << RT2661_SHIFT_D)); 898 RT2661_EEPROM_CTL(sc, RT2661_S | 899 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 900 } 901 902 RT2661_EEPROM_CTL(sc, RT2661_S); 903 904 /* read data Q15-Q0 */ 905 val = 0; 906 for (n = 15; n >= 0; n--) { 907 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 908 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 909 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 910 RT2661_EEPROM_CTL(sc, RT2661_S); 911 } 912 913 RT2661_EEPROM_CTL(sc, 0); 914 915 /* clear Chip Select and clock C */ 916 RT2661_EEPROM_CTL(sc, RT2661_S); 917 RT2661_EEPROM_CTL(sc, 0); 918 RT2661_EEPROM_CTL(sc, RT2661_C); 919 920 return val; 921 } 922 923 static void 924 rt2661_tx_intr(struct rt2661_softc *sc) 925 { 926 struct ifnet *ifp = &sc->sc_if; 927 struct rt2661_tx_ring *txq; 928 struct rt2661_tx_data *data; 929 struct rt2661_node *rn; 930 uint32_t val; 931 int qid, retrycnt, s; 932 933 s = splnet(); 934 935 for (;;) { 936 val = RAL_READ(sc, RT2661_STA_CSR4); 937 if (!(val & RT2661_TX_STAT_VALID)) 938 break; 939 940 /* retrieve the queue in which this frame was sent */ 941 qid = RT2661_TX_QID(val); 942 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 943 944 /* retrieve rate control algorithm context */ 945 data = &txq->data[txq->stat]; 946 rn = (struct rt2661_node *)data->ni; 947 948 /* if no frame has been sent, ignore */ 949 if (rn == NULL) 950 continue; 951 952 switch (RT2661_TX_RESULT(val)) { 953 case RT2661_TX_SUCCESS: 954 retrycnt = RT2661_TX_RETRYCNT(val); 955 956 DPRINTFN(10, ("data frame sent successfully after " 957 "%d retries\n", retrycnt)); 958 rn->amn.amn_txcnt++; 959 if (retrycnt > 0) 960 rn->amn.amn_retrycnt++; 961 ifp->if_opackets++; 962 break; 963 964 case RT2661_TX_RETRY_FAIL: 965 DPRINTFN(9, ("sending data frame failed (too much " 966 "retries)\n")); 967 rn->amn.amn_txcnt++; 968 rn->amn.amn_retrycnt++; 969 ifp->if_oerrors++; 970 break; 971 972 default: 973 /* other failure */ 974 aprint_error_dev(sc->sc_dev, "sending data frame failed 0x%08x\n", val); 975 ifp->if_oerrors++; 976 } 977 978 ieee80211_free_node(data->ni); 979 data->ni = NULL; 980 981 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 982 983 txq->queued--; 984 if (++txq->stat >= txq->count) /* faster than % count */ 985 txq->stat = 0; 986 } 987 988 sc->sc_tx_timer = 0; 989 ifp->if_flags &= ~IFF_OACTIVE; 990 rt2661_start(ifp); /* in softint */ 991 992 splx(s); 993 } 994 995 static void 996 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 997 { 998 struct rt2661_tx_desc *desc; 999 struct rt2661_tx_data *data; 1000 1001 for (;;) { 1002 desc = &txq->desc[txq->next]; 1003 data = &txq->data[txq->next]; 1004 1005 bus_dmamap_sync(sc->sc_dmat, txq->map, 1006 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1007 BUS_DMASYNC_POSTREAD); 1008 1009 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1010 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1011 break; 1012 1013 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1014 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1015 bus_dmamap_unload(sc->sc_dmat, data->map); 1016 m_freem(data->m); 1017 data->m = NULL; 1018 /* node reference is released in rt2661_tx_intr() */ 1019 1020 /* descriptor is no longer valid */ 1021 desc->flags &= ~htole32(RT2661_TX_VALID); 1022 1023 bus_dmamap_sync(sc->sc_dmat, txq->map, 1024 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1025 BUS_DMASYNC_PREWRITE); 1026 1027 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1028 1029 if (++txq->next >= txq->count) /* faster than % count */ 1030 txq->next = 0; 1031 } 1032 } 1033 1034 static void 1035 rt2661_rx_intr(struct rt2661_softc *sc) 1036 { 1037 struct ieee80211com *ic = &sc->sc_ic; 1038 struct ifnet *ifp = &sc->sc_if; 1039 struct rt2661_rx_desc *desc; 1040 struct rt2661_rx_data *data; 1041 struct ieee80211_frame *wh; 1042 struct ieee80211_node *ni; 1043 struct mbuf *mnew, *m; 1044 int error, rssi, s; 1045 1046 for (;;) { 1047 desc = &sc->rxq.desc[sc->rxq.cur]; 1048 data = &sc->rxq.data[sc->rxq.cur]; 1049 1050 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1051 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1052 BUS_DMASYNC_POSTREAD); 1053 1054 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1055 break; 1056 1057 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1058 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1059 /* 1060 * This should not happen since we did not request 1061 * to receive those frames when we filled TXRX_CSR0. 1062 */ 1063 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1064 le32toh(desc->flags))); 1065 ifp->if_ierrors++; 1066 goto skip; 1067 } 1068 1069 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1070 ifp->if_ierrors++; 1071 goto skip; 1072 } 1073 1074 /* 1075 * Try to allocate a new mbuf for this ring element and load it 1076 * before processing the current mbuf. If the ring element 1077 * cannot be loaded, drop the received packet and reuse the old 1078 * mbuf. In the unlikely case that the old mbuf can't be 1079 * reloaded either, explicitly panic. 1080 */ 1081 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1082 if (mnew == NULL) { 1083 ifp->if_ierrors++; 1084 goto skip; 1085 } 1086 1087 MCLGET(mnew, M_DONTWAIT); 1088 if (!(mnew->m_flags & M_EXT)) { 1089 m_freem(mnew); 1090 ifp->if_ierrors++; 1091 goto skip; 1092 } 1093 1094 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1095 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1096 bus_dmamap_unload(sc->sc_dmat, data->map); 1097 1098 error = bus_dmamap_load(sc->sc_dmat, data->map, 1099 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1100 if (error != 0) { 1101 m_freem(mnew); 1102 1103 /* try to reload the old mbuf */ 1104 error = bus_dmamap_load(sc->sc_dmat, data->map, 1105 mtod(data->m, void *), MCLBYTES, NULL, 1106 BUS_DMA_NOWAIT); 1107 if (error != 0) { 1108 /* very unlikely that it will fail... */ 1109 panic("%s: could not load old rx mbuf", 1110 device_xname(sc->sc_dev)); 1111 } 1112 /* physical address may have changed */ 1113 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1114 ifp->if_ierrors++; 1115 goto skip; 1116 } 1117 1118 /* 1119 * New mbuf successfully loaded, update Rx ring and continue 1120 * processing. 1121 */ 1122 m = data->m; 1123 data->m = mnew; 1124 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1125 1126 /* finalize mbuf */ 1127 m_set_rcvif(m, ifp); 1128 m->m_pkthdr.len = m->m_len = 1129 (le32toh(desc->flags) >> 16) & 0xfff; 1130 1131 s = splnet(); 1132 1133 if (sc->sc_drvbpf != NULL) { 1134 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1135 uint32_t tsf_lo, tsf_hi; 1136 1137 /* get timestamp (low and high 32 bits) */ 1138 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1139 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1140 1141 tap->wr_tsf = 1142 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1143 tap->wr_flags = 0; 1144 tap->wr_rate = rt2661_rxrate(desc); 1145 tap->wr_chan_freq = htole16(sc->sc_curchan->ic_freq); 1146 tap->wr_chan_flags = htole16(sc->sc_curchan->ic_flags); 1147 tap->wr_antsignal = desc->rssi; 1148 1149 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, 1150 BPF_D_IN); 1151 } 1152 1153 wh = mtod(m, struct ieee80211_frame *); 1154 ni = ieee80211_find_rxnode(ic, 1155 (struct ieee80211_frame_min *)wh); 1156 1157 /* send the frame to the 802.11 layer */ 1158 ieee80211_input(ic, m, ni, desc->rssi, 0); 1159 1160 /*- 1161 * Keep track of the average RSSI using an Exponential Moving 1162 * Average (EMA) of 8 Wilder's days: 1163 * avg = (1 / N) x rssi + ((N - 1) / N) x avg 1164 */ 1165 rssi = rt2661_get_rssi(sc, desc->rssi); 1166 sc->avg_rssi = (rssi + 7 * sc->avg_rssi) / 8; 1167 1168 /* node is no longer needed */ 1169 ieee80211_free_node(ni); 1170 1171 splx(s); 1172 1173 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1174 1175 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1176 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1177 BUS_DMASYNC_PREWRITE); 1178 1179 DPRINTFN(16, ("rx intr idx=%u\n", sc->rxq.cur)); 1180 1181 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1182 } 1183 1184 /* 1185 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 1186 * without calling if_start(). 1187 */ 1188 s = splnet(); 1189 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 1190 rt2661_start(ifp); 1191 splx(s); 1192 } 1193 1194 /* 1195 * This function is called in HostAP or IBSS modes when it's time to send a 1196 * new beacon (every ni_intval milliseconds). 1197 */ 1198 static void 1199 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1200 { 1201 struct ieee80211com *ic = &sc->sc_ic; 1202 1203 if (sc->sc_flags & RT2661_UPDATE_SLOT) { 1204 sc->sc_flags &= ~RT2661_UPDATE_SLOT; 1205 sc->sc_flags |= RT2661_SET_SLOTTIME; 1206 } else if (sc->sc_flags & RT2661_SET_SLOTTIME) { 1207 sc->sc_flags &= ~RT2661_SET_SLOTTIME; 1208 rt2661_set_slottime(sc); 1209 } 1210 1211 if (ic->ic_curmode == IEEE80211_MODE_11G) { 1212 /* update ERP Information Element */ 1213 RAL_WRITE_1(sc, sc->erp_csr, ic->ic_bss->ni_erp); 1214 RAL_RW_BARRIER_1(sc, sc->erp_csr); 1215 } 1216 1217 DPRINTFN(15, ("beacon expired\n")); 1218 } 1219 1220 static void 1221 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1222 { 1223 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1224 1225 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1226 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1227 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1228 1229 /* send wakeup command to MCU */ 1230 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1231 } 1232 1233 static void 1234 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1235 { 1236 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1237 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1238 } 1239 1240 int 1241 rt2661_intr(void *arg) 1242 { 1243 struct rt2661_softc *sc = arg; 1244 struct ifnet *ifp = &sc->sc_if; 1245 uint32_t r1, r2; 1246 1247 /* don't re-enable interrupts if we're shutting down */ 1248 if (!(ifp->if_flags & IFF_RUNNING)) { 1249 /* disable MAC and MCU interrupts */ 1250 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1251 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1252 return 0; 1253 } 1254 1255 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1256 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1257 1258 if ((r1 & RT2661_INT_CSR_ALL) == 0 && (r2 & RT2661_MCU_INT_ALL) == 0) 1259 return 0; 1260 1261 /* disable interrupts */ 1262 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1263 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1264 1265 softint_schedule(sc->sc_soft_ih); 1266 return 1; 1267 } 1268 1269 static void 1270 rt2661_softintr(void *arg) 1271 { 1272 struct rt2661_softc *sc = arg; 1273 uint32_t r1, r2; 1274 1275 for (;;) { 1276 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1277 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1278 1279 if ((r1 & RT2661_INT_CSR_ALL) == 0 && 1280 (r2 & RT2661_MCU_INT_ALL) == 0) 1281 break; 1282 1283 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1284 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1285 1286 if (r1 & RT2661_MGT_DONE) 1287 rt2661_tx_dma_intr(sc, &sc->mgtq); 1288 1289 if (r1 & RT2661_RX_DONE) 1290 rt2661_rx_intr(sc); 1291 1292 if (r1 & RT2661_TX0_DMA_DONE) 1293 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1294 1295 if (r1 & RT2661_TX1_DMA_DONE) 1296 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1297 1298 if (r1 & RT2661_TX2_DMA_DONE) 1299 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1300 1301 if (r1 & RT2661_TX3_DMA_DONE) 1302 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1303 1304 if (r1 & RT2661_TX_DONE) 1305 rt2661_tx_intr(sc); 1306 1307 if (r2 & RT2661_MCU_CMD_DONE) 1308 rt2661_mcu_cmd_intr(sc); 1309 1310 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1311 rt2661_mcu_beacon_expire(sc); 1312 1313 if (r2 & RT2661_MCU_WAKEUP) 1314 rt2661_mcu_wakeup(sc); 1315 } 1316 1317 /* enable interrupts */ 1318 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1319 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1320 } 1321 1322 /* quickly determine if a given rate is CCK or OFDM */ 1323 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1324 1325 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1326 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1327 1328 /* 1329 * This function is only used by the Rx radiotap code. It returns the rate at 1330 * which a given frame was received. 1331 */ 1332 static uint8_t 1333 rt2661_rxrate(struct rt2661_rx_desc *desc) 1334 { 1335 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1336 /* reverse function of rt2661_plcp_signal */ 1337 switch (desc->rate & 0xf) { 1338 case 0xb: return 12; 1339 case 0xf: return 18; 1340 case 0xa: return 24; 1341 case 0xe: return 36; 1342 case 0x9: return 48; 1343 case 0xd: return 72; 1344 case 0x8: return 96; 1345 case 0xc: return 108; 1346 } 1347 } else { 1348 if (desc->rate == 10) 1349 return 2; 1350 if (desc->rate == 20) 1351 return 4; 1352 if (desc->rate == 55) 1353 return 11; 1354 if (desc->rate == 110) 1355 return 22; 1356 } 1357 return 2; /* should not get there */ 1358 } 1359 1360 /* 1361 * Return the expected ack rate for a frame transmitted at rate `rate'. 1362 * XXX: this should depend on the destination node basic rate set. 1363 */ 1364 static int 1365 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1366 { 1367 switch (rate) { 1368 /* CCK rates */ 1369 case 2: 1370 return 2; 1371 case 4: 1372 case 11: 1373 case 22: 1374 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1375 1376 /* OFDM rates */ 1377 case 12: 1378 case 18: 1379 return 12; 1380 case 24: 1381 case 36: 1382 return 24; 1383 case 48: 1384 case 72: 1385 case 96: 1386 case 108: 1387 return 48; 1388 } 1389 1390 /* default to 1Mbps */ 1391 return 2; 1392 } 1393 1394 /* 1395 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1396 * The function automatically determines the operating mode depending on the 1397 * given rate. `flags' indicates whether short preamble is in use or not. 1398 */ 1399 static uint16_t 1400 rt2661_txtime(int len, int rate, uint32_t flags) 1401 { 1402 uint16_t txtime; 1403 1404 if (RAL_RATE_IS_OFDM(rate)) { 1405 /* IEEE Std 802.11g-2003, pp. 44 */ 1406 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1407 txtime = 16 + 4 + 4 * txtime + 6; 1408 } else { 1409 /* IEEE Std 802.11b-1999, pp. 28 */ 1410 txtime = (16 * len + rate - 1) / rate; 1411 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1412 txtime += 72 + 24; 1413 else 1414 txtime += 144 + 48; 1415 } 1416 return txtime; 1417 } 1418 1419 static uint8_t 1420 rt2661_plcp_signal(int rate) 1421 { 1422 switch (rate) { 1423 /* CCK rates (returned values are device-dependent) */ 1424 case 2: return 0x0; 1425 case 4: return 0x1; 1426 case 11: return 0x2; 1427 case 22: return 0x3; 1428 1429 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1430 case 12: return 0xb; 1431 case 18: return 0xf; 1432 case 24: return 0xa; 1433 case 36: return 0xe; 1434 case 48: return 0x9; 1435 case 72: return 0xd; 1436 case 96: return 0x8; 1437 case 108: return 0xc; 1438 1439 /* unsupported rates (should not get there) */ 1440 default: return 0xff; 1441 } 1442 } 1443 1444 static void 1445 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1446 uint32_t flags, uint16_t xflags, int len, int rate, 1447 const bus_dma_segment_t *segs, int nsegs, int ac) 1448 { 1449 struct ieee80211com *ic = &sc->sc_ic; 1450 uint16_t plcp_length; 1451 int i, remainder; 1452 1453 desc->flags = htole32(flags); 1454 desc->flags |= htole32(len << 16); 1455 1456 desc->xflags = htole16(xflags); 1457 desc->xflags |= htole16(nsegs << 13); 1458 1459 desc->wme = htole16( 1460 RT2661_QID(ac) | 1461 RT2661_AIFSN(2) | 1462 RT2661_LOGCWMIN(4) | 1463 RT2661_LOGCWMAX(10)); 1464 1465 /* 1466 * Remember in which queue this frame was sent. This field is driver 1467 * private data only. It will be made available by the NIC in STA_CSR4 1468 * on Tx interrupts. 1469 */ 1470 desc->qid = ac; 1471 1472 /* setup PLCP fields */ 1473 desc->plcp_signal = rt2661_plcp_signal(rate); 1474 desc->plcp_service = 4; 1475 1476 len += IEEE80211_CRC_LEN; 1477 if (RAL_RATE_IS_OFDM(rate)) { 1478 desc->flags |= htole32(RT2661_TX_OFDM); 1479 1480 plcp_length = len & 0xfff; 1481 desc->plcp_length_hi = plcp_length >> 6; 1482 desc->plcp_length_lo = plcp_length & 0x3f; 1483 } else { 1484 plcp_length = (16 * len + rate - 1) / rate; 1485 if (rate == 22) { 1486 remainder = (16 * len) % 22; 1487 if (remainder != 0 && remainder < 7) 1488 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1489 } 1490 desc->plcp_length_hi = plcp_length >> 8; 1491 desc->plcp_length_lo = plcp_length & 0xff; 1492 1493 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1494 desc->plcp_signal |= 0x08; 1495 } 1496 1497 /* RT2x61 supports scatter with up to 5 segments */ 1498 for (i = 0; i < nsegs; i++) { 1499 desc->addr[i] = htole32(segs[i].ds_addr); 1500 desc->len [i] = htole16(segs[i].ds_len); 1501 } 1502 1503 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1504 } 1505 1506 static int 1507 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1508 struct ieee80211_node *ni) 1509 { 1510 struct ieee80211com *ic = &sc->sc_ic; 1511 struct rt2661_tx_desc *desc; 1512 struct rt2661_tx_data *data; 1513 struct ieee80211_frame *wh; 1514 uint16_t dur; 1515 uint32_t flags = 0; 1516 int rate, error; 1517 1518 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1519 data = &sc->mgtq.data[sc->mgtq.cur]; 1520 1521 /* send mgt frames at the lowest available rate */ 1522 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1523 1524 wh = mtod(m0, struct ieee80211_frame *); 1525 1526 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1527 if (ieee80211_crypto_encap(ic, ni, m0) == NULL) { 1528 m_freem(m0); 1529 return ENOBUFS; 1530 } 1531 1532 /* packet header may have moved, reset our local pointer */ 1533 wh = mtod(m0, struct ieee80211_frame *); 1534 } 1535 1536 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1537 BUS_DMA_NOWAIT); 1538 if (error != 0) { 1539 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1540 error); 1541 m_freem(m0); 1542 return error; 1543 } 1544 1545 if (sc->sc_drvbpf != NULL) { 1546 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1547 1548 tap->wt_flags = 0; 1549 tap->wt_rate = rate; 1550 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1551 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1552 1553 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0, BPF_D_OUT); 1554 } 1555 1556 data->m = m0; 1557 data->ni = ni; 1558 1559 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1560 flags |= RT2661_TX_NEED_ACK; 1561 1562 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1563 sc->sifs; 1564 *(uint16_t *)wh->i_dur = htole16(dur); 1565 1566 /* tell hardware to set timestamp in probe responses */ 1567 if ((wh->i_fc[0] & 1568 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1569 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1570 flags |= RT2661_TX_TIMESTAMP; 1571 } 1572 1573 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1574 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1575 RT2661_QID_MGT); 1576 1577 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1578 BUS_DMASYNC_PREWRITE); 1579 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1580 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1581 BUS_DMASYNC_PREWRITE); 1582 1583 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1584 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1585 1586 /* kick mgt */ 1587 sc->mgtq.queued++; 1588 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1589 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1590 1591 return 0; 1592 } 1593 1594 /* 1595 * Build a RTS control frame. 1596 */ 1597 static struct mbuf * 1598 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1599 uint16_t dur) 1600 { 1601 struct ieee80211_frame_rts *rts; 1602 struct mbuf *m; 1603 1604 MGETHDR(m, M_DONTWAIT, MT_DATA); 1605 if (m == NULL) { 1606 sc->sc_ic.ic_stats.is_tx_nobuf++; 1607 aprint_error_dev(sc->sc_dev, "could not allocate RTS frame\n"); 1608 return NULL; 1609 } 1610 1611 rts = mtod(m, struct ieee80211_frame_rts *); 1612 1613 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1614 IEEE80211_FC0_SUBTYPE_RTS; 1615 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1616 *(uint16_t *)rts->i_dur = htole16(dur); 1617 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1618 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1619 1620 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1621 1622 return m; 1623 } 1624 1625 static int 1626 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1627 struct ieee80211_node *ni, int ac) 1628 { 1629 struct ieee80211com *ic = &sc->sc_ic; 1630 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1631 struct rt2661_tx_desc *desc; 1632 struct rt2661_tx_data *data; 1633 struct ieee80211_frame *wh; 1634 struct ieee80211_key *k; 1635 struct mbuf *mnew; 1636 uint16_t dur; 1637 uint32_t flags = 0; 1638 int rate, useprot, error, tid; 1639 1640 wh = mtod(m0, struct ieee80211_frame *); 1641 1642 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1643 rate = ic->ic_sup_rates[ic->ic_curmode]. 1644 rs_rates[ic->ic_fixed_rate]; 1645 } else 1646 rate = ni->ni_rates.rs_rates[ni->ni_txrate]; 1647 rate &= IEEE80211_RATE_VAL; 1648 if (rate == 0) 1649 rate = 2; /* XXX should not happen */ 1650 1651 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1652 k = ieee80211_crypto_encap(ic, ni, m0); 1653 if (k == NULL) { 1654 m_freem(m0); 1655 return ENOBUFS; 1656 } 1657 1658 /* packet header may have moved, reset our local pointer */ 1659 wh = mtod(m0, struct ieee80211_frame *); 1660 } 1661 1662 /* 1663 * Packet Bursting: backoff after ppb=8 frames to give other STAs a 1664 * chance to contend for the wireless medium. 1665 */ 1666 tid = WME_AC_TO_TID(M_WME_GETAC(m0)); 1667 if (ic->ic_opmode == IEEE80211_M_STA && (ni->ni_txseqs[tid] & 7)) 1668 flags |= RT2661_TX_IFS_SIFS; 1669 1670 /* 1671 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1672 * for directed frames only when the length of the MPDU is greater 1673 * than the length threshold indicated by" ic_rtsthreshold. 1674 * 1675 * IEEE Std 802.11-2003g, pp 13: "ERP STAs shall use protection 1676 * mechanism (such as RTS/CTS or CTS-to-self) for ERP-OFDM MPDUs of 1677 * type Data or an MMPDU". 1678 */ 1679 useprot = !IEEE80211_IS_MULTICAST(wh->i_addr1) && 1680 (m0->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1681 ((ic->ic_flags & IEEE80211_F_USEPROT) && RAL_RATE_IS_OFDM(rate))); 1682 if (useprot) { 1683 struct mbuf *m; 1684 int rtsrate, ackrate; 1685 1686 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1687 ackrate = rt2661_ack_rate(ic, rate); 1688 1689 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1690 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1691 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1692 3 * sc->sifs; 1693 1694 m = rt2661_get_rts(sc, wh, dur); 1695 if (m == NULL) { 1696 aprint_error_dev(sc->sc_dev, "could not allocate RTS " 1697 "frame\n"); 1698 m_freem(m0); 1699 return ENOBUFS; 1700 } 1701 1702 desc = &txq->desc[txq->cur]; 1703 data = &txq->data[txq->cur]; 1704 1705 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1706 BUS_DMA_NOWAIT); 1707 if (error != 0) { 1708 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1709 m_freem(m); 1710 m_freem(m0); 1711 return error; 1712 } 1713 1714 /* avoid multiple free() of the same node for each fragment */ 1715 ieee80211_ref_node(ni); 1716 1717 data->m = m; 1718 data->ni = ni; 1719 1720 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1721 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, 1722 data->map->dm_segs, data->map->dm_nsegs, ac); 1723 1724 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1725 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1726 bus_dmamap_sync(sc->sc_dmat, txq->map, 1727 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1728 BUS_DMASYNC_PREWRITE); 1729 1730 txq->queued++; 1731 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1732 1733 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS_SIFS; 1734 } 1735 1736 data = &txq->data[txq->cur]; 1737 desc = &txq->desc[txq->cur]; 1738 1739 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1740 BUS_DMA_NOWAIT); 1741 if (error != 0 && error != EFBIG) { 1742 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1743 error); 1744 m_freem(m0); 1745 return error; 1746 } 1747 if (error != 0) { 1748 /* too many fragments, linearize */ 1749 1750 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1751 if (mnew == NULL) { 1752 m_freem(m0); 1753 return ENOMEM; 1754 } 1755 1756 M_COPY_PKTHDR(mnew, m0); 1757 if (m0->m_pkthdr.len > MHLEN) { 1758 MCLGET(mnew, M_DONTWAIT); 1759 if (!(mnew->m_flags & M_EXT)) { 1760 m_freem(m0); 1761 m_freem(mnew); 1762 return ENOMEM; 1763 } 1764 } 1765 1766 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1767 m_freem(m0); 1768 mnew->m_len = mnew->m_pkthdr.len; 1769 m0 = mnew; 1770 1771 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1772 BUS_DMA_NOWAIT); 1773 if (error != 0) { 1774 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1775 m_freem(m0); 1776 return error; 1777 } 1778 1779 /* packet header have moved, reset our local pointer */ 1780 wh = mtod(m0, struct ieee80211_frame *); 1781 } 1782 1783 if (sc->sc_drvbpf != NULL) { 1784 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1785 1786 tap->wt_flags = 0; 1787 tap->wt_rate = rate; 1788 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1789 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1790 1791 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0, BPF_D_OUT); 1792 } 1793 1794 data->m = m0; 1795 data->ni = ni; 1796 1797 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1798 flags |= RT2661_TX_NEED_ACK; 1799 1800 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1801 ic->ic_flags) + sc->sifs; 1802 *(uint16_t *)wh->i_dur = htole16(dur); 1803 } 1804 1805 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1806 data->map->dm_segs, data->map->dm_nsegs, ac); 1807 1808 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1809 BUS_DMASYNC_PREWRITE); 1810 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1811 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1812 1813 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1814 m0->m_pkthdr.len, txq->cur, rate)); 1815 1816 /* kick Tx */ 1817 txq->queued++; 1818 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1819 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1820 1821 return 0; 1822 } 1823 1824 static void 1825 rt2661_start(struct ifnet *ifp) 1826 { 1827 struct rt2661_softc *sc = ifp->if_softc; 1828 struct ieee80211com *ic = &sc->sc_ic; 1829 struct mbuf *m0; 1830 struct ether_header *eh; 1831 struct ieee80211_node *ni = NULL; 1832 1833 /* 1834 * net80211 may still try to send management frames even if the 1835 * IFF_RUNNING flag is not set... 1836 */ 1837 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1838 return; 1839 1840 for (;;) { 1841 IF_POLL(&ic->ic_mgtq, m0); 1842 if (m0 != NULL) { 1843 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1844 ifp->if_flags |= IFF_OACTIVE; 1845 break; 1846 } 1847 IF_DEQUEUE(&ic->ic_mgtq, m0); 1848 if (m0 == NULL) 1849 break; 1850 1851 ni = M_GETCTX(m0, struct ieee80211_node *); 1852 M_CLEARCTX(m0); 1853 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 1854 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1855 break; 1856 1857 } else { 1858 IF_POLL(&ifp->if_snd, m0); 1859 if (m0 == NULL || ic->ic_state != IEEE80211_S_RUN) 1860 break; 1861 1862 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1863 /* there is no place left in this ring */ 1864 ifp->if_flags |= IFF_OACTIVE; 1865 break; 1866 } 1867 1868 IFQ_DEQUEUE(&ifp->if_snd, m0); 1869 1870 if (m0->m_len < sizeof (struct ether_header) && 1871 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1872 continue; 1873 1874 eh = mtod(m0, struct ether_header *); 1875 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1876 if (ni == NULL) { 1877 m_freem(m0); 1878 ifp->if_oerrors++; 1879 continue; 1880 } 1881 1882 bpf_mtap(ifp, m0, BPF_D_OUT); 1883 m0 = ieee80211_encap(ic, m0, ni); 1884 if (m0 == NULL) { 1885 ieee80211_free_node(ni); 1886 ifp->if_oerrors++; 1887 continue; 1888 } 1889 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 1890 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1891 if (ni != NULL) 1892 ieee80211_free_node(ni); 1893 ifp->if_oerrors++; 1894 break; 1895 } 1896 } 1897 1898 sc->sc_tx_timer = 5; 1899 ifp->if_timer = 1; 1900 } 1901 } 1902 1903 static void 1904 rt2661_watchdog(struct ifnet *ifp) 1905 { 1906 struct rt2661_softc *sc = ifp->if_softc; 1907 1908 ifp->if_timer = 0; 1909 1910 if (sc->sc_tx_timer > 0) { 1911 if (--sc->sc_tx_timer == 0) { 1912 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1913 rt2661_init(ifp); 1914 ifp->if_oerrors++; 1915 return; 1916 } 1917 ifp->if_timer = 1; 1918 } 1919 1920 ieee80211_watchdog(&sc->sc_ic); 1921 } 1922 1923 /* 1924 * This function allows for fast channel switching in monitor mode (used by 1925 * kismet). In IBSS mode, we must explicitly reset the interface to 1926 * generate a new beacon frame. 1927 */ 1928 static int 1929 rt2661_reset(struct ifnet *ifp) 1930 { 1931 struct rt2661_softc *sc = ifp->if_softc; 1932 struct ieee80211com *ic = &sc->sc_ic; 1933 1934 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1935 return ENETRESET; 1936 1937 rt2661_set_chan(sc, ic->ic_curchan); 1938 1939 return 0; 1940 } 1941 1942 static int 1943 rt2661_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1944 { 1945 struct rt2661_softc *sc = ifp->if_softc; 1946 struct ieee80211com *ic = &sc->sc_ic; 1947 int s, error = 0; 1948 1949 s = splnet(); 1950 1951 switch (cmd) { 1952 case SIOCSIFFLAGS: 1953 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1954 break; 1955 if (ifp->if_flags & IFF_UP) { 1956 if (ifp->if_flags & IFF_RUNNING) 1957 rt2661_update_promisc(sc); 1958 else 1959 rt2661_init(ifp); 1960 } else { 1961 if (ifp->if_flags & IFF_RUNNING) 1962 rt2661_stop(ifp, 1); 1963 } 1964 break; 1965 1966 case SIOCADDMULTI: 1967 case SIOCDELMULTI: 1968 /* XXX no h/w multicast filter? --dyoung */ 1969 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 1970 error = 0; 1971 break; 1972 1973 case SIOCS80211CHANNEL: 1974 /* 1975 * This allows for fast channel switching in monitor mode 1976 * (used by kismet). In IBSS mode, we must explicitly reset 1977 * the interface to generate a new beacon frame. 1978 */ 1979 error = ieee80211_ioctl(ic, cmd, data); 1980 if (error == ENETRESET && 1981 ic->ic_opmode == IEEE80211_M_MONITOR) { 1982 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1983 (IFF_UP | IFF_RUNNING)) 1984 rt2661_set_chan(sc, ic->ic_ibss_chan); 1985 error = 0; 1986 } 1987 break; 1988 1989 default: 1990 error = ieee80211_ioctl(ic, cmd, data); 1991 1992 } 1993 1994 if (error == ENETRESET) { 1995 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1996 (IFF_UP | IFF_RUNNING)) 1997 rt2661_init(ifp); 1998 error = 0; 1999 } 2000 2001 splx(s); 2002 2003 return error; 2004 } 2005 2006 static void 2007 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 2008 { 2009 uint32_t tmp; 2010 int ntries; 2011 2012 for (ntries = 0; ntries < 100; ntries++) { 2013 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2014 break; 2015 DELAY(1); 2016 } 2017 if (ntries == 100) { 2018 aprint_error_dev(sc->sc_dev, "could not write to BBP\n"); 2019 return; 2020 } 2021 2022 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 2023 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 2024 2025 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 2026 } 2027 2028 static uint8_t 2029 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2030 { 2031 uint32_t val; 2032 int ntries; 2033 2034 for (ntries = 0; ntries < 100; ntries++) { 2035 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2036 break; 2037 DELAY(1); 2038 } 2039 if (ntries == 100) { 2040 aprint_error_dev(sc->sc_dev, "could not read from BBP\n"); 2041 return 0; 2042 } 2043 2044 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2045 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2046 2047 for (ntries = 0; ntries < 100; ntries++) { 2048 val = RAL_READ(sc, RT2661_PHY_CSR3); 2049 if (!(val & RT2661_BBP_BUSY)) 2050 return val & 0xff; 2051 DELAY(1); 2052 } 2053 2054 aprint_error_dev(sc->sc_dev, "could not read from BBP\n"); 2055 return 0; 2056 } 2057 2058 static void 2059 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2060 { 2061 uint32_t tmp; 2062 int ntries; 2063 2064 for (ntries = 0; ntries < 100; ntries++) { 2065 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2066 break; 2067 DELAY(1); 2068 } 2069 if (ntries == 100) { 2070 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2071 return; 2072 } 2073 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2074 (reg & 3); 2075 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2076 2077 /* remember last written value in sc */ 2078 sc->rf_regs[reg] = val; 2079 2080 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2081 } 2082 2083 static int 2084 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2085 { 2086 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2087 return EIO; /* there is already a command pending */ 2088 2089 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2090 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2091 2092 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2093 2094 return 0; 2095 } 2096 2097 static void 2098 rt2661_select_antenna(struct rt2661_softc *sc) 2099 { 2100 uint8_t bbp4, bbp77; 2101 uint32_t tmp; 2102 2103 bbp4 = rt2661_bbp_read(sc, 4); 2104 bbp77 = rt2661_bbp_read(sc, 77); 2105 2106 /* TBD */ 2107 2108 /* make sure Rx is disabled before switching antenna */ 2109 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2110 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2111 2112 rt2661_bbp_write(sc, 4, bbp4); 2113 rt2661_bbp_write(sc, 77, bbp77); 2114 2115 /* restore Rx filter */ 2116 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2117 } 2118 2119 /* 2120 * Enable multi-rate retries for frames sent at OFDM rates. 2121 * In 802.11b/g mode, allow fallback to CCK rates. 2122 */ 2123 static void 2124 rt2661_enable_mrr(struct rt2661_softc *sc) 2125 { 2126 struct ieee80211com *ic = &sc->sc_ic; 2127 uint32_t tmp; 2128 2129 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2130 2131 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2132 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2133 tmp |= RT2661_MRR_CCK_FALLBACK; 2134 tmp |= RT2661_MRR_ENABLED; 2135 2136 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2137 } 2138 2139 static void 2140 rt2661_set_txpreamble(struct rt2661_softc *sc) 2141 { 2142 uint32_t tmp; 2143 2144 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2145 2146 tmp &= ~RT2661_SHORT_PREAMBLE; 2147 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2148 tmp |= RT2661_SHORT_PREAMBLE; 2149 2150 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2151 } 2152 2153 static void 2154 rt2661_set_basicrates(struct rt2661_softc *sc, 2155 const struct ieee80211_rateset *rs) 2156 { 2157 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2158 uint32_t mask = 0; 2159 uint8_t rate; 2160 int i, j; 2161 2162 for (i = 0; i < rs->rs_nrates; i++) { 2163 rate = rs->rs_rates[i]; 2164 2165 if (!(rate & IEEE80211_RATE_BASIC)) 2166 continue; 2167 2168 /* 2169 * Find h/w rate index. We know it exists because the rate 2170 * set has already been negotiated. 2171 */ 2172 for (j = 0; ieee80211_std_rateset_11g.rs_rates[j] != RV(rate); j++); 2173 2174 mask |= 1 << j; 2175 } 2176 2177 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2178 2179 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2180 #undef RV 2181 } 2182 2183 /* 2184 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2185 * driver. 2186 */ 2187 static void 2188 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2189 { 2190 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2191 uint32_t tmp; 2192 2193 /* update all BBP registers that depend on the band */ 2194 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2195 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2196 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2197 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2198 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2199 } 2200 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2201 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2202 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2203 } 2204 2205 sc->bbp17 = bbp17; 2206 rt2661_bbp_write(sc, 17, bbp17); 2207 rt2661_bbp_write(sc, 96, bbp96); 2208 rt2661_bbp_write(sc, 104, bbp104); 2209 2210 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2211 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2212 rt2661_bbp_write(sc, 75, 0x80); 2213 rt2661_bbp_write(sc, 86, 0x80); 2214 rt2661_bbp_write(sc, 88, 0x80); 2215 } 2216 2217 rt2661_bbp_write(sc, 35, bbp35); 2218 rt2661_bbp_write(sc, 97, bbp97); 2219 rt2661_bbp_write(sc, 98, bbp98); 2220 2221 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2222 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2223 if (IEEE80211_IS_CHAN_2GHZ(c)) 2224 tmp |= RT2661_PA_PE_2GHZ; 2225 else 2226 tmp |= RT2661_PA_PE_5GHZ; 2227 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2228 2229 /* 802.11a uses a 16 microseconds short interframe space */ 2230 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10; 2231 } 2232 2233 static void 2234 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2235 { 2236 struct ieee80211com *ic = &sc->sc_ic; 2237 const struct rfprog *rfprog; 2238 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2239 int8_t power; 2240 u_int i, chan; 2241 2242 chan = ieee80211_chan2ieee(ic, c); 2243 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2244 return; 2245 2246 /* select the appropriate RF settings based on what EEPROM says */ 2247 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2248 2249 /* find the settings for this channel (we know it exists) */ 2250 for (i = 0; rfprog[i].chan != chan; i++); 2251 2252 power = sc->txpow[i]; 2253 if (power < 0) { 2254 bbp94 += power; 2255 power = 0; 2256 } else if (power > 31) { 2257 bbp94 += power - 31; 2258 power = 31; 2259 } 2260 2261 /* 2262 * If we've yet to select a channel, or we are switching from the 2263 * 2GHz band to the 5GHz band or vice-versa, BBP registers need to 2264 * be reprogrammed. 2265 */ 2266 if (sc->sc_curchan == NULL || c->ic_flags != sc->sc_curchan->ic_flags) { 2267 rt2661_select_band(sc, c); 2268 rt2661_select_antenna(sc); 2269 } 2270 sc->sc_curchan = c; 2271 2272 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2273 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2274 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2275 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2276 2277 DELAY(200); 2278 2279 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2280 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2281 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2282 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2283 2284 DELAY(200); 2285 2286 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2287 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2288 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2289 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2290 2291 /* enable smart mode for MIMO-capable RFs */ 2292 bbp3 = rt2661_bbp_read(sc, 3); 2293 2294 bbp3 &= ~RT2661_SMART_MODE; 2295 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2296 bbp3 |= RT2661_SMART_MODE; 2297 2298 rt2661_bbp_write(sc, 3, bbp3); 2299 2300 if (bbp94 != RT2661_BBPR94_DEFAULT) 2301 rt2661_bbp_write(sc, 94, bbp94); 2302 2303 /* 5GHz radio needs a 1ms delay here */ 2304 if (IEEE80211_IS_CHAN_5GHZ(c)) 2305 DELAY(1000); 2306 } 2307 2308 static void 2309 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2310 { 2311 uint32_t tmp; 2312 2313 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2314 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2315 2316 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2317 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2318 } 2319 2320 static void 2321 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2322 { 2323 uint32_t tmp; 2324 2325 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2326 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2327 2328 tmp = addr[4] | addr[5] << 8 | 0xff << 16; 2329 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2330 } 2331 2332 static void 2333 rt2661_update_promisc(struct rt2661_softc *sc) 2334 { 2335 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2336 uint32_t tmp; 2337 2338 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2339 2340 tmp &= ~RT2661_DROP_NOT_TO_ME; 2341 if (!(ifp->if_flags & IFF_PROMISC)) 2342 tmp |= RT2661_DROP_NOT_TO_ME; 2343 2344 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2345 2346 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2347 "entering" : "leaving")); 2348 } 2349 2350 #if 0 2351 /* 2352 * Update QoS (802.11e) settings for each h/w Tx ring. 2353 */ 2354 static int 2355 rt2661_wme_update(struct ieee80211com *ic) 2356 { 2357 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2358 const struct wmeParams *wmep; 2359 2360 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2361 2362 /* XXX: not sure about shifts. */ 2363 /* XXX: the reference driver plays with AC_VI settings too. */ 2364 2365 /* update TxOp */ 2366 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2367 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2368 wmep[WME_AC_BK].wmep_txopLimit); 2369 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2370 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2371 wmep[WME_AC_VO].wmep_txopLimit); 2372 2373 /* update CWmin */ 2374 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2375 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2376 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2377 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2378 wmep[WME_AC_VO].wmep_logcwmin); 2379 2380 /* update CWmax */ 2381 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2382 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2383 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2384 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2385 wmep[WME_AC_VO].wmep_logcwmax); 2386 2387 /* update Aifsn */ 2388 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2389 wmep[WME_AC_BE].wmep_aifsn << 12 | 2390 wmep[WME_AC_BK].wmep_aifsn << 8 | 2391 wmep[WME_AC_VI].wmep_aifsn << 4 | 2392 wmep[WME_AC_VO].wmep_aifsn); 2393 2394 return 0; 2395 } 2396 #endif 2397 2398 static void 2399 rt2661_updateslot(struct ifnet *ifp) 2400 { 2401 struct rt2661_softc *sc = ifp->if_softc; 2402 struct ieee80211com *ic = &sc->sc_ic; 2403 2404 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2405 /* 2406 * In HostAP mode, we defer setting of new slot time until 2407 * updated ERP Information Element has propagated to all 2408 * associated STAs. 2409 */ 2410 sc->sc_flags |= RT2661_UPDATE_SLOT; 2411 } else 2412 rt2661_set_slottime(sc); 2413 } 2414 2415 static void 2416 rt2661_set_slottime(struct rt2661_softc *sc) 2417 { 2418 struct ieee80211com *ic = &sc->sc_ic; 2419 uint8_t slottime; 2420 uint32_t tmp; 2421 2422 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2423 2424 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2425 tmp = (tmp & ~0xff) | slottime; 2426 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2427 2428 DPRINTF(("setting slot time to %uus\n", slottime)); 2429 } 2430 2431 static const char * 2432 rt2661_get_rf(int rev) 2433 { 2434 switch (rev) { 2435 case RT2661_RF_5225: return "RT5225"; 2436 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2437 case RT2661_RF_2527: return "RT2527"; 2438 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2439 default: return "unknown"; 2440 } 2441 } 2442 2443 static void 2444 rt2661_read_eeprom(struct rt2661_softc *sc) 2445 { 2446 struct ieee80211com *ic = &sc->sc_ic; 2447 uint16_t val; 2448 int i; 2449 2450 /* read MAC address */ 2451 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2452 ic->ic_myaddr[0] = val & 0xff; 2453 ic->ic_myaddr[1] = val >> 8; 2454 2455 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2456 ic->ic_myaddr[2] = val & 0xff; 2457 ic->ic_myaddr[3] = val >> 8; 2458 2459 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2460 ic->ic_myaddr[4] = val & 0xff; 2461 ic->ic_myaddr[5] = val >> 8; 2462 2463 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2464 /* XXX: test if different from 0xffff? */ 2465 sc->rf_rev = (val >> 11) & 0x1f; 2466 sc->hw_radio = (val >> 10) & 0x1; 2467 sc->rx_ant = (val >> 4) & 0x3; 2468 sc->tx_ant = (val >> 2) & 0x3; 2469 sc->nb_ant = val & 0x3; 2470 2471 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2472 2473 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2474 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2475 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2476 2477 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2478 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2479 2480 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2481 if ((val & 0xff) != 0xff) 2482 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2483 2484 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2485 if ((val & 0xff) != 0xff) 2486 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2487 2488 /* adjust RSSI correction for external low-noise amplifier */ 2489 if (sc->ext_2ghz_lna) 2490 sc->rssi_2ghz_corr -= 14; 2491 if (sc->ext_5ghz_lna) 2492 sc->rssi_5ghz_corr -= 14; 2493 2494 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2495 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2496 2497 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2498 if ((val >> 8) != 0xff) 2499 sc->rfprog = (val >> 8) & 0x3; 2500 if ((val & 0xff) != 0xff) 2501 sc->rffreq = val & 0xff; 2502 2503 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2504 2505 /* read Tx power for all a/b/g channels */ 2506 for (i = 0; i < 19; i++) { 2507 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2508 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2509 DPRINTF(("Channel=%d Tx power=%d\n", 2510 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2511 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2512 DPRINTF(("Channel=%d Tx power=%d\n", 2513 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2514 } 2515 2516 /* read vendor-specific BBP values */ 2517 for (i = 0; i < 16; i++) { 2518 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2519 if (val == 0 || val == 0xffff) 2520 continue; /* skip invalid entries */ 2521 sc->bbp_prom[i].reg = val >> 8; 2522 sc->bbp_prom[i].val = val & 0xff; 2523 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2524 sc->bbp_prom[i].val)); 2525 } 2526 } 2527 2528 static int 2529 rt2661_bbp_init(struct rt2661_softc *sc) 2530 { 2531 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2532 int i, ntries; 2533 uint8_t val; 2534 2535 /* wait for BBP to be ready */ 2536 for (ntries = 0; ntries < 100; ntries++) { 2537 val = rt2661_bbp_read(sc, 0); 2538 if (val != 0 && val != 0xff) 2539 break; 2540 DELAY(100); 2541 } 2542 if (ntries == 100) { 2543 aprint_error_dev(sc->sc_dev, "timeout waiting for BBP\n"); 2544 return EIO; 2545 } 2546 2547 /* initialize BBP registers to default values */ 2548 for (i = 0; i < N(rt2661_def_bbp); i++) { 2549 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2550 rt2661_def_bbp[i].val); 2551 } 2552 2553 /* write vendor-specific BBP values (from EEPROM) */ 2554 for (i = 0; i < 16; i++) { 2555 if (sc->bbp_prom[i].reg == 0) 2556 continue; 2557 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2558 } 2559 2560 return 0; 2561 #undef N 2562 } 2563 2564 static int 2565 rt2661_init(struct ifnet *ifp) 2566 { 2567 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2568 struct rt2661_softc *sc = ifp->if_softc; 2569 struct ieee80211com *ic = &sc->sc_ic; 2570 const char *name = NULL; /* make lint happy */ 2571 uint8_t *ucode; 2572 size_t size; 2573 uint32_t tmp, star[3]; 2574 int i, ntries; 2575 firmware_handle_t fh; 2576 2577 /* for CardBus, power on the socket */ 2578 if (!(sc->sc_flags & RT2661_ENABLED)) { 2579 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2580 aprint_error_dev(sc->sc_dev, "could not enable device\n"); 2581 return EIO; 2582 } 2583 sc->sc_flags |= RT2661_ENABLED; 2584 } 2585 2586 rt2661_stop(ifp, 0); 2587 2588 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2589 switch (sc->sc_id) { 2590 case PCI_PRODUCT_RALINK_RT2561: 2591 name = "ral-rt2561"; 2592 break; 2593 case PCI_PRODUCT_RALINK_RT2561S: 2594 name = "ral-rt2561s"; 2595 break; 2596 case PCI_PRODUCT_RALINK_RT2661: 2597 name = "ral-rt2661"; 2598 break; 2599 } 2600 2601 if (firmware_open("ral", name, &fh) != 0) { 2602 aprint_error_dev(sc->sc_dev, "could not open microcode %s\n", name); 2603 rt2661_stop(ifp, 1); 2604 return EIO; 2605 } 2606 2607 size = firmware_get_size(fh); 2608 if (!(ucode = firmware_malloc(size))) { 2609 aprint_error_dev(sc->sc_dev, "could not alloc microcode memory\n"); 2610 firmware_close(fh); 2611 rt2661_stop(ifp, 1); 2612 return ENOMEM; 2613 } 2614 2615 if (firmware_read(fh, 0, ucode, size) != 0) { 2616 aprint_error_dev(sc->sc_dev, "could not read microcode %s\n", name); 2617 firmware_free(ucode, size); 2618 firmware_close(fh); 2619 rt2661_stop(ifp, 1); 2620 return EIO; 2621 } 2622 2623 if (rt2661_load_microcode(sc, ucode, size) != 0) { 2624 aprint_error_dev(sc->sc_dev, "could not load 8051 microcode\n"); 2625 firmware_free(ucode, size); 2626 firmware_close(fh); 2627 rt2661_stop(ifp, 1); 2628 return EIO; 2629 } 2630 2631 firmware_free(ucode, size); 2632 firmware_close(fh); 2633 sc->sc_flags |= RT2661_FWLOADED; 2634 } 2635 2636 /* initialize Tx rings */ 2637 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2638 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2639 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2640 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2641 2642 /* initialize Mgt ring */ 2643 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2644 2645 /* initialize Rx ring */ 2646 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2647 2648 /* initialize Tx rings sizes */ 2649 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2650 RT2661_TX_RING_COUNT << 24 | 2651 RT2661_TX_RING_COUNT << 16 | 2652 RT2661_TX_RING_COUNT << 8 | 2653 RT2661_TX_RING_COUNT); 2654 2655 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2656 RT2661_TX_DESC_WSIZE << 16 | 2657 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2658 RT2661_MGT_RING_COUNT); 2659 2660 /* initialize Rx rings */ 2661 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2662 RT2661_RX_DESC_BACK << 16 | 2663 RT2661_RX_DESC_WSIZE << 8 | 2664 RT2661_RX_RING_COUNT); 2665 2666 /* XXX: some magic here */ 2667 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2668 2669 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2670 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2671 2672 /* load base address of Rx ring */ 2673 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2674 2675 /* initialize MAC registers to default values */ 2676 for (i = 0; i < N(rt2661_def_mac); i++) 2677 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2678 2679 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2680 rt2661_set_macaddr(sc, ic->ic_myaddr); 2681 2682 /* set host ready */ 2683 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2684 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2685 2686 /* wait for BBP/RF to wakeup */ 2687 for (ntries = 0; ntries < 1000; ntries++) { 2688 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2689 break; 2690 DELAY(1000); 2691 } 2692 if (ntries == 1000) { 2693 printf("timeout waiting for BBP/RF to wakeup\n"); 2694 rt2661_stop(ifp, 1); 2695 return EIO; 2696 } 2697 2698 if (rt2661_bbp_init(sc) != 0) { 2699 rt2661_stop(ifp, 1); 2700 return EIO; 2701 } 2702 2703 /* select default channel */ 2704 sc->sc_curchan = ic->ic_curchan; 2705 rt2661_select_band(sc, sc->sc_curchan); 2706 rt2661_select_antenna(sc); 2707 rt2661_set_chan(sc, sc->sc_curchan); 2708 2709 /* update Rx filter */ 2710 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2711 2712 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2713 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2714 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2715 RT2661_DROP_ACKCTS; 2716 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2717 tmp |= RT2661_DROP_TODS; 2718 if (!(ifp->if_flags & IFF_PROMISC)) 2719 tmp |= RT2661_DROP_NOT_TO_ME; 2720 } 2721 2722 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2723 2724 /* clear STA registers */ 2725 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, star, N(star)); 2726 2727 /* initialize ASIC */ 2728 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2729 2730 /* clear any pending interrupt */ 2731 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2732 2733 /* enable interrupts */ 2734 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2735 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2736 2737 /* kick Rx */ 2738 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2739 2740 ifp->if_flags &= ~IFF_OACTIVE; 2741 ifp->if_flags |= IFF_RUNNING; 2742 2743 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2744 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2745 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2746 } else 2747 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2748 2749 return 0; 2750 #undef N 2751 } 2752 2753 static void 2754 rt2661_stop(struct ifnet *ifp, int disable) 2755 { 2756 struct rt2661_softc *sc = ifp->if_softc; 2757 struct ieee80211com *ic = &sc->sc_ic; 2758 uint32_t tmp; 2759 2760 sc->sc_tx_timer = 0; 2761 ifp->if_timer = 0; 2762 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2763 2764 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2765 2766 /* abort Tx (for all 5 Tx rings) */ 2767 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2768 2769 /* disable Rx (value remains after reset!) */ 2770 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2771 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2772 2773 /* reset ASIC */ 2774 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2775 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2776 2777 /* disable interrupts */ 2778 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2779 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2780 2781 /* clear any pending interrupt */ 2782 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2783 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2784 2785 /* reset Tx and Rx rings */ 2786 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2787 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2788 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2789 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2790 rt2661_reset_tx_ring(sc, &sc->mgtq); 2791 rt2661_reset_rx_ring(sc, &sc->rxq); 2792 2793 /* for CardBus, power down the socket */ 2794 if (disable && sc->sc_disable != NULL) { 2795 if (sc->sc_flags & RT2661_ENABLED) { 2796 (*sc->sc_disable)(sc); 2797 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2798 } 2799 } 2800 } 2801 2802 static int 2803 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2804 { 2805 int ntries; 2806 2807 /* reset 8051 */ 2808 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2809 2810 /* cancel any pending Host to MCU command */ 2811 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2812 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2813 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2814 2815 /* write 8051's microcode */ 2816 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2817 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2818 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2819 2820 /* kick 8051's ass */ 2821 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2822 2823 /* wait for 8051 to initialize */ 2824 for (ntries = 0; ntries < 500; ntries++) { 2825 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2826 break; 2827 DELAY(100); 2828 } 2829 if (ntries == 500) { 2830 printf("timeout waiting for MCU to initialize\n"); 2831 return EIO; 2832 } 2833 return 0; 2834 } 2835 2836 /* 2837 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2838 * false CCA count. This function is called periodically (every seconds) when 2839 * in the RUN state. Values taken from the reference driver. 2840 */ 2841 static void 2842 rt2661_rx_tune(struct rt2661_softc *sc) 2843 { 2844 uint8_t bbp17; 2845 uint16_t cca; 2846 int lo, hi, dbm; 2847 2848 /* 2849 * Tuning range depends on operating band and on the presence of an 2850 * external low-noise amplifier. 2851 */ 2852 lo = 0x20; 2853 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2854 lo += 0x08; 2855 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2856 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2857 lo += 0x10; 2858 hi = lo + 0x20; 2859 2860 dbm = sc->avg_rssi; 2861 /* retrieve false CCA count since last call (clear on read) */ 2862 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2863 2864 DPRINTFN(2, ("RSSI=%ddBm false CCA=%d\n", dbm, cca)); 2865 2866 if (dbm < -74) { 2867 /* very bad RSSI, tune using false CCA count */ 2868 bbp17 = sc->bbp17; /* current value */ 2869 2870 hi -= 2 * (-74 - dbm); 2871 if (hi < lo) 2872 hi = lo; 2873 2874 if (bbp17 > hi) 2875 bbp17 = hi; 2876 else if (cca > 512) 2877 bbp17 = min(bbp17 + 1, hi); 2878 else if (cca < 100) 2879 bbp17 = max(bbp17 - 1, lo); 2880 2881 } else if (dbm < -66) { 2882 bbp17 = lo + 0x08; 2883 } else if (dbm < -58) { 2884 bbp17 = lo + 0x10; 2885 } else if (dbm < -35) { 2886 bbp17 = hi; 2887 } else { /* very good RSSI >= -35dBm */ 2888 bbp17 = 0x60; /* very low sensitivity */ 2889 } 2890 2891 if (bbp17 != sc->bbp17) { 2892 DPRINTF(("BBP17 %x->%x\n", sc->bbp17, bbp17)); 2893 rt2661_bbp_write(sc, 17, bbp17); 2894 sc->bbp17 = bbp17; 2895 } 2896 } 2897 2898 #ifdef notyet 2899 /* 2900 * Enter/Leave radar detection mode. 2901 * This is for 802.11h additional regulatory domains. 2902 */ 2903 static void 2904 rt2661_radar_start(struct rt2661_softc *sc) 2905 { 2906 uint32_t tmp; 2907 2908 /* disable Rx */ 2909 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2910 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2911 2912 rt2661_bbp_write(sc, 82, 0x20); 2913 rt2661_bbp_write(sc, 83, 0x00); 2914 rt2661_bbp_write(sc, 84, 0x40); 2915 2916 /* save current BBP registers values */ 2917 sc->bbp18 = rt2661_bbp_read(sc, 18); 2918 sc->bbp21 = rt2661_bbp_read(sc, 21); 2919 sc->bbp22 = rt2661_bbp_read(sc, 22); 2920 sc->bbp16 = rt2661_bbp_read(sc, 16); 2921 sc->bbp17 = rt2661_bbp_read(sc, 17); 2922 sc->bbp64 = rt2661_bbp_read(sc, 64); 2923 2924 rt2661_bbp_write(sc, 18, 0xff); 2925 rt2661_bbp_write(sc, 21, 0x3f); 2926 rt2661_bbp_write(sc, 22, 0x3f); 2927 rt2661_bbp_write(sc, 16, 0xbd); 2928 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2929 rt2661_bbp_write(sc, 64, 0x21); 2930 2931 /* restore Rx filter */ 2932 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2933 } 2934 2935 static int 2936 rt2661_radar_stop(struct rt2661_softc *sc) 2937 { 2938 uint8_t bbp66; 2939 2940 /* read radar detection result */ 2941 bbp66 = rt2661_bbp_read(sc, 66); 2942 2943 /* restore BBP registers values */ 2944 rt2661_bbp_write(sc, 16, sc->bbp16); 2945 rt2661_bbp_write(sc, 17, sc->bbp17); 2946 rt2661_bbp_write(sc, 18, sc->bbp18); 2947 rt2661_bbp_write(sc, 21, sc->bbp21); 2948 rt2661_bbp_write(sc, 22, sc->bbp22); 2949 rt2661_bbp_write(sc, 64, sc->bbp64); 2950 2951 return bbp66 == 1; 2952 } 2953 #endif 2954 2955 static int 2956 rt2661_prepare_beacon(struct rt2661_softc *sc) 2957 { 2958 struct ieee80211com *ic = &sc->sc_ic; 2959 struct ieee80211_node *ni = ic->ic_bss; 2960 struct rt2661_tx_desc desc; 2961 struct mbuf *m0; 2962 struct ieee80211_beacon_offsets bo; 2963 int rate; 2964 2965 m0 = ieee80211_beacon_alloc(ic, ni, &bo); 2966 if (m0 == NULL) { 2967 aprint_error_dev(sc->sc_dev, "could not allocate beacon frame\n"); 2968 return ENOBUFS; 2969 } 2970 2971 /* send beacons at the lowest available rate */ 2972 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 2973 2974 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2975 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2976 2977 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2978 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2979 2980 /* copy beacon header and payload into NIC memory */ 2981 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2982 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2983 2984 m_freem(m0); 2985 2986 /* 2987 * Store offset of ERP Information Element so that we can update it 2988 * dynamically when the slot time changes. 2989 * XXX: this is ugly since it depends on how net80211 builds beacon 2990 * frames but ieee80211_beacon_alloc() doesn't store offsets for us. 2991 */ 2992 if (ic->ic_curmode == IEEE80211_MODE_11G) { 2993 sc->erp_csr = 2994 RT2661_HW_BEACON_BASE0 + 24 + 2995 sizeof (struct ieee80211_frame) + 2996 8 + 2 + 2 + 2 + ni->ni_esslen + 2997 2 + min(ni->ni_rates.rs_nrates, IEEE80211_RATE_SIZE) + 2998 2 + 1 + 2999 ((ic->ic_opmode == IEEE80211_M_IBSS) ? 4 : 6) + 3000 2; 3001 } 3002 3003 return 0; 3004 } 3005 3006 /* 3007 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 3008 * and HostAP operating modes. 3009 */ 3010 static void 3011 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 3012 { 3013 struct ieee80211com *ic = &sc->sc_ic; 3014 uint32_t tmp; 3015 3016 if (ic->ic_opmode != IEEE80211_M_STA) { 3017 /* 3018 * Change default 16ms TBTT adjustment to 8ms. 3019 * Must be done before enabling beacon generation. 3020 */ 3021 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 3022 } 3023 3024 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 3025 3026 /* set beacon interval (in 1/16ms unit) */ 3027 tmp |= ic->ic_bss->ni_intval * 16; 3028 3029 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 3030 if (ic->ic_opmode == IEEE80211_M_STA) 3031 tmp |= RT2661_TSF_MODE(1); 3032 else 3033 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 3034 3035 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 3036 } 3037 3038 /* 3039 * Retrieve the "Received Signal Strength Indicator" from the raw values 3040 * contained in Rx descriptors. The computation depends on which band the 3041 * frame was received. Correction values taken from the reference driver. 3042 */ 3043 static int 3044 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 3045 { 3046 int lna, agc, rssi; 3047 3048 lna = (raw >> 5) & 0x3; 3049 agc = raw & 0x1f; 3050 3051 rssi = 2 * agc; 3052 3053 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3054 rssi += sc->rssi_2ghz_corr; 3055 3056 if (lna == 1) 3057 rssi -= 64; 3058 else if (lna == 2) 3059 rssi -= 74; 3060 else if (lna == 3) 3061 rssi -= 90; 3062 } else { 3063 rssi += sc->rssi_5ghz_corr; 3064 3065 if (lna == 1) 3066 rssi -= 64; 3067 else if (lna == 2) 3068 rssi -= 86; 3069 else if (lna == 3) 3070 rssi -= 100; 3071 } 3072 return rssi; 3073 } 3074
Indexes created Thu Sep 25 16:09:42 GMT 2025