rt2661.c revision 1.42
1 /* $NetBSD: rt2661.c,v 1.42 2019/11/10 21:16:35 chs Exp $ */ 2 /* $OpenBSD: rt2661.c,v 1.17 2006/05/01 08:41:11 damien Exp $ */ 3 /* $FreeBSD: rt2560.c,v 1.5 2006/06/02 19:59:31 csjp Exp $ */ 4 5 /*- 6 * Copyright (c) 2006 7 * Damien Bergamini <damien.bergamini (at) free.fr> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 24 * http://www.ralinktech.com/ 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rt2661.c,v 1.42 2019/11/10 21:16:35 chs Exp $"); 29 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/callout.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 60 #include <net80211/ieee80211_var.h> 61 #include <net80211/ieee80211_amrr.h> 62 #include <net80211/ieee80211_radiotap.h> 63 64 #include <dev/ic/rt2661reg.h> 65 #include <dev/ic/rt2661var.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/firmload.h> 72 73 #ifdef RAL_DEBUG 74 #define DPRINTF(x) do { if (rt2661_debug > 0) printf x; } while (0) 75 #define DPRINTFN(n, x) do { if (rt2661_debug >= (n)) printf x; } while (0) 76 int rt2661_debug = 0; 77 #else 78 #define DPRINTF(x) 79 #define DPRINTFN(n, x) 80 #endif 81 82 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *, int); 84 static void rt2661_reset_tx_ring(struct rt2661_softc *, 85 struct rt2661_tx_ring *); 86 static void rt2661_free_tx_ring(struct rt2661_softc *, 87 struct rt2661_tx_ring *); 88 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *, int); 90 static void rt2661_reset_rx_ring(struct rt2661_softc *, 91 struct rt2661_rx_ring *); 92 static void rt2661_free_rx_ring(struct rt2661_softc *, 93 struct rt2661_rx_ring *); 94 static struct ieee80211_node * 95 rt2661_node_alloc(struct ieee80211_node_table *); 96 static int rt2661_media_change(struct ifnet *); 97 static void rt2661_next_scan(void *); 98 static void rt2661_iter_func(void *, struct ieee80211_node *); 99 static void rt2661_updatestats(void *); 100 static void rt2661_newassoc(struct ieee80211_node *, int); 101 static int rt2661_newstate(struct ieee80211com *, enum ieee80211_state, 102 int); 103 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 104 static void rt2661_tx_intr(struct rt2661_softc *); 105 static void rt2661_tx_dma_intr(struct rt2661_softc *, 106 struct rt2661_tx_ring *); 107 static void rt2661_rx_intr(struct rt2661_softc *); 108 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 109 static void rt2661_mcu_wakeup(struct rt2661_softc *); 110 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 111 int rt2661_intr(void *); 112 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 113 static int rt2661_ack_rate(struct ieee80211com *, int); 114 static uint16_t rt2661_txtime(int, int, uint32_t); 115 static uint8_t rt2661_plcp_signal(int); 116 static void rt2661_setup_tx_desc(struct rt2661_softc *, 117 struct rt2661_tx_desc *, uint32_t, uint16_t, int, int, 118 const bus_dma_segment_t *, int, int); 119 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 120 struct ieee80211_node *); 121 static struct mbuf * 122 rt2661_get_rts(struct rt2661_softc *, 123 struct ieee80211_frame *, uint16_t); 124 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 125 struct ieee80211_node *, int); 126 static void rt2661_start(struct ifnet *); 127 static void rt2661_watchdog(struct ifnet *); 128 static int rt2661_reset(struct ifnet *); 129 static int rt2661_ioctl(struct ifnet *, u_long, void *); 130 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t); 131 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 132 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t); 133 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, uint16_t); 134 static void rt2661_select_antenna(struct rt2661_softc *); 135 static void rt2661_enable_mrr(struct rt2661_softc *); 136 static void rt2661_set_txpreamble(struct rt2661_softc *); 137 static void rt2661_set_basicrates(struct rt2661_softc *, 138 const struct ieee80211_rateset *); 139 static void rt2661_select_band(struct rt2661_softc *, 140 struct ieee80211_channel *); 141 static void rt2661_set_chan(struct rt2661_softc *, 142 struct ieee80211_channel *); 143 static void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *); 144 static void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *); 145 static void rt2661_update_promisc(struct rt2661_softc *); 146 #if 0 147 static int rt2661_wme_update(struct ieee80211com *); 148 #endif 149 150 static void rt2661_updateslot(struct ifnet *); 151 static void rt2661_set_slottime(struct rt2661_softc *); 152 static const char * 153 rt2661_get_rf(int); 154 static void rt2661_read_eeprom(struct rt2661_softc *); 155 static int rt2661_bbp_init(struct rt2661_softc *); 156 static int rt2661_init(struct ifnet *); 157 static void rt2661_stop(struct ifnet *, int); 158 static int rt2661_load_microcode(struct rt2661_softc *, const uint8_t *, 159 int); 160 static void rt2661_rx_tune(struct rt2661_softc *); 161 #ifdef notyet 162 static void rt2661_radar_start(struct rt2661_softc *); 163 static int rt2661_radar_stop(struct rt2661_softc *); 164 #endif 165 static int rt2661_prepare_beacon(struct rt2661_softc *); 166 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 167 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 168 static void rt2661_softintr(void *); 169 170 static const struct { 171 uint32_t reg; 172 uint32_t val; 173 } rt2661_def_mac[] = { 174 RT2661_DEF_MAC 175 }; 176 177 static const struct { 178 uint8_t reg; 179 uint8_t val; 180 } rt2661_def_bbp[] = { 181 RT2661_DEF_BBP 182 }; 183 184 static const struct rfprog { 185 uint8_t chan; 186 uint32_t r1, r2, r3, r4; 187 } rt2661_rf5225_1[] = { 188 RT2661_RF5225_1 189 }, rt2661_rf5225_2[] = { 190 RT2661_RF5225_2 191 }; 192 193 int 194 rt2661_attach(void *xsc, int id) 195 { 196 struct rt2661_softc *sc = xsc; 197 struct ieee80211com *ic = &sc->sc_ic; 198 struct ifnet *ifp = &sc->sc_if; 199 uint32_t val; 200 int error, i, ntries; 201 202 sc->sc_id = id; 203 204 sc->amrr.amrr_min_success_threshold = 1; 205 sc->amrr.amrr_max_success_threshold = 15; 206 callout_init(&sc->scan_ch, 0); 207 callout_init(&sc->amrr_ch, 0); 208 209 /* wait for NIC to initialize */ 210 for (ntries = 0; ntries < 1000; ntries++) { 211 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 212 break; 213 DELAY(1000); 214 } 215 if (ntries == 1000) { 216 aprint_error_dev(sc->sc_dev, "timeout waiting for NIC to initialize\n"); 217 return EIO; 218 } 219 220 /* retrieve RF rev. no and various other things from EEPROM */ 221 rt2661_read_eeprom(sc); 222 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 223 ether_sprintf(ic->ic_myaddr)); 224 225 aprint_normal_dev(sc->sc_dev, "MAC/BBP RT%X, RF %s\n", val, 226 rt2661_get_rf(sc->rf_rev)); 227 228 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rt2661_softintr, sc); 229 if (sc->sc_soft_ih == NULL) { 230 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 231 goto fail0; 232 } 233 234 /* 235 * Allocate Tx and Rx rings. 236 */ 237 error = rt2661_alloc_tx_ring(sc, &sc->txq[0], RT2661_TX_RING_COUNT); 238 if (error != 0) { 239 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 0\n"); 240 goto fail1; 241 } 242 243 error = rt2661_alloc_tx_ring(sc, &sc->txq[1], RT2661_TX_RING_COUNT); 244 if (error != 0) { 245 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 1\n"); 246 goto fail2; 247 } 248 249 error = rt2661_alloc_tx_ring(sc, &sc->txq[2], RT2661_TX_RING_COUNT); 250 if (error != 0) { 251 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 2\n"); 252 goto fail3; 253 } 254 255 error = rt2661_alloc_tx_ring(sc, &sc->txq[3], RT2661_TX_RING_COUNT); 256 if (error != 0) { 257 aprint_error_dev(sc->sc_dev, "could not allocate Tx ring 3\n"); 258 goto fail4; 259 } 260 261 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 262 if (error != 0) { 263 aprint_error_dev(sc->sc_dev, "could not allocate Mgt ring\n"); 264 goto fail5; 265 } 266 267 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 268 if (error != 0) { 269 aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n"); 270 goto fail6; 271 } 272 273 ifp->if_softc = sc; 274 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 275 ifp->if_init = rt2661_init; 276 ifp->if_stop = rt2661_stop; 277 ifp->if_ioctl = rt2661_ioctl; 278 ifp->if_start = rt2661_start; 279 ifp->if_watchdog = rt2661_watchdog; 280 IFQ_SET_READY(&ifp->if_snd); 281 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 282 283 ic->ic_ifp = ifp; 284 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 285 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 286 ic->ic_state = IEEE80211_S_INIT; 287 288 /* set device capabilities */ 289 ic->ic_caps = 290 IEEE80211_C_IBSS | /* IBSS mode supported */ 291 IEEE80211_C_MONITOR | /* monitor mode supported */ 292 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 293 IEEE80211_C_TXPMGT | /* tx power management */ 294 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 295 IEEE80211_C_SHSLOT | /* short slot time supported */ 296 IEEE80211_C_WPA; /* 802.11i */ 297 298 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 299 /* set supported .11a rates */ 300 ic->ic_sup_rates[IEEE80211_MODE_11A] = ieee80211_std_rateset_11a; 301 302 /* set supported .11a channels */ 303 for (i = 36; i <= 64; i += 4) { 304 ic->ic_channels[i].ic_freq = 305 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 306 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 307 } 308 for (i = 100; i <= 140; i += 4) { 309 ic->ic_channels[i].ic_freq = 310 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 311 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 312 } 313 for (i = 149; i <= 165; i += 4) { 314 ic->ic_channels[i].ic_freq = 315 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 316 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 317 } 318 } 319 320 /* set supported .11b and .11g rates */ 321 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 322 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 323 324 /* set supported .11b and .11g channels (1 through 14) */ 325 for (i = 1; i <= 14; i++) { 326 ic->ic_channels[i].ic_freq = 327 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 328 ic->ic_channels[i].ic_flags = 329 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 330 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 331 } 332 333 error = if_initialize(ifp); 334 if (error != 0) { 335 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 336 error); 337 goto fail7; 338 } 339 ieee80211_ifattach(ic); 340 /* Use common softint-based if_input */ 341 ifp->if_percpuq = if_percpuq_create(ifp); 342 if_register(ifp); 343 344 ic->ic_node_alloc = rt2661_node_alloc; 345 ic->ic_newassoc = rt2661_newassoc; 346 ic->ic_updateslot = rt2661_updateslot; 347 ic->ic_reset = rt2661_reset; 348 349 /* override state transition machine */ 350 sc->sc_newstate = ic->ic_newstate; 351 ic->ic_newstate = rt2661_newstate; 352 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 353 354 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 355 sizeof(struct ieee80211_frame) + sizeof(sc->sc_txtap), 356 &sc->sc_drvbpf); 357 358 sc->sc_rxtap_len = roundup(sizeof(sc->sc_rxtap), sizeof(u_int32_t)); 359 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 360 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 361 362 sc->sc_txtap_len = roundup(sizeof(sc->sc_txtap), sizeof(u_int32_t)); 363 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 364 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 365 366 ieee80211_announce(ic); 367 368 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 369 pmf_class_network_register(sc->sc_dev, ifp); 370 else 371 aprint_error_dev(sc->sc_dev, 372 "couldn't establish power handler\n"); 373 374 return 0; 375 376 fail7: rt2661_free_rx_ring(sc, &sc->rxq); 377 fail6: rt2661_free_tx_ring(sc, &sc->mgtq); 378 fail5: rt2661_free_tx_ring(sc, &sc->txq[3]); 379 fail4: rt2661_free_tx_ring(sc, &sc->txq[2]); 380 fail3: rt2661_free_tx_ring(sc, &sc->txq[1]); 381 fail2: rt2661_free_tx_ring(sc, &sc->txq[0]); 382 fail1: softint_disestablish(sc->sc_soft_ih); 383 sc->sc_soft_ih = NULL; 384 fail0: return ENXIO; 385 } 386 387 int 388 rt2661_detach(void *xsc) 389 { 390 struct rt2661_softc *sc = xsc; 391 struct ifnet *ifp = &sc->sc_if; 392 393 callout_stop(&sc->scan_ch); 394 callout_stop(&sc->amrr_ch); 395 396 pmf_device_deregister(sc->sc_dev); 397 398 ieee80211_ifdetach(&sc->sc_ic); 399 if_detach(ifp); 400 401 rt2661_free_tx_ring(sc, &sc->txq[0]); 402 rt2661_free_tx_ring(sc, &sc->txq[1]); 403 rt2661_free_tx_ring(sc, &sc->txq[2]); 404 rt2661_free_tx_ring(sc, &sc->txq[3]); 405 rt2661_free_tx_ring(sc, &sc->mgtq); 406 rt2661_free_rx_ring(sc, &sc->rxq); 407 408 if (sc->sc_soft_ih != NULL) { 409 softint_disestablish(sc->sc_soft_ih); 410 sc->sc_soft_ih = NULL; 411 } 412 413 return 0; 414 } 415 416 static int 417 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 418 int count) 419 { 420 int i, nsegs, error; 421 422 ring->count = count; 423 ring->queued = 0; 424 ring->cur = ring->next = ring->stat = 0; 425 426 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 1, 427 count * RT2661_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 428 if (error != 0) { 429 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 430 goto fail; 431 } 432 433 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_TX_DESC_SIZE, 434 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 435 if (error != 0) { 436 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 437 goto fail; 438 } 439 440 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 441 count * RT2661_TX_DESC_SIZE, (void **)&ring->desc, 442 BUS_DMA_NOWAIT); 443 if (error != 0) { 444 aprint_error_dev(sc->sc_dev, "could not map desc DMA memory\n"); 445 goto fail; 446 } 447 448 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 449 count * RT2661_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 450 if (error != 0) { 451 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 452 goto fail; 453 } 454 455 memset(ring->desc, 0, count * RT2661_TX_DESC_SIZE); 456 ring->physaddr = ring->map->dm_segs->ds_addr; 457 458 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 459 M_WAITOK | M_ZERO); 460 461 for (i = 0; i < count; i++) { 462 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 463 RT2661_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 464 &ring->data[i].map); 465 if (error != 0) { 466 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 467 goto fail; 468 } 469 } 470 471 return 0; 472 473 fail: rt2661_free_tx_ring(sc, ring); 474 return error; 475 } 476 477 static void 478 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 479 { 480 struct rt2661_tx_desc *desc; 481 struct rt2661_tx_data *data; 482 int i; 483 484 for (i = 0; i < ring->count; i++) { 485 desc = &ring->desc[i]; 486 data = &ring->data[i]; 487 488 if (data->m != NULL) { 489 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 490 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 491 bus_dmamap_unload(sc->sc_dmat, data->map); 492 m_freem(data->m); 493 data->m = NULL; 494 } 495 496 if (data->ni != NULL) { 497 ieee80211_free_node(data->ni); 498 data->ni = NULL; 499 } 500 501 desc->flags = 0; 502 } 503 504 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 505 BUS_DMASYNC_PREWRITE); 506 507 ring->queued = 0; 508 ring->cur = ring->next = ring->stat = 0; 509 } 510 511 512 static void 513 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 514 { 515 struct rt2661_tx_data *data; 516 int i; 517 518 if (ring->desc != NULL) { 519 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 520 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 521 bus_dmamap_unload(sc->sc_dmat, ring->map); 522 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 523 ring->count * RT2661_TX_DESC_SIZE); 524 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 525 } 526 527 if (ring->data != NULL) { 528 for (i = 0; i < ring->count; i++) { 529 data = &ring->data[i]; 530 531 if (data->m != NULL) { 532 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 533 data->map->dm_mapsize, 534 BUS_DMASYNC_POSTWRITE); 535 bus_dmamap_unload(sc->sc_dmat, data->map); 536 m_freem(data->m); 537 } 538 539 if (data->ni != NULL) 540 ieee80211_free_node(data->ni); 541 542 if (data->map != NULL) 543 bus_dmamap_destroy(sc->sc_dmat, data->map); 544 } 545 free(ring->data, M_DEVBUF); 546 } 547 } 548 549 static int 550 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 551 int count) 552 { 553 struct rt2661_rx_desc *desc; 554 struct rt2661_rx_data *data; 555 int i, nsegs, error; 556 557 ring->count = count; 558 ring->cur = ring->next = 0; 559 560 error = bus_dmamap_create(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 1, 561 count * RT2661_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 562 if (error != 0) { 563 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 564 goto fail; 565 } 566 567 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2661_RX_DESC_SIZE, 568 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 569 if (error != 0) { 570 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 571 goto fail; 572 } 573 574 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 575 count * RT2661_RX_DESC_SIZE, (void **)&ring->desc, 576 BUS_DMA_NOWAIT); 577 if (error != 0) { 578 aprint_error_dev(sc->sc_dev, "could not map desc DMA memory\n"); 579 goto fail; 580 } 581 582 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 583 count * RT2661_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 584 if (error != 0) { 585 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 586 goto fail; 587 } 588 589 memset(ring->desc, 0, count * RT2661_RX_DESC_SIZE); 590 ring->physaddr = ring->map->dm_segs->ds_addr; 591 592 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 593 M_WAITOK | M_ZERO); 594 595 /* 596 * Pre-allocate Rx buffers and populate Rx ring. 597 */ 598 for (i = 0; i < count; i++) { 599 desc = &sc->rxq.desc[i]; 600 data = &sc->rxq.data[i]; 601 602 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 603 0, BUS_DMA_NOWAIT, &data->map); 604 if (error != 0) { 605 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 606 goto fail; 607 } 608 609 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 610 if (data->m == NULL) { 611 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 612 error = ENOMEM; 613 goto fail; 614 } 615 616 MCLGET(data->m, M_DONTWAIT); 617 if (!(data->m->m_flags & M_EXT)) { 618 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 619 error = ENOMEM; 620 goto fail; 621 } 622 623 error = bus_dmamap_load(sc->sc_dmat, data->map, 624 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 625 if (error != 0) { 626 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map"); 627 goto fail; 628 } 629 630 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 631 desc->flags = htole32(RT2661_RX_BUSY); 632 } 633 634 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 635 BUS_DMASYNC_PREWRITE); 636 637 return 0; 638 639 fail: rt2661_free_rx_ring(sc, ring); 640 return error; 641 } 642 643 static void 644 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 645 { 646 int i; 647 648 for (i = 0; i < ring->count; i++) 649 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 650 651 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 652 BUS_DMASYNC_PREWRITE); 653 654 ring->cur = ring->next = 0; 655 } 656 657 static void 658 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 659 { 660 struct rt2661_rx_data *data; 661 int i; 662 663 if (ring->desc != NULL) { 664 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 665 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 666 bus_dmamap_unload(sc->sc_dmat, ring->map); 667 bus_dmamem_unmap(sc->sc_dmat, (void *)ring->desc, 668 ring->count * RT2661_RX_DESC_SIZE); 669 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 670 } 671 672 if (ring->data != NULL) { 673 for (i = 0; i < ring->count; i++) { 674 data = &ring->data[i]; 675 676 if (data->m != NULL) { 677 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 678 data->map->dm_mapsize, 679 BUS_DMASYNC_POSTREAD); 680 bus_dmamap_unload(sc->sc_dmat, data->map); 681 m_freem(data->m); 682 } 683 684 if (data->map != NULL) 685 bus_dmamap_destroy(sc->sc_dmat, data->map); 686 } 687 free(ring->data, M_DEVBUF); 688 } 689 } 690 691 static struct ieee80211_node * 692 rt2661_node_alloc(struct ieee80211_node_table *nt) 693 { 694 struct rt2661_node *rn; 695 696 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 697 M_NOWAIT | M_ZERO); 698 699 return (rn != NULL) ? &rn->ni : NULL; 700 } 701 702 static int 703 rt2661_media_change(struct ifnet *ifp) 704 { 705 int error; 706 707 error = ieee80211_media_change(ifp); 708 if (error != ENETRESET) 709 return error; 710 711 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 712 rt2661_init(ifp); 713 714 return 0; 715 } 716 717 /* 718 * This function is called periodically (every 200ms) during scanning to 719 * switch from one channel to another. 720 */ 721 static void 722 rt2661_next_scan(void *arg) 723 { 724 struct rt2661_softc *sc = arg; 725 struct ieee80211com *ic = &sc->sc_ic; 726 int s; 727 728 s = splnet(); 729 if (ic->ic_state == IEEE80211_S_SCAN) 730 ieee80211_next_scan(ic); 731 splx(s); 732 } 733 734 /* 735 * This function is called for each neighbor node. 736 */ 737 static void 738 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 739 { 740 struct rt2661_softc *sc = arg; 741 struct rt2661_node *rn = (struct rt2661_node *)ni; 742 743 ieee80211_amrr_choose(&sc->amrr, ni, &rn->amn); 744 } 745 746 /* 747 * This function is called periodically (every 500ms) in RUN state to update 748 * various settings like rate control statistics or Rx sensitivity. 749 */ 750 static void 751 rt2661_updatestats(void *arg) 752 { 753 struct rt2661_softc *sc = arg; 754 struct ieee80211com *ic = &sc->sc_ic; 755 int s; 756 757 s = splnet(); 758 if (ic->ic_opmode == IEEE80211_M_STA) 759 rt2661_iter_func(sc, ic->ic_bss); 760 else 761 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 762 763 /* update rx sensitivity every 1 sec */ 764 if (++sc->ncalls & 1) 765 rt2661_rx_tune(sc); 766 splx(s); 767 768 callout_reset(&sc->amrr_ch, hz / 2, rt2661_updatestats, sc); 769 } 770 771 static void 772 rt2661_newassoc(struct ieee80211_node *ni, int isnew) 773 { 774 struct rt2661_softc *sc = ni->ni_ic->ic_ifp->if_softc; 775 int i; 776 777 ieee80211_amrr_node_init(&sc->amrr, &((struct rt2661_node *)ni)->amn); 778 779 /* set rate to some reasonable initial value */ 780 for (i = ni->ni_rates.rs_nrates - 1; 781 i > 0 && (ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL) > 72; 782 i--); 783 ni->ni_txrate = i; 784 } 785 786 static int 787 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 788 { 789 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 790 enum ieee80211_state ostate; 791 struct ieee80211_node *ni; 792 uint32_t tmp; 793 794 ostate = ic->ic_state; 795 callout_stop(&sc->scan_ch); 796 797 switch (nstate) { 798 case IEEE80211_S_INIT: 799 callout_stop(&sc->amrr_ch); 800 801 if (ostate == IEEE80211_S_RUN) { 802 /* abort TSF synchronization */ 803 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 804 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 805 } 806 break; 807 808 case IEEE80211_S_SCAN: 809 rt2661_set_chan(sc, ic->ic_curchan); 810 callout_reset(&sc->scan_ch, hz / 5, rt2661_next_scan, sc); 811 break; 812 813 case IEEE80211_S_AUTH: 814 case IEEE80211_S_ASSOC: 815 rt2661_set_chan(sc, ic->ic_curchan); 816 break; 817 818 case IEEE80211_S_RUN: 819 rt2661_set_chan(sc, ic->ic_curchan); 820 821 ni = ic->ic_bss; 822 823 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 824 rt2661_set_slottime(sc); 825 rt2661_enable_mrr(sc); 826 rt2661_set_txpreamble(sc); 827 rt2661_set_basicrates(sc, &ni->ni_rates); 828 rt2661_set_bssid(sc, ni->ni_bssid); 829 } 830 831 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 832 ic->ic_opmode == IEEE80211_M_IBSS) 833 rt2661_prepare_beacon(sc); 834 835 if (ic->ic_opmode == IEEE80211_M_STA) { 836 /* fake a join to init the tx rate */ 837 rt2661_newassoc(ni, 1); 838 } 839 840 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 841 sc->ncalls = 0; 842 sc->avg_rssi = -95; /* reset EMA */ 843 callout_reset(&sc->amrr_ch, hz / 2, 844 rt2661_updatestats, sc); 845 rt2661_enable_tsf_sync(sc); 846 } 847 break; 848 } 849 850 return sc->sc_newstate(ic, nstate, arg); 851 } 852 853 /* 854 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 855 * 93C66). 856 */ 857 static uint16_t 858 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 859 { 860 uint32_t tmp; 861 uint16_t val; 862 int n; 863 864 /* clock C once before the first command */ 865 RT2661_EEPROM_CTL(sc, 0); 866 867 RT2661_EEPROM_CTL(sc, RT2661_S); 868 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 869 RT2661_EEPROM_CTL(sc, RT2661_S); 870 871 /* write start bit (1) */ 872 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 873 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 874 875 /* write READ opcode (10) */ 876 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 877 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 878 RT2661_EEPROM_CTL(sc, RT2661_S); 879 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 880 881 /* write address (A5-A0 or A7-A0) */ 882 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 883 for (; n >= 0; n--) { 884 RT2661_EEPROM_CTL(sc, RT2661_S | 885 (((addr >> n) & 1) << RT2661_SHIFT_D)); 886 RT2661_EEPROM_CTL(sc, RT2661_S | 887 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 888 } 889 890 RT2661_EEPROM_CTL(sc, RT2661_S); 891 892 /* read data Q15-Q0 */ 893 val = 0; 894 for (n = 15; n >= 0; n--) { 895 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 896 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 897 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 898 RT2661_EEPROM_CTL(sc, RT2661_S); 899 } 900 901 RT2661_EEPROM_CTL(sc, 0); 902 903 /* clear Chip Select and clock C */ 904 RT2661_EEPROM_CTL(sc, RT2661_S); 905 RT2661_EEPROM_CTL(sc, 0); 906 RT2661_EEPROM_CTL(sc, RT2661_C); 907 908 return val; 909 } 910 911 static void 912 rt2661_tx_intr(struct rt2661_softc *sc) 913 { 914 struct ifnet *ifp = &sc->sc_if; 915 struct rt2661_tx_ring *txq; 916 struct rt2661_tx_data *data; 917 struct rt2661_node *rn; 918 uint32_t val; 919 int qid, retrycnt, s; 920 921 s = splnet(); 922 923 for (;;) { 924 val = RAL_READ(sc, RT2661_STA_CSR4); 925 if (!(val & RT2661_TX_STAT_VALID)) 926 break; 927 928 /* retrieve the queue in which this frame was sent */ 929 qid = RT2661_TX_QID(val); 930 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 931 932 /* retrieve rate control algorithm context */ 933 data = &txq->data[txq->stat]; 934 rn = (struct rt2661_node *)data->ni; 935 936 /* if no frame has been sent, ignore */ 937 if (rn == NULL) 938 continue; 939 940 switch (RT2661_TX_RESULT(val)) { 941 case RT2661_TX_SUCCESS: 942 retrycnt = RT2661_TX_RETRYCNT(val); 943 944 DPRINTFN(10, ("data frame sent successfully after " 945 "%d retries\n", retrycnt)); 946 rn->amn.amn_txcnt++; 947 if (retrycnt > 0) 948 rn->amn.amn_retrycnt++; 949 ifp->if_opackets++; 950 break; 951 952 case RT2661_TX_RETRY_FAIL: 953 DPRINTFN(9, ("sending data frame failed (too much " 954 "retries)\n")); 955 rn->amn.amn_txcnt++; 956 rn->amn.amn_retrycnt++; 957 ifp->if_oerrors++; 958 break; 959 960 default: 961 /* other failure */ 962 aprint_error_dev(sc->sc_dev, "sending data frame failed 0x%08x\n", val); 963 ifp->if_oerrors++; 964 } 965 966 ieee80211_free_node(data->ni); 967 data->ni = NULL; 968 969 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 970 971 txq->queued--; 972 if (++txq->stat >= txq->count) /* faster than % count */ 973 txq->stat = 0; 974 } 975 976 sc->sc_tx_timer = 0; 977 ifp->if_flags &= ~IFF_OACTIVE; 978 rt2661_start(ifp); /* in softint */ 979 980 splx(s); 981 } 982 983 static void 984 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 985 { 986 struct rt2661_tx_desc *desc; 987 struct rt2661_tx_data *data; 988 989 for (;;) { 990 desc = &txq->desc[txq->next]; 991 data = &txq->data[txq->next]; 992 993 bus_dmamap_sync(sc->sc_dmat, txq->map, 994 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 995 BUS_DMASYNC_POSTREAD); 996 997 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 998 !(le32toh(desc->flags) & RT2661_TX_VALID)) 999 break; 1000 1001 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1002 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1003 bus_dmamap_unload(sc->sc_dmat, data->map); 1004 m_freem(data->m); 1005 data->m = NULL; 1006 /* node reference is released in rt2661_tx_intr() */ 1007 1008 /* descriptor is no longer valid */ 1009 desc->flags &= ~htole32(RT2661_TX_VALID); 1010 1011 bus_dmamap_sync(sc->sc_dmat, txq->map, 1012 txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1013 BUS_DMASYNC_PREWRITE); 1014 1015 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1016 1017 if (++txq->next >= txq->count) /* faster than % count */ 1018 txq->next = 0; 1019 } 1020 } 1021 1022 static void 1023 rt2661_rx_intr(struct rt2661_softc *sc) 1024 { 1025 struct ieee80211com *ic = &sc->sc_ic; 1026 struct ifnet *ifp = &sc->sc_if; 1027 struct rt2661_rx_desc *desc; 1028 struct rt2661_rx_data *data; 1029 struct ieee80211_frame *wh; 1030 struct ieee80211_node *ni; 1031 struct mbuf *mnew, *m; 1032 int error, rssi, s; 1033 1034 for (;;) { 1035 desc = &sc->rxq.desc[sc->rxq.cur]; 1036 data = &sc->rxq.data[sc->rxq.cur]; 1037 1038 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1039 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1040 BUS_DMASYNC_POSTREAD); 1041 1042 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1043 break; 1044 1045 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1046 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1047 /* 1048 * This should not happen since we did not request 1049 * to receive those frames when we filled TXRX_CSR0. 1050 */ 1051 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1052 le32toh(desc->flags))); 1053 ifp->if_ierrors++; 1054 goto skip; 1055 } 1056 1057 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1058 ifp->if_ierrors++; 1059 goto skip; 1060 } 1061 1062 /* 1063 * Try to allocate a new mbuf for this ring element and load it 1064 * before processing the current mbuf. If the ring element 1065 * cannot be loaded, drop the received packet and reuse the old 1066 * mbuf. In the unlikely case that the old mbuf can't be 1067 * reloaded either, explicitly panic. 1068 */ 1069 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1070 if (mnew == NULL) { 1071 ifp->if_ierrors++; 1072 goto skip; 1073 } 1074 1075 MCLGET(mnew, M_DONTWAIT); 1076 if (!(mnew->m_flags & M_EXT)) { 1077 m_freem(mnew); 1078 ifp->if_ierrors++; 1079 goto skip; 1080 } 1081 1082 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1083 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1084 bus_dmamap_unload(sc->sc_dmat, data->map); 1085 1086 error = bus_dmamap_load(sc->sc_dmat, data->map, 1087 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1088 if (error != 0) { 1089 m_freem(mnew); 1090 1091 /* try to reload the old mbuf */ 1092 error = bus_dmamap_load(sc->sc_dmat, data->map, 1093 mtod(data->m, void *), MCLBYTES, NULL, 1094 BUS_DMA_NOWAIT); 1095 if (error != 0) { 1096 /* very unlikely that it will fail... */ 1097 panic("%s: could not load old rx mbuf", 1098 device_xname(sc->sc_dev)); 1099 } 1100 /* physical address may have changed */ 1101 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1102 ifp->if_ierrors++; 1103 goto skip; 1104 } 1105 1106 /* 1107 * New mbuf successfully loaded, update Rx ring and continue 1108 * processing. 1109 */ 1110 m = data->m; 1111 data->m = mnew; 1112 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1113 1114 /* finalize mbuf */ 1115 m_set_rcvif(m, ifp); 1116 m->m_pkthdr.len = m->m_len = 1117 (le32toh(desc->flags) >> 16) & 0xfff; 1118 1119 s = splnet(); 1120 1121 if (sc->sc_drvbpf != NULL) { 1122 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1123 uint32_t tsf_lo, tsf_hi; 1124 1125 /* get timestamp (low and high 32 bits) */ 1126 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1127 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1128 1129 tap->wr_tsf = 1130 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1131 tap->wr_flags = 0; 1132 tap->wr_rate = rt2661_rxrate(desc); 1133 tap->wr_chan_freq = htole16(sc->sc_curchan->ic_freq); 1134 tap->wr_chan_flags = htole16(sc->sc_curchan->ic_flags); 1135 tap->wr_antsignal = desc->rssi; 1136 1137 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, 1138 BPF_D_IN); 1139 } 1140 1141 wh = mtod(m, struct ieee80211_frame *); 1142 ni = ieee80211_find_rxnode(ic, 1143 (struct ieee80211_frame_min *)wh); 1144 1145 /* send the frame to the 802.11 layer */ 1146 ieee80211_input(ic, m, ni, desc->rssi, 0); 1147 1148 /*- 1149 * Keep track of the average RSSI using an Exponential Moving 1150 * Average (EMA) of 8 Wilder's days: 1151 * avg = (1 / N) x rssi + ((N - 1) / N) x avg 1152 */ 1153 rssi = rt2661_get_rssi(sc, desc->rssi); 1154 sc->avg_rssi = (rssi + 7 * sc->avg_rssi) / 8; 1155 1156 /* node is no longer needed */ 1157 ieee80211_free_node(ni); 1158 1159 splx(s); 1160 1161 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1162 1163 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1164 sc->rxq.cur * RT2661_RX_DESC_SIZE, RT2661_RX_DESC_SIZE, 1165 BUS_DMASYNC_PREWRITE); 1166 1167 DPRINTFN(16, ("rx intr idx=%u\n", sc->rxq.cur)); 1168 1169 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1170 } 1171 1172 /* 1173 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 1174 * without calling if_start(). 1175 */ 1176 s = splnet(); 1177 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 1178 rt2661_start(ifp); 1179 splx(s); 1180 } 1181 1182 /* 1183 * This function is called in HostAP or IBSS modes when it's time to send a 1184 * new beacon (every ni_intval milliseconds). 1185 */ 1186 static void 1187 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1188 { 1189 struct ieee80211com *ic = &sc->sc_ic; 1190 1191 if (sc->sc_flags & RT2661_UPDATE_SLOT) { 1192 sc->sc_flags &= ~RT2661_UPDATE_SLOT; 1193 sc->sc_flags |= RT2661_SET_SLOTTIME; 1194 } else if (sc->sc_flags & RT2661_SET_SLOTTIME) { 1195 sc->sc_flags &= ~RT2661_SET_SLOTTIME; 1196 rt2661_set_slottime(sc); 1197 } 1198 1199 if (ic->ic_curmode == IEEE80211_MODE_11G) { 1200 /* update ERP Information Element */ 1201 RAL_WRITE_1(sc, sc->erp_csr, ic->ic_bss->ni_erp); 1202 RAL_RW_BARRIER_1(sc, sc->erp_csr); 1203 } 1204 1205 DPRINTFN(15, ("beacon expired\n")); 1206 } 1207 1208 static void 1209 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1210 { 1211 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1212 1213 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1214 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1215 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1216 1217 /* send wakeup command to MCU */ 1218 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1219 } 1220 1221 static void 1222 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1223 { 1224 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1225 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1226 } 1227 1228 int 1229 rt2661_intr(void *arg) 1230 { 1231 struct rt2661_softc *sc = arg; 1232 struct ifnet *ifp = &sc->sc_if; 1233 uint32_t r1, r2; 1234 1235 /* don't re-enable interrupts if we're shutting down */ 1236 if (!(ifp->if_flags & IFF_RUNNING)) { 1237 /* disable MAC and MCU interrupts */ 1238 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1239 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1240 return 0; 1241 } 1242 1243 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1244 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1245 1246 if ((r1 & RT2661_INT_CSR_ALL) == 0 && (r2 & RT2661_MCU_INT_ALL) == 0) 1247 return 0; 1248 1249 /* disable interrupts */ 1250 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1251 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1252 1253 softint_schedule(sc->sc_soft_ih); 1254 return 1; 1255 } 1256 1257 static void 1258 rt2661_softintr(void *arg) 1259 { 1260 struct rt2661_softc *sc = arg; 1261 uint32_t r1, r2; 1262 1263 for (;;) { 1264 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1265 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1266 1267 if ((r1 & RT2661_INT_CSR_ALL) == 0 && 1268 (r2 & RT2661_MCU_INT_ALL) == 0) 1269 break; 1270 1271 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1272 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1273 1274 if (r1 & RT2661_MGT_DONE) 1275 rt2661_tx_dma_intr(sc, &sc->mgtq); 1276 1277 if (r1 & RT2661_RX_DONE) 1278 rt2661_rx_intr(sc); 1279 1280 if (r1 & RT2661_TX0_DMA_DONE) 1281 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1282 1283 if (r1 & RT2661_TX1_DMA_DONE) 1284 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1285 1286 if (r1 & RT2661_TX2_DMA_DONE) 1287 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1288 1289 if (r1 & RT2661_TX3_DMA_DONE) 1290 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1291 1292 if (r1 & RT2661_TX_DONE) 1293 rt2661_tx_intr(sc); 1294 1295 if (r2 & RT2661_MCU_CMD_DONE) 1296 rt2661_mcu_cmd_intr(sc); 1297 1298 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1299 rt2661_mcu_beacon_expire(sc); 1300 1301 if (r2 & RT2661_MCU_WAKEUP) 1302 rt2661_mcu_wakeup(sc); 1303 } 1304 1305 /* enable interrupts */ 1306 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1307 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1308 } 1309 1310 /* quickly determine if a given rate is CCK or OFDM */ 1311 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1312 1313 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1314 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1315 1316 /* 1317 * This function is only used by the Rx radiotap code. It returns the rate at 1318 * which a given frame was received. 1319 */ 1320 static uint8_t 1321 rt2661_rxrate(struct rt2661_rx_desc *desc) 1322 { 1323 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1324 /* reverse function of rt2661_plcp_signal */ 1325 switch (desc->rate & 0xf) { 1326 case 0xb: return 12; 1327 case 0xf: return 18; 1328 case 0xa: return 24; 1329 case 0xe: return 36; 1330 case 0x9: return 48; 1331 case 0xd: return 72; 1332 case 0x8: return 96; 1333 case 0xc: return 108; 1334 } 1335 } else { 1336 if (desc->rate == 10) 1337 return 2; 1338 if (desc->rate == 20) 1339 return 4; 1340 if (desc->rate == 55) 1341 return 11; 1342 if (desc->rate == 110) 1343 return 22; 1344 } 1345 return 2; /* should not get there */ 1346 } 1347 1348 /* 1349 * Return the expected ack rate for a frame transmitted at rate `rate'. 1350 * XXX: this should depend on the destination node basic rate set. 1351 */ 1352 static int 1353 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1354 { 1355 switch (rate) { 1356 /* CCK rates */ 1357 case 2: 1358 return 2; 1359 case 4: 1360 case 11: 1361 case 22: 1362 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1363 1364 /* OFDM rates */ 1365 case 12: 1366 case 18: 1367 return 12; 1368 case 24: 1369 case 36: 1370 return 24; 1371 case 48: 1372 case 72: 1373 case 96: 1374 case 108: 1375 return 48; 1376 } 1377 1378 /* default to 1Mbps */ 1379 return 2; 1380 } 1381 1382 /* 1383 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1384 * The function automatically determines the operating mode depending on the 1385 * given rate. `flags' indicates whether short preamble is in use or not. 1386 */ 1387 static uint16_t 1388 rt2661_txtime(int len, int rate, uint32_t flags) 1389 { 1390 uint16_t txtime; 1391 1392 if (RAL_RATE_IS_OFDM(rate)) { 1393 /* IEEE Std 802.11g-2003, pp. 44 */ 1394 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1395 txtime = 16 + 4 + 4 * txtime + 6; 1396 } else { 1397 /* IEEE Std 802.11b-1999, pp. 28 */ 1398 txtime = (16 * len + rate - 1) / rate; 1399 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1400 txtime += 72 + 24; 1401 else 1402 txtime += 144 + 48; 1403 } 1404 return txtime; 1405 } 1406 1407 static uint8_t 1408 rt2661_plcp_signal(int rate) 1409 { 1410 switch (rate) { 1411 /* CCK rates (returned values are device-dependent) */ 1412 case 2: return 0x0; 1413 case 4: return 0x1; 1414 case 11: return 0x2; 1415 case 22: return 0x3; 1416 1417 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1418 case 12: return 0xb; 1419 case 18: return 0xf; 1420 case 24: return 0xa; 1421 case 36: return 0xe; 1422 case 48: return 0x9; 1423 case 72: return 0xd; 1424 case 96: return 0x8; 1425 case 108: return 0xc; 1426 1427 /* unsupported rates (should not get there) */ 1428 default: return 0xff; 1429 } 1430 } 1431 1432 static void 1433 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1434 uint32_t flags, uint16_t xflags, int len, int rate, 1435 const bus_dma_segment_t *segs, int nsegs, int ac) 1436 { 1437 struct ieee80211com *ic = &sc->sc_ic; 1438 uint16_t plcp_length; 1439 int i, remainder; 1440 1441 desc->flags = htole32(flags); 1442 desc->flags |= htole32(len << 16); 1443 1444 desc->xflags = htole16(xflags); 1445 desc->xflags |= htole16(nsegs << 13); 1446 1447 desc->wme = htole16( 1448 RT2661_QID(ac) | 1449 RT2661_AIFSN(2) | 1450 RT2661_LOGCWMIN(4) | 1451 RT2661_LOGCWMAX(10)); 1452 1453 /* 1454 * Remember in which queue this frame was sent. This field is driver 1455 * private data only. It will be made available by the NIC in STA_CSR4 1456 * on Tx interrupts. 1457 */ 1458 desc->qid = ac; 1459 1460 /* setup PLCP fields */ 1461 desc->plcp_signal = rt2661_plcp_signal(rate); 1462 desc->plcp_service = 4; 1463 1464 len += IEEE80211_CRC_LEN; 1465 if (RAL_RATE_IS_OFDM(rate)) { 1466 desc->flags |= htole32(RT2661_TX_OFDM); 1467 1468 plcp_length = len & 0xfff; 1469 desc->plcp_length_hi = plcp_length >> 6; 1470 desc->plcp_length_lo = plcp_length & 0x3f; 1471 } else { 1472 plcp_length = (16 * len + rate - 1) / rate; 1473 if (rate == 22) { 1474 remainder = (16 * len) % 22; 1475 if (remainder != 0 && remainder < 7) 1476 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1477 } 1478 desc->plcp_length_hi = plcp_length >> 8; 1479 desc->plcp_length_lo = plcp_length & 0xff; 1480 1481 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1482 desc->plcp_signal |= 0x08; 1483 } 1484 1485 /* RT2x61 supports scatter with up to 5 segments */ 1486 for (i = 0; i < nsegs; i++) { 1487 desc->addr[i] = htole32(segs[i].ds_addr); 1488 desc->len [i] = htole16(segs[i].ds_len); 1489 } 1490 1491 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1492 } 1493 1494 static int 1495 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1496 struct ieee80211_node *ni) 1497 { 1498 struct ieee80211com *ic = &sc->sc_ic; 1499 struct rt2661_tx_desc *desc; 1500 struct rt2661_tx_data *data; 1501 struct ieee80211_frame *wh; 1502 uint16_t dur; 1503 uint32_t flags = 0; 1504 int rate, error; 1505 1506 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1507 data = &sc->mgtq.data[sc->mgtq.cur]; 1508 1509 /* send mgt frames at the lowest available rate */ 1510 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1511 1512 wh = mtod(m0, struct ieee80211_frame *); 1513 1514 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1515 if (ieee80211_crypto_encap(ic, ni, m0) == NULL) { 1516 m_freem(m0); 1517 return ENOBUFS; 1518 } 1519 1520 /* packet header may have moved, reset our local pointer */ 1521 wh = mtod(m0, struct ieee80211_frame *); 1522 } 1523 1524 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1525 BUS_DMA_NOWAIT); 1526 if (error != 0) { 1527 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1528 error); 1529 m_freem(m0); 1530 return error; 1531 } 1532 1533 if (sc->sc_drvbpf != NULL) { 1534 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1535 1536 tap->wt_flags = 0; 1537 tap->wt_rate = rate; 1538 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1539 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1540 1541 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0, BPF_D_OUT); 1542 } 1543 1544 data->m = m0; 1545 data->ni = ni; 1546 1547 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1548 flags |= RT2661_TX_NEED_ACK; 1549 1550 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1551 sc->sifs; 1552 *(uint16_t *)wh->i_dur = htole16(dur); 1553 1554 /* tell hardware to set timestamp in probe responses */ 1555 if ((wh->i_fc[0] & 1556 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1557 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1558 flags |= RT2661_TX_TIMESTAMP; 1559 } 1560 1561 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1562 m0->m_pkthdr.len, rate, data->map->dm_segs, data->map->dm_nsegs, 1563 RT2661_QID_MGT); 1564 1565 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1566 BUS_DMASYNC_PREWRITE); 1567 bus_dmamap_sync(sc->sc_dmat, sc->mgtq.map, 1568 sc->mgtq.cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1569 BUS_DMASYNC_PREWRITE); 1570 1571 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1572 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1573 1574 /* kick mgt */ 1575 sc->mgtq.queued++; 1576 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1577 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1578 1579 return 0; 1580 } 1581 1582 /* 1583 * Build a RTS control frame. 1584 */ 1585 static struct mbuf * 1586 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1587 uint16_t dur) 1588 { 1589 struct ieee80211_frame_rts *rts; 1590 struct mbuf *m; 1591 1592 MGETHDR(m, M_DONTWAIT, MT_DATA); 1593 if (m == NULL) { 1594 sc->sc_ic.ic_stats.is_tx_nobuf++; 1595 aprint_error_dev(sc->sc_dev, "could not allocate RTS frame\n"); 1596 return NULL; 1597 } 1598 1599 rts = mtod(m, struct ieee80211_frame_rts *); 1600 1601 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1602 IEEE80211_FC0_SUBTYPE_RTS; 1603 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1604 *(uint16_t *)rts->i_dur = htole16(dur); 1605 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1606 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1607 1608 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1609 1610 return m; 1611 } 1612 1613 static int 1614 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1615 struct ieee80211_node *ni, int ac) 1616 { 1617 struct ieee80211com *ic = &sc->sc_ic; 1618 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1619 struct rt2661_tx_desc *desc; 1620 struct rt2661_tx_data *data; 1621 struct ieee80211_frame *wh; 1622 struct ieee80211_key *k; 1623 struct mbuf *mnew; 1624 uint16_t dur; 1625 uint32_t flags = 0; 1626 int rate, useprot, error, tid; 1627 1628 wh = mtod(m0, struct ieee80211_frame *); 1629 1630 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1631 rate = ic->ic_sup_rates[ic->ic_curmode]. 1632 rs_rates[ic->ic_fixed_rate]; 1633 } else 1634 rate = ni->ni_rates.rs_rates[ni->ni_txrate]; 1635 rate &= IEEE80211_RATE_VAL; 1636 if (rate == 0) 1637 rate = 2; /* XXX should not happen */ 1638 1639 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1640 k = ieee80211_crypto_encap(ic, ni, m0); 1641 if (k == NULL) { 1642 m_freem(m0); 1643 return ENOBUFS; 1644 } 1645 1646 /* packet header may have moved, reset our local pointer */ 1647 wh = mtod(m0, struct ieee80211_frame *); 1648 } 1649 1650 /* 1651 * Packet Bursting: backoff after ppb=8 frames to give other STAs a 1652 * chance to contend for the wireless medium. 1653 */ 1654 tid = WME_AC_TO_TID(M_WME_GETAC(m0)); 1655 if (ic->ic_opmode == IEEE80211_M_STA && (ni->ni_txseqs[tid] & 7)) 1656 flags |= RT2661_TX_IFS_SIFS; 1657 1658 /* 1659 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1660 * for directed frames only when the length of the MPDU is greater 1661 * than the length threshold indicated by" ic_rtsthreshold. 1662 * 1663 * IEEE Std 802.11-2003g, pp 13: "ERP STAs shall use protection 1664 * mechanism (such as RTS/CTS or CTS-to-self) for ERP-OFDM MPDUs of 1665 * type Data or an MMPDU". 1666 */ 1667 useprot = !IEEE80211_IS_MULTICAST(wh->i_addr1) && 1668 (m0->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1669 ((ic->ic_flags & IEEE80211_F_USEPROT) && RAL_RATE_IS_OFDM(rate))); 1670 if (useprot) { 1671 struct mbuf *m; 1672 int rtsrate, ackrate; 1673 1674 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1675 ackrate = rt2661_ack_rate(ic, rate); 1676 1677 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1678 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1679 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1680 3 * sc->sifs; 1681 1682 m = rt2661_get_rts(sc, wh, dur); 1683 if (m == NULL) { 1684 aprint_error_dev(sc->sc_dev, "could not allocate RTS " 1685 "frame\n"); 1686 m_freem(m0); 1687 return ENOBUFS; 1688 } 1689 1690 desc = &txq->desc[txq->cur]; 1691 data = &txq->data[txq->cur]; 1692 1693 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1694 BUS_DMA_NOWAIT); 1695 if (error != 0) { 1696 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1697 m_freem(m); 1698 m_freem(m0); 1699 return error; 1700 } 1701 1702 /* avoid multiple free() of the same node for each fragment */ 1703 ieee80211_ref_node(ni); 1704 1705 data->m = m; 1706 data->ni = ni; 1707 1708 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1709 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, 1710 data->map->dm_segs, data->map->dm_nsegs, ac); 1711 1712 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1713 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1714 bus_dmamap_sync(sc->sc_dmat, txq->map, 1715 txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE, 1716 BUS_DMASYNC_PREWRITE); 1717 1718 txq->queued++; 1719 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1720 1721 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS_SIFS; 1722 } 1723 1724 data = &txq->data[txq->cur]; 1725 desc = &txq->desc[txq->cur]; 1726 1727 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1728 BUS_DMA_NOWAIT); 1729 if (error != 0 && error != EFBIG) { 1730 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1731 error); 1732 m_freem(m0); 1733 return error; 1734 } 1735 if (error != 0) { 1736 /* too many fragments, linearize */ 1737 1738 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1739 if (mnew == NULL) { 1740 m_freem(m0); 1741 return ENOMEM; 1742 } 1743 1744 m_copy_pkthdr(mnew, m0); 1745 if (m0->m_pkthdr.len > MHLEN) { 1746 MCLGET(mnew, M_DONTWAIT); 1747 if (!(mnew->m_flags & M_EXT)) { 1748 m_freem(m0); 1749 m_freem(mnew); 1750 return ENOMEM; 1751 } 1752 } 1753 1754 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1755 m_freem(m0); 1756 mnew->m_len = mnew->m_pkthdr.len; 1757 m0 = mnew; 1758 1759 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1760 BUS_DMA_NOWAIT); 1761 if (error != 0) { 1762 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1763 m_freem(m0); 1764 return error; 1765 } 1766 1767 /* packet header have moved, reset our local pointer */ 1768 wh = mtod(m0, struct ieee80211_frame *); 1769 } 1770 1771 if (sc->sc_drvbpf != NULL) { 1772 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1773 1774 tap->wt_flags = 0; 1775 tap->wt_rate = rate; 1776 tap->wt_chan_freq = htole16(sc->sc_curchan->ic_freq); 1777 tap->wt_chan_flags = htole16(sc->sc_curchan->ic_flags); 1778 1779 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0, BPF_D_OUT); 1780 } 1781 1782 data->m = m0; 1783 data->ni = ni; 1784 1785 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1786 flags |= RT2661_TX_NEED_ACK; 1787 1788 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1789 ic->ic_flags) + sc->sifs; 1790 *(uint16_t *)wh->i_dur = htole16(dur); 1791 } 1792 1793 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, 1794 data->map->dm_segs, data->map->dm_nsegs, ac); 1795 1796 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1797 BUS_DMASYNC_PREWRITE); 1798 bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE, 1799 RT2661_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1800 1801 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1802 m0->m_pkthdr.len, txq->cur, rate)); 1803 1804 /* kick Tx */ 1805 txq->queued++; 1806 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1807 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1); 1808 1809 return 0; 1810 } 1811 1812 static void 1813 rt2661_start(struct ifnet *ifp) 1814 { 1815 struct rt2661_softc *sc = ifp->if_softc; 1816 struct ieee80211com *ic = &sc->sc_ic; 1817 struct mbuf *m0; 1818 struct ether_header *eh; 1819 struct ieee80211_node *ni = NULL; 1820 1821 /* 1822 * net80211 may still try to send management frames even if the 1823 * IFF_RUNNING flag is not set... 1824 */ 1825 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1826 return; 1827 1828 for (;;) { 1829 IF_POLL(&ic->ic_mgtq, m0); 1830 if (m0 != NULL) { 1831 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1832 ifp->if_flags |= IFF_OACTIVE; 1833 break; 1834 } 1835 IF_DEQUEUE(&ic->ic_mgtq, m0); 1836 if (m0 == NULL) 1837 break; 1838 1839 ni = M_GETCTX(m0, struct ieee80211_node *); 1840 M_CLEARCTX(m0); 1841 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 1842 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1843 break; 1844 1845 } else { 1846 IF_POLL(&ifp->if_snd, m0); 1847 if (m0 == NULL || ic->ic_state != IEEE80211_S_RUN) 1848 break; 1849 1850 if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) { 1851 /* there is no place left in this ring */ 1852 ifp->if_flags |= IFF_OACTIVE; 1853 break; 1854 } 1855 1856 IFQ_DEQUEUE(&ifp->if_snd, m0); 1857 1858 if (m0->m_len < sizeof (struct ether_header) && 1859 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1860 continue; 1861 1862 eh = mtod(m0, struct ether_header *); 1863 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1864 if (ni == NULL) { 1865 m_freem(m0); 1866 ifp->if_oerrors++; 1867 continue; 1868 } 1869 1870 bpf_mtap(ifp, m0, BPF_D_OUT); 1871 m0 = ieee80211_encap(ic, m0, ni); 1872 if (m0 == NULL) { 1873 ieee80211_free_node(ni); 1874 ifp->if_oerrors++; 1875 continue; 1876 } 1877 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 1878 if (rt2661_tx_data(sc, m0, ni, 0) != 0) { 1879 if (ni != NULL) 1880 ieee80211_free_node(ni); 1881 ifp->if_oerrors++; 1882 break; 1883 } 1884 } 1885 1886 sc->sc_tx_timer = 5; 1887 ifp->if_timer = 1; 1888 } 1889 } 1890 1891 static void 1892 rt2661_watchdog(struct ifnet *ifp) 1893 { 1894 struct rt2661_softc *sc = ifp->if_softc; 1895 1896 ifp->if_timer = 0; 1897 1898 if (sc->sc_tx_timer > 0) { 1899 if (--sc->sc_tx_timer == 0) { 1900 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1901 rt2661_init(ifp); 1902 ifp->if_oerrors++; 1903 return; 1904 } 1905 ifp->if_timer = 1; 1906 } 1907 1908 ieee80211_watchdog(&sc->sc_ic); 1909 } 1910 1911 /* 1912 * This function allows for fast channel switching in monitor mode (used by 1913 * kismet). In IBSS mode, we must explicitly reset the interface to 1914 * generate a new beacon frame. 1915 */ 1916 static int 1917 rt2661_reset(struct ifnet *ifp) 1918 { 1919 struct rt2661_softc *sc = ifp->if_softc; 1920 struct ieee80211com *ic = &sc->sc_ic; 1921 1922 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1923 return ENETRESET; 1924 1925 rt2661_set_chan(sc, ic->ic_curchan); 1926 1927 return 0; 1928 } 1929 1930 static int 1931 rt2661_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1932 { 1933 struct rt2661_softc *sc = ifp->if_softc; 1934 struct ieee80211com *ic = &sc->sc_ic; 1935 int s, error = 0; 1936 1937 s = splnet(); 1938 1939 switch (cmd) { 1940 case SIOCSIFFLAGS: 1941 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1942 break; 1943 if (ifp->if_flags & IFF_UP) { 1944 if (ifp->if_flags & IFF_RUNNING) 1945 rt2661_update_promisc(sc); 1946 else 1947 rt2661_init(ifp); 1948 } else { 1949 if (ifp->if_flags & IFF_RUNNING) 1950 rt2661_stop(ifp, 1); 1951 } 1952 break; 1953 1954 case SIOCADDMULTI: 1955 case SIOCDELMULTI: 1956 /* XXX no h/w multicast filter? --dyoung */ 1957 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 1958 error = 0; 1959 break; 1960 1961 case SIOCS80211CHANNEL: 1962 /* 1963 * This allows for fast channel switching in monitor mode 1964 * (used by kismet). In IBSS mode, we must explicitly reset 1965 * the interface to generate a new beacon frame. 1966 */ 1967 error = ieee80211_ioctl(ic, cmd, data); 1968 if (error == ENETRESET && 1969 ic->ic_opmode == IEEE80211_M_MONITOR) { 1970 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1971 (IFF_UP | IFF_RUNNING)) 1972 rt2661_set_chan(sc, ic->ic_ibss_chan); 1973 error = 0; 1974 } 1975 break; 1976 1977 default: 1978 error = ieee80211_ioctl(ic, cmd, data); 1979 1980 } 1981 1982 if (error == ENETRESET) { 1983 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1984 (IFF_UP | IFF_RUNNING)) 1985 rt2661_init(ifp); 1986 error = 0; 1987 } 1988 1989 splx(s); 1990 1991 return error; 1992 } 1993 1994 static void 1995 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1996 { 1997 uint32_t tmp; 1998 int ntries; 1999 2000 for (ntries = 0; ntries < 100; ntries++) { 2001 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2002 break; 2003 DELAY(1); 2004 } 2005 if (ntries == 100) { 2006 aprint_error_dev(sc->sc_dev, "could not write to BBP\n"); 2007 return; 2008 } 2009 2010 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 2011 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 2012 2013 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 2014 } 2015 2016 static uint8_t 2017 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 2018 { 2019 uint32_t val; 2020 int ntries; 2021 2022 for (ntries = 0; ntries < 100; ntries++) { 2023 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 2024 break; 2025 DELAY(1); 2026 } 2027 if (ntries == 100) { 2028 aprint_error_dev(sc->sc_dev, "could not read from BBP\n"); 2029 return 0; 2030 } 2031 2032 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 2033 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 2034 2035 for (ntries = 0; ntries < 100; ntries++) { 2036 val = RAL_READ(sc, RT2661_PHY_CSR3); 2037 if (!(val & RT2661_BBP_BUSY)) 2038 return val & 0xff; 2039 DELAY(1); 2040 } 2041 2042 aprint_error_dev(sc->sc_dev, "could not read from BBP\n"); 2043 return 0; 2044 } 2045 2046 static void 2047 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 2048 { 2049 uint32_t tmp; 2050 int ntries; 2051 2052 for (ntries = 0; ntries < 100; ntries++) { 2053 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2054 break; 2055 DELAY(1); 2056 } 2057 if (ntries == 100) { 2058 aprint_error_dev(sc->sc_dev, "could not write to RF\n"); 2059 return; 2060 } 2061 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2062 (reg & 3); 2063 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2064 2065 /* remember last written value in sc */ 2066 sc->rf_regs[reg] = val; 2067 2068 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2069 } 2070 2071 static int 2072 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2073 { 2074 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2075 return EIO; /* there is already a command pending */ 2076 2077 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2078 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2079 2080 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2081 2082 return 0; 2083 } 2084 2085 static void 2086 rt2661_select_antenna(struct rt2661_softc *sc) 2087 { 2088 uint8_t bbp4, bbp77; 2089 uint32_t tmp; 2090 2091 bbp4 = rt2661_bbp_read(sc, 4); 2092 bbp77 = rt2661_bbp_read(sc, 77); 2093 2094 /* TBD */ 2095 2096 /* make sure Rx is disabled before switching antenna */ 2097 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2098 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2099 2100 rt2661_bbp_write(sc, 4, bbp4); 2101 rt2661_bbp_write(sc, 77, bbp77); 2102 2103 /* restore Rx filter */ 2104 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2105 } 2106 2107 /* 2108 * Enable multi-rate retries for frames sent at OFDM rates. 2109 * In 802.11b/g mode, allow fallback to CCK rates. 2110 */ 2111 static void 2112 rt2661_enable_mrr(struct rt2661_softc *sc) 2113 { 2114 struct ieee80211com *ic = &sc->sc_ic; 2115 uint32_t tmp; 2116 2117 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2118 2119 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2120 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2121 tmp |= RT2661_MRR_CCK_FALLBACK; 2122 tmp |= RT2661_MRR_ENABLED; 2123 2124 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2125 } 2126 2127 static void 2128 rt2661_set_txpreamble(struct rt2661_softc *sc) 2129 { 2130 uint32_t tmp; 2131 2132 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2133 2134 tmp &= ~RT2661_SHORT_PREAMBLE; 2135 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2136 tmp |= RT2661_SHORT_PREAMBLE; 2137 2138 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2139 } 2140 2141 static void 2142 rt2661_set_basicrates(struct rt2661_softc *sc, 2143 const struct ieee80211_rateset *rs) 2144 { 2145 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2146 uint32_t mask = 0; 2147 uint8_t rate; 2148 int i, j; 2149 2150 for (i = 0; i < rs->rs_nrates; i++) { 2151 rate = rs->rs_rates[i]; 2152 2153 if (!(rate & IEEE80211_RATE_BASIC)) 2154 continue; 2155 2156 /* 2157 * Find h/w rate index. We know it exists because the rate 2158 * set has already been negotiated. 2159 */ 2160 for (j = 0; ieee80211_std_rateset_11g.rs_rates[j] != RV(rate); j++); 2161 2162 mask |= 1 << j; 2163 } 2164 2165 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2166 2167 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2168 #undef RV 2169 } 2170 2171 /* 2172 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2173 * driver. 2174 */ 2175 static void 2176 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2177 { 2178 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2179 uint32_t tmp; 2180 2181 /* update all BBP registers that depend on the band */ 2182 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2183 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2184 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2185 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2186 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2187 } 2188 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2189 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2190 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2191 } 2192 2193 sc->bbp17 = bbp17; 2194 rt2661_bbp_write(sc, 17, bbp17); 2195 rt2661_bbp_write(sc, 96, bbp96); 2196 rt2661_bbp_write(sc, 104, bbp104); 2197 2198 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2199 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2200 rt2661_bbp_write(sc, 75, 0x80); 2201 rt2661_bbp_write(sc, 86, 0x80); 2202 rt2661_bbp_write(sc, 88, 0x80); 2203 } 2204 2205 rt2661_bbp_write(sc, 35, bbp35); 2206 rt2661_bbp_write(sc, 97, bbp97); 2207 rt2661_bbp_write(sc, 98, bbp98); 2208 2209 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2210 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2211 if (IEEE80211_IS_CHAN_2GHZ(c)) 2212 tmp |= RT2661_PA_PE_2GHZ; 2213 else 2214 tmp |= RT2661_PA_PE_5GHZ; 2215 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2216 2217 /* 802.11a uses a 16 microseconds short interframe space */ 2218 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10; 2219 } 2220 2221 static void 2222 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2223 { 2224 struct ieee80211com *ic = &sc->sc_ic; 2225 const struct rfprog *rfprog; 2226 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2227 int8_t power; 2228 u_int i, chan; 2229 2230 chan = ieee80211_chan2ieee(ic, c); 2231 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2232 return; 2233 2234 /* select the appropriate RF settings based on what EEPROM says */ 2235 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2236 2237 /* find the settings for this channel (we know it exists) */ 2238 for (i = 0; rfprog[i].chan != chan; i++); 2239 2240 power = sc->txpow[i]; 2241 if (power < 0) { 2242 bbp94 += power; 2243 power = 0; 2244 } else if (power > 31) { 2245 bbp94 += power - 31; 2246 power = 31; 2247 } 2248 2249 /* 2250 * If we've yet to select a channel, or we are switching from the 2251 * 2GHz band to the 5GHz band or vice-versa, BBP registers need to 2252 * be reprogrammed. 2253 */ 2254 if (sc->sc_curchan == NULL || c->ic_flags != sc->sc_curchan->ic_flags) { 2255 rt2661_select_band(sc, c); 2256 rt2661_select_antenna(sc); 2257 } 2258 sc->sc_curchan = c; 2259 2260 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2261 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2262 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2263 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2264 2265 DELAY(200); 2266 2267 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2268 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2269 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2270 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2271 2272 DELAY(200); 2273 2274 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2275 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2276 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2277 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2278 2279 /* enable smart mode for MIMO-capable RFs */ 2280 bbp3 = rt2661_bbp_read(sc, 3); 2281 2282 bbp3 &= ~RT2661_SMART_MODE; 2283 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2284 bbp3 |= RT2661_SMART_MODE; 2285 2286 rt2661_bbp_write(sc, 3, bbp3); 2287 2288 if (bbp94 != RT2661_BBPR94_DEFAULT) 2289 rt2661_bbp_write(sc, 94, bbp94); 2290 2291 /* 5GHz radio needs a 1ms delay here */ 2292 if (IEEE80211_IS_CHAN_5GHZ(c)) 2293 DELAY(1000); 2294 } 2295 2296 static void 2297 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2298 { 2299 uint32_t tmp; 2300 2301 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2302 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2303 2304 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2305 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2306 } 2307 2308 static void 2309 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2310 { 2311 uint32_t tmp; 2312 2313 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2314 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2315 2316 tmp = addr[4] | addr[5] << 8 | 0xff << 16; 2317 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2318 } 2319 2320 static void 2321 rt2661_update_promisc(struct rt2661_softc *sc) 2322 { 2323 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2324 uint32_t tmp; 2325 2326 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2327 2328 tmp &= ~RT2661_DROP_NOT_TO_ME; 2329 if (!(ifp->if_flags & IFF_PROMISC)) 2330 tmp |= RT2661_DROP_NOT_TO_ME; 2331 2332 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2333 2334 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2335 "entering" : "leaving")); 2336 } 2337 2338 #if 0 2339 /* 2340 * Update QoS (802.11e) settings for each h/w Tx ring. 2341 */ 2342 static int 2343 rt2661_wme_update(struct ieee80211com *ic) 2344 { 2345 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2346 const struct wmeParams *wmep; 2347 2348 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2349 2350 /* XXX: not sure about shifts. */ 2351 /* XXX: the reference driver plays with AC_VI settings too. */ 2352 2353 /* update TxOp */ 2354 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2355 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2356 wmep[WME_AC_BK].wmep_txopLimit); 2357 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2358 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2359 wmep[WME_AC_VO].wmep_txopLimit); 2360 2361 /* update CWmin */ 2362 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2363 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2364 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2365 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2366 wmep[WME_AC_VO].wmep_logcwmin); 2367 2368 /* update CWmax */ 2369 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2370 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2371 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2372 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2373 wmep[WME_AC_VO].wmep_logcwmax); 2374 2375 /* update Aifsn */ 2376 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2377 wmep[WME_AC_BE].wmep_aifsn << 12 | 2378 wmep[WME_AC_BK].wmep_aifsn << 8 | 2379 wmep[WME_AC_VI].wmep_aifsn << 4 | 2380 wmep[WME_AC_VO].wmep_aifsn); 2381 2382 return 0; 2383 } 2384 #endif 2385 2386 static void 2387 rt2661_updateslot(struct ifnet *ifp) 2388 { 2389 struct rt2661_softc *sc = ifp->if_softc; 2390 struct ieee80211com *ic = &sc->sc_ic; 2391 2392 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2393 /* 2394 * In HostAP mode, we defer setting of new slot time until 2395 * updated ERP Information Element has propagated to all 2396 * associated STAs. 2397 */ 2398 sc->sc_flags |= RT2661_UPDATE_SLOT; 2399 } else 2400 rt2661_set_slottime(sc); 2401 } 2402 2403 static void 2404 rt2661_set_slottime(struct rt2661_softc *sc) 2405 { 2406 struct ieee80211com *ic = &sc->sc_ic; 2407 uint8_t slottime; 2408 uint32_t tmp; 2409 2410 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2411 2412 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2413 tmp = (tmp & ~0xff) | slottime; 2414 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2415 2416 DPRINTF(("setting slot time to %uus\n", slottime)); 2417 } 2418 2419 static const char * 2420 rt2661_get_rf(int rev) 2421 { 2422 switch (rev) { 2423 case RT2661_RF_5225: return "RT5225"; 2424 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2425 case RT2661_RF_2527: return "RT2527"; 2426 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2427 default: return "unknown"; 2428 } 2429 } 2430 2431 static void 2432 rt2661_read_eeprom(struct rt2661_softc *sc) 2433 { 2434 struct ieee80211com *ic = &sc->sc_ic; 2435 uint16_t val; 2436 int i; 2437 2438 /* read MAC address */ 2439 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2440 ic->ic_myaddr[0] = val & 0xff; 2441 ic->ic_myaddr[1] = val >> 8; 2442 2443 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2444 ic->ic_myaddr[2] = val & 0xff; 2445 ic->ic_myaddr[3] = val >> 8; 2446 2447 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2448 ic->ic_myaddr[4] = val & 0xff; 2449 ic->ic_myaddr[5] = val >> 8; 2450 2451 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2452 /* XXX: test if different from 0xffff? */ 2453 sc->rf_rev = (val >> 11) & 0x1f; 2454 sc->hw_radio = (val >> 10) & 0x1; 2455 sc->rx_ant = (val >> 4) & 0x3; 2456 sc->tx_ant = (val >> 2) & 0x3; 2457 sc->nb_ant = val & 0x3; 2458 2459 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2460 2461 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2462 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2463 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2464 2465 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2466 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2467 2468 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2469 if ((val & 0xff) != 0xff) 2470 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2471 2472 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2473 if ((val & 0xff) != 0xff) 2474 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2475 2476 /* adjust RSSI correction for external low-noise amplifier */ 2477 if (sc->ext_2ghz_lna) 2478 sc->rssi_2ghz_corr -= 14; 2479 if (sc->ext_5ghz_lna) 2480 sc->rssi_5ghz_corr -= 14; 2481 2482 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2483 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2484 2485 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2486 if ((val >> 8) != 0xff) 2487 sc->rfprog = (val >> 8) & 0x3; 2488 if ((val & 0xff) != 0xff) 2489 sc->rffreq = val & 0xff; 2490 2491 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2492 2493 /* read Tx power for all a/b/g channels */ 2494 for (i = 0; i < 19; i++) { 2495 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2496 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2497 DPRINTF(("Channel=%d Tx power=%d\n", 2498 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2499 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2500 DPRINTF(("Channel=%d Tx power=%d\n", 2501 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2502 } 2503 2504 /* read vendor-specific BBP values */ 2505 for (i = 0; i < 16; i++) { 2506 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2507 if (val == 0 || val == 0xffff) 2508 continue; /* skip invalid entries */ 2509 sc->bbp_prom[i].reg = val >> 8; 2510 sc->bbp_prom[i].val = val & 0xff; 2511 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2512 sc->bbp_prom[i].val)); 2513 } 2514 } 2515 2516 static int 2517 rt2661_bbp_init(struct rt2661_softc *sc) 2518 { 2519 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2520 int i, ntries; 2521 uint8_t val; 2522 2523 /* wait for BBP to be ready */ 2524 for (ntries = 0; ntries < 100; ntries++) { 2525 val = rt2661_bbp_read(sc, 0); 2526 if (val != 0 && val != 0xff) 2527 break; 2528 DELAY(100); 2529 } 2530 if (ntries == 100) { 2531 aprint_error_dev(sc->sc_dev, "timeout waiting for BBP\n"); 2532 return EIO; 2533 } 2534 2535 /* initialize BBP registers to default values */ 2536 for (i = 0; i < N(rt2661_def_bbp); i++) { 2537 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2538 rt2661_def_bbp[i].val); 2539 } 2540 2541 /* write vendor-specific BBP values (from EEPROM) */ 2542 for (i = 0; i < 16; i++) { 2543 if (sc->bbp_prom[i].reg == 0) 2544 continue; 2545 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2546 } 2547 2548 return 0; 2549 #undef N 2550 } 2551 2552 static int 2553 rt2661_init(struct ifnet *ifp) 2554 { 2555 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2556 struct rt2661_softc *sc = ifp->if_softc; 2557 struct ieee80211com *ic = &sc->sc_ic; 2558 const char *name = NULL; /* make lint happy */ 2559 uint8_t *ucode; 2560 size_t size; 2561 uint32_t tmp, star[3]; 2562 int i, ntries; 2563 firmware_handle_t fh; 2564 2565 /* for CardBus, power on the socket */ 2566 if (!(sc->sc_flags & RT2661_ENABLED)) { 2567 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2568 aprint_error_dev(sc->sc_dev, "could not enable device\n"); 2569 return EIO; 2570 } 2571 sc->sc_flags |= RT2661_ENABLED; 2572 } 2573 2574 rt2661_stop(ifp, 0); 2575 2576 if (!(sc->sc_flags & RT2661_FWLOADED)) { 2577 switch (sc->sc_id) { 2578 case PCI_PRODUCT_RALINK_RT2561: 2579 name = "ral-rt2561"; 2580 break; 2581 case PCI_PRODUCT_RALINK_RT2561S: 2582 name = "ral-rt2561s"; 2583 break; 2584 case PCI_PRODUCT_RALINK_RT2661: 2585 name = "ral-rt2661"; 2586 break; 2587 } 2588 2589 if (firmware_open("ral", name, &fh) != 0) { 2590 aprint_error_dev(sc->sc_dev, "could not open microcode %s\n", name); 2591 rt2661_stop(ifp, 1); 2592 return EIO; 2593 } 2594 2595 size = firmware_get_size(fh); 2596 if (!(ucode = firmware_malloc(size))) { 2597 aprint_error_dev(sc->sc_dev, "could not alloc microcode memory\n"); 2598 firmware_close(fh); 2599 rt2661_stop(ifp, 1); 2600 return ENOMEM; 2601 } 2602 2603 if (firmware_read(fh, 0, ucode, size) != 0) { 2604 aprint_error_dev(sc->sc_dev, "could not read microcode %s\n", name); 2605 firmware_free(ucode, size); 2606 firmware_close(fh); 2607 rt2661_stop(ifp, 1); 2608 return EIO; 2609 } 2610 2611 if (rt2661_load_microcode(sc, ucode, size) != 0) { 2612 aprint_error_dev(sc->sc_dev, "could not load 8051 microcode\n"); 2613 firmware_free(ucode, size); 2614 firmware_close(fh); 2615 rt2661_stop(ifp, 1); 2616 return EIO; 2617 } 2618 2619 firmware_free(ucode, size); 2620 firmware_close(fh); 2621 sc->sc_flags |= RT2661_FWLOADED; 2622 } 2623 2624 /* initialize Tx rings */ 2625 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2626 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2627 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2628 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2629 2630 /* initialize Mgt ring */ 2631 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2632 2633 /* initialize Rx ring */ 2634 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2635 2636 /* initialize Tx rings sizes */ 2637 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2638 RT2661_TX_RING_COUNT << 24 | 2639 RT2661_TX_RING_COUNT << 16 | 2640 RT2661_TX_RING_COUNT << 8 | 2641 RT2661_TX_RING_COUNT); 2642 2643 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2644 RT2661_TX_DESC_WSIZE << 16 | 2645 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2646 RT2661_MGT_RING_COUNT); 2647 2648 /* initialize Rx rings */ 2649 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2650 RT2661_RX_DESC_BACK << 16 | 2651 RT2661_RX_DESC_WSIZE << 8 | 2652 RT2661_RX_RING_COUNT); 2653 2654 /* XXX: some magic here */ 2655 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2656 2657 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2658 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2659 2660 /* load base address of Rx ring */ 2661 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2662 2663 /* initialize MAC registers to default values */ 2664 for (i = 0; i < N(rt2661_def_mac); i++) 2665 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2666 2667 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2668 rt2661_set_macaddr(sc, ic->ic_myaddr); 2669 2670 /* set host ready */ 2671 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2672 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2673 2674 /* wait for BBP/RF to wakeup */ 2675 for (ntries = 0; ntries < 1000; ntries++) { 2676 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2677 break; 2678 DELAY(1000); 2679 } 2680 if (ntries == 1000) { 2681 printf("timeout waiting for BBP/RF to wakeup\n"); 2682 rt2661_stop(ifp, 1); 2683 return EIO; 2684 } 2685 2686 if (rt2661_bbp_init(sc) != 0) { 2687 rt2661_stop(ifp, 1); 2688 return EIO; 2689 } 2690 2691 /* select default channel */ 2692 sc->sc_curchan = ic->ic_curchan; 2693 rt2661_select_band(sc, sc->sc_curchan); 2694 rt2661_select_antenna(sc); 2695 rt2661_set_chan(sc, sc->sc_curchan); 2696 2697 /* update Rx filter */ 2698 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2699 2700 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2701 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2702 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2703 RT2661_DROP_ACKCTS; 2704 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2705 tmp |= RT2661_DROP_TODS; 2706 if (!(ifp->if_flags & IFF_PROMISC)) 2707 tmp |= RT2661_DROP_NOT_TO_ME; 2708 } 2709 2710 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2711 2712 /* clear STA registers */ 2713 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, star, N(star)); 2714 2715 /* initialize ASIC */ 2716 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2717 2718 /* clear any pending interrupt */ 2719 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2720 2721 /* enable interrupts */ 2722 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2723 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2724 2725 /* kick Rx */ 2726 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2727 2728 ifp->if_flags &= ~IFF_OACTIVE; 2729 ifp->if_flags |= IFF_RUNNING; 2730 2731 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2732 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2733 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2734 } else 2735 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2736 2737 return 0; 2738 #undef N 2739 } 2740 2741 static void 2742 rt2661_stop(struct ifnet *ifp, int disable) 2743 { 2744 struct rt2661_softc *sc = ifp->if_softc; 2745 struct ieee80211com *ic = &sc->sc_ic; 2746 uint32_t tmp; 2747 2748 sc->sc_tx_timer = 0; 2749 ifp->if_timer = 0; 2750 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2751 2752 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 2753 2754 /* abort Tx (for all 5 Tx rings) */ 2755 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2756 2757 /* disable Rx (value remains after reset!) */ 2758 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2759 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2760 2761 /* reset ASIC */ 2762 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2763 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2764 2765 /* disable interrupts */ 2766 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 2767 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2768 2769 /* clear any pending interrupt */ 2770 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2771 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2772 2773 /* reset Tx and Rx rings */ 2774 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2775 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2776 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2777 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2778 rt2661_reset_tx_ring(sc, &sc->mgtq); 2779 rt2661_reset_rx_ring(sc, &sc->rxq); 2780 2781 /* for CardBus, power down the socket */ 2782 if (disable && sc->sc_disable != NULL) { 2783 if (sc->sc_flags & RT2661_ENABLED) { 2784 (*sc->sc_disable)(sc); 2785 sc->sc_flags &= ~(RT2661_ENABLED | RT2661_FWLOADED); 2786 } 2787 } 2788 } 2789 2790 static int 2791 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2792 { 2793 int ntries; 2794 2795 /* reset 8051 */ 2796 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2797 2798 /* cancel any pending Host to MCU command */ 2799 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2800 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2801 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2802 2803 /* write 8051's microcode */ 2804 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2805 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2806 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2807 2808 /* kick 8051's ass */ 2809 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2810 2811 /* wait for 8051 to initialize */ 2812 for (ntries = 0; ntries < 500; ntries++) { 2813 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2814 break; 2815 DELAY(100); 2816 } 2817 if (ntries == 500) { 2818 printf("timeout waiting for MCU to initialize\n"); 2819 return EIO; 2820 } 2821 return 0; 2822 } 2823 2824 /* 2825 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2826 * false CCA count. This function is called periodically (every seconds) when 2827 * in the RUN state. Values taken from the reference driver. 2828 */ 2829 static void 2830 rt2661_rx_tune(struct rt2661_softc *sc) 2831 { 2832 uint8_t bbp17; 2833 uint16_t cca; 2834 int lo, hi, dbm; 2835 2836 /* 2837 * Tuning range depends on operating band and on the presence of an 2838 * external low-noise amplifier. 2839 */ 2840 lo = 0x20; 2841 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2842 lo += 0x08; 2843 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2844 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2845 lo += 0x10; 2846 hi = lo + 0x20; 2847 2848 dbm = sc->avg_rssi; 2849 /* retrieve false CCA count since last call (clear on read) */ 2850 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2851 2852 DPRINTFN(2, ("RSSI=%ddBm false CCA=%d\n", dbm, cca)); 2853 2854 if (dbm < -74) { 2855 /* very bad RSSI, tune using false CCA count */ 2856 bbp17 = sc->bbp17; /* current value */ 2857 2858 hi -= 2 * (-74 - dbm); 2859 if (hi < lo) 2860 hi = lo; 2861 2862 if (bbp17 > hi) 2863 bbp17 = hi; 2864 else if (cca > 512) 2865 bbp17 = uimin(bbp17 + 1, hi); 2866 else if (cca < 100) 2867 bbp17 = uimax(bbp17 - 1, lo); 2868 2869 } else if (dbm < -66) { 2870 bbp17 = lo + 0x08; 2871 } else if (dbm < -58) { 2872 bbp17 = lo + 0x10; 2873 } else if (dbm < -35) { 2874 bbp17 = hi; 2875 } else { /* very good RSSI >= -35dBm */ 2876 bbp17 = 0x60; /* very low sensitivity */ 2877 } 2878 2879 if (bbp17 != sc->bbp17) { 2880 DPRINTF(("BBP17 %x->%x\n", sc->bbp17, bbp17)); 2881 rt2661_bbp_write(sc, 17, bbp17); 2882 sc->bbp17 = bbp17; 2883 } 2884 } 2885 2886 #ifdef notyet 2887 /* 2888 * Enter/Leave radar detection mode. 2889 * This is for 802.11h additional regulatory domains. 2890 */ 2891 static void 2892 rt2661_radar_start(struct rt2661_softc *sc) 2893 { 2894 uint32_t tmp; 2895 2896 /* disable Rx */ 2897 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2898 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2899 2900 rt2661_bbp_write(sc, 82, 0x20); 2901 rt2661_bbp_write(sc, 83, 0x00); 2902 rt2661_bbp_write(sc, 84, 0x40); 2903 2904 /* save current BBP registers values */ 2905 sc->bbp18 = rt2661_bbp_read(sc, 18); 2906 sc->bbp21 = rt2661_bbp_read(sc, 21); 2907 sc->bbp22 = rt2661_bbp_read(sc, 22); 2908 sc->bbp16 = rt2661_bbp_read(sc, 16); 2909 sc->bbp17 = rt2661_bbp_read(sc, 17); 2910 sc->bbp64 = rt2661_bbp_read(sc, 64); 2911 2912 rt2661_bbp_write(sc, 18, 0xff); 2913 rt2661_bbp_write(sc, 21, 0x3f); 2914 rt2661_bbp_write(sc, 22, 0x3f); 2915 rt2661_bbp_write(sc, 16, 0xbd); 2916 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2917 rt2661_bbp_write(sc, 64, 0x21); 2918 2919 /* restore Rx filter */ 2920 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2921 } 2922 2923 static int 2924 rt2661_radar_stop(struct rt2661_softc *sc) 2925 { 2926 uint8_t bbp66; 2927 2928 /* read radar detection result */ 2929 bbp66 = rt2661_bbp_read(sc, 66); 2930 2931 /* restore BBP registers values */ 2932 rt2661_bbp_write(sc, 16, sc->bbp16); 2933 rt2661_bbp_write(sc, 17, sc->bbp17); 2934 rt2661_bbp_write(sc, 18, sc->bbp18); 2935 rt2661_bbp_write(sc, 21, sc->bbp21); 2936 rt2661_bbp_write(sc, 22, sc->bbp22); 2937 rt2661_bbp_write(sc, 64, sc->bbp64); 2938 2939 return bbp66 == 1; 2940 } 2941 #endif 2942 2943 static int 2944 rt2661_prepare_beacon(struct rt2661_softc *sc) 2945 { 2946 struct ieee80211com *ic = &sc->sc_ic; 2947 struct ieee80211_node *ni = ic->ic_bss; 2948 struct rt2661_tx_desc desc; 2949 struct mbuf *m0; 2950 struct ieee80211_beacon_offsets bo; 2951 int rate; 2952 2953 m0 = ieee80211_beacon_alloc(ic, ni, &bo); 2954 if (m0 == NULL) { 2955 aprint_error_dev(sc->sc_dev, "could not allocate beacon frame\n"); 2956 return ENOBUFS; 2957 } 2958 2959 /* send beacons at the lowest available rate */ 2960 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 2961 2962 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2963 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2964 2965 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2966 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2967 2968 /* copy beacon header and payload into NIC memory */ 2969 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2970 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2971 2972 m_freem(m0); 2973 2974 /* 2975 * Store offset of ERP Information Element so that we can update it 2976 * dynamically when the slot time changes. 2977 * XXX: this is ugly since it depends on how net80211 builds beacon 2978 * frames but ieee80211_beacon_alloc() doesn't store offsets for us. 2979 */ 2980 if (ic->ic_curmode == IEEE80211_MODE_11G) { 2981 sc->erp_csr = 2982 RT2661_HW_BEACON_BASE0 + 24 + 2983 sizeof (struct ieee80211_frame) + 2984 8 + 2 + 2 + 2 + ni->ni_esslen + 2985 2 + uimin(ni->ni_rates.rs_nrates, IEEE80211_RATE_SIZE) + 2986 2 + 1 + 2987 ((ic->ic_opmode == IEEE80211_M_IBSS) ? 4 : 6) + 2988 2; 2989 } 2990 2991 return 0; 2992 } 2993 2994 /* 2995 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2996 * and HostAP operating modes. 2997 */ 2998 static void 2999 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 3000 { 3001 struct ieee80211com *ic = &sc->sc_ic; 3002 uint32_t tmp; 3003 3004 if (ic->ic_opmode != IEEE80211_M_STA) { 3005 /* 3006 * Change default 16ms TBTT adjustment to 8ms. 3007 * Must be done before enabling beacon generation. 3008 */ 3009 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 3010 } 3011 3012 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 3013 3014 /* set beacon interval (in 1/16ms unit) */ 3015 tmp |= ic->ic_bss->ni_intval * 16; 3016 3017 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 3018 if (ic->ic_opmode == IEEE80211_M_STA) 3019 tmp |= RT2661_TSF_MODE(1); 3020 else 3021 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 3022 3023 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 3024 } 3025 3026 /* 3027 * Retrieve the "Received Signal Strength Indicator" from the raw values 3028 * contained in Rx descriptors. The computation depends on which band the 3029 * frame was received. Correction values taken from the reference driver. 3030 */ 3031 static int 3032 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 3033 { 3034 int lna, agc, rssi; 3035 3036 lna = (raw >> 5) & 0x3; 3037 agc = raw & 0x1f; 3038 3039 rssi = 2 * agc; 3040 3041 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 3042 rssi += sc->rssi_2ghz_corr; 3043 3044 if (lna == 1) 3045 rssi -= 64; 3046 else if (lna == 2) 3047 rssi -= 74; 3048 else if (lna == 3) 3049 rssi -= 90; 3050 } else { 3051 rssi += sc->rssi_5ghz_corr; 3052 3053 if (lna == 1) 3054 rssi -= 64; 3055 else if (lna == 2) 3056 rssi -= 86; 3057 else if (lna == 3) 3058 rssi -= 100; 3059 } 3060 return rssi; 3061 } 3062
Indexes created Thu Sep 25 08:09:54 GMT 2025