rt2661reg.h revision 1.1.62.1
1 /* $OpenBSD: rt2661reg.h,v 1.5 2006/01/14 12:43:27 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define RT2661_TX_RING_COUNT 32 21 #define RT2661_MGT_RING_COUNT 32 22 #define RT2661_RX_RING_COUNT 64 23 24 #define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc)) 25 #define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4) 26 #define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc)) 27 #define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4) 28 29 #define RT2661_MAX_SCATTER 5 30 31 /* 32 * Control and status registers. 33 */ 34 #define RT2661_HOST_CMD_CSR 0x0008 35 #define RT2661_MCU_CNTL_CSR 0x000c 36 #define RT2661_SOFT_RESET_CSR 0x0010 37 #define RT2661_MCU_INT_SOURCE_CSR 0x0014 38 #define RT2661_MCU_INT_MASK_CSR 0x0018 39 #define RT2661_PCI_USEC_CSR 0x001c 40 #define RT2661_H2M_MAILBOX_CSR 0x2100 41 #define RT2661_M2H_CMD_DONE_CSR 0x2104 42 #define RT2661_HW_BEACON_BASE0 0x2c00 43 #define RT2661_MAC_CSR0 0x3000 44 #define RT2661_MAC_CSR1 0x3004 45 #define RT2661_MAC_CSR2 0x3008 46 #define RT2661_MAC_CSR3 0x300c 47 #define RT2661_MAC_CSR4 0x3010 48 #define RT2661_MAC_CSR5 0x3014 49 #define RT2661_MAC_CSR6 0x3018 50 #define RT2661_MAC_CSR7 0x301c 51 #define RT2661_MAC_CSR8 0x3020 52 #define RT2661_MAC_CSR9 0x3024 53 #define RT2661_MAC_CSR10 0x3028 54 #define RT2661_MAC_CSR11 0x302c 55 #define RT2661_MAC_CSR12 0x3030 56 #define RT2661_MAC_CSR13 0x3034 57 #define RT2661_MAC_CSR14 0x3038 58 #define RT2661_MAC_CSR15 0x303c 59 #define RT2661_TXRX_CSR0 0x3040 60 #define RT2661_TXRX_CSR1 0x3044 61 #define RT2661_TXRX_CSR2 0x3048 62 #define RT2661_TXRX_CSR3 0x304c 63 #define RT2661_TXRX_CSR4 0x3050 64 #define RT2661_TXRX_CSR5 0x3054 65 #define RT2661_TXRX_CSR6 0x3058 66 #define RT2661_TXRX_CSR7 0x305c 67 #define RT2661_TXRX_CSR8 0x3060 68 #define RT2661_TXRX_CSR9 0x3064 69 #define RT2661_TXRX_CSR10 0x3068 70 #define RT2661_TXRX_CSR11 0x306c 71 #define RT2661_TXRX_CSR12 0x3070 72 #define RT2661_TXRX_CSR13 0x3074 73 #define RT2661_TXRX_CSR14 0x3078 74 #define RT2661_TXRX_CSR15 0x307c 75 #define RT2661_PHY_CSR0 0x3080 76 #define RT2661_PHY_CSR1 0x3084 77 #define RT2661_PHY_CSR2 0x3088 78 #define RT2661_PHY_CSR3 0x308c 79 #define RT2661_PHY_CSR4 0x3090 80 #define RT2661_PHY_CSR5 0x3094 81 #define RT2661_PHY_CSR6 0x3098 82 #define RT2661_PHY_CSR7 0x309c 83 #define RT2661_SEC_CSR0 0x30a0 84 #define RT2661_SEC_CSR1 0x30a4 85 #define RT2661_SEC_CSR2 0x30a8 86 #define RT2661_SEC_CSR3 0x30ac 87 #define RT2661_SEC_CSR4 0x30b0 88 #define RT2661_SEC_CSR5 0x30b4 89 #define RT2661_STA_CSR0 0x30c0 90 #define RT2661_STA_CSR1 0x30c4 91 #define RT2661_STA_CSR2 0x30c8 92 #define RT2661_STA_CSR3 0x30cc 93 #define RT2661_STA_CSR4 0x30d0 94 #define RT2661_AC0_BASE_CSR 0x3400 95 #define RT2661_AC1_BASE_CSR 0x3404 96 #define RT2661_AC2_BASE_CSR 0x3408 97 #define RT2661_AC3_BASE_CSR 0x340c 98 #define RT2661_MGT_BASE_CSR 0x3410 99 #define RT2661_TX_RING_CSR0 0x3418 100 #define RT2661_TX_RING_CSR1 0x341c 101 #define RT2661_AIFSN_CSR 0x3420 102 #define RT2661_CWMIN_CSR 0x3424 103 #define RT2661_CWMAX_CSR 0x3428 104 #define RT2661_TX_DMA_DST_CSR 0x342c 105 #define RT2661_TX_CNTL_CSR 0x3430 106 #define RT2661_LOAD_TX_RING_CSR 0x3434 107 #define RT2661_RX_BASE_CSR 0x3450 108 #define RT2661_RX_RING_CSR 0x3454 109 #define RT2661_RX_CNTL_CSR 0x3458 110 #define RT2661_PCI_CFG_CSR 0x3460 111 #define RT2661_INT_SOURCE_CSR 0x3468 112 #define RT2661_INT_MASK_CSR 0x346c 113 #define RT2661_E2PROM_CSR 0x3470 114 #define RT2661_AC_TXOP_CSR0 0x3474 115 #define RT2661_AC_TXOP_CSR1 0x3478 116 #define RT2661_TEST_MODE_CSR 0x3484 117 #define RT2661_IO_CNTL_CSR 0x3498 118 #define RT2661_MCU_CODE_BASE 0x4000 119 120 121 /* possible flags for register HOST_CMD_CSR */ 122 #define RT2661_KICK_CMD (1 << 7) 123 /* Host to MCU (8051) command identifiers */ 124 #define RT2661_MCU_CMD_SLEEP 0x30 125 #define RT2661_MCU_CMD_WAKEUP 0x31 126 #define RT2661_MCU_SET_LED 0x50 127 #define RT2661_MCU_SET_RSSI_LED 0x52 128 129 /* possible flags for register MCU_CNTL_CSR */ 130 #define RT2661_MCU_SEL (1 << 0) 131 #define RT2661_MCU_RESET (1 << 1) 132 #define RT2661_MCU_READY (1 << 2) 133 134 /* possible flags for register MCU_INT_SOURCE_CSR */ 135 #define RT2661_MCU_CMD_DONE 0xff 136 #define RT2661_MCU_WAKEUP (1 << 8) 137 #define RT2661_MCU_BEACON_EXPIRE (1 << 9) 138 139 /* possible flags for register H2M_MAILBOX_CSR */ 140 #define RT2661_H2M_BUSY (1 << 24) 141 #define RT2661_TOKEN_NO_INTR 0xff 142 143 /* possible flags for register MAC_CSR5 */ 144 #define RT2661_ONE_BSSID 3 145 146 /* possible flags for register TXRX_CSR0 */ 147 /* Tx filter flags are in the low 16 bits */ 148 #define RT2661_AUTO_TX_SEQ (1 << 15) 149 /* Rx filter flags are in the high 16 bits */ 150 #define RT2661_DISABLE_RX (1 << 16) 151 #define RT2661_DROP_CRC_ERROR (1 << 17) 152 #define RT2661_DROP_PHY_ERROR (1 << 18) 153 #define RT2661_DROP_CTL (1 << 19) 154 #define RT2661_DROP_NOT_TO_ME (1 << 20) 155 #define RT2661_DROP_TODS (1 << 21) 156 #define RT2661_DROP_VER_ERROR (1 << 22) 157 #define RT2661_DROP_MULTICAST (1 << 23) 158 #define RT2661_DROP_BROADCAST (1 << 24) 159 #define RT2661_DROP_ACKCTS (1 << 25) 160 161 /* possible flags for register TXRX_CSR4 */ 162 #define RT2661_SHORT_PREAMBLE (1 << 18) 163 #define RT2661_MRR_ENABLED (1 << 19) 164 #define RT2661_MRR_CCK_FALLBACK (1 << 22) 165 166 /* possible flags for register TXRX_CSR9 */ 167 #define RT2661_TSF_TICKING (1 << 16) 168 #define RT2661_TSF_MODE(x) (((x) & 0x3) << 17) 169 /* TBTT stands for Target Beacon Transmission Time */ 170 #define RT2661_ENABLE_TBTT (1 << 19) 171 #define RT2661_GENERATE_BEACON (1 << 20) 172 173 /* possible flags for register PHY_CSR0 */ 174 #define RT2661_PA_PE_2GHZ (1 << 16) 175 #define RT2661_PA_PE_5GHZ (1 << 17) 176 177 /* possible flags for register PHY_CSR3 */ 178 #define RT2661_BBP_READ (1 << 15) 179 #define RT2661_BBP_BUSY (1 << 16) 180 181 /* possible flags for register PHY_CSR4 */ 182 #define RT2661_RF_21BIT (21 << 24) 183 #define RT2661_RF_BUSY (1 << 31) 184 185 /* possible values for register STA_CSR4 */ 186 #define RT2661_TX_STAT_VALID (1 << 0) 187 #define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7) 188 #define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf) 189 #define RT2661_TX_QID(v) (((v) >> 8) & 0xf) 190 #define RT2661_TX_SUCCESS 0 191 #define RT2661_TX_RETRY_FAIL 6 192 193 /* possible flags for register TX_CNTL_CSR */ 194 #define RT2661_KICK_MGT (1 << 4) 195 196 /* possible flags for register INT_SOURCE_CSR */ 197 #define RT2661_TX_DONE (1 << 0) 198 #define RT2661_RX_DONE (1 << 1) 199 #define RT2661_TX0_DMA_DONE (1 << 16) 200 #define RT2661_TX1_DMA_DONE (1 << 17) 201 #define RT2661_TX2_DMA_DONE (1 << 18) 202 #define RT2661_TX3_DMA_DONE (1 << 19) 203 #define RT2661_MGT_DONE (1 << 20) 204 205 /* possible flags for register E2PROM_CSR */ 206 #define RT2661_C (1 << 1) 207 #define RT2661_S (1 << 2) 208 #define RT2661_D (1 << 3) 209 #define RT2661_Q (1 << 4) 210 #define RT2661_93C46 (1 << 5) 211 212 /* Tx descriptor */ 213 struct rt2661_tx_desc { 214 uint32_t flags; 215 #define RT2661_TX_BUSY (1 << 0) 216 #define RT2661_TX_VALID (1 << 1) 217 #define RT2661_TX_MORE_FRAG (1 << 2) 218 #define RT2661_TX_NEED_ACK (1 << 3) 219 #define RT2661_TX_TIMESTAMP (1 << 4) 220 #define RT2661_TX_OFDM (1 << 5) 221 #define RT2661_TX_IFS (1 << 6) 222 #define RT2661_TX_LONG_RETRY (1 << 7) 223 #define RT2661_TX_BURST (1 << 28) 224 225 uint16_t wme; 226 #define RT2661_QID(v) (v) 227 #define RT2661_AIFSN(v) ((v) << 4) 228 #define RT2661_LOGCWMIN(v) ((v) << 8) 229 #define RT2661_LOGCWMAX(v) ((v) << 12) 230 231 uint16_t xflags; 232 #define RT2661_TX_HWSEQ (1 << 12) 233 234 uint8_t plcp_signal; 235 uint8_t plcp_service; 236 #define RT2661_PLCP_LENGEXT 0x80 237 238 uint8_t plcp_length_lo; 239 uint8_t plcp_length_hi; 240 241 uint32_t iv; 242 uint32_t eiv; 243 244 uint8_t offset; 245 uint8_t qid; 246 #define RT2661_QID_MGT 13 247 248 uint8_t txpower; 249 #define RT2661_DEFAULT_TXPOWER 0 250 251 uint8_t reserved1; 252 253 uint32_t addr[RT2661_MAX_SCATTER]; 254 uint16_t len[RT2661_MAX_SCATTER]; 255 256 uint16_t reserved2; 257 } __packed; 258 259 /* Rx descriptor */ 260 struct rt2661_rx_desc { 261 uint32_t flags; 262 #define RT2661_RX_BUSY (1 << 0) 263 #define RT2661_RX_DROP (1 << 1) 264 #define RT2661_RX_CRC_ERROR (1 << 6) 265 #define RT2661_RX_OFDM (1 << 7) 266 #define RT2661_RX_PHY_ERROR (1 << 8) 267 #define RT2661_RX_CIPHER_MASK 0x00000600 268 269 uint8_t rate; 270 uint8_t rssi; 271 uint8_t reserved1; 272 uint8_t offset; 273 uint32_t iv; 274 uint32_t eiv; 275 uint32_t reserved2; 276 uint32_t physaddr; 277 uint32_t reserved3[10]; 278 } __packed; 279 280 #define RAL_RF1 0 281 #define RAL_RF2 2 282 #define RAL_RF3 1 283 #define RAL_RF4 3 284 285 /* dual-band RF */ 286 #define RT2661_RF_5225 1 287 #define RT2661_RF_5325 2 288 /* single-band RF */ 289 #define RT2661_RF_2527 3 290 #define RT2661_RF_2529 4 291 292 #define RT2661_RX_DESC_BACK 4 293 294 #define RT2661_SMART_MODE (1 << 0) 295 296 #define RT2661_BBPR94_DEFAULT 6 297 298 #define RT2661_SHIFT_D 3 299 #define RT2661_SHIFT_Q 4 300 301 #define RT2661_EEPROM_MAC01 0x02 302 #define RT2661_EEPROM_MAC23 0x03 303 #define RT2661_EEPROM_MAC45 0x04 304 #define RT2661_EEPROM_ANTENNA 0x10 305 #define RT2661_EEPROM_CONFIG2 0x11 306 #define RT2661_EEPROM_BBP_BASE 0x13 307 #define RT2661_EEPROM_TXPOWER 0x23 308 #define RT2661_EEPROM_FREQ_OFFSET 0x2f 309 #define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d 310 #define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e 311 312 #define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 313 314 /* 315 * control and status registers access macros 316 */ 317 #define RAL_READ(sc, reg) \ 318 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 319 320 #define RAL_READ_REGION_4(sc, offset, datap, count) \ 321 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 322 (datap), (count)) 323 324 #define RAL_WRITE(sc, reg, val) \ 325 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 326 327 #define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 328 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 329 (datap), (count)) 330 331 /* 332 * EEPROM access macro 333 */ 334 #define RT2661_EEPROM_CTL(sc, val) do { \ 335 RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \ 336 DELAY(RT2661_EEPROM_DELAY); \ 337 } while (/* CONSTCOND */0) 338
Indexes created Wed Oct 22 06:10:02 GMT 2025