rt2860reg.h revision 1.1.20.1
1 /* $NetBSD: rt2860reg.h,v 1.1.20.1 2016/05/29 08:44:21 skrll Exp $ */ 2 /* $OpenBSD: rt2860reg.h,v 1.32 2014/05/24 10:10:17 stsp Exp $ */ 3 4 /*- 5 * Copyright (c) 2007 6 * Damien Bergamini <damien.bergamini (at) free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* PCI registers */ 22 #define RT2860_PCI_CFG 0x0000 23 #define RT2860_PCI_EECTRL 0x0004 24 #define RT2860_PCI_MCUCTRL 0x0008 25 #define RT2860_PCI_SYSCTRL 0x000c 26 #define RT2860_PCIE_JTAG 0x0010 27 28 #define RT3090_AUX_CTRL 0x010c 29 30 #define RT3070_OPT_14 0x0114 31 32 /* SCH/DMA registers */ 33 #define RT2860_INT_STATUS 0x0200 34 #define RT2860_INT_MASK 0x0204 35 #define RT2860_WPDMA_GLO_CFG 0x0208 36 #define RT2860_WPDMA_RST_IDX 0x020c 37 #define RT2860_DELAY_INT_CFG 0x0210 38 #define RT2860_WMM_AIFSN_CFG 0x0214 39 #define RT2860_WMM_CWMIN_CFG 0x0218 40 #define RT2860_WMM_CWMAX_CFG 0x021c 41 #define RT2860_WMM_TXOP0_CFG 0x0220 42 #define RT2860_WMM_TXOP1_CFG 0x0224 43 #define RT2860_GPIO_CTRL 0x0228 44 #define RT2860_MCU_CMD_REG 0x022c 45 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) 46 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) 47 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) 48 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) 49 #define RT2860_RX_BASE_PTR 0x0290 50 #define RT2860_RX_MAX_CNT 0x0294 51 #define RT2860_RX_CALC_IDX 0x0298 52 #define RT2860_FS_DRX_IDX 0x029c 53 #define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ 54 #define RT2860_US_CYC_CNT 0x02a4 55 56 /* PBF registers */ 57 #define RT2860_SYS_CTRL 0x0400 58 #define RT2860_HOST_CMD 0x0404 59 #define RT2860_PBF_CFG 0x0408 60 #define RT2860_MAX_PCNT 0x040c 61 #define RT2860_BUF_CTRL 0x0410 62 #define RT2860_MCU_INT_STA 0x0414 63 #define RT2860_MCU_INT_ENA 0x0418 64 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) 65 #define RT2860_RX0Q_IO 0x0424 66 #define RT2860_BCN_OFFSET0 0x042c 67 #define RT2860_BCN_OFFSET1 0x0430 68 #define RT2860_TXRXQ_STA 0x0434 69 #define RT2860_TXRXQ_PCNT 0x0438 70 #define RT2860_PBF_DBG 0x043c 71 #define RT2860_CAP_CTRL 0x0440 72 73 /* RT3070 registers */ 74 #define RT3070_RF_CSR_CFG 0x0500 75 #define RT3070_EFUSE_CTRL 0x0580 76 #define RT3070_EFUSE_DATA0 0x0590 77 #define RT3070_EFUSE_DATA1 0x0594 78 #define RT3070_EFUSE_DATA2 0x0598 79 #define RT3070_EFUSE_DATA3 0x059c 80 #define RT3090_OSC_CTRL 0x05a4 81 #define RT3070_LDO_CFG0 0x05d4 82 #define RT3070_GPIO_SWITCH 0x05dc 83 84 /* RT5592 registers */ 85 #define RT5592_DEBUG_INDEX 0x05e8 86 87 /* MAC registers */ 88 #define RT2860_ASIC_VER_ID 0x1000 89 #define RT2860_MAC_SYS_CTRL 0x1004 90 #define RT2860_MAC_ADDR_DW0 0x1008 91 #define RT2860_MAC_ADDR_DW1 0x100c 92 #define RT2860_MAC_BSSID_DW0 0x1010 93 #define RT2860_MAC_BSSID_DW1 0x1014 94 #define RT2860_MAX_LEN_CFG 0x1018 95 #define RT2860_BBP_CSR_CFG 0x101c 96 #define RT2860_RF_CSR_CFG0 0x1020 97 #define RT2860_RF_CSR_CFG1 0x1024 98 #define RT2860_RF_CSR_CFG2 0x1028 99 #define RT2860_LED_CFG 0x102c 100 101 /* undocumented registers */ 102 #define RT2860_DEBUG 0x10f4 103 104 /* MAC Timing control registers */ 105 #define RT2860_XIFS_TIME_CFG 0x1100 106 #define RT2860_BKOFF_SLOT_CFG 0x1104 107 #define RT2860_NAV_TIME_CFG 0x1108 108 #define RT2860_CH_TIME_CFG 0x110c 109 #define RT2860_PBF_LIFE_TIMER 0x1110 110 #define RT2860_BCN_TIME_CFG 0x1114 111 #define RT2860_TBTT_SYNC_CFG 0x1118 112 #define RT2860_TSF_TIMER_DW0 0x111c 113 #define RT2860_TSF_TIMER_DW1 0x1120 114 #define RT2860_TBTT_TIMER 0x1124 115 #define RT2860_INT_TIMER_CFG 0x1128 116 #define RT2860_INT_TIMER_EN 0x112c 117 #define RT2860_CH_IDLE_TIME 0x1130 118 119 /* MAC Power Save configuration registers */ 120 #define RT2860_MAC_STATUS_REG 0x1200 121 #define RT2860_PWR_PIN_CFG 0x1204 122 #define RT2860_AUTO_WAKEUP_CFG 0x1208 123 124 /* MAC TX configuration registers */ 125 #define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) 126 #define RT2860_EDCA_TID_AC_MAP 0x1310 127 #define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) 128 #define RT2860_TX_PIN_CFG 0x1328 129 #define RT2860_TX_BAND_CFG 0x132c 130 #define RT2860_TX_SW_CFG0 0x1330 131 #define RT2860_TX_SW_CFG1 0x1334 132 #define RT2860_TX_SW_CFG2 0x1338 133 #define RT2860_TXOP_THRES_CFG 0x133c 134 #define RT2860_TXOP_CTRL_CFG 0x1340 135 #define RT2860_TX_RTS_CFG 0x1344 136 #define RT2860_TX_TIMEOUT_CFG 0x1348 137 #define RT2860_TX_RTY_CFG 0x134c 138 #define RT2860_TX_LINK_CFG 0x1350 139 #define RT2860_HT_FBK_CFG0 0x1354 140 #define RT2860_HT_FBK_CFG1 0x1358 141 #define RT2860_LG_FBK_CFG0 0x135c 142 #define RT2860_LG_FBK_CFG1 0x1360 143 #define RT2860_CCK_PROT_CFG 0x1364 144 #define RT2860_OFDM_PROT_CFG 0x1368 145 #define RT2860_MM20_PROT_CFG 0x136c 146 #define RT2860_MM40_PROT_CFG 0x1370 147 #define RT2860_GF20_PROT_CFG 0x1374 148 #define RT2860_GF40_PROT_CFG 0x1378 149 #define RT2860_EXP_CTS_TIME 0x137c 150 #define RT2860_EXP_ACK_TIME 0x1380 151 152 /* MAC RX configuration registers */ 153 #define RT2860_RX_FILTR_CFG 0x1400 154 #define RT2860_AUTO_RSP_CFG 0x1404 155 #define RT2860_LEGACY_BASIC_RATE 0x1408 156 #define RT2860_HT_BASIC_RATE 0x140c 157 #define RT2860_HT_CTRL_CFG 0x1410 158 #define RT2860_SIFS_COST_CFG 0x1414 159 #define RT2860_RX_PARSER_CFG 0x1418 160 161 /* MAC Security configuration registers */ 162 #define RT2860_TX_SEC_CNT0 0x1500 163 #define RT2860_RX_SEC_CNT0 0x1504 164 #define RT2860_CCMP_FC_MUTE 0x1508 165 166 /* MAC HCCA/PSMP configuration registers */ 167 #define RT2860_TXOP_HLDR_ADDR0 0x1600 168 #define RT2860_TXOP_HLDR_ADDR1 0x1604 169 #define RT2860_TXOP_HLDR_ET 0x1608 170 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c 171 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610 172 #define RT2860_QOS_CFPOLL_QC 0x1614 173 174 /* MAC Statistics Counters */ 175 #define RT2860_RX_STA_CNT0 0x1700 176 #define RT2860_RX_STA_CNT1 0x1704 177 #define RT2860_RX_STA_CNT2 0x1708 178 #define RT2860_TX_STA_CNT0 0x170c 179 #define RT2860_TX_STA_CNT1 0x1710 180 #define RT2860_TX_STA_CNT2 0x1714 181 #define RT2860_TX_STAT_FIFO 0x1718 182 183 /* RX WCID search table */ 184 #define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) 185 186 #define RT2860_FW_BASE 0x2000 187 #define RT2870_FW_BASE 0x3000 188 189 /* Pair-wise key table */ 190 #define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) 191 192 /* IV/EIV table */ 193 #define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) 194 195 /* WCID attribute table */ 196 #define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) 197 198 /* Shared Key Table */ 199 #define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) 200 201 /* Shared Key Mode */ 202 #define RT2860_SKEY_MODE_0_7 0x7000 203 #define RT2860_SKEY_MODE_8_15 0x7004 204 #define RT2860_SKEY_MODE_16_23 0x7008 205 #define RT2860_SKEY_MODE_24_31 0x700c 206 207 /* Shared Memory between MCU and host */ 208 #define RT2860_H2M_MAILBOX 0x7010 209 #define RT2860_H2M_MAILBOX_CID 0x7014 210 #define RT2860_H2M_MAILBOX_STATUS 0x701c 211 #define RT2860_H2M_INTSRC 0x7024 212 #define RT2860_H2M_BBPAGENT 0x7028 213 #define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) 214 215 216 /* possible flags for RT2860_PCI_CFG */ 217 #define RT2860_PCI_CFG_USB (1 << 17) 218 #define RT2860_PCI_CFG_PCI (1 << 16) 219 220 /* possible flags for register RT2860_PCI_EECTRL */ 221 #define RT2860_C (1 << 0) 222 #define RT2860_S (1 << 1) 223 #define RT2860_D (1 << 2) 224 #define RT2860_SHIFT_D 2 225 #define RT2860_Q (1 << 3) 226 #define RT2860_SHIFT_Q 3 227 228 /* possible flags for registers INT_STATUS/INT_MASK */ 229 #define RT2860_TX_COHERENT (1 << 17) 230 #define RT2860_RX_COHERENT (1 << 16) 231 #define RT2860_MAC_INT_4 (1 << 15) 232 #define RT2860_MAC_INT_3 (1 << 14) 233 #define RT2860_MAC_INT_2 (1 << 13) 234 #define RT2860_MAC_INT_1 (1 << 12) 235 #define RT2860_MAC_INT_0 (1 << 11) 236 #define RT2860_TX_RX_COHERENT (1 << 10) 237 #define RT2860_MCU_CMD_INT (1 << 9) 238 #define RT2860_TX_DONE_INT5 (1 << 8) 239 #define RT2860_TX_DONE_INT4 (1 << 7) 240 #define RT2860_TX_DONE_INT3 (1 << 6) 241 #define RT2860_TX_DONE_INT2 (1 << 5) 242 #define RT2860_TX_DONE_INT1 (1 << 4) 243 #define RT2860_TX_DONE_INT0 (1 << 3) 244 #define RT2860_RX_DONE_INT (1 << 2) 245 #define RT2860_TX_DLY_INT (1 << 1) 246 #define RT2860_RX_DLY_INT (1 << 0) 247 248 /* possible flags for register WPDMA_GLO_CFG */ 249 #define RT2860_HDR_SEG_LEN_SHIFT 8 250 #define RT2860_BIG_ENDIAN (1 << 7) 251 #define RT2860_TX_WB_DDONE (1 << 6) 252 #define RT2860_WPDMA_BT_SIZE_SHIFT 4 253 #define RT2860_WPDMA_BT_SIZE16 0 254 #define RT2860_WPDMA_BT_SIZE32 1 255 #define RT2860_WPDMA_BT_SIZE64 2 256 #define RT2860_WPDMA_BT_SIZE128 3 257 #define RT2860_RX_DMA_BUSY (1 << 3) 258 #define RT2860_RX_DMA_EN (1 << 2) 259 #define RT2860_TX_DMA_BUSY (1 << 1) 260 #define RT2860_TX_DMA_EN (1 << 0) 261 262 /* possible flags for register DELAY_INT_CFG */ 263 #define RT2860_TXDLY_INT_EN (1U << 31) 264 #define RT2860_TXMAX_PINT_SHIFT 24 265 #define RT2860_TXMAX_PTIME_SHIFT 16 266 #define RT2860_RXDLY_INT_EN (1U << 15) 267 #define RT2860_RXMAX_PINT_SHIFT 8 268 #define RT2860_RXMAX_PTIME_SHIFT 0 269 270 /* possible flags for register GPIO_CTRL */ 271 #define RT2860_GPIO_D_SHIFT 8 272 #define RT2860_GPIO_O_SHIFT 0 273 274 /* possible flags for register USB_DMA_CFG */ 275 #define RT2860_USB_TX_BUSY (1U << 31) 276 #define RT2860_USB_RX_BUSY (1U << 30) 277 #define RT2860_USB_EPOUT_VLD_SHIFT 24 278 #define RT2860_USB_TX_EN (1U << 23) 279 #define RT2860_USB_RX_EN (1U << 22) 280 #define RT2860_USB_RX_AGG_EN (1U << 21) 281 #define RT2860_USB_TXOP_HALT (1U << 20) 282 #define RT2860_USB_TX_CLEAR (1U << 19) 283 #define RT2860_USB_PHY_WD_EN (1U << 16) 284 #define RT2860_USB_PHY_MAN_RST (1U << 15) 285 #define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ 286 #define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ 287 288 /* possible flags for register US_CYC_CNT */ 289 #define RT2860_TEST_EN (1 << 24) 290 #define RT2860_TEST_SEL_SHIFT 16 291 #define RT2860_BT_MODE_EN (1 << 8) 292 #define RT2860_US_CYC_CNT_SHIFT 0 293 294 /* possible flags for register SYS_CTRL */ 295 #define RT2860_HST_PM_SEL (1 << 16) 296 #define RT2860_CAP_MODE (1 << 14) 297 #define RT2860_PME_OEN (1 << 13) 298 #define RT2860_CLKSELECT (1 << 12) 299 #define RT2860_PBF_CLK_EN (1 << 11) 300 #define RT2860_MAC_CLK_EN (1 << 10) 301 #define RT2860_DMA_CLK_EN (1 << 9) 302 #define RT2860_MCU_READY (1 << 7) 303 #define RT2860_ASY_RESET (1 << 4) 304 #define RT2860_PBF_RESET (1 << 3) 305 #define RT2860_MAC_RESET (1 << 2) 306 #define RT2860_DMA_RESET (1 << 1) 307 #define RT2860_MCU_RESET (1 << 0) 308 309 /* possible values for register HOST_CMD */ 310 #define RT2860_MCU_CMD_SLEEP 0x30 311 #define RT2860_MCU_CMD_WAKEUP 0x31 312 #define RT2860_MCU_CMD_LEDS 0x50 313 #define RT2860_MCU_CMD_LED_RSSI 0x51 314 #define RT2860_MCU_CMD_LED1 0x52 315 #define RT2860_MCU_CMD_LED2 0x53 316 #define RT2860_MCU_CMD_LED3 0x54 317 #define RT2860_MCU_CMD_RFRESET 0x72 318 #define RT2860_MCU_CMD_ANTSEL 0x73 319 #define RT2860_MCU_CMD_BBP 0x80 320 #define RT2860_MCU_CMD_PSLEVEL 0x83 321 322 /* possible flags for register PBF_CFG */ 323 #define RT2860_TX1Q_NUM_SHIFT 21 324 #define RT2860_TX2Q_NUM_SHIFT 16 325 #define RT2860_NULL0_MODE (1 << 15) 326 #define RT2860_NULL1_MODE (1 << 14) 327 #define RT2860_RX_DROP_MODE (1 << 13) 328 #define RT2860_TX0Q_MANUAL (1 << 12) 329 #define RT2860_TX1Q_MANUAL (1 << 11) 330 #define RT2860_TX2Q_MANUAL (1 << 10) 331 #define RT2860_RX0Q_MANUAL (1 << 9) 332 #define RT2860_HCCA_EN (1 << 8) 333 #define RT2860_TX0Q_EN (1 << 4) 334 #define RT2860_TX1Q_EN (1 << 3) 335 #define RT2860_TX2Q_EN (1 << 2) 336 #define RT2860_RX0Q_EN (1 << 1) 337 338 /* possible flags for register BUF_CTRL */ 339 #define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) 340 #define RT2860_NULL0_KICK (1 << 7) 341 #define RT2860_NULL1_KICK (1 << 6) 342 #define RT2860_BUF_RESET (1 << 5) 343 #define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) 344 #define RT2860_READ_RX0Q (1 << 0) 345 346 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ 347 #define RT2860_MCU_MAC_INT_8 (1 << 24) 348 #define RT2860_MCU_MAC_INT_7 (1 << 23) 349 #define RT2860_MCU_MAC_INT_6 (1 << 22) 350 #define RT2860_MCU_MAC_INT_4 (1 << 20) 351 #define RT2860_MCU_MAC_INT_3 (1 << 19) 352 #define RT2860_MCU_MAC_INT_2 (1 << 18) 353 #define RT2860_MCU_MAC_INT_1 (1 << 17) 354 #define RT2860_MCU_MAC_INT_0 (1 << 16) 355 #define RT2860_DTX0_INT (1 << 11) 356 #define RT2860_DTX1_INT (1 << 10) 357 #define RT2860_DTX2_INT (1 << 9) 358 #define RT2860_DRX0_INT (1 << 8) 359 #define RT2860_HCMD_INT (1 << 7) 360 #define RT2860_N0TX_INT (1 << 6) 361 #define RT2860_N1TX_INT (1 << 5) 362 #define RT2860_BCNTX_INT (1 << 4) 363 #define RT2860_MTX0_INT (1 << 3) 364 #define RT2860_MTX1_INT (1 << 2) 365 #define RT2860_MTX2_INT (1 << 1) 366 #define RT2860_MRX0_INT (1 << 0) 367 368 /* possible flags for register TXRXQ_PCNT */ 369 #define RT2860_RX0Q_PCNT_MASK 0xff000000 370 #define RT2860_TX2Q_PCNT_MASK 0x00ff0000 371 #define RT2860_TX1Q_PCNT_MASK 0x0000ff00 372 #define RT2860_TX0Q_PCNT_MASK 0x000000ff 373 374 /* possible flags for register CAP_CTRL */ 375 #define RT2860_CAP_ADC_FEQ (1U << 31) 376 #define RT2860_CAP_START (1U << 30) 377 #define RT2860_MAN_TRIG (1U << 29) 378 #define RT2860_TRIG_OFFSET_SHIFT 16 379 #define RT2860_START_ADDR_SHIFT 0 380 381 /* possible flags for register RF_CSR_CFG */ 382 #define RT3070_RF_KICK (1 << 17) 383 #define RT3070_RF_WRITE (1 << 16) 384 385 /* possible flags for register EFUSE_CTRL */ 386 #define RT3070_SEL_EFUSE (1U << 31) 387 #define RT3070_EFSROM_KICK (1U << 30) 388 #define RT3070_EFSROM_AIN_MASK 0x03ff0000 389 #define RT3070_EFSROM_AIN_SHIFT 16 390 #define RT3070_EFSROM_MODE_MASK 0x000000c0 391 #define RT3070_EFUSE_AOUT_MASK 0x0000003f 392 393 /* possible flag for register DEBUG_INDEX */ 394 #define RT5592_SEL_XTAL (1U << 31) 395 396 /* possible flags for register MAC_SYS_CTRL */ 397 #define RT2860_RX_TS_EN (1 << 7) 398 #define RT2860_WLAN_HALT_EN (1 << 6) 399 #define RT2860_PBF_LOOP_EN (1 << 5) 400 #define RT2860_CONT_TX_TEST (1 << 4) 401 #define RT2860_MAC_RX_EN (1 << 3) 402 #define RT2860_MAC_TX_EN (1 << 2) 403 #define RT2860_BBP_HRST (1 << 1) 404 #define RT2860_MAC_SRST (1 << 0) 405 406 /* possible flags for register MAC_BSSID_DW1 */ 407 #define RT2860_MULTI_BCN_NUM_SHIFT 18 408 #define RT2860_MULTI_BSSID_MODE_SHIFT 16 409 410 /* possible flags for register MAX_LEN_CFG */ 411 #define RT2860_MIN_MPDU_LEN_SHIFT 16 412 #define RT2860_MAX_PSDU_LEN_SHIFT 12 413 #define RT2860_MAX_PSDU_LEN8K 0 414 #define RT2860_MAX_PSDU_LEN16K 1 415 #define RT2860_MAX_PSDU_LEN32K 2 416 #define RT2860_MAX_PSDU_LEN64K 3 417 #define RT2860_MAX_MPDU_LEN_SHIFT 0 418 419 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ 420 #define RT2860_BBP_RW_PARALLEL (1 << 19) 421 #define RT2860_BBP_PAR_DUR_112_5 (1 << 18) 422 #define RT2860_BBP_CSR_KICK (1 << 17) 423 #define RT2860_BBP_CSR_READ (1 << 16) 424 #define RT2860_BBP_ADDR_SHIFT 8 425 #define RT2860_BBP_DATA_SHIFT 0 426 427 /* possible flags for register RF_CSR_CFG0 */ 428 #define RT2860_RF_REG_CTRL (1U << 31) 429 #define RT2860_RF_LE_SEL1 (1U << 30) 430 #define RT2860_RF_LE_STBY (1U << 29) 431 #define RT2860_RF_REG_WIDTH_SHIFT 24 432 #define RT2860_RF_REG_0_SHIFT 0 433 434 /* possible flags for register RF_CSR_CFG1 */ 435 #define RT2860_RF_DUR_5 (1 << 24) 436 #define RT2860_RF_REG_1_SHIFT 0 437 438 /* possible flags for register LED_CFG */ 439 #define RT2860_LED_POL (1 << 30) 440 #define RT2860_Y_LED_MODE_SHIFT 28 441 #define RT2860_G_LED_MODE_SHIFT 26 442 #define RT2860_R_LED_MODE_SHIFT 24 443 #define RT2860_LED_MODE_OFF 0 444 #define RT2860_LED_MODE_BLINK_TX 1 445 #define RT2860_LED_MODE_SLOW_BLINK 2 446 #define RT2860_LED_MODE_ON 3 447 #define RT2860_SLOW_BLK_TIME_SHIFT 16 448 #define RT2860_LED_OFF_TIME_SHIFT 8 449 #define RT2860_LED_ON_TIME_SHIFT 0 450 451 /* possible flags for register XIFS_TIME_CFG */ 452 #define RT2860_BB_RXEND_EN (1 << 29) 453 #define RT2860_EIFS_TIME_SHIFT 20 454 #define RT2860_OFDM_XIFS_TIME_SHIFT 16 455 #define RT2860_OFDM_SIFS_TIME_SHIFT 8 456 #define RT2860_CCK_SIFS_TIME_SHIFT 0 457 458 /* possible flags for register BKOFF_SLOT_CFG */ 459 #define RT2860_CC_DELAY_TIME_SHIFT 8 460 #define RT2860_SLOT_TIME 0 461 462 /* possible flags for register NAV_TIME_CFG */ 463 #define RT2860_NAV_UPD (1U << 31) 464 #define RT2860_NAV_UPD_VAL_SHIFT 16 465 #define RT2860_NAV_CLR_EN (1U << 15) 466 #define RT2860_NAV_TIMER_SHIFT 0 467 468 /* possible flags for register CH_TIME_CFG */ 469 #define RT2860_EIFS_AS_CH_BUSY (1 << 4) 470 #define RT2860_NAV_AS_CH_BUSY (1 << 3) 471 #define RT2860_RX_AS_CH_BUSY (1 << 2) 472 #define RT2860_TX_AS_CH_BUSY (1 << 1) 473 #define RT2860_CH_STA_TIMER_EN (1 << 0) 474 475 /* possible values for register BCN_TIME_CFG */ 476 #define RT2860_TSF_INS_COMP_SHIFT 24 477 #define RT2860_BCN_TX_EN (1 << 20) 478 #define RT2860_TBTT_TIMER_EN (1 << 19) 479 #define RT2860_TSF_SYNC_MODE_SHIFT 17 480 #define RT2860_TSF_SYNC_MODE_DIS 0 481 #define RT2860_TSF_SYNC_MODE_STA 1 482 #define RT2860_TSF_SYNC_MODE_IBSS 2 483 #define RT2860_TSF_SYNC_MODE_HOSTAP 3 484 #define RT2860_TSF_TIMER_EN (1 << 16) 485 #define RT2860_BCN_INTVAL_SHIFT 0 486 487 /* possible flags for register TBTT_SYNC_CFG */ 488 #define RT2860_BCN_CWMIN_SHIFT 20 489 #define RT2860_BCN_AIFSN_SHIFT 16 490 #define RT2860_BCN_EXP_WIN_SHIFT 8 491 #define RT2860_TBTT_ADJUST_SHIFT 0 492 493 /* possible flags for register INT_TIMER_CFG */ 494 #define RT2860_GP_TIMER_SHIFT 16 495 #define RT2860_PRE_TBTT_TIMER_SHIFT 0 496 497 /* possible flags for register INT_TIMER_EN */ 498 #define RT2860_GP_TIMER_EN (1 << 1) 499 #define RT2860_PRE_TBTT_INT_EN (1 << 0) 500 501 /* possible flags for register MAC_STATUS_REG */ 502 #define RT2860_RX_STATUS_BUSY (1 << 1) 503 #define RT2860_TX_STATUS_BUSY (1 << 0) 504 505 /* possible flags for register PWR_PIN_CFG */ 506 #define RT2860_IO_ADDA_PD (1 << 3) 507 #define RT2860_IO_PLL_PD (1 << 2) 508 #define RT2860_IO_RA_PE (1 << 1) 509 #define RT2860_IO_RF_PE (1 << 0) 510 511 /* possible flags for register AUTO_WAKEUP_CFG */ 512 #define RT2860_AUTO_WAKEUP_EN (1 << 15) 513 #define RT2860_SLEEP_TBTT_NUM_SHIFT 8 514 #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 515 516 /* possible flags for register TX_PIN_CFG */ 517 #define RT3593_LNA_PE_G2_POL (1U << 31) 518 #define RT3593_LNA_PE_A2_POL (1U << 30) 519 #define RT3593_LNA_PE_G2_EN (1U << 29) 520 #define RT3593_LNA_PE_A2_EN (1U << 28) 521 #define RT3593_LNA_PE2_EN (RT3593_LNA_PE_A2_EN | RT3593_LNA_PE_G2_EN) 522 #define RT3593_PA_PE_G2_POL (1U << 27) 523 #define RT3593_PA_PE_A2_POL (1U << 26) 524 #define RT3593_PA_PE_G2_EN (1U << 25) 525 #define RT3593_PA_PE_A2_EN (1U << 24) 526 #define RT2860_TRSW_POL (1U << 19) 527 #define RT2860_TRSW_EN (1U << 18) 528 #define RT2860_RFTR_POL (1U << 17) 529 #define RT2860_RFTR_EN (1U << 16) 530 #define RT2860_LNA_PE_G1_POL (1U << 15) 531 #define RT2860_LNA_PE_A1_POL (1U << 14) 532 #define RT2860_LNA_PE_G0_POL (1U << 13) 533 #define RT2860_LNA_PE_A0_POL (1U << 12) 534 #define RT2860_LNA_PE_G1_EN (1U << 11) 535 #define RT2860_LNA_PE_A1_EN (1U << 10) 536 #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) 537 #define RT2860_LNA_PE_G0_EN (1U << 9) 538 #define RT2860_LNA_PE_A0_EN (1U << 8) 539 #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) 540 #define RT2860_PA_PE_G1_POL (1U << 7) 541 #define RT2860_PA_PE_A1_POL (1U << 6) 542 #define RT2860_PA_PE_G0_POL (1U << 5) 543 #define RT2860_PA_PE_A0_POL (1U << 4) 544 #define RT2860_PA_PE_G1_EN (1U << 3) 545 #define RT2860_PA_PE_A1_EN (1U << 2) 546 #define RT2860_PA_PE_G0_EN (1U << 1) 547 #define RT2860_PA_PE_A0_EN (1U << 0) 548 549 /* possible flags for register TX_BAND_CFG */ 550 #define RT2860_5G_BAND_SEL_N (1 << 2) 551 #define RT2860_5G_BAND_SEL_P (1 << 1) 552 #define RT2860_TX_BAND_SEL (1 << 0) 553 554 /* possible flags for register TX_SW_CFG0 */ 555 #define RT2860_DLY_RFTR_EN_SHIFT 24 556 #define RT2860_DLY_TRSW_EN_SHIFT 16 557 #define RT2860_DLY_PAPE_EN_SHIFT 8 558 #define RT2860_DLY_TXPE_EN_SHIFT 0 559 560 /* possible flags for register TX_SW_CFG1 */ 561 #define RT2860_DLY_RFTR_DIS_SHIFT 16 562 #define RT2860_DLY_TRSW_DIS_SHIFT 8 563 #define RT2860_DLY_PAPE_DIS SHIFT 0 564 565 /* possible flags for register TX_SW_CFG2 */ 566 #define RT2860_DLY_LNA_EN_SHIFT 24 567 #define RT2860_DLY_LNA_DIS_SHIFT 16 568 #define RT2860_DLY_DAC_EN_SHIFT 8 569 #define RT2860_DLY_DAC_DIS_SHIFT 0 570 571 /* possible flags for register TXOP_THRES_CFG */ 572 #define RT2860_TXOP_REM_THRES_SHIFT 24 573 #define RT2860_CF_END_THRES_SHIFT 16 574 #define RT2860_RDG_IN_THRES 8 575 #define RT2860_RDG_OUT_THRES 0 576 577 /* possible flags for register TXOP_CTRL_CFG */ 578 #define RT2860_EXT_CW_MIN_SHIFT 16 579 #define RT2860_EXT_CCA_DLY_SHIFT 8 580 #define RT2860_EXT_CCA_EN (1 << 7) 581 #define RT2860_LSIG_TXOP_EN (1 << 6) 582 #define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4) 583 #define RT2860_TXOP_TRUN_EN_TXOP (1 << 3) 584 #define RT2860_TXOP_TRUN_EN_RATE (1 << 2) 585 #define RT2860_TXOP_TRUN_EN_AC (1 << 1) 586 #define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0) 587 588 /* possible flags for register TX_RTS_CFG */ 589 #define RT2860_RTS_FBK_EN (1 << 24) 590 #define RT2860_RTS_THRES_SHIFT 8 591 #define RT2860_RTS_RTY_LIMIT_SHIFT 0 592 593 /* possible flags for register TX_TIMEOUT_CFG */ 594 #define RT2860_TXOP_TIMEOUT_SHIFT 16 595 #define RT2860_RX_ACK_TIMEOUT_SHIFT 8 596 #define RT2860_MPDU_LIFE_TIME_SHIFT 4 597 598 /* possible flags for register TX_RTY_CFG */ 599 #define RT2860_TX_AUTOFB_EN (1 << 30) 600 #define RT2860_AGG_RTY_MODE_TIMER (1 << 29) 601 #define RT2860_NAG_RTY_MODE_TIMER (1 << 28) 602 #define RT2860_LONG_RTY_THRES_SHIFT 16 603 #define RT2860_LONG_RTY_LIMIT_SHIFT 8 604 #define RT2860_SHORT_RTY_LIMIT_SHIFT 0 605 606 /* possible flags for register TX_LINK_CFG */ 607 #define RT2860_REMOTE_MFS_SHIFT 24 608 #define RT2860_REMOTE_MFB_SHIFT 16 609 #define RT2860_TX_CFACK_EN (1 << 12) 610 #define RT2860_TX_RDG_EN (1 << 11) 611 #define RT2860_TX_MRQ_EN (1 << 10) 612 #define RT2860_REMOTE_UMFS_EN (1 << 9) 613 #define RT2860_TX_MFB_EN (1 << 8) 614 #define RT2860_REMOTE_MFB_LT_SHIFT 0 615 616 /* possible flags for registers *_PROT_CFG */ 617 #define RT2860_RTSTH_EN (1 << 26) 618 #define RT2860_TXOP_ALLOW_GF40 (1 << 25) 619 #define RT2860_TXOP_ALLOW_GF20 (1 << 24) 620 #define RT2860_TXOP_ALLOW_MM40 (1 << 23) 621 #define RT2860_TXOP_ALLOW_MM20 (1 << 22) 622 #define RT2860_TXOP_ALLOW_OFDM (1 << 21) 623 #define RT2860_TXOP_ALLOW_CCK (1 << 20) 624 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20) 625 #define RT2860_PROT_NAV_SHORT (1 << 18) 626 #define RT2860_PROT_NAV_LONG (2 << 18) 627 #define RT2860_PROT_CTRL_RTS_CTS (1 << 16) 628 #define RT2860_PROT_CTRL_CTS (2 << 16) 629 630 /* possible flags for registers EXP_{CTS,ACK}_TIME */ 631 #define RT2860_EXP_OFDM_TIME_SHIFT 16 632 #define RT2860_EXP_CCK_TIME_SHIFT 0 633 634 /* possible flags for register RX_FILTR_CFG */ 635 #define RT2860_DROP_CTRL_RSV (1 << 16) 636 #define RT2860_DROP_BAR (1 << 15) 637 #define RT2860_DROP_BA (1 << 14) 638 #define RT2860_DROP_PSPOLL (1 << 13) 639 #define RT2860_DROP_RTS (1 << 12) 640 #define RT2860_DROP_CTS (1 << 11) 641 #define RT2860_DROP_ACK (1 << 10) 642 #define RT2860_DROP_CFEND (1 << 9) 643 #define RT2860_DROP_CFACK (1 << 8) 644 #define RT2860_DROP_DUPL (1 << 7) 645 #define RT2860_DROP_BC (1 << 6) 646 #define RT2860_DROP_MC (1 << 5) 647 #define RT2860_DROP_VER_ERR (1 << 4) 648 #define RT2860_DROP_NOT_MYBSS (1 << 3) 649 #define RT2860_DROP_UC_NOME (1 << 2) 650 #define RT2860_DROP_PHY_ERR (1 << 1) 651 #define RT2860_DROP_CRC_ERR (1 << 0) 652 653 /* possible flags for register AUTO_RSP_CFG */ 654 #define RT2860_CTRL_PWR_BIT (1 << 7) 655 #define RT2860_BAC_ACK_POLICY (1 << 6) 656 #define RT2860_CCK_SHORT_EN (1 << 4) 657 #define RT2860_CTS_40M_REF_EN (1 << 3) 658 #define RT2860_CTS_40M_MODE_EN (1 << 2) 659 #define RT2860_BAC_ACKPOLICY_EN (1 << 1) 660 #define RT2860_AUTO_RSP_EN (1 << 0) 661 662 /* possible flags for register SIFS_COST_CFG */ 663 #define RT2860_OFDM_SIFS_COST_SHIFT 8 664 #define RT2860_CCK_SIFS_COST_SHIFT 0 665 666 /* possible flags for register TXOP_HLDR_ET */ 667 #define RT2860_TXOP_ETM1_EN (1 << 25) 668 #define RT2860_TXOP_ETM0_EN (1 << 24) 669 #define RT2860_TXOP_ETM_THRES_SHIFT 16 670 #define RT2860_TXOP_ETO_EN (1 << 8) 671 #define RT2860_TXOP_ETO_THRES_SHIFT 1 672 #define RT2860_PER_RX_RST_EN (1 << 0) 673 674 /* possible flags for register TX_STAT_FIFO */ 675 #define RT2860_TXQ_MCS_SHIFT 16 676 #define RT2860_TXQ_WCID_SHIFT 8 677 #define RT2860_TXQ_ACKREQ (1 << 7) 678 #define RT2860_TXQ_AGG (1 << 6) 679 #define RT2860_TXQ_OK (1 << 5) 680 #define RT2860_TXQ_PID_SHIFT 1 681 #define RT2860_TXQ_VLD (1 << 0) 682 683 /* possible flags for register WCID_ATTR */ 684 #define RT2860_MODE_NOSEC 0 685 #define RT2860_MODE_WEP40 1 686 #define RT2860_MODE_WEP104 2 687 #define RT2860_MODE_TKIP 3 688 #define RT2860_MODE_AES_CCMP 4 689 #define RT2860_MODE_CKIP40 5 690 #define RT2860_MODE_CKIP104 6 691 #define RT2860_MODE_CKIP128 7 692 #define RT2860_RX_PKEY_EN (1 << 0) 693 694 /* possible flags for register H2M_MAILBOX */ 695 #define RT2860_H2M_BUSY (1 << 24) 696 #define RT2860_TOKEN_NO_INTR 0xff 697 698 699 /* possible flags for MCU command RT2860_MCU_CMD_LEDS */ 700 #define RT2860_LED_RADIO (1 << 13) 701 #define RT2860_LED_LINK_2GHZ (1 << 14) 702 #define RT2860_LED_LINK_5GHZ (1 << 15) 703 704 705 /* possible flags for RT3020 RF register 1 */ 706 #define RT3070_RF_BLOCK (1 << 0) 707 #define RT3070_PLL_PD (1 << 1) 708 #define RT3070_RX0_PD (1 << 2) 709 #define RT3070_TX0_PD (1 << 3) 710 #define RT3070_RX1_PD (1 << 4) 711 #define RT3070_TX1_PD (1 << 5) 712 #define RT3070_RX2_PD (1 << 6) 713 #define RT3070_TX2_PD (1 << 7) 714 715 /* possible flags for RT3020 RF register 7 */ 716 #define RT3070_TUNE (1 << 0) 717 718 /* possible flags for RT3020 RF register 15 */ 719 #define RT3070_TX_LO2 (1 << 3) 720 721 /* possible flags for RT3020 RF register 17 */ 722 #define RT3070_TX_LO1 (1 << 3) 723 724 /* possible flags for RT3020 RF register 20 */ 725 #define RT3070_RX_LO1 (1 << 3) 726 727 /* possible flags for RT3020 RF register 21 */ 728 #define RT3070_RX_LO2 (1 << 3) 729 #define RT3070_RX_CTB (1 << 7) 730 731 /* possible flags for RT3020 RF register 22 */ 732 #define RT3070_BB_LOOPBACK (1 << 0) 733 734 /* possible flags for RT3053 RF register 1 */ 735 #define RT3593_VCO (1 << 0) 736 737 /* possible flags for RT3053 RF register 2 */ 738 #define RT3593_RESCAL (1 << 7) 739 740 /* possible flags for RT3053 RF register 3 */ 741 #define RT3593_VCOCAL (1 << 7) 742 743 /* possible flags for RT3053 RF register 6 */ 744 #define RT3593_VCO_IC (1 << 6) 745 746 /* possible flags for RT3053 RF register 18 */ 747 #define RT3593_AUTOTUNE_BYPASS (1 << 6) 748 749 /* possible flags for RT3053 RF register 20 */ 750 #define RT3593_LDO_PLL_VC_MASK 0x0e 751 #define RT3593_LDO_RF_VC_MASK 0xe0 752 753 /* possible flags for RT3053 RF register 22 */ 754 #define RT3593_CP_IC_MASK 0xe0 755 #define RT3593_CP_IC_SHIFT 5 756 757 /* possible flags for RT5390 RF register 38. */ 758 #define RT5390_RX_LO1 (1 << 5) 759 760 /* possible flags for RT5390 RF register 39. */ 761 #define RT5390_RX_LO2 (1 << 7) 762 763 /* possible flags for RT3053 RF register 46 */ 764 #define RT3593_RX_CTB (1 << 5) 765 766 /* possible flags for RT3053 RF register 50 */ 767 #define RT3593_TX_LO2 (1 << 4) 768 769 /* possible flags for RT3053 RF register 51 */ 770 #define RT3593_TX_LO1 (1 << 4) 771 772 /* Possible flags for RT5390 BBP register 4. */ 773 #define RT5390_MAC_IF_CTRL (1 << 6) 774 775 /* possible flags for RT5390 BBP register 105. */ 776 #define RT5390_MLD (1 << 2) 777 #define RT5390_EN_SIG_MODULATION (1 << 3) 778 779 #define RT3090_DEF_LNA 10 780 781 /* RT2860 TX descriptor */ 782 struct rt2860_txd { 783 uint32_t sdp0; /* Segment Data Pointer 0 */ 784 uint16_t sdl1; /* Segment Data Length 1 */ 785 #define RT2860_TX_BURST (1 << 15) 786 #define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ 787 788 uint16_t sdl0; /* Segment Data Length 0 */ 789 #define RT2860_TX_DDONE (1 << 15) 790 #define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ 791 792 uint32_t sdp1; /* Segment Data Pointer 1 */ 793 uint8_t reserved[3]; 794 uint8_t flags; 795 #define RT2860_TX_QSEL_SHIFT 1 796 #define RT2860_TX_QSEL_MGMT (0 << 1) 797 #define RT2860_TX_QSEL_HCCA (1 << 1) 798 #define RT2860_TX_QSEL_EDCA (2 << 1) 799 #define RT2860_TX_WIV (1 << 0) 800 } __packed; 801 802 /* RT2870 TX descriptor */ 803 struct rt2870_txd { 804 uint16_t len; 805 uint8_t pad; 806 uint8_t flags; 807 } __packed; 808 809 /* TX Wireless Information */ 810 struct rt2860_txwi { 811 uint8_t flags; 812 #define RT2860_TX_MPDU_DSITY_SHIFT 5 813 #define RT2860_TX_AMPDU (1 << 4) 814 #define RT2860_TX_TS (1 << 3) 815 #define RT2860_TX_CFACK (1 << 2) 816 #define RT2860_TX_MMPS (1 << 1) 817 #define RT2860_TX_FRAG (1 << 0) 818 819 uint8_t txop; 820 #define RT2860_TX_TXOP_HT 0 821 #define RT2860_TX_TXOP_PIFS 1 822 #define RT2860_TX_TXOP_SIFS 2 823 #define RT2860_TX_TXOP_BACKOFF 3 824 825 uint16_t phy; 826 #define RT2860_PHY_MODE 0xc000 827 #define RT2860_PHY_CCK (0 << 14) 828 #define RT2860_PHY_OFDM (1 << 14) 829 #define RT2860_PHY_HT (2 << 14) 830 #define RT2860_PHY_HT_GF (3 << 14) 831 #define RT2860_PHY_SGI (1 << 8) 832 #define RT2860_PHY_BW40 (1 << 7) 833 #define RT2860_PHY_MCS 0x7f 834 #define RT2860_PHY_SHPRE (1 << 3) 835 836 uint8_t xflags; 837 #define RT2860_TX_BAWINSIZE_SHIFT 2 838 #define RT2860_TX_NSEQ (1 << 1) 839 #define RT2860_TX_ACK (1 << 0) 840 841 uint8_t wcid; /* Wireless Client ID */ 842 uint16_t len; 843 #define RT2860_TX_PID_SHIFT 12 844 845 uint32_t iv; 846 uint32_t eiv; 847 } __packed; 848 849 /* RT2860 RX descriptor */ 850 struct rt2860_rxd { 851 uint32_t sdp0; 852 uint16_t sdl1; /* unused */ 853 uint16_t sdl0; 854 #define RT2860_RX_DDONE (1 << 15) 855 #define RT2860_RX_LS0 (1 << 14) 856 857 uint32_t sdp1; /* unused */ 858 uint32_t flags; 859 #define RT2860_RX_DEC (1 << 16) 860 #define RT2860_RX_AMPDU (1 << 15) 861 #define RT2860_RX_L2PAD (1 << 14) 862 #define RT2860_RX_RSSI (1 << 13) 863 #define RT2860_RX_HTC (1 << 12) 864 #define RT2860_RX_AMSDU (1 << 11) 865 #define RT2860_RX_MICERR (1 << 10) 866 #define RT2860_RX_ICVERR (1 << 9) 867 #define RT2860_RX_CRCERR (1 << 8) 868 #define RT2860_RX_MYBSS (1 << 7) 869 #define RT2860_RX_BC (1 << 6) 870 #define RT2860_RX_MC (1 << 5) 871 #define RT2860_RX_UC2ME (1 << 4) 872 #define RT2860_RX_FRAG (1 << 3) 873 #define RT2860_RX_NULL (1 << 2) 874 #define RT2860_RX_DATA (1 << 1) 875 #define RT2860_RX_BA (1 << 0) 876 } __packed; 877 878 /* RT2870 RX descriptor */ 879 struct rt2870_rxd { 880 /* single 32-bit field */ 881 uint32_t flags; 882 } __packed; 883 884 /* RX Wireless Information */ 885 struct rt2860_rxwi { 886 uint8_t wcid; 887 uint8_t keyidx; 888 #define RT2860_RX_UDF_SHIFT 5 889 #define RT2860_RX_BSS_IDX_SHIFT 2 890 891 uint16_t len; 892 #define RT2860_RX_TID_SHIFT 12 893 894 uint16_t seq; 895 uint16_t phy; 896 uint8_t rssi[3]; 897 uint8_t reserved1; 898 uint8_t snr[2]; 899 uint16_t reserved2; 900 } __packed; 901 902 903 /* first DMA segment contains TXWI + 802.11 header + 32-bit padding */ 904 #define RT2860_TXWI_DMASZ \ 905 (sizeof (struct rt2860_txwi) + \ 906 sizeof (struct ieee80211_htframe) + \ 907 sizeof (uint16_t)) 908 909 #define RT2860_RF1 0 910 #define RT2860_RF2 2 911 #define RT2860_RF3 1 912 #define RT2860_RF4 3 913 914 #define RT2860_RF_2820 1 /* 2T3R */ 915 #define RT2860_RF_2850 2 /* dual-band 2T3R */ 916 #define RT2860_RF_2720 3 /* 1T2R */ 917 #define RT2860_RF_2750 4 /* dual-band 1T2R */ 918 #define RT3070_RF_3020 5 /* 1T1R */ 919 #define RT3070_RF_2020 6 /* b/g */ 920 #define RT3070_RF_3021 7 /* 1T2R */ 921 #define RT3070_RF_3022 8 /* 2T2R */ 922 #define RT3070_RF_3052 9 /* dual-band 2T2R */ 923 #define RT3070_RF_3320 11 /* 1T1R */ 924 #define RT3070_RF_3053 13 /* dual-band 3T3R */ 925 #define RT5592_RF_5592 0x000f /* dual-band 2T2R */ 926 #define RT5390_RF_5370 0x5370 /* 1T1R */ 927 #define RT5390_RF_5372 0x5372 /* 2T2R */ 928 929 /* USB commands for RT2870 only */ 930 #define RT2870_RESET 1 931 #define RT2870_WRITE_2 2 932 #define RT2870_WRITE_REGION_1 6 933 #define RT2870_READ_REGION_1 7 934 #define RT2870_EEPROM_READ 9 935 936 #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 937 938 #define RT2860_EEPROM_VERSION 0x01 939 #define RT2860_EEPROM_MAC01 0x02 940 #define RT2860_EEPROM_MAC23 0x03 941 #define RT2860_EEPROM_MAC45 0x04 942 #define RT2860_EEPROM_PCIE_PSLEVEL 0x11 943 #define RT2860_EEPROM_REV 0x12 944 #define RT2860_EEPROM_ANTENNA 0x1a 945 #define RT2860_EEPROM_CONFIG 0x1b 946 #define RT2860_EEPROM_COUNTRY 0x1c 947 #define RT2860_EEPROM_FREQ_LEDS 0x1d 948 #define RT2860_EEPROM_LED1 0x1e 949 #define RT2860_EEPROM_LED2 0x1f 950 #define RT2860_EEPROM_LED3 0x20 951 #define RT2860_EEPROM_LNA 0x22 952 #define RT2860_EEPROM_RSSI1_2GHZ 0x23 953 #define RT2860_EEPROM_RSSI2_2GHZ 0x24 954 #define RT2860_EEPROM_RSSI1_5GHZ 0x25 955 #define RT2860_EEPROM_RSSI2_5GHZ 0x26 956 #define RT2860_EEPROM_DELTAPWR 0x28 957 #define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 958 #define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 959 #define RT2860_EEPROM_TSSI1_2GHZ 0x37 960 #define RT2860_EEPROM_TSSI2_2GHZ 0x38 961 #define RT2860_EEPROM_TSSI3_2GHZ 0x39 962 #define RT2860_EEPROM_TSSI4_2GHZ 0x3a 963 #define RT2860_EEPROM_TSSI5_2GHZ 0x3b 964 #define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c 965 #define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 966 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a 967 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b 968 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c 969 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d 970 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e 971 #define RT2860_EEPROM_RPWR 0x6f 972 #define RT2860_EEPROM_BBP_BASE 0x78 973 #define RT3071_EEPROM_RF_BASE 0x82 974 975 /* EEPROM registers for RT3593. */ 976 #define RT3593_EEPROM_FREQ_LEDS 0x21 977 #define RT3593_EEPROM_FREQ 0x22 978 #define RT3593_EEPROM_LED1 0x22 979 #define RT3593_EEPROM_LED2 0x23 980 #define RT3593_EEPROM_LED3 0x24 981 #define RT3593_EEPROM_LNA 0x26 982 #define RT3593_EEPROM_LNA_5GHZ 0x27 983 #define RT3593_EEPROM_RSSI1_2GHZ 0x28 984 #define RT3593_EEPROM_RSSI2_2GHZ 0x29 985 #define RT3593_EEPROM_RSSI1_5GHZ 0x2a 986 #define RT3593_EEPROM_RSSI2_5GHZ 0x2b 987 #define RT3593_EEPROM_PWR2GHZ_BASE1 0x30 988 #define RT3593_EEPROM_PWR2GHZ_BASE2 0x37 989 #define RT3593_EEPROM_PWR2GHZ_BASE3 0x3e 990 #define RT3593_EEPROM_PWR5GHZ_BASE1 0x4b 991 #define RT3593_EEPROM_PWR5GHZ_BASE2 0x65 992 #define RT3593_EEPROM_PWR5GHZ_BASE3 0x7f 993 994 /* 995 * EEPROM IQ calibration. 996 */ 997 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ 0x130 998 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131 999 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133 1000 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ 0x134 1001 #define RT5390_EEPROM_RF_IQ_COMPENSATION_CTL 0x13c 1002 #define RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL 0x13d 1003 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ 0x144 1004 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145 1005 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ 0x146 1006 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ 0x147 1007 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ 0x148 1008 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ 0x149 1009 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ 0x14a 1010 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ 0x14b 1011 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ 0x14c 1012 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ 0x14d 1013 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ 0x14e 1014 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ 0x14f 1015 1016 #define RT2860_RIDX_CCK1 0 1017 #define RT2860_RIDX_CCK11 3 1018 #define RT2860_RIDX_OFDM6 4 1019 #define RT2860_RIDX_MAX 11 1020 static const struct rt2860_rate { 1021 uint8_t rate; 1022 uint8_t mcs; 1023 enum ieee80211_phytype phy; 1024 uint8_t ctl_ridx; 1025 uint16_t sp_ack_dur; 1026 uint16_t lp_ack_dur; 1027 } rt2860_rates[] = { 1028 { 2, 0, IEEE80211_T_DS, 0, 314, 314 }, 1029 { 4, 1, IEEE80211_T_DS, 1, 258, 162 }, 1030 { 11, 2, IEEE80211_T_DS, 2, 223, 127 }, 1031 { 22, 3, IEEE80211_T_DS, 3, 213, 117 }, 1032 { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 }, 1033 { 18, 1, IEEE80211_T_OFDM, 4, 52, 52 }, 1034 { 24, 2, IEEE80211_T_OFDM, 6, 48, 48 }, 1035 { 36, 3, IEEE80211_T_OFDM, 6, 44, 44 }, 1036 { 48, 4, IEEE80211_T_OFDM, 8, 44, 44 }, 1037 { 72, 5, IEEE80211_T_OFDM, 8, 40, 40 }, 1038 { 96, 6, IEEE80211_T_OFDM, 8, 40, 40 }, 1039 { 108, 7, IEEE80211_T_OFDM, 8, 40, 40 } 1040 }; 1041 1042 /* 1043 * Control and status registers access macros. 1044 */ 1045 #define RAL_READ(sc, reg) \ 1046 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1047 1048 #define RAL_WRITE(sc, reg, val) \ 1049 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1050 1051 #define RAL_BARRIER_WRITE(sc) \ 1052 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 1053 BUS_SPACE_BARRIER_WRITE) 1054 1055 #define RAL_BARRIER_READ_WRITE(sc) \ 1056 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 1057 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1058 1059 #define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 1060 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 1061 (datap), (count)) 1062 1063 #define RAL_SET_REGION_4(sc, offset, val, count) \ 1064 bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 1065 (val), (count)) 1066 1067 /* 1068 * EEPROM access macro. 1069 */ 1070 #define RT2860_EEPROM_CTL(sc, val) do { \ 1071 RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \ 1072 RAL_BARRIER_READ_WRITE((sc)); \ 1073 DELAY(RT2860_EEPROM_DELAY); \ 1074 } while (/* CONSTCOND */0) 1075 1076 /* 1077 * Default values for MAC registers; values taken from the reference driver. 1078 */ 1079 #define RT2860_DEF_MAC \ 1080 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1081 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1082 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1083 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1084 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1085 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1086 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1087 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1088 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1089 { RT2860_LED_CFG, 0x7f031e46 }, \ 1090 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1091 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1092 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1093 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1094 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1095 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1096 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1097 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1098 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1099 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1100 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1101 { RT2860_MM40_PROT_CFG, 0x03f54084 }, \ 1102 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1103 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1104 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1105 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1106 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1107 { RT2860_PWR_PIN_CFG, 0x00000003 } 1108 1109 /* XXX only a few registers differ from above, try to merge? */ 1110 #define RT2870_DEF_MAC \ 1111 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1112 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1113 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1114 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1115 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1116 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1117 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1118 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1119 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1120 { RT2860_LED_CFG, 0x7f031e46 }, \ 1121 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1122 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1123 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1124 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1125 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1126 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1127 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1128 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1129 { RT2860_PBF_CFG, 0x00f40006 }, \ 1130 { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \ 1131 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1132 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1133 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1134 { RT2860_MM40_PROT_CFG, 0x03f44084 }, \ 1135 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1136 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1137 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1138 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1139 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1140 { RT2860_PWR_PIN_CFG, 0x00000003 } 1141 1142 /* 1143 * Default values for BBP registers; values taken from the reference driver. 1144 */ 1145 #define RT2860_DEF_BBP \ 1146 { 65, 0x2c }, \ 1147 { 66, 0x38 }, \ 1148 { 69, 0x12 }, \ 1149 { 70, 0x0a }, \ 1150 { 73, 0x10 }, \ 1151 { 81, 0x37 }, \ 1152 { 82, 0x62 }, \ 1153 { 83, 0x6a }, \ 1154 { 84, 0x99 }, \ 1155 { 86, 0x00 }, \ 1156 { 91, 0x04 }, \ 1157 { 92, 0x00 }, \ 1158 { 103, 0x00 }, \ 1159 { 105, 0x05 }, \ 1160 { 106, 0x35 } 1161 1162 #define RT5390_DEF_BBP \ 1163 { 31, 0x08 }, \ 1164 { 65, 0x2c }, \ 1165 { 66, 0x38 }, \ 1166 { 68, 0x0b }, \ 1167 { 69, 0x0d }, \ 1168 { 70, 0x06 }, \ 1169 { 73, 0x13 }, \ 1170 { 75, 0x46 }, \ 1171 { 76, 0x28 }, \ 1172 { 77, 0x59 }, \ 1173 { 81, 0x37 }, \ 1174 { 82, 0x62 }, \ 1175 { 83, 0x7a }, \ 1176 { 84, 0x9a }, \ 1177 { 86, 0x38 }, \ 1178 { 91, 0x04 }, \ 1179 { 92, 0x02 }, \ 1180 { 103, 0xc0 }, \ 1181 { 104, 0x92 }, \ 1182 { 105, 0x3c }, \ 1183 { 106, 0x03 }, \ 1184 { 128, 0x12 } 1185 1186 #define RT5592_DEF_BBP \ 1187 { 20, 0x06 }, \ 1188 { 31, 0x08 }, \ 1189 { 65, 0x2c }, \ 1190 { 66, 0x38 }, \ 1191 { 68, 0xdd }, \ 1192 { 69, 0x1a }, \ 1193 { 70, 0x05 }, \ 1194 { 73, 0x13 }, \ 1195 { 74, 0x0f }, \ 1196 { 75, 0x4f }, \ 1197 { 76, 0x28 }, \ 1198 { 77, 0x59 }, \ 1199 { 81, 0x37 }, \ 1200 { 82, 0x62 }, \ 1201 { 83, 0x6a }, \ 1202 { 84, 0x9a }, \ 1203 { 86, 0x38 }, \ 1204 { 88, 0x90 }, \ 1205 { 91, 0x04 }, \ 1206 { 92, 0x02 }, \ 1207 { 95, 0x9a }, \ 1208 { 98, 0x12 }, \ 1209 { 103, 0xc0 }, \ 1210 { 104, 0x92 }, \ 1211 { 105, 0x3c }, \ 1212 { 106, 0x35 }, \ 1213 { 128, 0x12 }, \ 1214 { 134, 0xd0 }, \ 1215 { 135, 0xf6 }, \ 1216 { 137, 0x0f } 1217 1218 /* 1219 * Default settings for RF registers; values derived from the reference driver. 1220 */ 1221 #define RT2860_RF2850 \ 1222 { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, \ 1223 { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, \ 1224 { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, \ 1225 { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, \ 1226 { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, \ 1227 { 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 }, \ 1228 { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 }, \ 1229 { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, \ 1230 { 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 }, \ 1231 { 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 }, \ 1232 { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 }, \ 1233 { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, \ 1234 { 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 }, \ 1235 { 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 }, \ 1236 { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 }, \ 1237 { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, \ 1238 { 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 }, \ 1239 { 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 }, \ 1240 { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 }, \ 1241 { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, \ 1242 { 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 }, \ 1243 { 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 }, \ 1244 { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 }, \ 1245 { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, \ 1246 { 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 }, \ 1247 { 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 }, \ 1248 { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }, \ 1249 { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, \ 1250 { 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 }, \ 1251 { 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 }, \ 1252 { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }, \ 1253 { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, \ 1254 { 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 }, \ 1255 { 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 }, \ 1256 { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }, \ 1257 { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, \ 1258 { 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 }, \ 1259 { 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 }, \ 1260 { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }, \ 1261 { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, \ 1262 { 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 }, \ 1263 { 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 }, \ 1264 { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }, \ 1265 { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, \ 1266 { 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 }, \ 1267 { 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 }, \ 1268 { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }, \ 1269 { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, \ 1270 { 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 }, \ 1271 { 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 }, \ 1272 { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 }, \ 1273 { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, \ 1274 { 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 } 1275 1276 #define RT3070_RF3052 \ 1277 { 0xf1, 2, 2 }, \ 1278 { 0xf1, 2, 7 }, \ 1279 { 0xf2, 2, 2 }, \ 1280 { 0xf2, 2, 7 }, \ 1281 { 0xf3, 2, 2 }, \ 1282 { 0xf3, 2, 7 }, \ 1283 { 0xf4, 2, 2 }, \ 1284 { 0xf4, 2, 7 }, \ 1285 { 0xf5, 2, 2 }, \ 1286 { 0xf5, 2, 7 }, \ 1287 { 0xf6, 2, 2 }, \ 1288 { 0xf6, 2, 7 }, \ 1289 { 0xf7, 2, 2 }, \ 1290 { 0xf8, 2, 4 }, \ 1291 { 0x56, 0, 4 }, \ 1292 { 0x56, 0, 6 }, \ 1293 { 0x56, 0, 8 }, \ 1294 { 0x57, 0, 0 }, \ 1295 { 0x57, 0, 2 }, \ 1296 { 0x57, 0, 4 }, \ 1297 { 0x57, 0, 8 }, \ 1298 { 0x57, 0, 10 }, \ 1299 { 0x58, 0, 0 }, \ 1300 { 0x58, 0, 4 }, \ 1301 { 0x58, 0, 6 }, \ 1302 { 0x58, 0, 8 }, \ 1303 { 0x5b, 0, 8 }, \ 1304 { 0x5b, 0, 10 }, \ 1305 { 0x5c, 0, 0 }, \ 1306 { 0x5c, 0, 4 }, \ 1307 { 0x5c, 0, 6 }, \ 1308 { 0x5c, 0, 8 }, \ 1309 { 0x5d, 0, 0 }, \ 1310 { 0x5d, 0, 2 }, \ 1311 { 0x5d, 0, 4 }, \ 1312 { 0x5d, 0, 8 }, \ 1313 { 0x5d, 0, 10 }, \ 1314 { 0x5e, 0, 0 }, \ 1315 { 0x5e, 0, 4 }, \ 1316 { 0x5e, 0, 6 }, \ 1317 { 0x5e, 0, 8 }, \ 1318 { 0x5f, 0, 0 }, \ 1319 { 0x5f, 0, 9 }, \ 1320 { 0x5f, 0, 11 }, \ 1321 { 0x60, 0, 1 }, \ 1322 { 0x60, 0, 5 }, \ 1323 { 0x60, 0, 7 }, \ 1324 { 0x60, 0, 9 }, \ 1325 { 0x61, 0, 1 }, \ 1326 { 0x61, 0, 3 }, \ 1327 { 0x61, 0, 5 }, \ 1328 { 0x61, 0, 7 }, \ 1329 { 0x61, 0, 9 } 1330 1331 #define RT5592_RF5592_20MHZ \ 1332 { 0x1e2, 4, 10, 3 }, \ 1333 { 0x1e3, 4, 10, 3 }, \ 1334 { 0x1e4, 4, 10, 3 }, \ 1335 { 0x1e5, 4, 10, 3 }, \ 1336 { 0x1e6, 4, 10, 3 }, \ 1337 { 0x1e7, 4, 10, 3 }, \ 1338 { 0x1e8, 4, 10, 3 }, \ 1339 { 0x1e9, 4, 10, 3 }, \ 1340 { 0x1ea, 4, 10, 3 }, \ 1341 { 0x1eb, 4, 10, 3 }, \ 1342 { 0x1ec, 4, 10, 3 }, \ 1343 { 0x1ed, 4, 10, 3 }, \ 1344 { 0x1ee, 4, 10, 3 }, \ 1345 { 0x1f0, 8, 10, 3 }, \ 1346 { 0xac, 8, 12, 1 }, \ 1347 { 0xad, 0, 12, 1 }, \ 1348 { 0xad, 4, 12, 1 }, \ 1349 { 0xae, 0, 12, 1 }, \ 1350 { 0xae, 4, 12, 1 }, \ 1351 { 0xae, 8, 12, 1 }, \ 1352 { 0xaf, 4, 12, 1 }, \ 1353 { 0xaf, 8, 12, 1 }, \ 1354 { 0xb0, 0, 12, 1 }, \ 1355 { 0xb0, 8, 12, 1 }, \ 1356 { 0xb1, 0, 12, 1 }, \ 1357 { 0xb1, 4, 12, 1 }, \ 1358 { 0xb7, 4, 12, 1 }, \ 1359 { 0xb7, 8, 12, 1 }, \ 1360 { 0xb8, 0, 12, 1 }, \ 1361 { 0xb8, 8, 12, 1 }, \ 1362 { 0xb9, 0, 12, 1 }, \ 1363 { 0xb9, 4, 12, 1 }, \ 1364 { 0xba, 0, 12, 1 }, \ 1365 { 0xba, 4, 12, 1 }, \ 1366 { 0xba, 8, 12, 1 }, \ 1367 { 0xbb, 4, 12, 1 }, \ 1368 { 0xbb, 8, 12, 1 }, \ 1369 { 0xbc, 0, 12, 1 }, \ 1370 { 0xbc, 8, 12, 1 }, \ 1371 { 0xbd, 0, 12, 1 }, \ 1372 { 0xbd, 4, 12, 1 }, \ 1373 { 0xbe, 0, 12, 1 }, \ 1374 { 0xbf, 6, 12, 1 }, \ 1375 { 0xbf, 10, 12, 1 }, \ 1376 { 0xc0, 2, 12, 1 }, \ 1377 { 0xc0, 10, 12, 1 }, \ 1378 { 0xc1, 2, 12, 1 }, \ 1379 { 0xc1, 6, 12, 1 }, \ 1380 { 0xc2, 2, 12, 1 }, \ 1381 { 0xa4, 0, 12, 1 }, \ 1382 { 0xa4, 4, 12, 1 }, \ 1383 { 0xa5, 8, 12, 1 }, \ 1384 { 0xa6, 0, 12, 1 } 1385 1386 #define RT5592_RF5592_40MHZ \ 1387 { 0xf1, 2, 10, 3 }, \ 1388 { 0xf1, 7, 10, 3 }, \ 1389 { 0xf2, 2, 10, 3 }, \ 1390 { 0xf2, 7, 10, 3 }, \ 1391 { 0xf3, 2, 10, 3 }, \ 1392 { 0xf3, 7, 10, 3 }, \ 1393 { 0xf4, 2, 10, 3 }, \ 1394 { 0xf4, 7, 10, 3 }, \ 1395 { 0xf5, 2, 10, 3 }, \ 1396 { 0xf5, 7, 10, 3 }, \ 1397 { 0xf6, 2, 10, 3 }, \ 1398 { 0xf6, 7, 10, 3 }, \ 1399 { 0xf7, 2, 10, 3 }, \ 1400 { 0xf8, 4, 10, 3 }, \ 1401 { 0x56, 4, 12, 1 }, \ 1402 { 0x56, 6, 12, 1 }, \ 1403 { 0x56, 8, 12, 1 }, \ 1404 { 0x57, 0, 12, 1 }, \ 1405 { 0x57, 2, 12, 1 }, \ 1406 { 0x57, 4, 12, 1 }, \ 1407 { 0x57, 8, 12, 1 }, \ 1408 { 0x57, 10, 12, 1 }, \ 1409 { 0x58, 0, 12, 1 }, \ 1410 { 0x58, 4, 12, 1 }, \ 1411 { 0x58, 6, 12, 1 }, \ 1412 { 0x58, 8, 12, 1 }, \ 1413 { 0x5b, 8, 12, 1 }, \ 1414 { 0x5b, 10, 12, 1 }, \ 1415 { 0x5c, 0, 12, 1 }, \ 1416 { 0x5c, 4, 12, 1 }, \ 1417 { 0x5c, 6, 12, 1 }, \ 1418 { 0x5c, 8, 12, 1 }, \ 1419 { 0x5d, 0, 12, 1 }, \ 1420 { 0x5d, 2, 12, 1 }, \ 1421 { 0x5d, 4, 12, 1 }, \ 1422 { 0x5d, 8, 12, 1 }, \ 1423 { 0x5d, 10, 12, 1 }, \ 1424 { 0x5e, 0, 12, 1 }, \ 1425 { 0x5e, 4, 12, 1 }, \ 1426 { 0x5e, 6, 12, 1 }, \ 1427 { 0x5e, 8, 12, 1 }, \ 1428 { 0x5f, 0, 12, 1 }, \ 1429 { 0x5f, 9, 12, 1 }, \ 1430 { 0x5f, 11, 12, 1 }, \ 1431 { 0x60, 1, 12, 1 }, \ 1432 { 0x60, 5, 12, 1 }, \ 1433 { 0x60, 7, 12, 1 }, \ 1434 { 0x60, 9, 12, 1 }, \ 1435 { 0x61, 1, 12, 1 }, \ 1436 { 0x52, 0, 12, 1 }, \ 1437 { 0x52, 4, 12, 1 }, \ 1438 { 0x52, 8, 12, 1 }, \ 1439 { 0x53, 0, 12, 1 } 1440 1441 #define RT3070_DEF_RF \ 1442 { 4, 0x40 }, \ 1443 { 5, 0x03 }, \ 1444 { 6, 0x02 }, \ 1445 { 7, 0x70 }, \ 1446 { 9, 0x0f }, \ 1447 { 10, 0x41 }, \ 1448 { 11, 0x21 }, \ 1449 { 12, 0x7b }, \ 1450 { 14, 0x90 }, \ 1451 { 15, 0x58 }, \ 1452 { 16, 0xb3 }, \ 1453 { 17, 0x92 }, \ 1454 { 18, 0x2c }, \ 1455 { 19, 0x02 }, \ 1456 { 20, 0xba }, \ 1457 { 21, 0xdb }, \ 1458 { 24, 0x16 }, \ 1459 { 25, 0x01 }, \ 1460 { 29, 0x1f } 1461 1462 #define RT3572_DEF_RF \ 1463 { 0, 0x70 }, \ 1464 { 1, 0x81 }, \ 1465 { 2, 0xf1 }, \ 1466 { 3, 0x02 }, \ 1467 { 4, 0x4c }, \ 1468 { 5, 0x05 }, \ 1469 { 6, 0x4a }, \ 1470 { 7, 0xd8 }, \ 1471 { 9, 0xc3 }, \ 1472 { 10, 0xf1 }, \ 1473 { 11, 0xb9 }, \ 1474 { 12, 0x70 }, \ 1475 { 13, 0x65 }, \ 1476 { 14, 0xa0 }, \ 1477 { 15, 0x53 }, \ 1478 { 16, 0x4c }, \ 1479 { 17, 0x23 }, \ 1480 { 18, 0xac }, \ 1481 { 19, 0x93 }, \ 1482 { 20, 0xb3 }, \ 1483 { 21, 0xd0 }, \ 1484 { 22, 0x00 }, \ 1485 { 23, 0x3c }, \ 1486 { 24, 0x16 }, \ 1487 { 25, 0x15 }, \ 1488 { 26, 0x85 }, \ 1489 { 27, 0x00 }, \ 1490 { 28, 0x00 }, \ 1491 { 29, 0x9b }, \ 1492 { 30, 0x09 }, \ 1493 { 31, 0x10 } 1494 1495 #define RT3593_DEF_RF \ 1496 { 1, 0x03 }, \ 1497 { 3, 0x80 }, \ 1498 { 5, 0x00 }, \ 1499 { 6, 0x40 }, \ 1500 { 8, 0xf1 }, \ 1501 { 9, 0x02 }, \ 1502 { 10, 0xd3 }, \ 1503 { 11, 0x40 }, \ 1504 { 12, 0x4e }, \ 1505 { 13, 0x12 }, \ 1506 { 18, 0x40 }, \ 1507 { 22, 0x20 }, \ 1508 { 30, 0x10 }, \ 1509 { 31, 0x80 }, \ 1510 { 32, 0x78 }, \ 1511 { 33, 0x3b }, \ 1512 { 34, 0x3c }, \ 1513 { 35, 0xe0 }, \ 1514 { 38, 0x86 }, \ 1515 { 39, 0x23 }, \ 1516 { 44, 0xd3 }, \ 1517 { 45, 0xbb }, \ 1518 { 46, 0x60 }, \ 1519 { 49, 0x81 }, \ 1520 { 50, 0x86 }, \ 1521 { 51, 0x75 }, \ 1522 { 52, 0x45 }, \ 1523 { 53, 0x18 }, \ 1524 { 54, 0x18 }, \ 1525 { 55, 0x18 }, \ 1526 { 56, 0xdb }, \ 1527 { 57, 0x6e } 1528 1529 #define RT5390_DEF_RF \ 1530 { 1, 0x0f }, \ 1531 { 2, 0x80 }, \ 1532 { 3, 0x88 }, \ 1533 { 5, 0x10 }, \ 1534 { 6, 0xa0 }, \ 1535 { 7, 0x00 }, \ 1536 { 10, 0x53 }, \ 1537 { 11, 0x4a }, \ 1538 { 12, 0x46 }, \ 1539 { 13, 0x9f }, \ 1540 { 14, 0x00 }, \ 1541 { 15, 0x00 }, \ 1542 { 16, 0x00 }, \ 1543 { 18, 0x03 }, \ 1544 { 19, 0x00 }, \ 1545 { 20, 0x00 }, \ 1546 { 21, 0x00 }, \ 1547 { 22, 0x20 }, \ 1548 { 23, 0x00 }, \ 1549 { 24, 0x00 }, \ 1550 { 25, 0xc0 }, \ 1551 { 26, 0x00 }, \ 1552 { 27, 0x09 }, \ 1553 { 28, 0x00 }, \ 1554 { 29, 0x10 }, \ 1555 { 30, 0x10 }, \ 1556 { 31, 0x80 }, \ 1557 { 32, 0x80 }, \ 1558 { 33, 0x00 }, \ 1559 { 34, 0x07 }, \ 1560 { 35, 0x12 }, \ 1561 { 36, 0x00 }, \ 1562 { 37, 0x08 }, \ 1563 { 38, 0x85 }, \ 1564 { 39, 0x1b }, \ 1565 { 40, 0x0b }, \ 1566 { 41, 0xbb }, \ 1567 { 42, 0xd2 }, \ 1568 { 43, 0x9a }, \ 1569 { 44, 0x0e }, \ 1570 { 45, 0xa2 }, \ 1571 { 46, 0x7b }, \ 1572 { 47, 0x00 }, \ 1573 { 48, 0x10 }, \ 1574 { 49, 0x94 }, \ 1575 { 52, 0x38 }, \ 1576 { 53, 0x84 }, \ 1577 { 54, 0x78 }, \ 1578 { 55, 0x44 }, \ 1579 { 56, 0x22 }, \ 1580 { 57, 0x80 }, \ 1581 { 58, 0x7f }, \ 1582 { 59, 0x8f }, \ 1583 { 60, 0x45 }, \ 1584 { 61, 0xdd }, \ 1585 { 62, 0x00 }, \ 1586 { 63, 0x00 } 1587 1588 #define RT5392_DEF_RF \ 1589 { 1, 0x17 }, \ 1590 { 3, 0x88 }, \ 1591 { 5, 0x10 }, \ 1592 { 6, 0xe0 }, \ 1593 { 7, 0x00 }, \ 1594 { 10, 0x53 }, \ 1595 { 11, 0x4a }, \ 1596 { 12, 0x46 }, \ 1597 { 13, 0x9f }, \ 1598 { 14, 0x00 }, \ 1599 { 15, 0x00 }, \ 1600 { 16, 0x00 }, \ 1601 { 18, 0x03 }, \ 1602 { 19, 0x4d }, \ 1603 { 20, 0x00 }, \ 1604 { 21, 0x8d }, \ 1605 { 22, 0x20 }, \ 1606 { 23, 0x0b }, \ 1607 { 24, 0x44 }, \ 1608 { 25, 0x80 }, \ 1609 { 26, 0x82 }, \ 1610 { 27, 0x09 }, \ 1611 { 28, 0x00 }, \ 1612 { 29, 0x10 }, \ 1613 { 30, 0x10 }, \ 1614 { 31, 0x80 }, \ 1615 { 32, 0x20 }, \ 1616 { 33, 0xc0 }, \ 1617 { 34, 0x07 }, \ 1618 { 35, 0x12 }, \ 1619 { 36, 0x00 }, \ 1620 { 37, 0x08 }, \ 1621 { 38, 0x89 }, \ 1622 { 39, 0x1b }, \ 1623 { 40, 0x0f }, \ 1624 { 41, 0xbb }, \ 1625 { 42, 0xd5 }, \ 1626 { 43, 0x9b }, \ 1627 { 44, 0x0e }, \ 1628 { 45, 0xa2 }, \ 1629 { 46, 0x73 }, \ 1630 { 47, 0x0c }, \ 1631 { 48, 0x10 }, \ 1632 { 49, 0x94 }, \ 1633 { 50, 0x94 }, \ 1634 { 51, 0x3a }, \ 1635 { 52, 0x48 }, \ 1636 { 53, 0x44 }, \ 1637 { 54, 0x38 }, \ 1638 { 55, 0x43 }, \ 1639 { 56, 0xa1 }, \ 1640 { 57, 0x00 }, \ 1641 { 58, 0x39 }, \ 1642 { 59, 0x07 }, \ 1643 { 60, 0x45 }, \ 1644 { 61, 0x91 }, \ 1645 { 62, 0x39 }, \ 1646 { 63, 0x07 } 1647 1648 #define RT5592_DEF_RF \ 1649 { 1, 0x3f }, \ 1650 { 3, 0x08 }, \ 1651 { 5, 0x10 }, \ 1652 { 6, 0xe4 }, \ 1653 { 7, 0x00 }, \ 1654 { 14, 0x00 }, \ 1655 { 15, 0x00 }, \ 1656 { 16, 0x00 }, \ 1657 { 18, 0x03 }, \ 1658 { 19, 0x4d }, \ 1659 { 20, 0x10 }, \ 1660 { 21, 0x8d }, \ 1661 { 26, 0x82 }, \ 1662 { 28, 0x00 }, \ 1663 { 29, 0x10 }, \ 1664 { 33, 0xc0 }, \ 1665 { 34, 0x07 }, \ 1666 { 35, 0x12 }, \ 1667 { 47, 0x0c }, \ 1668 { 53, 0x22 }, \ 1669 { 63, 0x07 } 1670 1671 #define RT5592_2GHZ_DEF_RF \ 1672 { 10, 0x90 }, \ 1673 { 11, 0x4a }, \ 1674 { 12, 0x52 }, \ 1675 { 13, 0x42 }, \ 1676 { 22, 0x40 }, \ 1677 { 24, 0x4a }, \ 1678 { 25, 0x80 }, \ 1679 { 27, 0x42 }, \ 1680 { 36, 0x80 }, \ 1681 { 37, 0x08 }, \ 1682 { 38, 0x89 }, \ 1683 { 39, 0x1b }, \ 1684 { 40, 0x0d }, \ 1685 { 41, 0x9b }, \ 1686 { 42, 0xd5 }, \ 1687 { 43, 0x72 }, \ 1688 { 44, 0x0e }, \ 1689 { 45, 0xa2 }, \ 1690 { 46, 0x6b }, \ 1691 { 48, 0x10 }, \ 1692 { 51, 0x3e }, \ 1693 { 52, 0x48 }, \ 1694 { 54, 0x38 }, \ 1695 { 56, 0xa1 }, \ 1696 { 57, 0x00 }, \ 1697 { 58, 0x39 }, \ 1698 { 60, 0x45 }, \ 1699 { 61, 0x91 }, \ 1700 { 62, 0x39 } 1701 1702 #define RT5592_5GHZ_DEF_RF \ 1703 { 10, 0x97 }, \ 1704 { 11, 0x40 }, \ 1705 { 25, 0xbf }, \ 1706 { 27, 0x42 }, \ 1707 { 36, 0x00 }, \ 1708 { 37, 0x04 }, \ 1709 { 38, 0x85 }, \ 1710 { 40, 0x42 }, \ 1711 { 41, 0xbb }, \ 1712 { 42, 0xd7 }, \ 1713 { 45, 0x41 }, \ 1714 { 48, 0x00 }, \ 1715 { 57, 0x77 }, \ 1716 { 60, 0x05 }, \ 1717 { 61, 0x01 } 1718 1719 #define RT5592_CHAN_5GHZ \ 1720 { 36, 64, 12, 0x2e }, \ 1721 { 100, 165, 12, 0x0e }, \ 1722 { 36, 64, 13, 0x22 }, \ 1723 { 100, 165, 13, 0x42 }, \ 1724 { 36, 64, 22, 0x60 }, \ 1725 { 100, 165, 22, 0x40 }, \ 1726 { 36, 64, 23, 0x7f }, \ 1727 { 100, 153, 23, 0x3c }, \ 1728 { 155, 165, 23, 0x38 }, \ 1729 { 36, 50, 24, 0x09 }, \ 1730 { 52, 64, 24, 0x07 }, \ 1731 { 100, 153, 24, 0x06 }, \ 1732 { 155, 165, 24, 0x05 }, \ 1733 { 36, 64, 39, 0x1c }, \ 1734 { 100, 138, 39, 0x1a }, \ 1735 { 140, 165, 39, 0x18 }, \ 1736 { 36, 64, 43, 0x5b }, \ 1737 { 100, 138, 43, 0x3b }, \ 1738 { 140, 165, 43, 0x1b }, \ 1739 { 36, 64, 44, 0x40 }, \ 1740 { 100, 138, 44, 0x20 }, \ 1741 { 140, 165, 44, 0x10 }, \ 1742 { 36, 64, 46, 0x00 }, \ 1743 { 100, 138, 46, 0x18 }, \ 1744 { 140, 165, 46, 0x08 }, \ 1745 { 36, 64, 51, 0xfe }, \ 1746 { 100, 124, 51, 0xfc }, \ 1747 { 126, 165, 51, 0xec }, \ 1748 { 36, 64, 52, 0x0c }, \ 1749 { 100, 138, 52, 0x06 }, \ 1750 { 140, 165, 52, 0x06 }, \ 1751 { 36, 64, 54, 0xf8 }, \ 1752 { 100, 165, 54, 0xeb }, \ 1753 { 36, 50, 55, 0x06 }, \ 1754 { 52, 64, 55, 0x04 }, \ 1755 { 100, 138, 55, 0x01 }, \ 1756 { 140, 165, 55, 0x00 }, \ 1757 { 36, 50, 56, 0xd3 }, \ 1758 { 52, 128, 56, 0xbb }, \ 1759 { 130, 165, 56, 0xab }, \ 1760 { 36, 64, 58, 0x15 }, \ 1761 { 100, 116, 58, 0x1d }, \ 1762 { 118, 165, 58, 0x15 }, \ 1763 { 36, 64, 59, 0x7f }, \ 1764 { 100, 138, 59, 0x3f }, \ 1765 { 140, 165, 59, 0x7c }, \ 1766 { 36, 64, 62, 0x15 }, \ 1767 { 100, 116, 62, 0x1d }, \ 1768 { 118, 165, 62, 0x15 } 1769
Indexes created Tue Oct 21 16:10:11 GMT 2025