rt2860reg.h revision 1.6
1 /* $NetBSD: rt2860reg.h,v 1.6 2016/09/16 09:25:30 mlelstv Exp $ */ 2 /* $OpenBSD: rt2860reg.h,v 1.32 2014/05/24 10:10:17 stsp Exp $ */ 3 4 /*- 5 * Copyright (c) 2007 6 * Damien Bergamini <damien.bergamini (at) free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define RT2860_NOISE_FLOOR -95 22 23 /* PCI registers */ 24 #define RT2860_PCI_CFG 0x0000 25 #define RT2860_PCI_EECTRL 0x0004 26 #define RT2860_PCI_MCUCTRL 0x0008 27 #define RT2860_PCI_SYSCTRL 0x000c 28 #define RT2860_PCIE_JTAG 0x0010 29 30 #define RT3090_AUX_CTRL 0x010c 31 32 #define RT3070_OPT_14 0x0114 33 34 /* SCH/DMA registers */ 35 #define RT2860_INT_STATUS 0x0200 36 #define RT2860_INT_MASK 0x0204 37 #define RT2860_WPDMA_GLO_CFG 0x0208 38 #define RT2860_WPDMA_RST_IDX 0x020c 39 #define RT2860_DELAY_INT_CFG 0x0210 40 #define RT2860_WMM_AIFSN_CFG 0x0214 41 #define RT2860_WMM_CWMIN_CFG 0x0218 42 #define RT2860_WMM_CWMAX_CFG 0x021c 43 #define RT2860_WMM_TXOP0_CFG 0x0220 44 #define RT2860_WMM_TXOP1_CFG 0x0224 45 #define RT2860_GPIO_CTRL 0x0228 46 #define RT2860_MCU_CMD_REG 0x022c 47 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) 48 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) 49 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) 50 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) 51 #define RT2860_RX_BASE_PTR 0x0290 52 #define RT2860_RX_MAX_CNT 0x0294 53 #define RT2860_RX_CALC_IDX 0x0298 54 #define RT2860_FS_DRX_IDX 0x029c 55 #define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ 56 #define RT2860_US_CYC_CNT 0x02a4 57 58 /* PBF registers */ 59 #define RT2860_SYS_CTRL 0x0400 60 #define RT2860_HOST_CMD 0x0404 61 #define RT2860_PBF_CFG 0x0408 62 #define RT2860_MAX_PCNT 0x040c 63 #define RT2860_BUF_CTRL 0x0410 64 #define RT2860_MCU_INT_STA 0x0414 65 #define RT2860_MCU_INT_ENA 0x0418 66 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) 67 #define RT2860_RX0Q_IO 0x0424 68 #define RT2860_BCN_OFFSET0 0x042c 69 #define RT2860_BCN_OFFSET1 0x0430 70 #define RT2860_TXRXQ_STA 0x0434 71 #define RT2860_TXRXQ_PCNT 0x0438 72 #define RT2860_PBF_DBG 0x043c 73 #define RT2860_CAP_CTRL 0x0440 74 75 /* RT3070 registers */ 76 #define RT3070_RF_CSR_CFG 0x0500 77 #define RT3070_EFUSE_CTRL 0x0580 78 #define RT3070_EFUSE_DATA0 0x0590 79 #define RT3070_EFUSE_DATA1 0x0594 80 #define RT3070_EFUSE_DATA2 0x0598 81 #define RT3070_EFUSE_DATA3 0x059c 82 #define RT3090_OSC_CTRL 0x05a4 83 #define RT3070_LDO_CFG0 0x05d4 84 #define RT3070_GPIO_SWITCH 0x05dc 85 86 87 88 /* RT5592 registers */ 89 #define RT5592_DEBUG_INDEX 0x05e8 90 91 /* MAC registers */ 92 #define RT2860_ASIC_VER_ID 0x1000 93 #define RT2860_MAC_SYS_CTRL 0x1004 94 #define RT2860_MAC_ADDR_DW0 0x1008 95 #define RT2860_MAC_ADDR_DW1 0x100c 96 #define RT2860_MAC_BSSID_DW0 0x1010 97 #define RT2860_MAC_BSSID_DW1 0x1014 98 #define RT2860_MAX_LEN_CFG 0x1018 99 #define RT2860_BBP_CSR_CFG 0x101c 100 #define RT2860_RF_CSR_CFG0 0x1020 101 #define RT2860_RF_CSR_CFG1 0x1024 102 #define RT2860_RF_CSR_CFG2 0x1028 103 #define RT2860_LED_CFG 0x102c 104 105 /* undocumented registers */ 106 #define RT2860_DEBUG 0x10f4 107 108 /* MAC Timing control registers */ 109 #define RT2860_XIFS_TIME_CFG 0x1100 110 #define RT2860_BKOFF_SLOT_CFG 0x1104 111 #define RT2860_NAV_TIME_CFG 0x1108 112 #define RT2860_CH_TIME_CFG 0x110c 113 #define RT2860_PBF_LIFE_TIMER 0x1110 114 #define RT2860_BCN_TIME_CFG 0x1114 115 #define RT2860_TBTT_SYNC_CFG 0x1118 116 #define RT2860_TSF_TIMER_DW0 0x111c 117 #define RT2860_TSF_TIMER_DW1 0x1120 118 #define RT2860_TBTT_TIMER 0x1124 119 #define RT2860_INT_TIMER_CFG 0x1128 120 #define RT2860_INT_TIMER_EN 0x112c 121 #define RT2860_CH_IDLE_TIME 0x1130 122 123 /* MAC Power Save configuration registers */ 124 #define RT2860_MAC_STATUS_REG 0x1200 125 #define RT2860_PWR_PIN_CFG 0x1204 126 #define RT2860_AUTO_WAKEUP_CFG 0x1208 127 128 /* MAC TX configuration registers */ 129 #define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) 130 #define RT2860_EDCA_TID_AC_MAP 0x1310 131 #define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) 132 #define RT2860_TX_PIN_CFG 0x1328 133 #define RT2860_TX_BAND_CFG 0x132c 134 #define RT2860_TX_SW_CFG0 0x1330 135 #define RT2860_TX_SW_CFG1 0x1334 136 #define RT2860_TX_SW_CFG2 0x1338 137 #define RT2860_TXOP_THRES_CFG 0x133c 138 #define RT2860_TXOP_CTRL_CFG 0x1340 139 #define RT2860_TX_RTS_CFG 0x1344 140 #define RT2860_TX_TIMEOUT_CFG 0x1348 141 #define RT2860_TX_RTY_CFG 0x134c 142 #define RT2860_TX_LINK_CFG 0x1350 143 #define RT2860_HT_FBK_CFG0 0x1354 144 #define RT2860_HT_FBK_CFG1 0x1358 145 #define RT2860_LG_FBK_CFG0 0x135c 146 #define RT2860_LG_FBK_CFG1 0x1360 147 #define RT2860_CCK_PROT_CFG 0x1364 148 #define RT2860_OFDM_PROT_CFG 0x1368 149 #define RT2860_MM20_PROT_CFG 0x136c 150 #define RT2860_MM40_PROT_CFG 0x1370 151 #define RT2860_GF20_PROT_CFG 0x1374 152 #define RT2860_GF40_PROT_CFG 0x1378 153 #define RT2860_EXP_CTS_TIME 0x137c 154 #define RT2860_EXP_ACK_TIME 0x1380 155 156 /* MAC RX configuration registers */ 157 #define RT2860_RX_FILTR_CFG 0x1400 158 #define RT2860_AUTO_RSP_CFG 0x1404 159 #define RT2860_LEGACY_BASIC_RATE 0x1408 160 #define RT2860_HT_BASIC_RATE 0x140c 161 #define RT2860_HT_CTRL_CFG 0x1410 162 #define RT2860_SIFS_COST_CFG 0x1414 163 #define RT2860_RX_PARSER_CFG 0x1418 164 165 /* MAC Security configuration registers */ 166 #define RT2860_TX_SEC_CNT0 0x1500 167 #define RT2860_RX_SEC_CNT0 0x1504 168 #define RT2860_CCMP_FC_MUTE 0x1508 169 170 /* MAC HCCA/PSMP configuration registers */ 171 #define RT2860_TXOP_HLDR_ADDR0 0x1600 172 #define RT2860_TXOP_HLDR_ADDR1 0x1604 173 #define RT2860_TXOP_HLDR_ET 0x1608 174 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c 175 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610 176 #define RT2860_QOS_CFPOLL_QC 0x1614 177 178 /* MAC Statistics Counters */ 179 #define RT2860_RX_STA_CNT0 0x1700 180 #define RT2860_RX_STA_CNT1 0x1704 181 #define RT2860_RX_STA_CNT2 0x1708 182 #define RT2860_TX_STA_CNT0 0x170c 183 #define RT2860_TX_STA_CNT1 0x1710 184 #define RT2860_TX_STA_CNT2 0x1714 185 #define RT2860_TX_STAT_FIFO 0x1718 186 187 /* RX WCID search table */ 188 #define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) 189 190 #define RT2860_FW_BASE 0x2000 191 #define RT2870_FW_BASE 0x3000 192 193 /* Pair-wise key table */ 194 #define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) 195 196 /* IV/EIV table */ 197 #define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) 198 199 /* WCID attribute table */ 200 #define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) 201 202 /* Shared Key Table */ 203 #define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) 204 205 /* Shared Key Mode */ 206 #define RT2860_SKEY_MODE_0_7 0x7000 207 #define RT2860_SKEY_MODE_8_15 0x7004 208 #define RT2860_SKEY_MODE_16_23 0x7008 209 #define RT2860_SKEY_MODE_24_31 0x700c 210 211 /* Shared Memory between MCU and host */ 212 #define RT2860_H2M_MAILBOX 0x7010 213 #define RT2860_H2M_MAILBOX_CID 0x7014 214 #define RT2860_H2M_MAILBOX_STATUS 0x701c 215 #define RT2860_H2M_INTSRC 0x7024 216 #define RT2860_H2M_BBPAGENT 0x7028 217 #define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) 218 219 220 /* possible flags for RT2860_PCI_CFG */ 221 #define RT2860_PCI_CFG_USB (1U << 17) 222 #define RT2860_PCI_CFG_PCI (1U << 16) 223 224 /* possible flags for register RT2860_PCI_EECTRL */ 225 #define RT2860_C (1U << 0) 226 #define RT2860_S (1U << 1) 227 #define RT2860_D (1U << 2) 228 #define RT2860_SHIFT_D 2 229 #define RT2860_Q (1U << 3) 230 #define RT2860_SHIFT_Q 3 231 232 /* possible flags for registers INT_STATUS/INT_MASK */ 233 #define RT2860_TX_COHERENT (1U << 17) 234 #define RT2860_RX_COHERENT (1U << 16) 235 #define RT2860_MAC_INT_4 (1U << 15) 236 #define RT2860_MAC_INT_3 (1U << 14) 237 #define RT2860_MAC_INT_2 (1U << 13) 238 #define RT2860_MAC_INT_1 (1U << 12) 239 #define RT2860_MAC_INT_0 (1U << 11) 240 #define RT2860_TX_RX_COHERENT (1U << 10) 241 #define RT2860_MCU_CMD_INT (1U << 9) 242 #define RT2860_TX_DONE_INT5 (1U << 8) 243 #define RT2860_TX_DONE_INT4 (1U << 7) 244 #define RT2860_TX_DONE_INT3 (1U << 6) 245 #define RT2860_TX_DONE_INT2 (1U << 5) 246 #define RT2860_TX_DONE_INT1 (1U << 4) 247 #define RT2860_TX_DONE_INT0 (1U << 3) 248 #define RT2860_RX_DONE_INT (1U << 2) 249 #define RT2860_TX_DLY_INT (1U << 1) 250 #define RT2860_RX_DLY_INT (1U << 0) 251 252 /* possible flags for register WPDMA_GLO_CFG */ 253 #define RT2860_HDR_SEG_LEN_SHIFT 8 254 #define RT2860_BIG_ENDIAN (1U << 7) 255 #define RT2860_TX_WB_DDONE (1U << 6) 256 #define RT2860_WPDMA_BT_SIZE_SHIFT 4 257 #define RT2860_WPDMA_BT_SIZE16 0 258 #define RT2860_WPDMA_BT_SIZE32 1 259 #define RT2860_WPDMA_BT_SIZE64 2 260 #define RT2860_WPDMA_BT_SIZE128 3 261 #define RT2860_RX_DMA_BUSY (1U << 3) 262 #define RT2860_RX_DMA_EN (1U << 2) 263 #define RT2860_TX_DMA_BUSY (1U << 1) 264 #define RT2860_TX_DMA_EN (1U << 0) 265 266 /* flags for register WPDMA_RST_IDX */ 267 #define RT2860_RST_DRX_IDX0 (1U << 16) 268 #define RT2860_RST_DTX_IDX5 (1U << 5) 269 #define RT2860_RST_DTX_IDX4 (1U << 4) 270 #define RT2860_RST_DTX_IDX3 (1U << 3) 271 #define RT2860_RST_DTX_IDX2 (1U << 2) 272 #define RT2860_RST_DTX_IDX1 (1U << 1) 273 #define RT2860_RST_DTX_IDX0 (1U << 0) 274 275 /* possible flags for register DELAY_INT_CFG */ 276 #define RT2860_TXDLY_INT_EN (1U << 31) 277 #define RT2860_TXMAX_PINT_SHIFT 24 278 #define RT2860_TXMAX_PTIME_SHIFT 16 279 #define RT2860_RXDLY_INT_EN (1U << 15) 280 #define RT2860_RXMAX_PINT_SHIFT 8 281 #define RT2860_RXMAX_PTIME_SHIFT 0 282 283 /* possible flags for register GPIO_CTRL */ 284 #define RT2860_GPIO_D_SHIFT 8 285 #define RT2860_GPIO_O_SHIFT 0 286 287 /* possible flags for register USB_DMA_CFG */ 288 #define RT2860_USB_TX_BUSY (1U << 31) 289 #define RT2860_USB_RX_BUSY (1U << 30) 290 #define RT2860_USB_EPOUT_VLD_SHIFT 24 291 #define RT2860_USB_TX_EN (1U << 23) 292 #define RT2860_USB_RX_EN (1U << 22) 293 #define RT2860_USB_RX_AGG_EN (1U << 21) 294 #define RT2860_USB_TXOP_HALT (1U << 20) 295 #define RT2860_USB_TX_CLEAR (1U << 19) 296 #define RT2860_USB_PHY_WD_EN (1U << 16) 297 #define RT2860_USB_PHY_MAN_RST (1U << 15) 298 #define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ 299 #define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ 300 301 /* possible flags for register US_CYC_CNT */ 302 #define RT2860_TEST_EN (1U << 24) 303 #define RT2860_TEST_SEL_SHIFT 16 304 #define RT2860_BT_MODE_EN (1U << 8) 305 #define RT2860_US_CYC_CNT_SHIFT 0 306 307 /* possible flags for register SYS_CTRL */ 308 #define RT2860_HST_PM_SEL (1U << 16) 309 #define RT2860_CAP_MODE (1U << 14) 310 #define RT2860_PME_OEN (1U << 13) 311 #define RT2860_CLKSELECT (1U << 12) 312 #define RT2860_PBF_CLK_EN (1U << 11) 313 #define RT2860_MAC_CLK_EN (1U << 10) 314 #define RT2860_DMA_CLK_EN (1U << 9) 315 #define RT2860_MCU_READY (1U << 7) 316 #define RT2860_ASY_RESET (1U << 4) 317 #define RT2860_PBF_RESET (1U << 3) 318 #define RT2860_MAC_RESET (1U << 2) 319 #define RT2860_DMA_RESET (1U << 1) 320 #define RT2860_MCU_RESET (1U << 0) 321 322 /* possible values for register HOST_CMD */ 323 #define RT2860_MCU_CMD_SLEEP 0x30 324 #define RT2860_MCU_CMD_WAKEUP 0x31 325 #define RT2860_MCU_CMD_LEDS 0x50 326 #define RT2860_MCU_CMD_LED_RSSI 0x51 327 #define RT2860_MCU_CMD_LED1 0x52 328 #define RT2860_MCU_CMD_LED2 0x53 329 #define RT2860_MCU_CMD_LED3 0x54 330 #define RT2860_MCU_CMD_RFRESET 0x72 331 #define RT2860_MCU_CMD_ANTSEL 0x73 332 #define RT2860_MCU_CMD_BBP 0x80 333 #define RT2860_MCU_CMD_PSLEVEL 0x83 334 335 /* possible flags for register PBF_CFG */ 336 #define RT2860_TX1Q_NUM_SHIFT 21 337 #define RT2860_TX2Q_NUM_SHIFT 16 338 #define RT2860_NULL0_MODE (1U << 15) 339 #define RT2860_NULL1_MODE (1U << 14) 340 #define RT2860_RX_DROP_MODE (1U << 13) 341 #define RT2860_TX0Q_MANUAL (1U << 12) 342 #define RT2860_TX1Q_MANUAL (1U << 11) 343 #define RT2860_TX2Q_MANUAL (1U << 10) 344 #define RT2860_RX0Q_MANUAL (1U << 9) 345 #define RT2860_HCCA_EN (1U << 8) 346 #define RT2860_TX0Q_EN (1U << 4) 347 #define RT2860_TX1Q_EN (1U << 3) 348 #define RT2860_TX2Q_EN (1U << 2) 349 #define RT2860_RX0Q_EN (1U << 1) 350 351 /* possible flags for register BUF_CTRL */ 352 #define RT2860_WRITE_TXQ(qid) (1U << (11 - (qid))) 353 #define RT2860_NULL0_KICK (1U << 7) 354 #define RT2860_NULL1_KICK (1U << 6) 355 #define RT2860_BUF_RESET (1U << 5) 356 #define RT2860_READ_TXQ(qid) (1U << (3 - (qid)) 357 #define RT2860_READ_RX0Q (1U << 0) 358 359 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ 360 #define RT2860_MCU_MAC_INT_8 (1U << 24) 361 #define RT2860_MCU_MAC_INT_7 (1U << 23) 362 #define RT2860_MCU_MAC_INT_6 (1U << 22) 363 #define RT2860_MCU_MAC_INT_4 (1U << 20) 364 #define RT2860_MCU_MAC_INT_3 (1U << 19) 365 #define RT2860_MCU_MAC_INT_2 (1U << 18) 366 #define RT2860_MCU_MAC_INT_1 (1U << 17) 367 #define RT2860_MCU_MAC_INT_0 (1U << 16) 368 #define RT2860_DTX0_INT (1U << 11) 369 #define RT2860_DTX1_INT (1U << 10) 370 #define RT2860_DTX2_INT (1U << 9) 371 #define RT2860_DRX0_INT (1U << 8) 372 #define RT2860_HCMD_INT (1U << 7) 373 #define RT2860_N0TX_INT (1U << 6) 374 #define RT2860_N1TX_INT (1U << 5) 375 #define RT2860_BCNTX_INT (1U << 4) 376 #define RT2860_MTX0_INT (1U << 3) 377 #define RT2860_MTX1_INT (1U << 2) 378 #define RT2860_MTX2_INT (1U << 1) 379 #define RT2860_MRX0_INT (1U << 0) 380 381 /* possible flags for register TXRXQ_PCNT */ 382 #define RT2860_RX0Q_PCNT_MASK 0xff000000 383 #define RT2860_TX2Q_PCNT_MASK 0x00ff0000 384 #define RT2860_TX1Q_PCNT_MASK 0x0000ff00 385 #define RT2860_TX0Q_PCNT_MASK 0x000000ff 386 387 /* possible flags for register CAP_CTRL */ 388 #define RT2860_CAP_ADC_FEQ (1U << 31) 389 #define RT2860_CAP_START (1U << 30) 390 #define RT2860_MAN_TRIG (1U << 29) 391 #define RT2860_TRIG_OFFSET_SHIFT 16 392 #define RT2860_START_ADDR_SHIFT 0 393 394 /* possible flags for register RF_CSR_CFG */ 395 #define RT3070_RF_KICK (1U << 17) 396 #define RT3070_RF_WRITE (1U << 16) 397 398 /* possible flags for register EFUSE_CTRL */ 399 #define RT3070_SEL_EFUSE (1U << 31) 400 #define RT3070_EFSROM_KICK (1U << 30) 401 #define RT3070_EFSROM_AIN_MASK 0x03ff0000 402 #define RT3070_EFSROM_AIN_SHIFT 16 403 #define RT3070_EFSROM_MODE_MASK 0x000000c0 404 #define RT3070_EFUSE_AOUT_MASK 0x0000003f 405 406 /* possible flag for register DEBUG_INDEX */ 407 #define RT5592_SEL_XTAL (1U << 31) 408 409 /* possible flags for register MAC_SYS_CTRL */ 410 #define RT2860_RX_TS_EN (1U << 7) 411 #define RT2860_WLAN_HALT_EN (1U << 6) 412 #define RT2860_PBF_LOOP_EN (1U << 5) 413 #define RT2860_CONT_TX_TEST (1U << 4) 414 #define RT2860_MAC_RX_EN (1U << 3) 415 #define RT2860_MAC_TX_EN (1U << 2) 416 #define RT2860_BBP_HRST (1U << 1) 417 #define RT2860_MAC_SRST (1U << 0) 418 419 /* possible flags for register MAC_BSSID_DW1 */ 420 #define RT2860_MULTI_BCN_NUM_SHIFT 18 421 #define RT2860_MULTI_BSSID_MODE_SHIFT 16 422 423 /* possible flags for register MAX_LEN_CFG */ 424 #define RT2860_MIN_MPDU_LEN_SHIFT 16 425 #define RT2860_MAX_PSDU_LEN_SHIFT 12 426 #define RT2860_MAX_PSDU_LEN8K 0 427 #define RT2860_MAX_PSDU_LEN16K 1 428 #define RT2860_MAX_PSDU_LEN32K 2 429 #define RT2860_MAX_PSDU_LEN64K 3 430 #define RT2860_MAX_MPDU_LEN_SHIFT 0 431 432 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ 433 #define RT2860_BBP_RW_PARALLEL (1U << 19) 434 #define RT2860_BBP_PAR_DUR_112_5 (1U << 18) 435 #define RT2860_BBP_CSR_KICK (1U << 17) 436 #define RT2860_BBP_CSR_READ (1U << 16) 437 #define RT2860_BBP_ADDR_SHIFT 8 438 #define RT2860_BBP_DATA_SHIFT 0 439 440 /* possible flags for register RF_CSR_CFG0 */ 441 #define RT2860_RF_REG_CTRL (1U << 31) 442 #define RT2860_RF_LE_SEL1 (1U << 30) 443 #define RT2860_RF_LE_STBY (1U << 29) 444 #define RT2860_RF_REG_WIDTH_SHIFT 24 445 #define RT2860_RF_REG_0_SHIFT 0 446 447 /* possible flags for register RF_CSR_CFG1 */ 448 #define RT2860_RF_DUR_5 (1U << 24) 449 #define RT2860_RF_REG_1_SHIFT 0 450 451 /* possible flags for register LED_CFG */ 452 #define RT2860_LED_POL (1U << 30) 453 #define RT2860_Y_LED_MODE_SHIFT 28 454 #define RT2860_G_LED_MODE_SHIFT 26 455 #define RT2860_R_LED_MODE_SHIFT 24 456 #define RT2860_LED_MODE_OFF 0 457 #define RT2860_LED_MODE_BLINK_TX 1 458 #define RT2860_LED_MODE_SLOW_BLINK 2 459 #define RT2860_LED_MODE_ON 3 460 #define RT2860_SLOW_BLK_TIME_SHIFT 16 461 #define RT2860_LED_OFF_TIME_SHIFT 8 462 #define RT2860_LED_ON_TIME_SHIFT 0 463 464 /* possible flags for register XIFS_TIME_CFG */ 465 #define RT2860_BB_RXEND_EN (1U << 29) 466 #define RT2860_EIFS_TIME_SHIFT 20 467 #define RT2860_OFDM_XIFS_TIME_SHIFT 16 468 #define RT2860_OFDM_SIFS_TIME_SHIFT 8 469 #define RT2860_CCK_SIFS_TIME_SHIFT 0 470 471 /* possible flags for register BKOFF_SLOT_CFG */ 472 #define RT2860_CC_DELAY_TIME_SHIFT 8 473 #define RT2860_SLOT_TIME 0 474 475 /* possible flags for register NAV_TIME_CFG */ 476 #define RT2860_NAV_UPD (1U << 31) 477 #define RT2860_NAV_UPD_VAL_SHIFT 16 478 #define RT2860_NAV_CLR_EN (1U << 15) 479 #define RT2860_NAV_TIMER_SHIFT 0 480 481 /* possible flags for register CH_TIME_CFG */ 482 #define RT2860_EIFS_AS_CH_BUSY (1U << 4) 483 #define RT2860_NAV_AS_CH_BUSY (1U << 3) 484 #define RT2860_RX_AS_CH_BUSY (1U << 2) 485 #define RT2860_TX_AS_CH_BUSY (1U << 1) 486 #define RT2860_CH_STA_TIMER_EN (1U << 0) 487 488 /* possible values for register BCN_TIME_CFG */ 489 #define RT2860_TSF_INS_COMP_SHIFT 24 490 #define RT2860_BCN_TX_EN (1U << 20) 491 #define RT2860_TBTT_TIMER_EN (1U << 19) 492 #define RT2860_TSF_SYNC_MODE_SHIFT 17 493 #define RT2860_TSF_SYNC_MODE_DIS 0 494 #define RT2860_TSF_SYNC_MODE_STA 1 495 #define RT2860_TSF_SYNC_MODE_IBSS 2 496 #define RT2860_TSF_SYNC_MODE_HOSTAP 3 497 #define RT2860_TSF_TIMER_EN (1U << 16) 498 #define RT2860_BCN_INTVAL_SHIFT 0 499 500 /* possible flags for register TBTT_SYNC_CFG */ 501 #define RT2860_BCN_CWMIN_SHIFT 20 502 #define RT2860_BCN_AIFSN_SHIFT 16 503 #define RT2860_BCN_EXP_WIN_SHIFT 8 504 #define RT2860_TBTT_ADJUST_SHIFT 0 505 506 /* possible flags for register INT_TIMER_CFG */ 507 #define RT2860_GP_TIMER_SHIFT 16 508 #define RT2860_PRE_TBTT_TIMER_SHIFT 0 509 510 /* possible flags for register INT_TIMER_EN */ 511 #define RT2860_GP_TIMER_EN (1U << 1) 512 #define RT2860_PRE_TBTT_INT_EN (1U << 0) 513 514 /* possible flags for register MAC_STATUS_REG */ 515 #define RT2860_RX_STATUS_BUSY (1U << 1) 516 #define RT2860_TX_STATUS_BUSY (1U << 0) 517 518 /* possible flags for register PWR_PIN_CFG */ 519 #define RT2860_IO_ADDA_PD (1U << 3) 520 #define RT2860_IO_PLL_PD (1U << 2) 521 #define RT2860_IO_RA_PE (1U << 1) 522 #define RT2860_IO_RF_PE (1U << 0) 523 524 /* possible flags for register AUTO_WAKEUP_CFG */ 525 #define RT2860_AUTO_WAKEUP_EN (1U << 15) 526 #define RT2860_SLEEP_TBTT_NUM_SHIFT 8 527 #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 528 529 /* possible flags for register TX_PIN_CFG */ 530 #define RT3593_LNA_PE_G2_POL (1U << 31) 531 #define RT3593_LNA_PE_A2_POL (1U << 30) 532 #define RT3593_LNA_PE_G2_EN (1U << 29) 533 #define RT3593_LNA_PE_A2_EN (1U << 28) 534 #define RT3593_LNA_PE2_EN (RT3593_LNA_PE_A2_EN | RT3593_LNA_PE_G2_EN) 535 #define RT3593_PA_PE_G2_POL (1U << 27) 536 #define RT3593_PA_PE_A2_POL (1U << 26) 537 #define RT3593_PA_PE_G2_EN (1U << 25) 538 #define RT3593_PA_PE_A2_EN (1U << 24) 539 #define RT2860_TRSW_POL (1U << 19) 540 #define RT2860_TRSW_EN (1U << 18) 541 #define RT2860_RFTR_POL (1U << 17) 542 #define RT2860_RFTR_EN (1U << 16) 543 #define RT2860_LNA_PE_G1_POL (1U << 15) 544 #define RT2860_LNA_PE_A1_POL (1U << 14) 545 #define RT2860_LNA_PE_G0_POL (1U << 13) 546 #define RT2860_LNA_PE_A0_POL (1U << 12) 547 #define RT2860_LNA_PE_G1_EN (1U << 11) 548 #define RT2860_LNA_PE_A1_EN (1U << 10) 549 #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) 550 #define RT2860_LNA_PE_G0_EN (1U << 9) 551 #define RT2860_LNA_PE_A0_EN (1U << 8) 552 #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) 553 #define RT2860_PA_PE_G1_POL (1U << 7) 554 #define RT2860_PA_PE_A1_POL (1U << 6) 555 #define RT2860_PA_PE_G0_POL (1U << 5) 556 #define RT2860_PA_PE_A0_POL (1U << 4) 557 #define RT2860_PA_PE_G1_EN (1U << 3) 558 #define RT2860_PA_PE_A1_EN (1U << 2) 559 #define RT2860_PA_PE_G0_EN (1U << 1) 560 #define RT2860_PA_PE_A0_EN (1U << 0) 561 562 /* possible flags for register TX_BAND_CFG */ 563 #define RT2860_5G_BAND_SEL_N (1U << 2) 564 #define RT2860_5G_BAND_SEL_P (1U << 1) 565 #define RT2860_TX_BAND_SEL (1U << 0) 566 567 /* possible flags for register TX_SW_CFG0 */ 568 #define RT2860_DLY_RFTR_EN_SHIFT 24 569 #define RT2860_DLY_TRSW_EN_SHIFT 16 570 #define RT2860_DLY_PAPE_EN_SHIFT 8 571 #define RT2860_DLY_TXPE_EN_SHIFT 0 572 573 /* possible flags for register TX_SW_CFG1 */ 574 #define RT2860_DLY_RFTR_DIS_SHIFT 16 575 #define RT2860_DLY_TRSW_DIS_SHIFT 8 576 #define RT2860_DLY_PAPE_DIS SHIFT 0 577 578 /* possible flags for register TX_SW_CFG2 */ 579 #define RT2860_DLY_LNA_EN_SHIFT 24 580 #define RT2860_DLY_LNA_DIS_SHIFT 16 581 #define RT2860_DLY_DAC_EN_SHIFT 8 582 #define RT2860_DLY_DAC_DIS_SHIFT 0 583 584 /* possible flags for register TXOP_THRES_CFG */ 585 #define RT2860_TXOP_REM_THRES_SHIFT 24 586 #define RT2860_CF_END_THRES_SHIFT 16 587 #define RT2860_RDG_IN_THRES 8 588 #define RT2860_RDG_OUT_THRES 0 589 590 /* possible flags for register TXOP_CTRL_CFG */ 591 #define RT2860_EXT_CW_MIN_SHIFT 16 592 #define RT2860_EXT_CCA_DLY_SHIFT 8 593 #define RT2860_EXT_CCA_EN (1U << 7) 594 #define RT2860_LSIG_TXOP_EN (1U << 6) 595 #define RT2860_TXOP_TRUN_EN_MIMOPS (1U << 4) 596 #define RT2860_TXOP_TRUN_EN_TXOP (1U << 3) 597 #define RT2860_TXOP_TRUN_EN_RATE (1U << 2) 598 #define RT2860_TXOP_TRUN_EN_AC (1U << 1) 599 #define RT2860_TXOP_TRUN_EN_TIMEOUT (1U << 0) 600 601 /* possible flags for register TX_RTS_CFG */ 602 #define RT2860_RTS_FBK_EN (1U << 24) 603 #define RT2860_RTS_THRES_SHIFT 8 604 #define RT2860_RTS_RTY_LIMIT_SHIFT 0 605 606 /* possible flags for register TX_TIMEOUT_CFG */ 607 #define RT2860_TXOP_TIMEOUT_SHIFT 16 608 #define RT2860_RX_ACK_TIMEOUT_SHIFT 8 609 #define RT2860_MPDU_LIFE_TIME_SHIFT 4 610 611 /* possible flags for register TX_RTY_CFG */ 612 #define RT2860_TX_AUTOFB_EN (1U << 30) 613 #define RT2860_AGG_RTY_MODE_TIMER (1U << 29) 614 #define RT2860_NAG_RTY_MODE_TIMER (1U << 28) 615 #define RT2860_LONG_RTY_THRES_SHIFT 16 616 #define RT2860_LONG_RTY_LIMIT_SHIFT 8 617 #define RT2860_SHORT_RTY_LIMIT_SHIFT 0 618 619 /* possible flags for register TX_LINK_CFG */ 620 #define RT2860_REMOTE_MFS_SHIFT 24 621 #define RT2860_REMOTE_MFB_SHIFT 16 622 #define RT2860_TX_CFACK_EN (1U << 12) 623 #define RT2860_TX_RDG_EN (1U << 11) 624 #define RT2860_TX_MRQ_EN (1U << 10) 625 #define RT2860_REMOTE_UMFS_EN (1U << 9) 626 #define RT2860_TX_MFB_EN (1U << 8) 627 #define RT2860_REMOTE_MFB_LT_SHIFT 0 628 629 /* possible flags for registers *_PROT_CFG */ 630 #define RT2860_RTSTH_EN (1U << 26) 631 #define RT2860_TXOP_ALLOW_GF40 (1U << 25) 632 #define RT2860_TXOP_ALLOW_GF20 (1U << 24) 633 #define RT2860_TXOP_ALLOW_MM40 (1U << 23) 634 #define RT2860_TXOP_ALLOW_MM20 (1U << 22) 635 #define RT2860_TXOP_ALLOW_OFDM (1U << 21) 636 #define RT2860_TXOP_ALLOW_CCK (1U << 20) 637 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20) 638 #define RT2860_PROT_NAV_SHORT (1U << 18) 639 #define RT2860_PROT_NAV_LONG (2 << 18) 640 #define RT2860_PROT_CTRL_RTS_CTS (1U << 16) 641 #define RT2860_PROT_CTRL_CTS (2 << 16) 642 643 /* possible flags for registers EXP_{CTS,ACK}_TIME */ 644 #define RT2860_EXP_OFDM_TIME_SHIFT 16 645 #define RT2860_EXP_CCK_TIME_SHIFT 0 646 647 /* possible flags for register RX_FILTR_CFG */ 648 #define RT2860_DROP_CTRL_RSV (1U << 16) 649 #define RT2860_DROP_BAR (1U << 15) 650 #define RT2860_DROP_BA (1U << 14) 651 #define RT2860_DROP_PSPOLL (1U << 13) 652 #define RT2860_DROP_RTS (1U << 12) 653 #define RT2860_DROP_CTS (1U << 11) 654 #define RT2860_DROP_ACK (1U << 10) 655 #define RT2860_DROP_CFEND (1U << 9) 656 #define RT2860_DROP_CFACK (1U << 8) 657 #define RT2860_DROP_DUPL (1U << 7) 658 #define RT2860_DROP_BC (1U << 6) 659 #define RT2860_DROP_MC (1U << 5) 660 #define RT2860_DROP_VER_ERR (1U << 4) 661 #define RT2860_DROP_NOT_MYBSS (1U << 3) 662 #define RT2860_DROP_UC_NOME (1U << 2) 663 #define RT2860_DROP_PHY_ERR (1U << 1) 664 #define RT2860_DROP_CRC_ERR (1U << 0) 665 666 /* possible flags for register AUTO_RSP_CFG */ 667 #define RT2860_CTRL_PWR_BIT (1U << 7) 668 #define RT2860_BAC_ACK_POLICY (1U << 6) 669 #define RT2860_CCK_SHORT_EN (1U << 4) 670 #define RT2860_CTS_40M_REF_EN (1U << 3) 671 #define RT2860_CTS_40M_MODE_EN (1U << 2) 672 #define RT2860_BAC_ACKPOLICY_EN (1U << 1) 673 #define RT2860_AUTO_RSP_EN (1U << 0) 674 675 /* possible flags for register SIFS_COST_CFG */ 676 #define RT2860_OFDM_SIFS_COST_SHIFT 8 677 #define RT2860_CCK_SIFS_COST_SHIFT 0 678 679 /* possible flags for register TXOP_HLDR_ET */ 680 #define RT2860_TXOP_ETM1_EN (1U << 25) 681 #define RT2860_TXOP_ETM0_EN (1U << 24) 682 #define RT2860_TXOP_ETM_THRES_SHIFT 16 683 #define RT2860_TXOP_ETO_EN (1U << 8) 684 #define RT2860_TXOP_ETO_THRES_SHIFT 1 685 #define RT2860_PER_RX_RST_EN (1U << 0) 686 687 /* possible flags for register TX_STAT_FIFO */ 688 #define RT2860_TXQ_MCS_SHIFT 16 689 #define RT2860_TXQ_WCID_SHIFT 8 690 #define RT2860_TXQ_ACKREQ (1U << 7) 691 #define RT2860_TXQ_AGG (1U << 6) 692 #define RT2860_TXQ_OK (1U << 5) 693 #define RT2860_TXQ_PID_SHIFT 1 694 #define RT2860_TXQ_VLD (1U << 0) 695 696 /* possible flags for register WCID_ATTR */ 697 #define RT2860_MODE_NOSEC 0 698 #define RT2860_MODE_WEP40 1 699 #define RT2860_MODE_WEP104 2 700 #define RT2860_MODE_TKIP 3 701 #define RT2860_MODE_AES_CCMP 4 702 #define RT2860_MODE_CKIP40 5 703 #define RT2860_MODE_CKIP104 6 704 #define RT2860_MODE_CKIP128 7 705 #define RT2860_RX_PKEY_EN (1U << 0) 706 707 /* possible flags for register H2M_MAILBOX */ 708 #define RT2860_H2M_BUSY (1U << 24) 709 #define RT2860_TOKEN_NO_INTR 0xff 710 711 712 /* possible flags for MCU command RT2860_MCU_CMD_LEDS */ 713 #define RT2860_LED_RADIO (1U << 13) 714 #define RT2860_LED_LINK_2GHZ (1U << 14) 715 #define RT2860_LED_LINK_5GHZ (1U << 15) 716 717 718 /* possible flags for RT3020 RF register 1 */ 719 #define RT3070_RF_BLOCK (1U << 0) 720 #define RT3070_PLL_PD (1U << 1) 721 #define RT3070_RX0_PD (1U << 2) 722 #define RT3070_TX0_PD (1U << 3) 723 #define RT3070_RX1_PD (1U << 4) 724 #define RT3070_TX1_PD (1U << 5) 725 #define RT3070_RX2_PD (1U << 6) 726 #define RT3070_TX2_PD (1U << 7) 727 728 /* possible flags for RT3020 RF register 7 */ 729 #define RT3070_TUNE (1U << 0) 730 731 /* possible flags for RT3020 RF register 15 */ 732 #define RT3070_TX_LO2 (1U << 3) 733 734 /* possible flags for RT3020 RF register 17 */ 735 #define RT3070_TX_LO1 (1U << 3) 736 737 /* possible flags for RT3020 RF register 20 */ 738 #define RT3070_RX_LO1 (1U << 3) 739 740 /* possible flags for RT3020 RF register 21 */ 741 #define RT3070_RX_LO2 (1U << 3) 742 #define RT3070_RX_CTB (1U << 7) 743 744 /* possible flags for RT3020 RF register 22 */ 745 #define RT3070_BB_LOOPBACK (1U << 0) 746 747 /* possible flags for RT3053 RF register 1 */ 748 #define RT3593_VCO (1U << 0) 749 750 /* possible flags for RT3053 RF register 2 */ 751 #define RT3593_RESCAL (1U << 7) 752 753 /* possible flags for RT3053 RF register 3 */ 754 #define RT3593_VCOCAL (1U << 7) 755 756 /* possible flags for RT3053 RF register 6 */ 757 #define RT3593_VCO_IC (1U << 6) 758 759 /* possible flags for RT3053 RF register 18 */ 760 #define RT3593_AUTOTUNE_BYPASS (1U << 6) 761 762 /* possible flags for RT3053 RF register 20 */ 763 #define RT3593_LDO_PLL_VC_MASK 0x0e 764 #define RT3593_LDO_RF_VC_MASK 0xe0 765 766 /* possible flags for RT3053 RF register 22 */ 767 #define RT3593_CP_IC_MASK 0xe0 768 #define RT3593_CP_IC_SHIFT 5 769 770 /* possible flags for RT5390 RF register 38. */ 771 #define RT5390_RX_LO1 (1U << 5) 772 773 /* possible flags for RT5390 RF register 39. */ 774 #define RT5390_RX_LO2 (1U << 7) 775 776 /* possible flags for RT5390 RF register 42 */ 777 #define RT5390_RX_CTB (1U << 6) 778 779 /* possible flags for RT3053 RF register 46 */ 780 #define RT3593_RX_CTB (1U << 5) 781 782 /* possible flags for RT3053 RF register 50 */ 783 #define RT3593_TX_LO2 (1U << 4) 784 785 /* possible flags for RT3053 RF register 51 */ 786 #define RT3593_TX_LO1 (1U << 4) 787 788 /* Possible flags for RT5390 RF register 2. */ 789 #define RT5390_RESCAL (1 << 7) 790 791 /* Possible flags for RT5390 RF register 3. */ 792 #define RT5390_VCOCAL (1 << 7) 793 794 /* Possible flags for RT5390 BBP register 4. */ 795 #define RT5390_MAC_IF_CTRL (1U << 6) 796 797 /* possible flags for RT5390 BBP register 105. */ 798 #define RT5390_MLD (1U << 2) 799 #define RT5390_EN_SIG_MODULATION (1U << 3) 800 801 #define RT3090_DEF_LNA 10 802 803 /* RT2860 TX descriptor */ 804 struct rt2860_txd { 805 uint32_t sdp0; /* Segment Data Pointer 0 */ 806 uint16_t sdl1; /* Segment Data Length 1 */ 807 #define RT2860_TX_BURST (1U << 15) 808 #define RT2860_TX_LS1 (1U << 14) /* SDP1 is the last segment */ 809 810 uint16_t sdl0; /* Segment Data Length 0 */ 811 #define RT2860_TX_DDONE (1U << 15) 812 #define RT2860_TX_LS0 (1U << 14) /* SDP0 is the last segment */ 813 814 uint32_t sdp1; /* Segment Data Pointer 1 */ 815 uint8_t reserved[3]; 816 uint8_t flags; 817 #define RT2860_TX_QSEL_SHIFT 1 818 #define RT2860_TX_QSEL_MGMT (0 << 1) 819 #define RT2860_TX_QSEL_HCCA (1U << 1) 820 #define RT2860_TX_QSEL_EDCA (2 << 1) 821 #define RT2860_TX_WIV (1U << 0) 822 } __packed; 823 824 /* RT2870 TX descriptor */ 825 struct rt2870_txd { 826 uint16_t len; 827 uint8_t pad; 828 uint8_t flags; 829 } __packed; 830 831 /* TX Wireless Information */ 832 struct rt2860_txwi { 833 uint8_t flags; 834 #define RT2860_TX_MPDU_DSITY_SHIFT 5 835 #define RT2860_TX_AMPDU (1U << 4) 836 #define RT2860_TX_TS (1U << 3) 837 #define RT2860_TX_CFACK (1U << 2) 838 #define RT2860_TX_MMPS (1U << 1) 839 #define RT2860_TX_FRAG (1U << 0) 840 841 uint8_t txop; 842 #define RT2860_TX_TXOP_HT 0 843 #define RT2860_TX_TXOP_PIFS 1 844 #define RT2860_TX_TXOP_SIFS 2 845 #define RT2860_TX_TXOP_BACKOFF 3 846 847 uint16_t phy; 848 #define RT2860_PHY_MODE 0xc000 849 #define RT2860_PHY_CCK (0 << 14) 850 #define RT2860_PHY_OFDM (1U << 14) 851 #define RT2860_PHY_HT (2 << 14) 852 #define RT2860_PHY_HT_GF (3 << 14) 853 #define RT2860_PHY_SGI (1U << 8) 854 #define RT2860_PHY_BW40 (1U << 7) 855 #define RT2860_PHY_MCS 0x7f 856 #define RT2860_PHY_SHPRE (1U << 3) 857 858 uint8_t xflags; 859 #define RT2860_TX_BAWINSIZE_SHIFT 2 860 #define RT2860_TX_NSEQ (1U << 1) 861 #define RT2860_TX_ACK (1U << 0) 862 863 uint8_t wcid; /* Wireless Client ID */ 864 uint16_t len; 865 #define RT2860_TX_PID_SHIFT 12 866 867 uint32_t iv; 868 uint32_t eiv; 869 } __packed; 870 871 /* RT2860 RX descriptor */ 872 struct rt2860_rxd { 873 uint32_t sdp0; 874 uint16_t sdl1; /* unused */ 875 uint16_t sdl0; 876 #define RT2860_RX_DDONE (1U << 15) 877 #define RT2860_RX_LS0 (1U << 14) 878 879 uint32_t sdp1; /* unused */ 880 uint32_t flags; 881 #define RT2860_RX_DEC (1U << 16) 882 #define RT2860_RX_AMPDU (1U << 15) 883 #define RT2860_RX_L2PAD (1U << 14) 884 #define RT2860_RX_RSSI (1U << 13) 885 #define RT2860_RX_HTC (1U << 12) 886 #define RT2860_RX_AMSDU (1U << 11) 887 #define RT2860_RX_MICERR (1U << 10) 888 #define RT2860_RX_ICVERR (1U << 9) 889 #define RT2860_RX_CRCERR (1U << 8) 890 #define RT2860_RX_MYBSS (1U << 7) 891 #define RT2860_RX_BC (1U << 6) 892 #define RT2860_RX_MC (1U << 5) 893 #define RT2860_RX_UC2ME (1U << 4) 894 #define RT2860_RX_FRAG (1U << 3) 895 #define RT2860_RX_NULL (1U << 2) 896 #define RT2860_RX_DATA (1U << 1) 897 #define RT2860_RX_BA (1U << 0) 898 } __packed; 899 900 /* RT2870 RX descriptor */ 901 struct rt2870_rxd { 902 /* single 32-bit field */ 903 uint32_t flags; 904 } __packed; 905 906 /* RX Wireless Information */ 907 struct rt2860_rxwi { 908 uint8_t wcid; 909 uint8_t keyidx; 910 #define RT2860_RX_UDF_SHIFT 5 911 #define RT2860_RX_BSS_IDX_SHIFT 2 912 913 uint16_t len; 914 #define RT2860_RX_TID_SHIFT 12 915 916 uint16_t seq; 917 uint16_t phy; 918 uint8_t rssi[3]; 919 uint8_t reserved1; 920 uint8_t snr[2]; 921 uint16_t reserved2; 922 } __packed; 923 924 925 /* first DMA segment contains TXWI + 802.11 header + 32-bit padding */ 926 #define RT2860_TXWI_DMASZ \ 927 (sizeof (struct rt2860_txwi) + \ 928 sizeof (struct ieee80211_htframe) + \ 929 sizeof (uint16_t)) 930 931 #define RT2860_RF1 0 932 #define RT2860_RF2 2 933 #define RT2860_RF3 1 934 #define RT2860_RF4 3 935 936 #define RT2860_RF_2820 0x0001 /* 2T3R */ 937 #define RT2860_RF_2850 0x0002 /* dual-band 2T3R */ 938 #define RT2860_RF_2720 0x0003 /* 1T2R */ 939 #define RT2860_RF_2750 0x0004 /* dual-band 1T2R */ 940 #define RT3070_RF_3020 0x0005 /* 1T1R */ 941 #define RT3070_RF_2020 0x0006 /* b/g */ 942 #define RT3070_RF_3021 0x0007 /* 1T2R */ 943 #define RT3070_RF_3022 0x0008 /* 2T2R */ 944 #define RT3070_RF_3052 0x0009 /* dual-band 2T2R */ 945 #define RT3070_RF_3320 0x000b /* 1T1R */ 946 #define RT3070_RF_3053 0x000d /* dual-band 3T3R */ 947 #define RT5592_RF_5592 0x000f /* dual-band 2T2R */ 948 #define RT5390_RF_5360 0x5360 /* 1T1R */ 949 #define RT5390_RF_5370 0x5370 /* 1T1R */ 950 #define RT5390_RF_5372 0x5372 /* 2T2R */ 951 #define RT5390_RF_5390 0x5390 /* 1T1R */ 952 953 954 /* USB commands for RT2870 only */ 955 #define RT2870_RESET 1 956 #define RT2870_WRITE_2 2 957 #define RT2870_WRITE_REGION_1 6 958 #define RT2870_READ_REGION_1 7 959 #define RT2870_EEPROM_READ 9 960 961 #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 962 963 #define RT2860_EEPROM_CHIPID 0x00 964 #define RT2860_EEPROM_VERSION 0x01 965 #define RT2860_EEPROM_MAC01 0x02 966 #define RT2860_EEPROM_MAC23 0x03 967 #define RT2860_EEPROM_MAC45 0x04 968 #define RT2860_EEPROM_PCIE_PSLEVEL 0x11 969 #define RT2860_EEPROM_REV 0x12 970 #define RT2860_EEPROM_ANTENNA 0x1a 971 #define RT2860_EEPROM_CONFIG 0x1b 972 #define RT2860_EEPROM_COUNTRY 0x1c 973 #define RT2860_EEPROM_FREQ_LEDS 0x1d 974 #define RT2860_EEPROM_LED1 0x1e 975 #define RT2860_EEPROM_LED2 0x1f 976 #define RT2860_EEPROM_LED3 0x20 977 #define RT2860_EEPROM_LNA 0x22 978 #define RT2860_EEPROM_RSSI1_2GHZ 0x23 979 #define RT2860_EEPROM_RSSI2_2GHZ 0x24 980 #define RT2860_EEPROM_RSSI1_5GHZ 0x25 981 #define RT2860_EEPROM_RSSI2_5GHZ 0x26 982 #define RT2860_EEPROM_DELTAPWR 0x28 983 #define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 984 #define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 985 #define RT2860_EEPROM_TSSI1_2GHZ 0x37 986 #define RT2860_EEPROM_TSSI2_2GHZ 0x38 987 #define RT2860_EEPROM_TSSI3_2GHZ 0x39 988 #define RT2860_EEPROM_TSSI4_2GHZ 0x3a 989 #define RT2860_EEPROM_TSSI5_2GHZ 0x3b 990 #define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c 991 #define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 992 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a 993 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b 994 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c 995 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d 996 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e 997 #define RT2860_EEPROM_RPWR 0x6f 998 #define RT2860_EEPROM_BBP_BASE 0x78 999 #define RT3071_EEPROM_RF_BASE 0x82 1000 1001 /* EEPROM registers for RT3593. */ 1002 #define RT3593_EEPROM_FREQ_LEDS 0x21 1003 #define RT3593_EEPROM_FREQ 0x22 1004 #define RT3593_EEPROM_LED1 0x22 1005 #define RT3593_EEPROM_LED2 0x23 1006 #define RT3593_EEPROM_LED3 0x24 1007 #define RT3593_EEPROM_LNA 0x26 1008 #define RT3593_EEPROM_LNA_5GHZ 0x27 1009 #define RT3593_EEPROM_RSSI1_2GHZ 0x28 1010 #define RT3593_EEPROM_RSSI2_2GHZ 0x29 1011 #define RT3593_EEPROM_RSSI1_5GHZ 0x2a 1012 #define RT3593_EEPROM_RSSI2_5GHZ 0x2b 1013 #define RT3593_EEPROM_PWR2GHZ_BASE1 0x30 1014 #define RT3593_EEPROM_PWR2GHZ_BASE2 0x37 1015 #define RT3593_EEPROM_PWR2GHZ_BASE3 0x3e 1016 #define RT3593_EEPROM_PWR5GHZ_BASE1 0x4b 1017 #define RT3593_EEPROM_PWR5GHZ_BASE2 0x65 1018 #define RT3593_EEPROM_PWR5GHZ_BASE3 0x7f 1019 1020 /* 1021 * EEPROM IQ calibration. 1022 */ 1023 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ 0x130 1024 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131 1025 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133 1026 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ 0x134 1027 #define RT5390_EEPROM_RF_IQ_COMPENSATION_CTL 0x13c 1028 #define RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL 0x13d 1029 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ 0x144 1030 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145 1031 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ 0x146 1032 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ 0x147 1033 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ 0x148 1034 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ 0x149 1035 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ 0x14a 1036 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ 0x14b 1037 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ 0x14c 1038 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ 0x14d 1039 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ 0x14e 1040 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ 0x14f 1041 1042 #define RT2860_RIDX_CCK1 0 1043 #define RT2860_RIDX_CCK11 3 1044 #define RT2860_RIDX_OFDM6 4 1045 #define RT2860_RIDX_MAX 11 1046 static const struct rt2860_rate { 1047 uint8_t rate; 1048 uint8_t mcs; 1049 enum ieee80211_phytype phy; 1050 uint8_t ctl_ridx; 1051 uint16_t sp_ack_dur; 1052 uint16_t lp_ack_dur; 1053 } rt2860_rates[] = { 1054 { 2, 0, IEEE80211_T_DS, 0, 314, 314 }, 1055 { 4, 1, IEEE80211_T_DS, 1, 258, 162 }, 1056 { 11, 2, IEEE80211_T_DS, 2, 223, 127 }, 1057 { 22, 3, IEEE80211_T_DS, 3, 213, 117 }, 1058 { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 }, 1059 { 18, 1, IEEE80211_T_OFDM, 4, 52, 52 }, 1060 { 24, 2, IEEE80211_T_OFDM, 6, 48, 48 }, 1061 { 36, 3, IEEE80211_T_OFDM, 6, 44, 44 }, 1062 { 48, 4, IEEE80211_T_OFDM, 8, 44, 44 }, 1063 { 72, 5, IEEE80211_T_OFDM, 8, 40, 40 }, 1064 { 96, 6, IEEE80211_T_OFDM, 8, 40, 40 }, 1065 { 108, 7, IEEE80211_T_OFDM, 8, 40, 40 } 1066 }; 1067 1068 /* 1069 * Control and status registers access macros. 1070 */ 1071 #define RAL_READ(sc, reg) \ 1072 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1073 1074 #define RAL_WRITE(sc, reg, val) \ 1075 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1076 1077 #define RAL_BARRIER_WRITE(sc) \ 1078 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 1079 BUS_SPACE_BARRIER_WRITE) 1080 1081 #define RAL_BARRIER_READ_WRITE(sc) \ 1082 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 1083 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1084 1085 #define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 1086 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 1087 (datap), (count)) 1088 1089 #define RAL_SET_REGION_4(sc, offset, val, count) \ 1090 bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 1091 (val), (count)) 1092 1093 /* 1094 * EEPROM access macro. 1095 */ 1096 #define RT2860_EEPROM_CTL(sc, val) do { \ 1097 RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \ 1098 RAL_BARRIER_READ_WRITE((sc)); \ 1099 DELAY(RT2860_EEPROM_DELAY); \ 1100 } while (/* CONSTCOND */0) 1101 1102 /* 1103 * Default values for MAC registers; values taken from the reference driver. 1104 */ 1105 #define RT2860_DEF_MAC \ 1106 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1107 { RT2860_BCN_OFFSET1, 0x6f77d0c8 }, \ 1108 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1109 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1110 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1111 { RT2860_RX_FILTR_CFG, 0x00017f97 }, \ 1112 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1113 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1114 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1115 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1116 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1117 { RT2860_MAX_LEN_CFG, 0x00001f00 }, \ 1118 { RT2860_LED_CFG, 0x7f031e46 }, \ 1119 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1120 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1121 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1122 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1123 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1124 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1125 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1126 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1127 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1128 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1129 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1130 { RT2860_MM40_PROT_CFG, 0x03f54084 }, \ 1131 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1132 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1133 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1134 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1135 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1136 { RT2860_PWR_PIN_CFG, 0x00000003 } 1137 1138 /* XXX only a few registers differ from above, try to merge? */ 1139 #define RT2870_DEF_MAC \ 1140 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1141 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1142 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1143 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1144 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1145 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1146 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1147 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1148 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1149 { RT2860_LED_CFG, 0x7f031e46 }, \ 1150 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1151 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1152 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1153 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1154 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1155 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1156 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1157 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1158 { RT2860_PBF_CFG, 0x00f40006 }, \ 1159 { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \ 1160 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1161 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1162 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1163 { RT2860_MM40_PROT_CFG, 0x03f44084 }, \ 1164 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1165 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1166 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1167 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1168 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1169 { RT2860_PWR_PIN_CFG, 0x00000003 } 1170 1171 /* 1172 * Default values for BBP registers; values taken from the reference driver. 1173 */ 1174 #define RT2860_DEF_BBP \ 1175 { 65, 0x2c }, \ 1176 { 66, 0x38 }, \ 1177 { 68, 0x0b }, \ 1178 { 69, 0x12 }, \ 1179 { 70, 0x0a }, \ 1180 { 73, 0x10 }, \ 1181 { 81, 0x37 }, \ 1182 { 82, 0x62 }, \ 1183 { 83, 0x6a }, \ 1184 { 84, 0x99 }, \ 1185 { 86, 0x00 }, \ 1186 { 91, 0x04 }, \ 1187 { 92, 0x00 }, \ 1188 { 103, 0x00 }, \ 1189 { 105, 0x05 }, \ 1190 { 106, 0x35 } 1191 1192 #define RT5390_DEF_BBP \ 1193 { 31, 0x08 }, \ 1194 { 65, 0x2c }, \ 1195 { 66, 0x38 }, \ 1196 { 68, 0x0b }, \ 1197 { 69, 0x12 }, \ 1198 { 70, 0x0a }, \ 1199 { 73, 0x13 }, \ 1200 { 75, 0x46 }, \ 1201 { 76, 0x28 }, \ 1202 { 77, 0x59 }, \ 1203 { 81, 0x37 }, \ 1204 { 82, 0x62 }, \ 1205 { 83, 0x7a }, \ 1206 { 84, 0x19 }, \ 1207 { 86, 0x38 }, \ 1208 { 91, 0x04 }, \ 1209 { 92, 0x02 }, \ 1210 { 103, 0xc0 }, \ 1211 { 104, 0x92 }, \ 1212 { 105, 0x3c }, \ 1213 { 106, 0x03 }, \ 1214 { 128, 0x12 } 1215 1216 #define RT5592_DEF_BBP \ 1217 { 20, 0x06 }, \ 1218 { 31, 0x08 }, \ 1219 { 65, 0x2c }, \ 1220 { 66, 0x38 }, \ 1221 { 68, 0xdd }, \ 1222 { 69, 0x1a }, \ 1223 { 70, 0x05 }, \ 1224 { 73, 0x13 }, \ 1225 { 74, 0x0f }, \ 1226 { 75, 0x4f }, \ 1227 { 76, 0x28 }, \ 1228 { 77, 0x59 }, \ 1229 { 81, 0x37 }, \ 1230 { 82, 0x62 }, \ 1231 { 83, 0x6a }, \ 1232 { 84, 0x9a }, \ 1233 { 86, 0x38 }, \ 1234 { 88, 0x90 }, \ 1235 { 91, 0x04 }, \ 1236 { 92, 0x02 }, \ 1237 { 95, 0x9a }, \ 1238 { 98, 0x12 }, \ 1239 { 103, 0xc0 }, \ 1240 { 104, 0x92 }, \ 1241 { 105, 0x3c }, \ 1242 { 106, 0x35 }, \ 1243 { 128, 0x12 }, \ 1244 { 134, 0xd0 }, \ 1245 { 135, 0xf6 }, \ 1246 { 137, 0x0f } 1247 1248 /* 1249 * Default settings for RF registers; values derived from the reference driver. 1250 */ 1251 #define RT2860_RF2850 \ 1252 { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, \ 1253 { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, \ 1254 { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, \ 1255 { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, \ 1256 { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, \ 1257 { 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 }, \ 1258 { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 }, \ 1259 { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, \ 1260 { 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 }, \ 1261 { 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 }, \ 1262 { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 }, \ 1263 { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, \ 1264 { 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 }, \ 1265 { 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 }, \ 1266 { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 }, \ 1267 { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, \ 1268 { 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 }, \ 1269 { 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 }, \ 1270 { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 }, \ 1271 { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, \ 1272 { 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 }, \ 1273 { 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 }, \ 1274 { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 }, \ 1275 { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, \ 1276 { 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 }, \ 1277 { 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 }, \ 1278 { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }, \ 1279 { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, \ 1280 { 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 }, \ 1281 { 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 }, \ 1282 { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }, \ 1283 { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, \ 1284 { 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 }, \ 1285 { 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 }, \ 1286 { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }, \ 1287 { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, \ 1288 { 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 }, \ 1289 { 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 }, \ 1290 { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }, \ 1291 { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, \ 1292 { 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 }, \ 1293 { 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 }, \ 1294 { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }, \ 1295 { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, \ 1296 { 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 }, \ 1297 { 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 }, \ 1298 { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }, \ 1299 { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, \ 1300 { 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 }, \ 1301 { 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 }, \ 1302 { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 }, \ 1303 { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, \ 1304 { 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 } 1305 1306 #define RT3070_RF3052 \ 1307 { 0xf1, 2, 2 }, \ 1308 { 0xf1, 2, 7 }, \ 1309 { 0xf2, 2, 2 }, \ 1310 { 0xf2, 2, 7 }, \ 1311 { 0xf3, 2, 2 }, \ 1312 { 0xf3, 2, 7 }, \ 1313 { 0xf4, 2, 2 }, \ 1314 { 0xf4, 2, 7 }, \ 1315 { 0xf5, 2, 2 }, \ 1316 { 0xf5, 2, 7 }, \ 1317 { 0xf6, 2, 2 }, \ 1318 { 0xf6, 2, 7 }, \ 1319 { 0xf7, 2, 2 }, \ 1320 { 0xf8, 2, 4 }, \ 1321 { 0x56, 0, 4 }, \ 1322 { 0x56, 0, 6 }, \ 1323 { 0x56, 0, 8 }, \ 1324 { 0x57, 0, 0 }, \ 1325 { 0x57, 0, 2 }, \ 1326 { 0x57, 0, 4 }, \ 1327 { 0x57, 0, 8 }, \ 1328 { 0x57, 0, 10 }, \ 1329 { 0x58, 0, 0 }, \ 1330 { 0x58, 0, 4 }, \ 1331 { 0x58, 0, 6 }, \ 1332 { 0x58, 0, 8 }, \ 1333 { 0x5b, 0, 8 }, \ 1334 { 0x5b, 0, 10 }, \ 1335 { 0x5c, 0, 0 }, \ 1336 { 0x5c, 0, 4 }, \ 1337 { 0x5c, 0, 6 }, \ 1338 { 0x5c, 0, 8 }, \ 1339 { 0x5d, 0, 0 }, \ 1340 { 0x5d, 0, 2 }, \ 1341 { 0x5d, 0, 4 }, \ 1342 { 0x5d, 0, 8 }, \ 1343 { 0x5d, 0, 10 }, \ 1344 { 0x5e, 0, 0 }, \ 1345 { 0x5e, 0, 4 }, \ 1346 { 0x5e, 0, 6 }, \ 1347 { 0x5e, 0, 8 }, \ 1348 { 0x5f, 0, 0 }, \ 1349 { 0x5f, 0, 9 }, \ 1350 { 0x5f, 0, 11 }, \ 1351 { 0x60, 0, 1 }, \ 1352 { 0x60, 0, 5 }, \ 1353 { 0x60, 0, 7 }, \ 1354 { 0x60, 0, 9 }, \ 1355 { 0x61, 0, 1 }, \ 1356 { 0x61, 0, 3 }, \ 1357 { 0x61, 0, 5 }, \ 1358 { 0x61, 0, 7 }, \ 1359 { 0x61, 0, 9 } 1360 1361 #define RT5592_RF5592_20MHZ \ 1362 { 0x1e2, 4, 10, 3 }, \ 1363 { 0x1e3, 4, 10, 3 }, \ 1364 { 0x1e4, 4, 10, 3 }, \ 1365 { 0x1e5, 4, 10, 3 }, \ 1366 { 0x1e6, 4, 10, 3 }, \ 1367 { 0x1e7, 4, 10, 3 }, \ 1368 { 0x1e8, 4, 10, 3 }, \ 1369 { 0x1e9, 4, 10, 3 }, \ 1370 { 0x1ea, 4, 10, 3 }, \ 1371 { 0x1eb, 4, 10, 3 }, \ 1372 { 0x1ec, 4, 10, 3 }, \ 1373 { 0x1ed, 4, 10, 3 }, \ 1374 { 0x1ee, 4, 10, 3 }, \ 1375 { 0x1f0, 8, 10, 3 }, \ 1376 { 0xac, 8, 12, 1 }, \ 1377 { 0xad, 0, 12, 1 }, \ 1378 { 0xad, 4, 12, 1 }, \ 1379 { 0xae, 0, 12, 1 }, \ 1380 { 0xae, 4, 12, 1 }, \ 1381 { 0xae, 8, 12, 1 }, \ 1382 { 0xaf, 4, 12, 1 }, \ 1383 { 0xaf, 8, 12, 1 }, \ 1384 { 0xb0, 0, 12, 1 }, \ 1385 { 0xb0, 8, 12, 1 }, \ 1386 { 0xb1, 0, 12, 1 }, \ 1387 { 0xb1, 4, 12, 1 }, \ 1388 { 0xb7, 4, 12, 1 }, \ 1389 { 0xb7, 8, 12, 1 }, \ 1390 { 0xb8, 0, 12, 1 }, \ 1391 { 0xb8, 8, 12, 1 }, \ 1392 { 0xb9, 0, 12, 1 }, \ 1393 { 0xb9, 4, 12, 1 }, \ 1394 { 0xba, 0, 12, 1 }, \ 1395 { 0xba, 4, 12, 1 }, \ 1396 { 0xba, 8, 12, 1 }, \ 1397 { 0xbb, 4, 12, 1 }, \ 1398 { 0xbb, 8, 12, 1 }, \ 1399 { 0xbc, 0, 12, 1 }, \ 1400 { 0xbc, 8, 12, 1 }, \ 1401 { 0xbd, 0, 12, 1 }, \ 1402 { 0xbd, 4, 12, 1 }, \ 1403 { 0xbe, 0, 12, 1 }, \ 1404 { 0xbf, 6, 12, 1 }, \ 1405 { 0xbf, 10, 12, 1 }, \ 1406 { 0xc0, 2, 12, 1 }, \ 1407 { 0xc0, 10, 12, 1 }, \ 1408 { 0xc1, 2, 12, 1 }, \ 1409 { 0xc1, 6, 12, 1 }, \ 1410 { 0xc2, 2, 12, 1 }, \ 1411 { 0xa4, 0, 12, 1 }, \ 1412 { 0xa4, 4, 12, 1 }, \ 1413 { 0xa5, 8, 12, 1 }, \ 1414 { 0xa6, 0, 12, 1 } 1415 1416 #define RT5592_RF5592_40MHZ \ 1417 { 0xf1, 2, 10, 3 }, \ 1418 { 0xf1, 7, 10, 3 }, \ 1419 { 0xf2, 2, 10, 3 }, \ 1420 { 0xf2, 7, 10, 3 }, \ 1421 { 0xf3, 2, 10, 3 }, \ 1422 { 0xf3, 7, 10, 3 }, \ 1423 { 0xf4, 2, 10, 3 }, \ 1424 { 0xf4, 7, 10, 3 }, \ 1425 { 0xf5, 2, 10, 3 }, \ 1426 { 0xf5, 7, 10, 3 }, \ 1427 { 0xf6, 2, 10, 3 }, \ 1428 { 0xf6, 7, 10, 3 }, \ 1429 { 0xf7, 2, 10, 3 }, \ 1430 { 0xf8, 4, 10, 3 }, \ 1431 { 0x56, 4, 12, 1 }, \ 1432 { 0x56, 6, 12, 1 }, \ 1433 { 0x56, 8, 12, 1 }, \ 1434 { 0x57, 0, 12, 1 }, \ 1435 { 0x57, 2, 12, 1 }, \ 1436 { 0x57, 4, 12, 1 }, \ 1437 { 0x57, 8, 12, 1 }, \ 1438 { 0x57, 10, 12, 1 }, \ 1439 { 0x58, 0, 12, 1 }, \ 1440 { 0x58, 4, 12, 1 }, \ 1441 { 0x58, 6, 12, 1 }, \ 1442 { 0x58, 8, 12, 1 }, \ 1443 { 0x5b, 8, 12, 1 }, \ 1444 { 0x5b, 10, 12, 1 }, \ 1445 { 0x5c, 0, 12, 1 }, \ 1446 { 0x5c, 4, 12, 1 }, \ 1447 { 0x5c, 6, 12, 1 }, \ 1448 { 0x5c, 8, 12, 1 }, \ 1449 { 0x5d, 0, 12, 1 }, \ 1450 { 0x5d, 2, 12, 1 }, \ 1451 { 0x5d, 4, 12, 1 }, \ 1452 { 0x5d, 8, 12, 1 }, \ 1453 { 0x5d, 10, 12, 1 }, \ 1454 { 0x5e, 0, 12, 1 }, \ 1455 { 0x5e, 4, 12, 1 }, \ 1456 { 0x5e, 6, 12, 1 }, \ 1457 { 0x5e, 8, 12, 1 }, \ 1458 { 0x5f, 0, 12, 1 }, \ 1459 { 0x5f, 9, 12, 1 }, \ 1460 { 0x5f, 11, 12, 1 }, \ 1461 { 0x60, 1, 12, 1 }, \ 1462 { 0x60, 5, 12, 1 }, \ 1463 { 0x60, 7, 12, 1 }, \ 1464 { 0x60, 9, 12, 1 }, \ 1465 { 0x61, 1, 12, 1 }, \ 1466 { 0x52, 0, 12, 1 }, \ 1467 { 0x52, 4, 12, 1 }, \ 1468 { 0x52, 8, 12, 1 }, \ 1469 { 0x53, 0, 12, 1 } 1470 1471 #define RT3070_DEF_RF \ 1472 { 4, 0x40 }, \ 1473 { 5, 0x03 }, \ 1474 { 6, 0x02 }, \ 1475 { 7, 0x60 }, \ 1476 { 9, 0x0f }, \ 1477 { 10, 0x41 }, \ 1478 { 11, 0x21 }, \ 1479 { 12, 0x7b }, \ 1480 { 14, 0x90 }, \ 1481 { 15, 0x58 }, \ 1482 { 16, 0xb3 }, \ 1483 { 17, 0x92 }, \ 1484 { 18, 0x2c }, \ 1485 { 19, 0x02 }, \ 1486 { 20, 0xba }, \ 1487 { 21, 0xdb }, \ 1488 { 24, 0x16 }, \ 1489 { 25, 0x03 }, \ 1490 { 29, 0x1f } 1491 1492 #define RT5390_DEF_RF \ 1493 { 1, 0x0f }, \ 1494 { 2, 0x80 }, \ 1495 { 3, 0x88 }, \ 1496 { 5, 0x10 }, \ 1497 { 6, 0xe0 }, \ 1498 { 7, 0x00 }, \ 1499 { 10, 0x53 }, \ 1500 { 11, 0x4a }, \ 1501 { 12, 0x46 }, \ 1502 { 13, 0x9f }, \ 1503 { 14, 0x00 }, \ 1504 { 15, 0x00 }, \ 1505 { 16, 0x00 }, \ 1506 { 18, 0x03 }, \ 1507 { 19, 0x00 }, \ 1508 { 20, 0x00 }, \ 1509 { 21, 0x00 }, \ 1510 { 22, 0x20 }, \ 1511 { 23, 0x00 }, \ 1512 { 24, 0x00 }, \ 1513 { 25, 0x80 }, \ 1514 { 26, 0x00 }, \ 1515 { 27, 0x09 }, \ 1516 { 28, 0x00 }, \ 1517 { 29, 0x10 }, \ 1518 { 30, 0x10 }, \ 1519 { 31, 0x80 }, \ 1520 { 32, 0x80 }, \ 1521 { 33, 0x00 }, \ 1522 { 34, 0x07 }, \ 1523 { 35, 0x12 }, \ 1524 { 36, 0x00 }, \ 1525 { 37, 0x08 }, \ 1526 { 38, 0x85 }, \ 1527 { 39, 0x1b }, \ 1528 { 40, 0x0b }, \ 1529 { 41, 0xbb }, \ 1530 { 42, 0xd2 }, \ 1531 { 43, 0x9a }, \ 1532 { 44, 0x0e }, \ 1533 { 45, 0xa2 }, \ 1534 { 46, 0x73 }, \ 1535 { 47, 0x00 }, \ 1536 { 48, 0x10 }, \ 1537 { 49, 0x94 }, \ 1538 { 52, 0x38 }, \ 1539 { 53, 0x00 }, \ 1540 { 54, 0x78 }, \ 1541 { 55, 0x23 }, \ 1542 { 56, 0x22 }, \ 1543 { 57, 0x80 }, \ 1544 { 58, 0x7f }, \ 1545 { 59, 0x07 }, \ 1546 { 60, 0x45 }, \ 1547 { 61, 0xd1 }, \ 1548 { 62, 0x00 }, \ 1549 { 63, 0x00 } 1550 1551 #define RT5392_DEF_RF \ 1552 { 1, 0x17 }, \ 1553 { 2, 0x80 }, \ 1554 { 3, 0x88 }, \ 1555 { 5, 0x10 }, \ 1556 { 6, 0xe0 }, \ 1557 { 7, 0x00 }, \ 1558 { 10, 0x53 }, \ 1559 { 11, 0x4a }, \ 1560 { 12, 0x46 }, \ 1561 { 13, 0x9f }, \ 1562 { 14, 0x00 }, \ 1563 { 15, 0x00 }, \ 1564 { 16, 0x00 }, \ 1565 { 18, 0x03 }, \ 1566 { 19, 0x4d }, \ 1567 { 20, 0x00 }, \ 1568 { 21, 0x8d }, \ 1569 { 22, 0x20 }, \ 1570 { 23, 0x0b }, \ 1571 { 24, 0x44 }, \ 1572 { 25, 0x80 }, \ 1573 { 26, 0x82 }, \ 1574 { 27, 0x09 }, \ 1575 { 28, 0x00 }, \ 1576 { 29, 0x10 }, \ 1577 { 30, 0x10 }, \ 1578 { 31, 0x80 }, \ 1579 { 32, 0x80 }, \ 1580 { 33, 0xc0 }, \ 1581 { 34, 0x07 }, \ 1582 { 35, 0x12 }, \ 1583 { 36, 0x00 }, \ 1584 { 37, 0x08 }, \ 1585 { 38, 0x89 }, \ 1586 { 39, 0x1b }, \ 1587 { 40, 0x0f }, \ 1588 { 41, 0xbb }, \ 1589 { 42, 0xd5 }, \ 1590 { 43, 0x9b }, \ 1591 { 44, 0x0e }, \ 1592 { 45, 0xa2 }, \ 1593 { 46, 0x73 }, \ 1594 { 47, 0x0c }, \ 1595 { 48, 0x10 }, \ 1596 { 49, 0x94 }, \ 1597 { 50, 0x94 }, \ 1598 { 51, 0x3a }, \ 1599 { 52, 0x48 }, \ 1600 { 53, 0x44 }, \ 1601 { 54, 0x38 }, \ 1602 { 55, 0x43 }, \ 1603 { 56, 0xa1 }, \ 1604 { 57, 0x00 }, \ 1605 { 58, 0x39 }, \ 1606 { 59, 0x07 }, \ 1607 { 60, 0x45 }, \ 1608 { 61, 0x91 }, \ 1609 { 62, 0x39 }, \ 1610 { 63, 0x00 } 1611 1612 #define RT3572_DEF_RF \ 1613 { 0, 0x70 }, \ 1614 { 1, 0x81 }, \ 1615 { 2, 0xf1 }, \ 1616 { 3, 0x02 }, \ 1617 { 4, 0x4c }, \ 1618 { 5, 0x05 }, \ 1619 { 6, 0x4a }, \ 1620 { 7, 0xd8 }, \ 1621 { 9, 0xc3 }, \ 1622 { 10, 0xf1 }, \ 1623 { 11, 0xb9 }, \ 1624 { 12, 0x70 }, \ 1625 { 13, 0x65 }, \ 1626 { 14, 0xa0 }, \ 1627 { 15, 0x53 }, \ 1628 { 16, 0x4c }, \ 1629 { 17, 0x23 }, \ 1630 { 18, 0xac }, \ 1631 { 19, 0x93 }, \ 1632 { 20, 0xb3 }, \ 1633 { 21, 0xd0 }, \ 1634 { 22, 0x00 }, \ 1635 { 23, 0x3c }, \ 1636 { 24, 0x16 }, \ 1637 { 25, 0x15 }, \ 1638 { 26, 0x85 }, \ 1639 { 27, 0x00 }, \ 1640 { 28, 0x00 }, \ 1641 { 29, 0x9b }, \ 1642 { 30, 0x09 }, \ 1643 { 31, 0x10 } 1644 1645 #define RT3593_DEF_RF \ 1646 { 1, 0x03 }, \ 1647 { 3, 0x80 }, \ 1648 { 5, 0x00 }, \ 1649 { 6, 0x40 }, \ 1650 { 8, 0xf1 }, \ 1651 { 9, 0x02 }, \ 1652 { 10, 0xd3 }, \ 1653 { 11, 0x40 }, \ 1654 { 12, 0x4e }, \ 1655 { 13, 0x12 }, \ 1656 { 18, 0x40 }, \ 1657 { 22, 0x20 }, \ 1658 { 30, 0x10 }, \ 1659 { 31, 0x80 }, \ 1660 { 32, 0x78 }, \ 1661 { 33, 0x3b }, \ 1662 { 34, 0x3c }, \ 1663 { 35, 0xe0 }, \ 1664 { 38, 0x86 }, \ 1665 { 39, 0x23 }, \ 1666 { 44, 0xd3 }, \ 1667 { 45, 0xbb }, \ 1668 { 46, 0x60 }, \ 1669 { 49, 0x81 }, \ 1670 { 50, 0x86 }, \ 1671 { 51, 0x75 }, \ 1672 { 52, 0x45 }, \ 1673 { 53, 0x18 }, \ 1674 { 54, 0x18 }, \ 1675 { 55, 0x18 }, \ 1676 { 56, 0xdb }, \ 1677 { 57, 0x6e } 1678 1679 #define RT5592_DEF_RF \ 1680 { 1, 0x3f }, \ 1681 { 3, 0x08 }, \ 1682 { 5, 0x10 }, \ 1683 { 6, 0xe4 }, \ 1684 { 7, 0x00 }, \ 1685 { 14, 0x00 }, \ 1686 { 15, 0x00 }, \ 1687 { 16, 0x00 }, \ 1688 { 18, 0x03 }, \ 1689 { 19, 0x4d }, \ 1690 { 20, 0x10 }, \ 1691 { 21, 0x8d }, \ 1692 { 26, 0x82 }, \ 1693 { 28, 0x00 }, \ 1694 { 29, 0x10 }, \ 1695 { 33, 0xc0 }, \ 1696 { 34, 0x07 }, \ 1697 { 35, 0x12 }, \ 1698 { 47, 0x0c }, \ 1699 { 53, 0x22 }, \ 1700 { 63, 0x07 } 1701 1702 #define RT5592_2GHZ_DEF_RF \ 1703 { 10, 0x90 }, \ 1704 { 11, 0x4a }, \ 1705 { 12, 0x52 }, \ 1706 { 13, 0x42 }, \ 1707 { 22, 0x40 }, \ 1708 { 24, 0x4a }, \ 1709 { 25, 0x80 }, \ 1710 { 27, 0x42 }, \ 1711 { 36, 0x80 }, \ 1712 { 37, 0x08 }, \ 1713 { 38, 0x89 }, \ 1714 { 39, 0x1b }, \ 1715 { 40, 0x0d }, \ 1716 { 41, 0x9b }, \ 1717 { 42, 0xd5 }, \ 1718 { 43, 0x72 }, \ 1719 { 44, 0x0e }, \ 1720 { 45, 0xa2 }, \ 1721 { 46, 0x6b }, \ 1722 { 48, 0x10 }, \ 1723 { 51, 0x3e }, \ 1724 { 52, 0x48 }, \ 1725 { 54, 0x38 }, \ 1726 { 56, 0xa1 }, \ 1727 { 57, 0x00 }, \ 1728 { 58, 0x39 }, \ 1729 { 60, 0x45 }, \ 1730 { 61, 0x91 }, \ 1731 { 62, 0x39 } 1732 1733 #define RT5592_5GHZ_DEF_RF \ 1734 { 10, 0x97 }, \ 1735 { 11, 0x40 }, \ 1736 { 25, 0xbf }, \ 1737 { 27, 0x42 }, \ 1738 { 36, 0x00 }, \ 1739 { 37, 0x04 }, \ 1740 { 38, 0x85 }, \ 1741 { 40, 0x42 }, \ 1742 { 41, 0xbb }, \ 1743 { 42, 0xd7 }, \ 1744 { 45, 0x41 }, \ 1745 { 48, 0x00 }, \ 1746 { 57, 0x77 }, \ 1747 { 60, 0x05 }, \ 1748 { 61, 0x01 } 1749 1750 #define RT5592_CHAN_5GHZ \ 1751 { 36, 64, 12, 0x2e }, \ 1752 { 100, 165, 12, 0x0e }, \ 1753 { 36, 64, 13, 0x22 }, \ 1754 { 100, 165, 13, 0x42 }, \ 1755 { 36, 64, 22, 0x60 }, \ 1756 { 100, 165, 22, 0x40 }, \ 1757 { 36, 64, 23, 0x7f }, \ 1758 { 100, 153, 23, 0x3c }, \ 1759 { 155, 165, 23, 0x38 }, \ 1760 { 36, 50, 24, 0x09 }, \ 1761 { 52, 64, 24, 0x07 }, \ 1762 { 100, 153, 24, 0x06 }, \ 1763 { 155, 165, 24, 0x05 }, \ 1764 { 36, 64, 39, 0x1c }, \ 1765 { 100, 138, 39, 0x1a }, \ 1766 { 140, 165, 39, 0x18 }, \ 1767 { 36, 64, 43, 0x5b }, \ 1768 { 100, 138, 43, 0x3b }, \ 1769 { 140, 165, 43, 0x1b }, \ 1770 { 36, 64, 44, 0x40 }, \ 1771 { 100, 138, 44, 0x20 }, \ 1772 { 140, 165, 44, 0x10 }, \ 1773 { 36, 64, 46, 0x00 }, \ 1774 { 100, 138, 46, 0x18 }, \ 1775 { 140, 165, 46, 0x08 }, \ 1776 { 36, 64, 51, 0xfe }, \ 1777 { 100, 124, 51, 0xfc }, \ 1778 { 126, 165, 51, 0xec }, \ 1779 { 36, 64, 52, 0x0c }, \ 1780 { 100, 138, 52, 0x06 }, \ 1781 { 140, 165, 52, 0x06 }, \ 1782 { 36, 64, 54, 0xf8 }, \ 1783 { 100, 165, 54, 0xeb }, \ 1784 { 36, 50, 55, 0x06 }, \ 1785 { 52, 64, 55, 0x04 }, \ 1786 { 100, 138, 55, 0x01 }, \ 1787 { 140, 165, 55, 0x00 }, \ 1788 { 36, 50, 56, 0xd3 }, \ 1789 { 52, 128, 56, 0xbb }, \ 1790 { 130, 165, 56, 0xab }, \ 1791 { 36, 64, 58, 0x15 }, \ 1792 { 100, 116, 58, 0x1d }, \ 1793 { 118, 165, 58, 0x15 }, \ 1794 { 36, 64, 59, 0x7f }, \ 1795 { 100, 138, 59, 0x3f }, \ 1796 { 140, 165, 59, 0x7c }, \ 1797 { 36, 64, 62, 0x15 }, \ 1798 { 100, 116, 62, 0x1d }, \ 1799 { 118, 165, 62, 0x15 } 1800
Indexes created Sun Oct 19 16:10:00 GMT 2025