rtl8169.c revision 1.125
1 /* $NetBSD: rtl8169.c,v 1.125 2009/09/02 15:11:13 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.125 2009/09/02 15:11:13 tsutsui Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul (at) windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 #include "bpfilter.h" 115 116 #include <sys/param.h> 117 #include <sys/endian.h> 118 #include <sys/systm.h> 119 #include <sys/sockio.h> 120 #include <sys/mbuf.h> 121 #include <sys/malloc.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/device.h> 125 126 #include <net/if.h> 127 #include <net/if_arp.h> 128 #include <net/if_dl.h> 129 #include <net/if_ether.h> 130 #include <net/if_media.h> 131 #include <net/if_vlanvar.h> 132 133 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 134 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 135 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 136 137 #if NBPFILTER > 0 138 #include <net/bpf.h> 139 #endif 140 141 #include <sys/bus.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/ic/rtl81x9reg.h> 147 #include <dev/ic/rtl81x9var.h> 148 149 #include <dev/ic/rtl8169var.h> 150 151 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 152 153 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 154 static int re_rx_list_init(struct rtk_softc *); 155 static int re_tx_list_init(struct rtk_softc *); 156 static void re_rxeof(struct rtk_softc *); 157 static void re_txeof(struct rtk_softc *); 158 static void re_tick(void *); 159 static void re_start(struct ifnet *); 160 static int re_ioctl(struct ifnet *, u_long, void *); 161 static int re_init(struct ifnet *); 162 static void re_stop(struct ifnet *, int); 163 static void re_watchdog(struct ifnet *); 164 165 static int re_enable(struct rtk_softc *); 166 static void re_disable(struct rtk_softc *); 167 168 static int re_gmii_readreg(device_t, int, int); 169 static void re_gmii_writereg(device_t, int, int, int); 170 171 static int re_miibus_readreg(device_t, int, int); 172 static void re_miibus_writereg(device_t, int, int, int); 173 static void re_miibus_statchg(device_t); 174 175 static void re_reset(struct rtk_softc *); 176 177 static inline void 178 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 179 { 180 181 d->re_bufaddr_lo = htole32((uint32_t)addr); 182 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 183 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32); 184 else 185 d->re_bufaddr_hi = 0; 186 } 187 188 static int 189 re_gmii_readreg(device_t dev, int phy, int reg) 190 { 191 struct rtk_softc *sc = device_private(dev); 192 uint32_t rval; 193 int i; 194 195 if (phy != 7) 196 return 0; 197 198 /* Let the rgephy driver read the GMEDIASTAT register */ 199 200 if (reg == RTK_GMEDIASTAT) { 201 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 202 return rval; 203 } 204 205 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 206 DELAY(1000); 207 208 for (i = 0; i < RTK_TIMEOUT; i++) { 209 rval = CSR_READ_4(sc, RTK_PHYAR); 210 if (rval & RTK_PHYAR_BUSY) 211 break; 212 DELAY(100); 213 } 214 215 if (i == RTK_TIMEOUT) { 216 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 217 return 0; 218 } 219 220 return rval & RTK_PHYAR_PHYDATA; 221 } 222 223 static void 224 re_gmii_writereg(device_t dev, int phy, int reg, int data) 225 { 226 struct rtk_softc *sc = device_private(dev); 227 uint32_t rval; 228 int i; 229 230 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 231 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 232 DELAY(1000); 233 234 for (i = 0; i < RTK_TIMEOUT; i++) { 235 rval = CSR_READ_4(sc, RTK_PHYAR); 236 if (!(rval & RTK_PHYAR_BUSY)) 237 break; 238 DELAY(100); 239 } 240 241 if (i == RTK_TIMEOUT) { 242 printf("%s: PHY write reg %x <- %x failed\n", 243 device_xname(sc->sc_dev), reg, data); 244 } 245 } 246 247 static int 248 re_miibus_readreg(device_t dev, int phy, int reg) 249 { 250 struct rtk_softc *sc = device_private(dev); 251 uint16_t rval = 0; 252 uint16_t re8139_reg = 0; 253 int s; 254 255 s = splnet(); 256 257 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 258 rval = re_gmii_readreg(dev, phy, reg); 259 splx(s); 260 return rval; 261 } 262 263 /* Pretend the internal PHY is only at address 0 */ 264 if (phy) { 265 splx(s); 266 return 0; 267 } 268 switch (reg) { 269 case MII_BMCR: 270 re8139_reg = RTK_BMCR; 271 break; 272 case MII_BMSR: 273 re8139_reg = RTK_BMSR; 274 break; 275 case MII_ANAR: 276 re8139_reg = RTK_ANAR; 277 break; 278 case MII_ANER: 279 re8139_reg = RTK_ANER; 280 break; 281 case MII_ANLPAR: 282 re8139_reg = RTK_LPAR; 283 break; 284 case MII_PHYIDR1: 285 case MII_PHYIDR2: 286 splx(s); 287 return 0; 288 /* 289 * Allow the rlphy driver to read the media status 290 * register. If we have a link partner which does not 291 * support NWAY, this is the register which will tell 292 * us the results of parallel detection. 293 */ 294 case RTK_MEDIASTAT: 295 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 296 splx(s); 297 return rval; 298 default: 299 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 300 splx(s); 301 return 0; 302 } 303 rval = CSR_READ_2(sc, re8139_reg); 304 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 305 /* 8139C+ has different bit layout. */ 306 rval &= ~(BMCR_LOOP | BMCR_ISO); 307 } 308 splx(s); 309 return rval; 310 } 311 312 static void 313 re_miibus_writereg(device_t dev, int phy, int reg, int data) 314 { 315 struct rtk_softc *sc = device_private(dev); 316 uint16_t re8139_reg = 0; 317 int s; 318 319 s = splnet(); 320 321 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 322 re_gmii_writereg(dev, phy, reg, data); 323 splx(s); 324 return; 325 } 326 327 /* Pretend the internal PHY is only at address 0 */ 328 if (phy) { 329 splx(s); 330 return; 331 } 332 switch (reg) { 333 case MII_BMCR: 334 re8139_reg = RTK_BMCR; 335 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 336 /* 8139C+ has different bit layout. */ 337 data &= ~(BMCR_LOOP | BMCR_ISO); 338 } 339 break; 340 case MII_BMSR: 341 re8139_reg = RTK_BMSR; 342 break; 343 case MII_ANAR: 344 re8139_reg = RTK_ANAR; 345 break; 346 case MII_ANER: 347 re8139_reg = RTK_ANER; 348 break; 349 case MII_ANLPAR: 350 re8139_reg = RTK_LPAR; 351 break; 352 case MII_PHYIDR1: 353 case MII_PHYIDR2: 354 splx(s); 355 return; 356 break; 357 default: 358 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 359 splx(s); 360 return; 361 } 362 CSR_WRITE_2(sc, re8139_reg, data); 363 splx(s); 364 return; 365 } 366 367 static void 368 re_miibus_statchg(device_t dev) 369 { 370 371 return; 372 } 373 374 static void 375 re_reset(struct rtk_softc *sc) 376 { 377 int i; 378 379 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 380 381 for (i = 0; i < RTK_TIMEOUT; i++) { 382 DELAY(10); 383 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 384 break; 385 } 386 if (i == RTK_TIMEOUT) 387 printf("%s: reset never completed!\n", 388 device_xname(sc->sc_dev)); 389 390 /* 391 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 392 * but also says "Rtl8169s sigle chip detected". 393 */ 394 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 395 CSR_WRITE_1(sc, RTK_LDPS, 1); 396 397 } 398 399 /* 400 * The following routine is designed to test for a defect on some 401 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 402 * lines connected to the bus, however for a 32-bit only card, they 403 * should be pulled high. The result of this defect is that the 404 * NIC will not work right if you plug it into a 64-bit slot: DMA 405 * operations will be done with 64-bit transfers, which will fail 406 * because the 64-bit data lines aren't connected. 407 * 408 * There's no way to work around this (short of talking a soldering 409 * iron to the board), however we can detect it. The method we use 410 * here is to put the NIC into digital loopback mode, set the receiver 411 * to promiscuous mode, and then try to send a frame. We then compare 412 * the frame data we sent to what was received. If the data matches, 413 * then the NIC is working correctly, otherwise we know the user has 414 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 415 * slot. In the latter case, there's no way the NIC can work correctly, 416 * so we print out a message on the console and abort the device attach. 417 */ 418 419 int 420 re_diag(struct rtk_softc *sc) 421 { 422 struct ifnet *ifp = &sc->ethercom.ec_if; 423 struct mbuf *m0; 424 struct ether_header *eh; 425 struct re_rxsoft *rxs; 426 struct re_desc *cur_rx; 427 bus_dmamap_t dmamap; 428 uint16_t status; 429 uint32_t rxstat; 430 int total_len, i, s, error = 0; 431 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 432 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 433 434 /* Allocate a single mbuf */ 435 436 MGETHDR(m0, M_DONTWAIT, MT_DATA); 437 if (m0 == NULL) 438 return ENOBUFS; 439 440 /* 441 * Initialize the NIC in test mode. This sets the chip up 442 * so that it can send and receive frames, but performs the 443 * following special functions: 444 * - Puts receiver in promiscuous mode 445 * - Enables digital loopback mode 446 * - Leaves interrupts turned off 447 */ 448 449 ifp->if_flags |= IFF_PROMISC; 450 sc->re_testmode = 1; 451 re_init(ifp); 452 re_stop(ifp, 0); 453 DELAY(100000); 454 re_init(ifp); 455 456 /* Put some data in the mbuf */ 457 458 eh = mtod(m0, struct ether_header *); 459 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN); 460 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN); 461 eh->ether_type = htons(ETHERTYPE_IP); 462 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 463 464 /* 465 * Queue the packet, start transmission. 466 */ 467 468 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 469 s = splnet(); 470 IF_ENQUEUE(&ifp->if_snd, m0); 471 re_start(ifp); 472 splx(s); 473 m0 = NULL; 474 475 /* Wait for it to propagate through the chip */ 476 477 DELAY(100000); 478 for (i = 0; i < RTK_TIMEOUT; i++) { 479 status = CSR_READ_2(sc, RTK_ISR); 480 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 481 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 482 break; 483 DELAY(10); 484 } 485 if (i == RTK_TIMEOUT) { 486 aprint_error_dev(sc->sc_dev, 487 "diagnostic failed, failed to receive packet " 488 "in loopback mode\n"); 489 error = EIO; 490 goto done; 491 } 492 493 /* 494 * The packet should have been dumped into the first 495 * entry in the RX DMA ring. Grab it from there. 496 */ 497 498 rxs = &sc->re_ldata.re_rxsoft[0]; 499 dmamap = rxs->rxs_dmamap; 500 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 501 BUS_DMASYNC_POSTREAD); 502 bus_dmamap_unload(sc->sc_dmat, dmamap); 503 504 m0 = rxs->rxs_mbuf; 505 rxs->rxs_mbuf = NULL; 506 eh = mtod(m0, struct ether_header *); 507 508 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 509 cur_rx = &sc->re_ldata.re_rx_list[0]; 510 rxstat = le32toh(cur_rx->re_cmdstat); 511 total_len = rxstat & sc->re_rxlenmask; 512 513 if (total_len != ETHER_MIN_LEN) { 514 aprint_error_dev(sc->sc_dev, 515 "diagnostic failed, received short packet\n"); 516 error = EIO; 517 goto done; 518 } 519 520 /* Test that the received packet data matches what we sent. */ 521 522 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 523 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 524 ntohs(eh->ether_type) != ETHERTYPE_IP) { 525 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 526 "expected TX data: %s/%s/0x%x\n" 527 "received RX data: %s/%s/0x%x\n" 528 "You may have a defective 32-bit NIC plugged " 529 "into a 64-bit PCI slot.\n" 530 "Please re-install the NIC in a 32-bit slot " 531 "for proper operation.\n" 532 "Read the re(4) man page for more details.\n" , 533 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 534 ether_sprintf(eh->ether_dhost), 535 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 536 error = EIO; 537 } 538 539 done: 540 /* Turn interface off, release resources */ 541 542 sc->re_testmode = 0; 543 ifp->if_flags &= ~IFF_PROMISC; 544 re_stop(ifp, 0); 545 if (m0 != NULL) 546 m_freem(m0); 547 548 return error; 549 } 550 551 552 /* 553 * Attach the interface. Allocate softc structures, do ifmedia 554 * setup and ethernet/BPF attach. 555 */ 556 void 557 re_attach(struct rtk_softc *sc) 558 { 559 uint8_t eaddr[ETHER_ADDR_LEN]; 560 uint16_t val; 561 struct ifnet *ifp; 562 int error = 0, i, addr_len; 563 564 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 565 uint32_t hwrev; 566 567 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 568 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 569 switch (hwrev) { 570 case RTK_HWREV_8169: 571 sc->sc_quirk |= RTKQ_8169NONS; 572 break; 573 case RTK_HWREV_8169S: 574 case RTK_HWREV_8110S: 575 case RTK_HWREV_8169_8110SB: 576 case RTK_HWREV_8169_8110SC: 577 sc->sc_quirk |= RTKQ_MACLDPS; 578 break; 579 case RTK_HWREV_8168_SPIN1: 580 case RTK_HWREV_8168_SPIN2: 581 case RTK_HWREV_8168_SPIN3: 582 sc->sc_quirk |= RTKQ_MACSTAT; 583 break; 584 case RTK_HWREV_8168C: 585 case RTK_HWREV_8168C_SPIN2: 586 case RTK_HWREV_8168CP: 587 case RTK_HWREV_8168D: 588 case RTK_HWREV_8168DP: 589 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 590 RTKQ_MACSTAT | RTKQ_CMDSTOP; 591 /* 592 * From FreeBSD driver: 593 * 594 * These (8168/8111) controllers support jumbo frame 595 * but it seems that enabling it requires touching 596 * additional magic registers. Depending on MAC 597 * revisions some controllers need to disable 598 * checksum offload. So disable jumbo frame until 599 * I have better idea what it really requires to 600 * make it support. 601 * RTL8168C/CP : supports up to 6KB jumbo frame. 602 * RTL8111C/CP : supports up to 9KB jumbo frame. 603 */ 604 sc->sc_quirk |= RTKQ_NOJUMBO; 605 break; 606 case RTK_HWREV_8100E: 607 case RTK_HWREV_8100E_SPIN2: 608 case RTK_HWREV_8101E: 609 sc->sc_quirk |= RTKQ_NOJUMBO; 610 break; 611 case RTK_HWREV_8102E: 612 case RTK_HWREV_8102EL: 613 case RTK_HWREV_8103E: 614 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 615 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 616 break; 617 default: 618 aprint_normal_dev(sc->sc_dev, 619 "Unknown revision (0x%08x)\n", hwrev); 620 /* assume the latest features */ 621 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 622 sc->sc_quirk |= RTKQ_NOJUMBO; 623 } 624 625 /* Set RX length mask */ 626 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 627 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 628 } else { 629 sc->sc_quirk |= RTKQ_NOJUMBO; 630 631 /* Set RX length mask */ 632 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 633 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 634 } 635 636 /* Reset the adapter. */ 637 re_reset(sc); 638 639 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 640 /* 641 * Get station address from ID registers. 642 */ 643 for (i = 0; i < ETHER_ADDR_LEN; i++) 644 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 645 } else { 646 /* 647 * Get station address from the EEPROM. 648 */ 649 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 650 addr_len = RTK_EEADDR_LEN1; 651 else 652 addr_len = RTK_EEADDR_LEN0; 653 654 /* 655 * Get station address from the EEPROM. 656 */ 657 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 658 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 659 eaddr[(i * 2) + 0] = val & 0xff; 660 eaddr[(i * 2) + 1] = val >> 8; 661 } 662 } 663 664 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 665 ether_sprintf(eaddr)); 666 667 if (sc->re_ldata.re_tx_desc_cnt > 668 PAGE_SIZE / sizeof(struct re_desc)) { 669 sc->re_ldata.re_tx_desc_cnt = 670 PAGE_SIZE / sizeof(struct re_desc); 671 } 672 673 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 674 sc->re_ldata.re_tx_desc_cnt); 675 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 676 677 /* Allocate DMA'able memory for the TX ring */ 678 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 679 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 680 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 681 aprint_error_dev(sc->sc_dev, 682 "can't allocate tx listseg, error = %d\n", error); 683 goto fail_0; 684 } 685 686 /* Load the map for the TX ring. */ 687 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 688 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 689 (void **)&sc->re_ldata.re_tx_list, 690 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 691 aprint_error_dev(sc->sc_dev, 692 "can't map tx list, error = %d\n", error); 693 goto fail_1; 694 } 695 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 696 697 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 698 RE_TX_LIST_SZ(sc), 0, 0, 699 &sc->re_ldata.re_tx_list_map)) != 0) { 700 aprint_error_dev(sc->sc_dev, 701 "can't create tx list map, error = %d\n", error); 702 goto fail_2; 703 } 704 705 706 if ((error = bus_dmamap_load(sc->sc_dmat, 707 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 708 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 709 aprint_error_dev(sc->sc_dev, 710 "can't load tx list, error = %d\n", error); 711 goto fail_3; 712 } 713 714 /* Create DMA maps for TX buffers */ 715 for (i = 0; i < RE_TX_QLEN; i++) { 716 error = bus_dmamap_create(sc->sc_dmat, 717 round_page(IP_MAXPACKET), 718 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 719 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 720 if (error) { 721 aprint_error_dev(sc->sc_dev, 722 "can't create DMA map for TX\n"); 723 goto fail_4; 724 } 725 } 726 727 /* Allocate DMA'able memory for the RX ring */ 728 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 729 if ((error = bus_dmamem_alloc(sc->sc_dmat, 730 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 731 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 732 aprint_error_dev(sc->sc_dev, 733 "can't allocate rx listseg, error = %d\n", error); 734 goto fail_4; 735 } 736 737 /* Load the map for the RX ring. */ 738 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 739 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 740 (void **)&sc->re_ldata.re_rx_list, 741 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 742 aprint_error_dev(sc->sc_dev, 743 "can't map rx list, error = %d\n", error); 744 goto fail_5; 745 } 746 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 747 748 if ((error = bus_dmamap_create(sc->sc_dmat, 749 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 750 &sc->re_ldata.re_rx_list_map)) != 0) { 751 aprint_error_dev(sc->sc_dev, 752 "can't create rx list map, error = %d\n", error); 753 goto fail_6; 754 } 755 756 if ((error = bus_dmamap_load(sc->sc_dmat, 757 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 758 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 759 aprint_error_dev(sc->sc_dev, 760 "can't load rx list, error = %d\n", error); 761 goto fail_7; 762 } 763 764 /* Create DMA maps for RX buffers */ 765 for (i = 0; i < RE_RX_DESC_CNT; i++) { 766 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 767 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 768 if (error) { 769 aprint_error_dev(sc->sc_dev, 770 "can't create DMA map for RX\n"); 771 goto fail_8; 772 } 773 } 774 775 /* 776 * Record interface as attached. From here, we should not fail. 777 */ 778 sc->sc_flags |= RTK_ATTACHED; 779 780 ifp = &sc->ethercom.ec_if; 781 ifp->if_softc = sc; 782 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 783 ifp->if_mtu = ETHERMTU; 784 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 785 ifp->if_ioctl = re_ioctl; 786 sc->ethercom.ec_capabilities |= 787 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 788 ifp->if_start = re_start; 789 ifp->if_stop = re_stop; 790 791 /* 792 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 793 * so we have a workaround to handle the bug by padding 794 * such packets manually. 795 */ 796 ifp->if_capabilities |= 797 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 798 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 799 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 800 IFCAP_TSOv4; 801 802 /* 803 * XXX 804 * Still have no idea how to make TSO work on 8168C, 8168CP, 805 * 8102E, 8111C and 8111CP. 806 */ 807 if ((sc->sc_quirk & RTKQ_DESCV2) != 0) 808 ifp->if_capabilities &= ~IFCAP_TSOv4; 809 810 ifp->if_watchdog = re_watchdog; 811 ifp->if_init = re_init; 812 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 813 ifp->if_capenable = ifp->if_capabilities; 814 IFQ_SET_READY(&ifp->if_snd); 815 816 callout_init(&sc->rtk_tick_ch, 0); 817 818 /* Do MII setup */ 819 sc->mii.mii_ifp = ifp; 820 sc->mii.mii_readreg = re_miibus_readreg; 821 sc->mii.mii_writereg = re_miibus_writereg; 822 sc->mii.mii_statchg = re_miibus_statchg; 823 sc->ethercom.ec_mii = &sc->mii; 824 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 825 ether_mediastatus); 826 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 827 MII_OFFSET_ANY, 0); 828 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 829 830 /* 831 * Call MI attach routine. 832 */ 833 if_attach(ifp); 834 ether_ifattach(ifp, eaddr); 835 836 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 837 pmf_class_network_register(sc->sc_dev, ifp); 838 else 839 aprint_error_dev(sc->sc_dev, 840 "couldn't establish power handler\n"); 841 842 return; 843 844 fail_8: 845 /* Destroy DMA maps for RX buffers. */ 846 for (i = 0; i < RE_RX_DESC_CNT; i++) 847 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 848 bus_dmamap_destroy(sc->sc_dmat, 849 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 850 851 /* Free DMA'able memory for the RX ring. */ 852 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 853 fail_7: 854 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 855 fail_6: 856 bus_dmamem_unmap(sc->sc_dmat, 857 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 858 fail_5: 859 bus_dmamem_free(sc->sc_dmat, 860 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 861 862 fail_4: 863 /* Destroy DMA maps for TX buffers. */ 864 for (i = 0; i < RE_TX_QLEN; i++) 865 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 866 bus_dmamap_destroy(sc->sc_dmat, 867 sc->re_ldata.re_txq[i].txq_dmamap); 868 869 /* Free DMA'able memory for the TX ring. */ 870 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 871 fail_3: 872 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 873 fail_2: 874 bus_dmamem_unmap(sc->sc_dmat, 875 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 876 fail_1: 877 bus_dmamem_free(sc->sc_dmat, 878 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 879 fail_0: 880 return; 881 } 882 883 884 /* 885 * re_activate: 886 * Handle device activation/deactivation requests. 887 */ 888 int 889 re_activate(device_t self, enum devact act) 890 { 891 struct rtk_softc *sc = device_private(self); 892 int s, error = 0; 893 894 s = splnet(); 895 switch (act) { 896 case DVACT_ACTIVATE: 897 error = EOPNOTSUPP; 898 break; 899 case DVACT_DEACTIVATE: 900 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 901 if_deactivate(&sc->ethercom.ec_if); 902 break; 903 } 904 splx(s); 905 906 return error; 907 } 908 909 /* 910 * re_detach: 911 * Detach a rtk interface. 912 */ 913 int 914 re_detach(struct rtk_softc *sc) 915 { 916 struct ifnet *ifp = &sc->ethercom.ec_if; 917 int i; 918 919 /* 920 * Succeed now if there isn't any work to do. 921 */ 922 if ((sc->sc_flags & RTK_ATTACHED) == 0) 923 return 0; 924 925 /* Unhook our tick handler. */ 926 callout_stop(&sc->rtk_tick_ch); 927 928 /* Detach all PHYs. */ 929 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 930 931 /* Delete all remaining media. */ 932 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 933 934 ether_ifdetach(ifp); 935 if_detach(ifp); 936 937 /* Destroy DMA maps for RX buffers. */ 938 for (i = 0; i < RE_RX_DESC_CNT; i++) 939 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 940 bus_dmamap_destroy(sc->sc_dmat, 941 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 942 943 /* Free DMA'able memory for the RX ring. */ 944 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 945 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 946 bus_dmamem_unmap(sc->sc_dmat, 947 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 948 bus_dmamem_free(sc->sc_dmat, 949 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 950 951 /* Destroy DMA maps for TX buffers. */ 952 for (i = 0; i < RE_TX_QLEN; i++) 953 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 954 bus_dmamap_destroy(sc->sc_dmat, 955 sc->re_ldata.re_txq[i].txq_dmamap); 956 957 /* Free DMA'able memory for the TX ring. */ 958 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 959 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 960 bus_dmamem_unmap(sc->sc_dmat, 961 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 962 bus_dmamem_free(sc->sc_dmat, 963 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 964 965 pmf_device_deregister(sc->sc_dev); 966 967 return 0; 968 } 969 970 /* 971 * re_enable: 972 * Enable the RTL81X9 chip. 973 */ 974 static int 975 re_enable(struct rtk_softc *sc) 976 { 977 978 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 979 if ((*sc->sc_enable)(sc) != 0) { 980 printf("%s: device enable failed\n", 981 device_xname(sc->sc_dev)); 982 return EIO; 983 } 984 sc->sc_flags |= RTK_ENABLED; 985 } 986 return 0; 987 } 988 989 /* 990 * re_disable: 991 * Disable the RTL81X9 chip. 992 */ 993 static void 994 re_disable(struct rtk_softc *sc) 995 { 996 997 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 998 (*sc->sc_disable)(sc); 999 sc->sc_flags &= ~RTK_ENABLED; 1000 } 1001 } 1002 1003 static int 1004 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1005 { 1006 struct mbuf *n = NULL; 1007 bus_dmamap_t map; 1008 struct re_desc *d; 1009 struct re_rxsoft *rxs; 1010 uint32_t cmdstat; 1011 int error; 1012 1013 if (m == NULL) { 1014 MGETHDR(n, M_DONTWAIT, MT_DATA); 1015 if (n == NULL) 1016 return ENOBUFS; 1017 1018 MCLGET(n, M_DONTWAIT); 1019 if ((n->m_flags & M_EXT) == 0) { 1020 m_freem(n); 1021 return ENOBUFS; 1022 } 1023 m = n; 1024 } else 1025 m->m_data = m->m_ext.ext_buf; 1026 1027 /* 1028 * Initialize mbuf length fields and fixup 1029 * alignment so that the frame payload is 1030 * longword aligned. 1031 */ 1032 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1033 m->m_data += RE_ETHER_ALIGN; 1034 1035 rxs = &sc->re_ldata.re_rxsoft[idx]; 1036 map = rxs->rxs_dmamap; 1037 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1038 BUS_DMA_READ|BUS_DMA_NOWAIT); 1039 1040 if (error) 1041 goto out; 1042 1043 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1044 BUS_DMASYNC_PREREAD); 1045 1046 d = &sc->re_ldata.re_rx_list[idx]; 1047 #ifdef DIAGNOSTIC 1048 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1049 cmdstat = le32toh(d->re_cmdstat); 1050 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1051 if (cmdstat & RE_RDESC_STAT_OWN) { 1052 panic("%s: tried to map busy RX descriptor", 1053 device_xname(sc->sc_dev)); 1054 } 1055 #endif 1056 1057 rxs->rxs_mbuf = m; 1058 1059 d->re_vlanctl = 0; 1060 cmdstat = map->dm_segs[0].ds_len; 1061 if (idx == (RE_RX_DESC_CNT - 1)) 1062 cmdstat |= RE_RDESC_CMD_EOR; 1063 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1064 d->re_cmdstat = htole32(cmdstat); 1065 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1066 cmdstat |= RE_RDESC_CMD_OWN; 1067 d->re_cmdstat = htole32(cmdstat); 1068 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1069 1070 return 0; 1071 out: 1072 if (n != NULL) 1073 m_freem(n); 1074 return ENOMEM; 1075 } 1076 1077 static int 1078 re_tx_list_init(struct rtk_softc *sc) 1079 { 1080 int i; 1081 1082 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1083 for (i = 0; i < RE_TX_QLEN; i++) { 1084 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1085 } 1086 1087 bus_dmamap_sync(sc->sc_dmat, 1088 sc->re_ldata.re_tx_list_map, 0, 1089 sc->re_ldata.re_tx_list_map->dm_mapsize, 1090 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1091 sc->re_ldata.re_txq_prodidx = 0; 1092 sc->re_ldata.re_txq_considx = 0; 1093 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1094 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1095 sc->re_ldata.re_tx_nextfree = 0; 1096 1097 return 0; 1098 } 1099 1100 static int 1101 re_rx_list_init(struct rtk_softc *sc) 1102 { 1103 int i; 1104 1105 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1106 1107 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1108 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1109 return ENOBUFS; 1110 } 1111 1112 sc->re_ldata.re_rx_prodidx = 0; 1113 sc->re_head = sc->re_tail = NULL; 1114 1115 return 0; 1116 } 1117 1118 /* 1119 * RX handler for C+ and 8169. For the gigE chips, we support 1120 * the reception of jumbo frames that have been fragmented 1121 * across multiple 2K mbuf cluster buffers. 1122 */ 1123 static void 1124 re_rxeof(struct rtk_softc *sc) 1125 { 1126 struct mbuf *m; 1127 struct ifnet *ifp; 1128 int i, total_len; 1129 struct re_desc *cur_rx; 1130 struct re_rxsoft *rxs; 1131 uint32_t rxstat, rxvlan; 1132 1133 ifp = &sc->ethercom.ec_if; 1134 1135 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1136 cur_rx = &sc->re_ldata.re_rx_list[i]; 1137 RE_RXDESCSYNC(sc, i, 1138 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1139 rxstat = le32toh(cur_rx->re_cmdstat); 1140 rxvlan = le32toh(cur_rx->re_vlanctl); 1141 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1142 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1143 break; 1144 } 1145 total_len = rxstat & sc->re_rxlenmask; 1146 rxs = &sc->re_ldata.re_rxsoft[i]; 1147 m = rxs->rxs_mbuf; 1148 1149 /* Invalidate the RX mbuf and unload its map */ 1150 1151 bus_dmamap_sync(sc->sc_dmat, 1152 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1153 BUS_DMASYNC_POSTREAD); 1154 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1155 1156 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1157 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1158 if (sc->re_head == NULL) 1159 sc->re_head = sc->re_tail = m; 1160 else { 1161 m->m_flags &= ~M_PKTHDR; 1162 sc->re_tail->m_next = m; 1163 sc->re_tail = m; 1164 } 1165 re_newbuf(sc, i, NULL); 1166 continue; 1167 } 1168 1169 /* 1170 * NOTE: for the 8139C+, the frame length field 1171 * is always 12 bits in size, but for the gigE chips, 1172 * it is 13 bits (since the max RX frame length is 16K). 1173 * Unfortunately, all 32 bits in the status word 1174 * were already used, so to make room for the extra 1175 * length bit, RealTek took out the 'frame alignment 1176 * error' bit and shifted the other status bits 1177 * over one slot. The OWN, EOR, FS and LS bits are 1178 * still in the same places. We have already extracted 1179 * the frame length and checked the OWN bit, so rather 1180 * than using an alternate bit mapping, we shift the 1181 * status bits one space to the right so we can evaluate 1182 * them using the 8169 status as though it was in the 1183 * same format as that of the 8139C+. 1184 */ 1185 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1186 rxstat >>= 1; 1187 1188 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1189 #ifdef RE_DEBUG 1190 printf("%s: RX error (rxstat = 0x%08x)", 1191 device_xname(sc->sc_dev), rxstat); 1192 if (rxstat & RE_RDESC_STAT_FRALIGN) 1193 printf(", frame alignment error"); 1194 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1195 printf(", out of buffer space"); 1196 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1197 printf(", FIFO overrun"); 1198 if (rxstat & RE_RDESC_STAT_GIANT) 1199 printf(", giant packet"); 1200 if (rxstat & RE_RDESC_STAT_RUNT) 1201 printf(", runt packet"); 1202 if (rxstat & RE_RDESC_STAT_CRCERR) 1203 printf(", CRC error"); 1204 printf("\n"); 1205 #endif 1206 ifp->if_ierrors++; 1207 /* 1208 * If this is part of a multi-fragment packet, 1209 * discard all the pieces. 1210 */ 1211 if (sc->re_head != NULL) { 1212 m_freem(sc->re_head); 1213 sc->re_head = sc->re_tail = NULL; 1214 } 1215 re_newbuf(sc, i, m); 1216 continue; 1217 } 1218 1219 /* 1220 * If allocating a replacement mbuf fails, 1221 * reload the current one. 1222 */ 1223 1224 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1225 ifp->if_ierrors++; 1226 if (sc->re_head != NULL) { 1227 m_freem(sc->re_head); 1228 sc->re_head = sc->re_tail = NULL; 1229 } 1230 re_newbuf(sc, i, m); 1231 continue; 1232 } 1233 1234 if (sc->re_head != NULL) { 1235 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1236 /* 1237 * Special case: if there's 4 bytes or less 1238 * in this buffer, the mbuf can be discarded: 1239 * the last 4 bytes is the CRC, which we don't 1240 * care about anyway. 1241 */ 1242 if (m->m_len <= ETHER_CRC_LEN) { 1243 sc->re_tail->m_len -= 1244 (ETHER_CRC_LEN - m->m_len); 1245 m_freem(m); 1246 } else { 1247 m->m_len -= ETHER_CRC_LEN; 1248 m->m_flags &= ~M_PKTHDR; 1249 sc->re_tail->m_next = m; 1250 } 1251 m = sc->re_head; 1252 sc->re_head = sc->re_tail = NULL; 1253 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1254 } else 1255 m->m_pkthdr.len = m->m_len = 1256 (total_len - ETHER_CRC_LEN); 1257 1258 ifp->if_ipackets++; 1259 m->m_pkthdr.rcvif = ifp; 1260 1261 /* Do RX checksumming */ 1262 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1263 /* Check IP header checksum */ 1264 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) { 1265 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1266 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1267 m->m_pkthdr.csum_flags |= 1268 M_CSUM_IPv4_BAD; 1269 1270 /* Check TCP/UDP checksum */ 1271 if (RE_TCPPKT(rxstat)) { 1272 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1273 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1274 m->m_pkthdr.csum_flags |= 1275 M_CSUM_TCP_UDP_BAD; 1276 } else if (RE_UDPPKT(rxstat)) { 1277 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1278 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1279 m->m_pkthdr.csum_flags |= 1280 M_CSUM_TCP_UDP_BAD; 1281 } 1282 } 1283 } else { 1284 /* Check IPv4 header checksum */ 1285 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) { 1286 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1287 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1288 m->m_pkthdr.csum_flags |= 1289 M_CSUM_IPv4_BAD; 1290 1291 /* Check TCPv4/UDPv4 checksum */ 1292 if (RE_TCPPKT(rxstat)) { 1293 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1294 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1295 m->m_pkthdr.csum_flags |= 1296 M_CSUM_TCP_UDP_BAD; 1297 } else if (RE_UDPPKT(rxstat)) { 1298 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1299 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1300 m->m_pkthdr.csum_flags |= 1301 M_CSUM_TCP_UDP_BAD; 1302 } 1303 } 1304 /* XXX Check TCPv6/UDPv6 checksum? */ 1305 } 1306 1307 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1308 VLAN_INPUT_TAG(ifp, m, 1309 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA), 1310 continue); 1311 } 1312 #if NBPFILTER > 0 1313 if (ifp->if_bpf) 1314 bpf_mtap(ifp->if_bpf, m); 1315 #endif 1316 (*ifp->if_input)(ifp, m); 1317 } 1318 1319 sc->re_ldata.re_rx_prodidx = i; 1320 } 1321 1322 static void 1323 re_txeof(struct rtk_softc *sc) 1324 { 1325 struct ifnet *ifp; 1326 struct re_txq *txq; 1327 uint32_t txstat; 1328 int idx, descidx; 1329 1330 ifp = &sc->ethercom.ec_if; 1331 1332 for (idx = sc->re_ldata.re_txq_considx; 1333 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1334 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1335 txq = &sc->re_ldata.re_txq[idx]; 1336 KASSERT(txq->txq_mbuf != NULL); 1337 1338 descidx = txq->txq_descidx; 1339 RE_TXDESCSYNC(sc, descidx, 1340 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1341 txstat = 1342 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1343 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1344 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1345 if (txstat & RE_TDESC_CMD_OWN) { 1346 break; 1347 } 1348 1349 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1350 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1351 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1352 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1353 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1354 m_freem(txq->txq_mbuf); 1355 txq->txq_mbuf = NULL; 1356 1357 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1358 ifp->if_collisions++; 1359 if (txstat & RE_TDESC_STAT_TXERRSUM) 1360 ifp->if_oerrors++; 1361 else 1362 ifp->if_opackets++; 1363 } 1364 1365 sc->re_ldata.re_txq_considx = idx; 1366 1367 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1368 ifp->if_flags &= ~IFF_OACTIVE; 1369 1370 /* 1371 * If not all descriptors have been released reaped yet, 1372 * reload the timer so that we will eventually get another 1373 * interrupt that will cause us to re-enter this routine. 1374 * This is done in case the transmitter has gone idle. 1375 */ 1376 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1377 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1378 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1379 /* 1380 * Some chips will ignore a second TX request 1381 * issued while an existing transmission is in 1382 * progress. If the transmitter goes idle but 1383 * there are still packets waiting to be sent, 1384 * we need to restart the channel here to flush 1385 * them out. This only seems to be required with 1386 * the PCIe devices. 1387 */ 1388 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1389 } 1390 } else 1391 ifp->if_timer = 0; 1392 } 1393 1394 static void 1395 re_tick(void *arg) 1396 { 1397 struct rtk_softc *sc = arg; 1398 int s; 1399 1400 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1401 s = splnet(); 1402 1403 mii_tick(&sc->mii); 1404 splx(s); 1405 1406 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1407 } 1408 1409 int 1410 re_intr(void *arg) 1411 { 1412 struct rtk_softc *sc = arg; 1413 struct ifnet *ifp; 1414 uint16_t status; 1415 int handled = 0; 1416 1417 if (!device_has_power(sc->sc_dev)) 1418 return 0; 1419 1420 ifp = &sc->ethercom.ec_if; 1421 1422 if ((ifp->if_flags & IFF_UP) == 0) 1423 return 0; 1424 1425 for (;;) { 1426 1427 status = CSR_READ_2(sc, RTK_ISR); 1428 /* If the card has gone away the read returns 0xffff. */ 1429 if (status == 0xffff) 1430 break; 1431 if (status) { 1432 handled = 1; 1433 CSR_WRITE_2(sc, RTK_ISR, status); 1434 } 1435 1436 if ((status & RTK_INTRS_CPLUS) == 0) 1437 break; 1438 1439 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1440 re_rxeof(sc); 1441 1442 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1443 RTK_ISR_TX_DESC_UNAVAIL)) 1444 re_txeof(sc); 1445 1446 if (status & RTK_ISR_SYSTEM_ERR) { 1447 re_init(ifp); 1448 } 1449 1450 if (status & RTK_ISR_LINKCHG) { 1451 callout_stop(&sc->rtk_tick_ch); 1452 re_tick(sc); 1453 } 1454 } 1455 1456 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd)) 1457 re_start(ifp); 1458 1459 return handled; 1460 } 1461 1462 1463 1464 /* 1465 * Main transmit routine for C+ and gigE NICs. 1466 */ 1467 1468 static void 1469 re_start(struct ifnet *ifp) 1470 { 1471 struct rtk_softc *sc; 1472 struct mbuf *m; 1473 bus_dmamap_t map; 1474 struct re_txq *txq; 1475 struct re_desc *d; 1476 struct m_tag *mtag; 1477 uint32_t cmdstat, re_flags, vlanctl; 1478 int ofree, idx, error, nsegs, seg; 1479 int startdesc, curdesc, lastdesc; 1480 bool pad; 1481 1482 sc = ifp->if_softc; 1483 ofree = sc->re_ldata.re_txq_free; 1484 1485 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1486 1487 IFQ_POLL(&ifp->if_snd, m); 1488 if (m == NULL) 1489 break; 1490 1491 if (sc->re_ldata.re_txq_free == 0 || 1492 sc->re_ldata.re_tx_free == 0) { 1493 /* no more free slots left */ 1494 ifp->if_flags |= IFF_OACTIVE; 1495 break; 1496 } 1497 1498 /* 1499 * Set up checksum offload. Note: checksum offload bits must 1500 * appear in all descriptors of a multi-descriptor transmit 1501 * attempt. (This is according to testing done with an 8169 1502 * chip. I'm not sure if this is a requirement or a bug.) 1503 */ 1504 1505 vlanctl = 0; 1506 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1507 uint32_t segsz = m->m_pkthdr.segsz; 1508 1509 re_flags = RE_TDESC_CMD_LGSEND | 1510 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1511 } else { 1512 /* 1513 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1514 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1515 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1516 */ 1517 re_flags = 0; 1518 if ((m->m_pkthdr.csum_flags & 1519 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1520 != 0) { 1521 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1522 re_flags |= RE_TDESC_CMD_IPCSUM; 1523 if (m->m_pkthdr.csum_flags & 1524 M_CSUM_TCPv4) { 1525 re_flags |= 1526 RE_TDESC_CMD_TCPCSUM; 1527 } else if (m->m_pkthdr.csum_flags & 1528 M_CSUM_UDPv4) { 1529 re_flags |= 1530 RE_TDESC_CMD_UDPCSUM; 1531 } 1532 } else { 1533 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1534 if (m->m_pkthdr.csum_flags & 1535 M_CSUM_TCPv4) { 1536 vlanctl |= 1537 RE_TDESC_VLANCTL_TCPCSUM; 1538 } else if (m->m_pkthdr.csum_flags & 1539 M_CSUM_UDPv4) { 1540 vlanctl |= 1541 RE_TDESC_VLANCTL_UDPCSUM; 1542 } 1543 } 1544 } 1545 } 1546 1547 txq = &sc->re_ldata.re_txq[idx]; 1548 map = txq->txq_dmamap; 1549 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1550 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1551 1552 if (__predict_false(error)) { 1553 /* XXX try to defrag if EFBIG? */ 1554 printf("%s: can't map mbuf (error %d)\n", 1555 device_xname(sc->sc_dev), error); 1556 1557 IFQ_DEQUEUE(&ifp->if_snd, m); 1558 m_freem(m); 1559 ifp->if_oerrors++; 1560 continue; 1561 } 1562 1563 nsegs = map->dm_nsegs; 1564 pad = false; 1565 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1566 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1567 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1568 pad = true; 1569 nsegs++; 1570 } 1571 1572 if (nsegs > sc->re_ldata.re_tx_free) { 1573 /* 1574 * Not enough free descriptors to transmit this packet. 1575 */ 1576 ifp->if_flags |= IFF_OACTIVE; 1577 bus_dmamap_unload(sc->sc_dmat, map); 1578 break; 1579 } 1580 1581 IFQ_DEQUEUE(&ifp->if_snd, m); 1582 1583 /* 1584 * Make sure that the caches are synchronized before we 1585 * ask the chip to start DMA for the packet data. 1586 */ 1587 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1588 BUS_DMASYNC_PREWRITE); 1589 1590 /* 1591 * Set up hardware VLAN tagging. Note: vlan tag info must 1592 * appear in all descriptors of a multi-descriptor 1593 * transmission attempt. 1594 */ 1595 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) 1596 vlanctl |= bswap16(VLAN_TAG_VALUE(mtag)) | 1597 RE_TDESC_VLANCTL_TAG; 1598 1599 /* 1600 * Map the segment array into descriptors. 1601 * Note that we set the start-of-frame and 1602 * end-of-frame markers for either TX or RX, 1603 * but they really only have meaning in the TX case. 1604 * (In the RX case, it's the chip that tells us 1605 * where packets begin and end.) 1606 * We also keep track of the end of the ring 1607 * and set the end-of-ring bits as needed, 1608 * and we set the ownership bits in all except 1609 * the very first descriptor. (The caller will 1610 * set this descriptor later when it start 1611 * transmission or reception.) 1612 */ 1613 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1614 lastdesc = -1; 1615 for (seg = 0; seg < map->dm_nsegs; 1616 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1617 d = &sc->re_ldata.re_tx_list[curdesc]; 1618 #ifdef DIAGNOSTIC 1619 RE_TXDESCSYNC(sc, curdesc, 1620 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1621 cmdstat = le32toh(d->re_cmdstat); 1622 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1623 if (cmdstat & RE_TDESC_STAT_OWN) { 1624 panic("%s: tried to map busy TX descriptor", 1625 device_xname(sc->sc_dev)); 1626 } 1627 #endif 1628 1629 d->re_vlanctl = htole32(vlanctl); 1630 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1631 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1632 if (seg == 0) 1633 cmdstat |= RE_TDESC_CMD_SOF; 1634 else 1635 cmdstat |= RE_TDESC_CMD_OWN; 1636 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1637 cmdstat |= RE_TDESC_CMD_EOR; 1638 if (seg == nsegs - 1) { 1639 cmdstat |= RE_TDESC_CMD_EOF; 1640 lastdesc = curdesc; 1641 } 1642 d->re_cmdstat = htole32(cmdstat); 1643 RE_TXDESCSYNC(sc, curdesc, 1644 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1645 } 1646 if (__predict_false(pad)) { 1647 d = &sc->re_ldata.re_tx_list[curdesc]; 1648 d->re_vlanctl = htole32(vlanctl); 1649 re_set_bufaddr(d, RE_TXPADDADDR(sc)); 1650 cmdstat = re_flags | 1651 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1652 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1653 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1654 cmdstat |= RE_TDESC_CMD_EOR; 1655 d->re_cmdstat = htole32(cmdstat); 1656 RE_TXDESCSYNC(sc, curdesc, 1657 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1658 lastdesc = curdesc; 1659 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1660 } 1661 KASSERT(lastdesc != -1); 1662 1663 /* Transfer ownership of packet to the chip. */ 1664 1665 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1666 htole32(RE_TDESC_CMD_OWN); 1667 RE_TXDESCSYNC(sc, startdesc, 1668 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1669 1670 /* update info of TX queue and descriptors */ 1671 txq->txq_mbuf = m; 1672 txq->txq_descidx = lastdesc; 1673 txq->txq_nsegs = nsegs; 1674 1675 sc->re_ldata.re_txq_free--; 1676 sc->re_ldata.re_tx_free -= nsegs; 1677 sc->re_ldata.re_tx_nextfree = curdesc; 1678 1679 #if NBPFILTER > 0 1680 /* 1681 * If there's a BPF listener, bounce a copy of this frame 1682 * to him. 1683 */ 1684 if (ifp->if_bpf) 1685 bpf_mtap(ifp->if_bpf, m); 1686 #endif 1687 } 1688 1689 if (sc->re_ldata.re_txq_free < ofree) { 1690 /* 1691 * TX packets are enqueued. 1692 */ 1693 sc->re_ldata.re_txq_prodidx = idx; 1694 1695 /* 1696 * Start the transmitter to poll. 1697 * 1698 * RealTek put the TX poll request register in a different 1699 * location on the 8169 gigE chip. I don't know why. 1700 */ 1701 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1702 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1703 else 1704 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1705 1706 /* 1707 * Use the countdown timer for interrupt moderation. 1708 * 'TX done' interrupts are disabled. Instead, we reset the 1709 * countdown timer, which will begin counting until it hits 1710 * the value in the TIMERINT register, and then trigger an 1711 * interrupt. Each time we write to the TIMERCNT register, 1712 * the timer count is reset to 0. 1713 */ 1714 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1715 1716 /* 1717 * Set a timeout in case the chip goes out to lunch. 1718 */ 1719 ifp->if_timer = 5; 1720 } 1721 } 1722 1723 static int 1724 re_init(struct ifnet *ifp) 1725 { 1726 struct rtk_softc *sc = ifp->if_softc; 1727 const uint8_t *enaddr; 1728 uint32_t rxcfg = 0; 1729 uint32_t reg; 1730 uint16_t cfg; 1731 int error; 1732 1733 if ((error = re_enable(sc)) != 0) 1734 goto out; 1735 1736 /* 1737 * Cancel pending I/O and free all RX/TX buffers. 1738 */ 1739 re_stop(ifp, 0); 1740 1741 re_reset(sc); 1742 1743 /* 1744 * Enable C+ RX and TX mode, as well as VLAN stripping and 1745 * RX checksum offload. We must configure the C+ register 1746 * before all others. 1747 */ 1748 cfg = RE_CPLUSCMD_PCI_MRW; 1749 1750 /* 1751 * XXX: For old 8169 set bit 14. 1752 * For 8169S/8110S and above, do not set bit 14. 1753 */ 1754 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1755 cfg |= (0x1 << 14); 1756 1757 if ((ifp->if_capenable & ETHERCAP_VLAN_HWTAGGING) != 0) 1758 cfg |= RE_CPLUSCMD_VLANSTRIP; 1759 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx | 1760 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0) 1761 cfg |= RE_CPLUSCMD_RXCSUM_ENB; 1762 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) { 1763 cfg |= RE_CPLUSCMD_MACSTAT_DIS; 1764 cfg |= RE_CPLUSCMD_TXENB; 1765 } else 1766 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB; 1767 1768 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg); 1769 1770 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1771 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1772 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1773 1774 DELAY(10000); 1775 1776 /* 1777 * Init our MAC address. Even though the chipset 1778 * documentation doesn't mention it, we need to enter "Config 1779 * register write enable" mode to modify the ID registers. 1780 */ 1781 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1782 enaddr = CLLADDR(ifp->if_sadl); 1783 reg = enaddr[0] | (enaddr[1] << 8) | 1784 (enaddr[2] << 16) | (enaddr[3] << 24); 1785 CSR_WRITE_4(sc, RTK_IDR0, reg); 1786 reg = enaddr[4] | (enaddr[5] << 8); 1787 CSR_WRITE_4(sc, RTK_IDR4, reg); 1788 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1789 1790 /* 1791 * For C+ mode, initialize the RX descriptors and mbufs. 1792 */ 1793 re_rx_list_init(sc); 1794 re_tx_list_init(sc); 1795 1796 /* 1797 * Load the addresses of the RX and TX lists into the chip. 1798 */ 1799 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1800 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1801 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1802 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1803 1804 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1805 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1806 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1807 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1808 1809 /* 1810 * Enable transmit and receive. 1811 */ 1812 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1813 1814 /* 1815 * Set the initial TX and RX configuration. 1816 */ 1817 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1818 /* test mode is needed only for old 8169 */ 1819 CSR_WRITE_4(sc, RTK_TXCFG, 1820 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1821 } else 1822 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1823 1824 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1825 1826 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1827 1828 /* Set the individual bit to receive frames for this host only. */ 1829 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1830 rxcfg |= RTK_RXCFG_RX_INDIV; 1831 1832 /* If we want promiscuous mode, set the allframes bit. */ 1833 if (ifp->if_flags & IFF_PROMISC) 1834 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1835 else 1836 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1837 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1838 1839 /* 1840 * Set capture broadcast bit to capture broadcast frames. 1841 */ 1842 if (ifp->if_flags & IFF_BROADCAST) 1843 rxcfg |= RTK_RXCFG_RX_BROAD; 1844 else 1845 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1846 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1847 1848 /* 1849 * Program the multicast filter, if necessary. 1850 */ 1851 rtk_setmulti(sc); 1852 1853 /* 1854 * Enable interrupts. 1855 */ 1856 if (sc->re_testmode) 1857 CSR_WRITE_2(sc, RTK_IMR, 0); 1858 else 1859 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1860 1861 /* Start RX/TX process. */ 1862 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1863 #ifdef notdef 1864 /* Enable receiver and transmitter. */ 1865 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1866 #endif 1867 1868 /* 1869 * Initialize the timer interrupt register so that 1870 * a timer interrupt will be generated once the timer 1871 * reaches a certain number of ticks. The timer is 1872 * reloaded on each transmit. This gives us TX interrupt 1873 * moderation, which dramatically improves TX frame rate. 1874 */ 1875 1876 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1877 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1878 else { 1879 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1880 1881 /* 1882 * For 8169 gigE NICs, set the max allowed RX packet 1883 * size so we can receive jumbo frames. 1884 */ 1885 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1886 } 1887 1888 if (sc->re_testmode) 1889 return 0; 1890 1891 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 1892 1893 ifp->if_flags |= IFF_RUNNING; 1894 ifp->if_flags &= ~IFF_OACTIVE; 1895 1896 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1897 1898 out: 1899 if (error) { 1900 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1901 ifp->if_timer = 0; 1902 printf("%s: interface not running\n", 1903 device_xname(sc->sc_dev)); 1904 } 1905 1906 return error; 1907 } 1908 1909 static int 1910 re_ioctl(struct ifnet *ifp, u_long command, void *data) 1911 { 1912 struct rtk_softc *sc = ifp->if_softc; 1913 struct ifreq *ifr = data; 1914 int s, error = 0; 1915 1916 s = splnet(); 1917 1918 switch (command) { 1919 case SIOCSIFMTU: 1920 /* 1921 * Disable jumbo frames if it's not supported. 1922 */ 1923 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 1924 ifr->ifr_mtu > ETHERMTU) { 1925 error = EINVAL; 1926 break; 1927 } 1928 1929 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 1930 error = EINVAL; 1931 else if ((error = ifioctl_common(ifp, command, data)) == 1932 ENETRESET) 1933 error = 0; 1934 break; 1935 default: 1936 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1937 break; 1938 1939 error = 0; 1940 1941 if (command == SIOCSIFCAP) 1942 error = (*ifp->if_init)(ifp); 1943 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1944 ; 1945 else if (ifp->if_flags & IFF_RUNNING) 1946 rtk_setmulti(sc); 1947 break; 1948 } 1949 1950 splx(s); 1951 1952 return error; 1953 } 1954 1955 static void 1956 re_watchdog(struct ifnet *ifp) 1957 { 1958 struct rtk_softc *sc; 1959 int s; 1960 1961 sc = ifp->if_softc; 1962 s = splnet(); 1963 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1964 ifp->if_oerrors++; 1965 1966 re_txeof(sc); 1967 re_rxeof(sc); 1968 1969 re_init(ifp); 1970 1971 splx(s); 1972 } 1973 1974 /* 1975 * Stop the adapter and free any mbufs allocated to the 1976 * RX and TX lists. 1977 */ 1978 static void 1979 re_stop(struct ifnet *ifp, int disable) 1980 { 1981 int i; 1982 struct rtk_softc *sc = ifp->if_softc; 1983 1984 callout_stop(&sc->rtk_tick_ch); 1985 1986 mii_down(&sc->mii); 1987 1988 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0) 1989 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB | 1990 RTK_CMD_RX_ENB); 1991 else 1992 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1993 DELAY(1000); 1994 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1995 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 1996 1997 if (sc->re_head != NULL) { 1998 m_freem(sc->re_head); 1999 sc->re_head = sc->re_tail = NULL; 2000 } 2001 2002 /* Free the TX list buffers. */ 2003 for (i = 0; i < RE_TX_QLEN; i++) { 2004 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 2005 bus_dmamap_unload(sc->sc_dmat, 2006 sc->re_ldata.re_txq[i].txq_dmamap); 2007 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 2008 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 2009 } 2010 } 2011 2012 /* Free the RX list buffers. */ 2013 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2014 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 2015 bus_dmamap_unload(sc->sc_dmat, 2016 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2017 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2018 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2019 } 2020 } 2021 2022 if (disable) 2023 re_disable(sc); 2024 2025 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2026 ifp->if_timer = 0; 2027 } 2028
Indexes created Tue Sep 23 02:09:52 GMT 2025