rtl8169.c revision 1.13
1 /* $NetBSD: rtl8169.c,v 1.13 2005/03/12 08:01:51 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul (at) windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 50 * and the RTL8110S. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7.5K, so the max MTU possible with this 110 * driver is 7500 bytes. 111 */ 112 113 #include "bpfilter.h" 114 #include "vlan.h" 115 116 #include <sys/param.h> 117 #include <sys/endian.h> 118 #include <sys/systm.h> 119 #include <sys/sockio.h> 120 #include <sys/mbuf.h> 121 #include <sys/malloc.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/device.h> 125 126 #include <net/if.h> 127 #include <net/if_arp.h> 128 #include <net/if_dl.h> 129 #include <net/if_ether.h> 130 #include <net/if_media.h> 131 #include <net/if_vlanvar.h> 132 133 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 134 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 135 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 136 137 #if NBPFILTER > 0 138 #include <net/bpf.h> 139 #endif 140 141 #include <machine/bus.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 #include <dev/pci/pcidevs.h> 149 150 #include <dev/ic/rtl81x9reg.h> 151 #include <dev/ic/rtl81x9var.h> 152 153 #include <dev/ic/rtl8169var.h> 154 155 156 static int re_encap(struct rtk_softc *, struct mbuf *, int *); 157 158 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 159 static int re_rx_list_init(struct rtk_softc *); 160 static int re_tx_list_init(struct rtk_softc *); 161 static void re_rxeof(struct rtk_softc *); 162 static void re_txeof(struct rtk_softc *); 163 static void re_tick(void *); 164 static void re_start(struct ifnet *); 165 static int re_ioctl(struct ifnet *, u_long, caddr_t); 166 static int re_init(struct ifnet *); 167 static void re_stop(struct ifnet *, int); 168 static void re_watchdog(struct ifnet *); 169 170 static void re_shutdown(void *); 171 static int re_enable(struct rtk_softc *); 172 static void re_disable(struct rtk_softc *); 173 static void re_power(int, void *); 174 175 static int re_ifmedia_upd(struct ifnet *); 176 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177 178 static int re_gmii_readreg(struct device *, int, int); 179 static void re_gmii_writereg(struct device *, int, int, int); 180 181 static int re_miibus_readreg(struct device *, int, int); 182 static void re_miibus_writereg(struct device *, int, int, int); 183 static void re_miibus_statchg(struct device *); 184 185 static void re_reset(struct rtk_softc *); 186 187 static int 188 re_gmii_readreg(struct device *self, int phy, int reg) 189 { 190 struct rtk_softc *sc = (void *)self; 191 u_int32_t rval; 192 int i; 193 194 if (phy != 7) 195 return 0; 196 197 /* Let the rgephy driver read the GMEDIASTAT register */ 198 199 if (reg == RTK_GMEDIASTAT) { 200 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 201 return rval; 202 } 203 204 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 205 DELAY(1000); 206 207 for (i = 0; i < RTK_TIMEOUT; i++) { 208 rval = CSR_READ_4(sc, RTK_PHYAR); 209 if (rval & RTK_PHYAR_BUSY) 210 break; 211 DELAY(100); 212 } 213 214 if (i == RTK_TIMEOUT) { 215 aprint_error("%s: PHY read failed\n", sc->sc_dev.dv_xname); 216 return 0; 217 } 218 219 return rval & RTK_PHYAR_PHYDATA; 220 } 221 222 static void 223 re_gmii_writereg(struct device *dev, int phy, int reg, int data) 224 { 225 struct rtk_softc *sc = (void *)dev; 226 u_int32_t rval; 227 int i; 228 229 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 230 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 231 DELAY(1000); 232 233 for (i = 0; i < RTK_TIMEOUT; i++) { 234 rval = CSR_READ_4(sc, RTK_PHYAR); 235 if (!(rval & RTK_PHYAR_BUSY)) 236 break; 237 DELAY(100); 238 } 239 240 if (i == RTK_TIMEOUT) { 241 aprint_error("%s: PHY write reg %x <- %x failed\n", 242 sc->sc_dev.dv_xname, reg, data); 243 return; 244 } 245 246 return; 247 } 248 249 static int 250 re_miibus_readreg(struct device *dev, int phy, int reg) 251 { 252 struct rtk_softc *sc = (void *)dev; 253 u_int16_t rval = 0; 254 u_int16_t re8139_reg = 0; 255 int s; 256 257 s = splnet(); 258 259 if (sc->rtk_type == RTK_8169) { 260 rval = re_gmii_readreg(dev, phy, reg); 261 splx(s); 262 return rval; 263 } 264 265 /* Pretend the internal PHY is only at address 0 */ 266 if (phy) { 267 splx(s); 268 return 0; 269 } 270 switch (reg) { 271 case MII_BMCR: 272 re8139_reg = RTK_BMCR; 273 break; 274 case MII_BMSR: 275 re8139_reg = RTK_BMSR; 276 break; 277 case MII_ANAR: 278 re8139_reg = RTK_ANAR; 279 break; 280 case MII_ANER: 281 re8139_reg = RTK_ANER; 282 break; 283 case MII_ANLPAR: 284 re8139_reg = RTK_LPAR; 285 break; 286 case MII_PHYIDR1: 287 case MII_PHYIDR2: 288 splx(s); 289 return 0; 290 /* 291 * Allow the rlphy driver to read the media status 292 * register. If we have a link partner which does not 293 * support NWAY, this is the register which will tell 294 * us the results of parallel detection. 295 */ 296 case RTK_MEDIASTAT: 297 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 298 splx(s); 299 return rval; 300 default: 301 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 302 splx(s); 303 return 0; 304 } 305 rval = CSR_READ_2(sc, re8139_reg); 306 splx(s); 307 return rval; 308 } 309 310 static void 311 re_miibus_writereg(struct device *dev, int phy, int reg, int data) 312 { 313 struct rtk_softc *sc = (void *)dev; 314 u_int16_t re8139_reg = 0; 315 int s; 316 317 s = splnet(); 318 319 if (sc->rtk_type == RTK_8169) { 320 re_gmii_writereg(dev, phy, reg, data); 321 splx(s); 322 return; 323 } 324 325 /* Pretend the internal PHY is only at address 0 */ 326 if (phy) { 327 splx(s); 328 return; 329 } 330 switch (reg) { 331 case MII_BMCR: 332 re8139_reg = RTK_BMCR; 333 break; 334 case MII_BMSR: 335 re8139_reg = RTK_BMSR; 336 break; 337 case MII_ANAR: 338 re8139_reg = RTK_ANAR; 339 break; 340 case MII_ANER: 341 re8139_reg = RTK_ANER; 342 break; 343 case MII_ANLPAR: 344 re8139_reg = RTK_LPAR; 345 break; 346 case MII_PHYIDR1: 347 case MII_PHYIDR2: 348 splx(s); 349 return; 350 break; 351 default: 352 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 353 splx(s); 354 return; 355 } 356 CSR_WRITE_2(sc, re8139_reg, data); 357 splx(s); 358 return; 359 } 360 361 static void 362 re_miibus_statchg(struct device *dev) 363 { 364 365 return; 366 } 367 368 static void 369 re_reset(struct rtk_softc *sc) 370 { 371 register int i; 372 373 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 374 375 for (i = 0; i < RTK_TIMEOUT; i++) { 376 DELAY(10); 377 if (!(CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET)) 378 break; 379 } 380 if (i == RTK_TIMEOUT) 381 aprint_error("%s: reset never completed!\n", 382 sc->sc_dev.dv_xname); 383 384 /* 385 * NB: Realtek-supplied Linux driver does this only for 386 * MCFG_METHOD_2, which corresponds to sc->sc_rev == 2. 387 */ 388 if (1) /* XXX check softc flag for 8169s version */ 389 CSR_WRITE_1(sc, 0x82, 1); 390 391 return; 392 } 393 394 /* 395 * The following routine is designed to test for a defect on some 396 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 397 * lines connected to the bus, however for a 32-bit only card, they 398 * should be pulled high. The result of this defect is that the 399 * NIC will not work right if you plug it into a 64-bit slot: DMA 400 * operations will be done with 64-bit transfers, which will fail 401 * because the 64-bit data lines aren't connected. 402 * 403 * There's no way to work around this (short of talking a soldering 404 * iron to the board), however we can detect it. The method we use 405 * here is to put the NIC into digital loopback mode, set the receiver 406 * to promiscuous mode, and then try to send a frame. We then compare 407 * the frame data we sent to what was received. If the data matches, 408 * then the NIC is working correctly, otherwise we know the user has 409 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 410 * slot. In the latter case, there's no way the NIC can work correctly, 411 * so we print out a message on the console and abort the device attach. 412 */ 413 414 int 415 re_diag(struct rtk_softc *sc) 416 { 417 struct ifnet *ifp = &sc->ethercom.ec_if; 418 struct mbuf *m0; 419 struct ether_header *eh; 420 struct rtk_desc *cur_rx; 421 bus_dmamap_t dmamap; 422 u_int16_t status; 423 u_int32_t rxstat; 424 int total_len, i, s, error = 0; 425 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 426 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 427 428 /* Allocate a single mbuf */ 429 430 MGETHDR(m0, M_DONTWAIT, MT_DATA); 431 if (m0 == NULL) 432 return ENOBUFS; 433 434 /* 435 * Initialize the NIC in test mode. This sets the chip up 436 * so that it can send and receive frames, but performs the 437 * following special functions: 438 * - Puts receiver in promiscuous mode 439 * - Enables digital loopback mode 440 * - Leaves interrupts turned off 441 */ 442 443 ifp->if_flags |= IFF_PROMISC; 444 sc->rtk_testmode = 1; 445 re_init(ifp); 446 re_stop(ifp, 0); 447 DELAY(100000); 448 re_init(ifp); 449 450 /* Put some data in the mbuf */ 451 452 eh = mtod(m0, struct ether_header *); 453 bcopy((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 454 bcopy((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 455 eh->ether_type = htons(ETHERTYPE_IP); 456 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 457 458 /* 459 * Queue the packet, start transmission. 460 */ 461 462 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 463 s = splnet(); 464 IF_ENQUEUE(&ifp->if_snd, m0); 465 re_start(ifp); 466 splx(s); 467 m0 = NULL; 468 469 /* Wait for it to propagate through the chip */ 470 471 DELAY(100000); 472 for (i = 0; i < RTK_TIMEOUT; i++) { 473 status = CSR_READ_2(sc, RTK_ISR); 474 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 475 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 476 break; 477 DELAY(10); 478 } 479 if (i == RTK_TIMEOUT) { 480 aprint_error("%s: diagnostic failed, failed to receive packet " 481 "in loopback mode\n", sc->sc_dev.dv_xname); 482 error = EIO; 483 goto done; 484 } 485 486 /* 487 * The packet should have been dumped into the first 488 * entry in the RX DMA ring. Grab it from there. 489 */ 490 491 dmamap = sc->rtk_ldata.rtk_rx_list_map; 492 bus_dmamap_sync(sc->sc_dmat, 493 dmamap, 0, dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 494 dmamap = sc->rtk_ldata.rtk_rx_dmamap[0]; 495 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 496 BUS_DMASYNC_POSTWRITE); 497 bus_dmamap_unload(sc->sc_dmat, 498 sc->rtk_ldata.rtk_rx_dmamap[0]); 499 500 m0 = sc->rtk_ldata.rtk_rx_mbuf[0]; 501 sc->rtk_ldata.rtk_rx_mbuf[0] = NULL; 502 eh = mtod(m0, struct ether_header *); 503 504 cur_rx = &sc->rtk_ldata.rtk_rx_list[0]; 505 total_len = RTK_RXBYTES(cur_rx); 506 rxstat = le32toh(cur_rx->rtk_cmdstat); 507 508 if (total_len != ETHER_MIN_LEN) { 509 aprint_error("%s: diagnostic failed, received short packet\n", 510 sc->sc_dev.dv_xname); 511 error = EIO; 512 goto done; 513 } 514 515 /* Test that the received packet data matches what we sent. */ 516 517 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 518 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 519 ntohs(eh->ether_type) != ETHERTYPE_IP) { 520 aprint_error("%s: WARNING, DMA FAILURE!\n", 521 sc->sc_dev.dv_xname); 522 aprint_error("%s: expected TX data: %s", 523 sc->sc_dev.dv_xname, ether_sprintf(dst)); 524 aprint_error("/%s/0x%x\n", ether_sprintf(src), ETHERTYPE_IP); 525 aprint_error("%s: received RX data: %s", 526 sc->sc_dev.dv_xname, 527 ether_sprintf(eh->ether_dhost)); 528 aprint_error("/%s/0x%x\n", ether_sprintf(eh->ether_shost), 529 ntohs(eh->ether_type)); 530 aprint_error("%s: You may have a defective 32-bit NIC plugged " 531 "into a 64-bit PCI slot.\n", sc->sc_dev.dv_xname); 532 aprint_error("%s: Please re-install the NIC in a 32-bit slot " 533 "for proper operation.\n", sc->sc_dev.dv_xname); 534 aprint_error("%s: Read the re(4) man page for more details.\n", 535 sc->sc_dev.dv_xname); 536 error = EIO; 537 } 538 539 done: 540 /* Turn interface off, release resources */ 541 542 sc->rtk_testmode = 0; 543 ifp->if_flags &= ~IFF_PROMISC; 544 re_stop(ifp, 0); 545 if (m0 != NULL) 546 m_freem(m0); 547 548 return error; 549 } 550 551 552 /* 553 * Attach the interface. Allocate softc structures, do ifmedia 554 * setup and ethernet/BPF attach. 555 */ 556 void 557 re_attach(struct rtk_softc *sc) 558 { 559 u_char eaddr[ETHER_ADDR_LEN]; 560 u_int16_t val; 561 struct ifnet *ifp; 562 int error = 0, i, addr_len; 563 564 565 /* XXX JRS: bus-attach-independent code begins approximately here */ 566 567 /* Reset the adapter. */ 568 re_reset(sc); 569 570 if (sc->rtk_type == RTK_8169) { 571 uint32_t hwrev; 572 573 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 574 hwrev = CSR_READ_4(sc, RTK_TXCFG) & 0x7c800000; 575 if (hwrev == (0x1 << 28)) { 576 sc->sc_rev = 4; 577 } else if (hwrev == (0x1 << 26)) { 578 sc->sc_rev = 3; 579 } else if (hwrev == (0x1 << 23)) { 580 sc->sc_rev = 2; 581 } else 582 sc->sc_rev = 1; 583 584 /* Set RX length mask */ 585 586 sc->rtk_rxlenmask = RTK_RDESC_STAT_GFRAGLEN; 587 588 /* Force station address autoload from the EEPROM */ 589 590 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_AUTOLOAD); 591 for (i = 0; i < RTK_TIMEOUT; i++) { 592 if (!(CSR_READ_1(sc, RTK_EECMD) & RTK_EEMODE_AUTOLOAD)) 593 break; 594 DELAY(100); 595 } 596 if (i == RTK_TIMEOUT) 597 aprint_error("%s: eeprom autoload timed out\n", 598 sc->sc_dev.dv_xname); 599 600 for (i = 0; i < ETHER_ADDR_LEN; i++) 601 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 602 } else { 603 604 /* Set RX length mask */ 605 606 sc->rtk_rxlenmask = RTK_RDESC_STAT_FRAGLEN; 607 608 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 609 addr_len = RTK_EEADDR_LEN1; 610 else 611 addr_len = RTK_EEADDR_LEN0; 612 613 /* 614 * Get station address from the EEPROM. 615 */ 616 for (i = 0; i < 3; i++) { 617 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 618 eaddr[(i * 2) + 0] = val & 0xff; 619 eaddr[(i * 2) + 1] = val >> 8; 620 } 621 } 622 623 aprint_normal("%s: Ethernet address %s\n", 624 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 625 626 627 /* Allocate DMA'able memory for the TX ring */ 628 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_TX_LIST_SZ, 629 RTK_ETHER_ALIGN, 0, &sc->rtk_ldata.rtk_tx_listseg, 630 1, &sc->rtk_ldata.rtk_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 631 aprint_error("%s: can't allocate tx listseg, error = %d\n", 632 sc->sc_dev.dv_xname, error); 633 goto fail_0; 634 } 635 636 /* Load the map for the TX ring. */ 637 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_tx_listseg, 638 sc->rtk_ldata.rtk_tx_listnseg, RTK_TX_LIST_SZ, 639 (caddr_t *)&sc->rtk_ldata.rtk_tx_list, 640 BUS_DMA_NOWAIT)) != 0) { 641 aprint_error("%s: can't map tx list, error = %d\n", 642 sc->sc_dev.dv_xname, error); 643 goto fail_1; 644 } 645 memset(sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ); 646 647 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_TX_LIST_SZ, 1, 648 RTK_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 649 &sc->rtk_ldata.rtk_tx_list_map)) != 0) { 650 aprint_error("%s: can't create tx list map, error = %d\n", 651 sc->sc_dev.dv_xname, error); 652 goto fail_2; 653 } 654 655 656 if ((error = bus_dmamap_load(sc->sc_dmat, 657 sc->rtk_ldata.rtk_tx_list_map, sc->rtk_ldata.rtk_tx_list, 658 RTK_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 659 aprint_error("%s: can't load tx list, error = %d\n", 660 sc->sc_dev.dv_xname, error); 661 goto fail_3; 662 } 663 664 /* Create DMA maps for TX buffers */ 665 for (i = 0; i < RTK_TX_DESC_CNT; i++) { 666 error = bus_dmamap_create(sc->sc_dmat, 667 round_page(IP_MAXPACKET), 668 RTK_TX_DESC_CNT - 4, RTK_TDESC_CMD_FRAGLEN, 669 0, BUS_DMA_ALLOCNOW, 670 &sc->rtk_ldata.rtk_tx_dmamap[i]); 671 if (error) { 672 aprint_error("%s: can't create DMA map for TX\n", 673 sc->sc_dev.dv_xname); 674 goto fail_4; 675 } 676 } 677 678 /* Allocate DMA'able memory for the RX ring */ 679 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_RX_LIST_SZ, 680 RTK_RING_ALIGN, 0, &sc->rtk_ldata.rtk_rx_listseg, 1, 681 &sc->rtk_ldata.rtk_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 682 aprint_error("%s: can't allocate rx listseg, error = %d\n", 683 sc->sc_dev.dv_xname, error); 684 goto fail_4; 685 } 686 687 /* Load the map for the RX ring. */ 688 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_rx_listseg, 689 sc->rtk_ldata.rtk_rx_listnseg, RTK_RX_LIST_SZ, 690 (caddr_t *)&sc->rtk_ldata.rtk_rx_list, 691 BUS_DMA_NOWAIT)) != 0) { 692 aprint_error("%s: can't map rx list, error = %d\n", 693 sc->sc_dev.dv_xname, error); 694 goto fail_5; 695 } 696 memset(sc->rtk_ldata.rtk_rx_list, 0, RTK_TX_LIST_SZ); 697 698 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_RX_LIST_SZ, 1, 699 RTK_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 700 &sc->rtk_ldata.rtk_rx_list_map)) != 0) { 701 aprint_error("%s: can't create rx list map, error = %d\n", 702 sc->sc_dev.dv_xname, error); 703 goto fail_6; 704 } 705 706 if ((error = bus_dmamap_load(sc->sc_dmat, 707 sc->rtk_ldata.rtk_rx_list_map, sc->rtk_ldata.rtk_rx_list, 708 RTK_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 709 aprint_error("%s: can't load rx list, error = %d\n", 710 sc->sc_dev.dv_xname, error); 711 goto fail_7; 712 } 713 714 /* Create DMA maps for RX buffers */ 715 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 716 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 717 0, BUS_DMA_ALLOCNOW, &sc->rtk_ldata.rtk_rx_dmamap[i]); 718 if (error) { 719 aprint_error("%s: can't create DMA map for RX\n", 720 sc->sc_dev.dv_xname); 721 goto fail_8; 722 } 723 } 724 725 /* 726 * Record interface as attached. From here, we should not fail. 727 */ 728 sc->sc_flags |= RTK_ATTACHED; 729 730 ifp = &sc->ethercom.ec_if; 731 ifp->if_softc = sc; 732 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 733 ifp->if_mtu = ETHERMTU; 734 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 735 ifp->if_ioctl = re_ioctl; 736 sc->ethercom.ec_capabilities |= 737 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 738 ifp->if_start = re_start; 739 ifp->if_stop = re_stop; 740 ifp->if_capabilities |= 741 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4 | 742 IFCAP_TSOv4; 743 ifp->if_watchdog = re_watchdog; 744 ifp->if_init = re_init; 745 if (sc->rtk_type == RTK_8169) 746 ifp->if_baudrate = 1000000000; 747 else 748 ifp->if_baudrate = 100000000; 749 ifp->if_snd.ifq_maxlen = RTK_IFQ_MAXLEN; 750 ifp->if_capenable = ifp->if_capabilities; 751 IFQ_SET_READY(&ifp->if_snd); 752 753 callout_init(&sc->rtk_tick_ch); 754 755 /* Do MII setup */ 756 sc->mii.mii_ifp = ifp; 757 sc->mii.mii_readreg = re_miibus_readreg; 758 sc->mii.mii_writereg = re_miibus_writereg; 759 sc->mii.mii_statchg = re_miibus_statchg; 760 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, re_ifmedia_upd, 761 re_ifmedia_sts); 762 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 763 MII_OFFSET_ANY, 0); 764 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 765 766 /* 767 * Call MI attach routine. 768 */ 769 if_attach(ifp); 770 ether_ifattach(ifp, eaddr); 771 772 773 /* 774 * Make sure the interface is shutdown during reboot. 775 */ 776 sc->sc_sdhook = shutdownhook_establish(re_shutdown, sc); 777 if (sc->sc_sdhook == NULL) 778 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 779 sc->sc_dev.dv_xname); 780 /* 781 * Add a suspend hook to make sure we come back up after a 782 * resume. 783 */ 784 sc->sc_powerhook = powerhook_establish(re_power, sc); 785 if (sc->sc_powerhook == NULL) 786 aprint_error("%s: WARNING: unable to establish power hook\n", 787 sc->sc_dev.dv_xname); 788 789 790 return; 791 792 fail_8: 793 /* Destroy DMA maps for RX buffers. */ 794 for (i = 0; i < RTK_RX_DESC_CNT; i++) 795 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 796 bus_dmamap_destroy(sc->sc_dmat, 797 sc->rtk_ldata.rtk_rx_dmamap[i]); 798 799 /* Free DMA'able memory for the RX ring. */ 800 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 801 fail_7: 802 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 803 fail_6: 804 bus_dmamem_unmap(sc->sc_dmat, 805 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 806 fail_5: 807 bus_dmamem_free(sc->sc_dmat, 808 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 809 810 fail_4: 811 /* Destroy DMA maps for TX buffers. */ 812 for (i = 0; i < RTK_TX_DESC_CNT; i++) 813 if (sc->rtk_ldata.rtk_tx_dmamap[i] != NULL) 814 bus_dmamap_destroy(sc->sc_dmat, 815 sc->rtk_ldata.rtk_tx_dmamap[i]); 816 817 /* Free DMA'able memory for the TX ring. */ 818 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 819 fail_3: 820 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 821 fail_2: 822 bus_dmamem_unmap(sc->sc_dmat, 823 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ); 824 fail_1: 825 bus_dmamem_free(sc->sc_dmat, 826 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 827 fail_0: 828 return; 829 } 830 831 832 /* 833 * re_activate: 834 * Handle device activation/deactivation requests. 835 */ 836 int 837 re_activate(struct device *self, enum devact act) 838 { 839 struct rtk_softc *sc = (void *) self; 840 int s, error = 0; 841 842 s = splnet(); 843 switch (act) { 844 case DVACT_ACTIVATE: 845 error = EOPNOTSUPP; 846 break; 847 case DVACT_DEACTIVATE: 848 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 849 if_deactivate(&sc->ethercom.ec_if); 850 break; 851 } 852 splx(s); 853 854 return error; 855 } 856 857 /* 858 * re_detach: 859 * Detach a rtk interface. 860 */ 861 int 862 re_detach(struct rtk_softc *sc) 863 { 864 struct ifnet *ifp = &sc->ethercom.ec_if; 865 int i; 866 867 /* 868 * Succeed now if there isn't any work to do. 869 */ 870 if ((sc->sc_flags & RTK_ATTACHED) == 0) 871 return 0; 872 873 /* Unhook our tick handler. */ 874 callout_stop(&sc->rtk_tick_ch); 875 876 /* Detach all PHYs. */ 877 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 878 879 /* Delete all remaining media. */ 880 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 881 882 ether_ifdetach(ifp); 883 if_detach(ifp); 884 885 /* XXX undo re_allocmem() */ 886 887 /* Destroy DMA maps for RX buffers. */ 888 for (i = 0; i < RTK_RX_DESC_CNT; i++) 889 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 890 bus_dmamap_destroy(sc->sc_dmat, 891 sc->rtk_ldata.rtk_rx_dmamap[i]); 892 893 /* Free DMA'able memory for the RX ring. */ 894 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 895 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 896 bus_dmamem_unmap(sc->sc_dmat, 897 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 898 bus_dmamem_free(sc->sc_dmat, 899 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 900 901 /* Destroy DMA maps for TX buffers. */ 902 for (i = 0; i < RTK_TX_DESC_CNT; i++) 903 if (sc->rtk_ldata.rtk_tx_dmamap[i] != NULL) 904 bus_dmamap_destroy(sc->sc_dmat, 905 sc->rtk_ldata.rtk_tx_dmamap[i]); 906 907 /* Free DMA'able memory for the TX ring. */ 908 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 909 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 910 bus_dmamem_unmap(sc->sc_dmat, 911 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ); 912 bus_dmamem_free(sc->sc_dmat, 913 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 914 915 916 shutdownhook_disestablish(sc->sc_sdhook); 917 powerhook_disestablish(sc->sc_powerhook); 918 919 return 0; 920 } 921 922 /* 923 * re_enable: 924 * Enable the RTL81X9 chip. 925 */ 926 static int 927 re_enable(struct rtk_softc *sc) 928 { 929 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 930 if ((*sc->sc_enable)(sc) != 0) { 931 aprint_error("%s: device enable failed\n", 932 sc->sc_dev.dv_xname); 933 return EIO; 934 } 935 sc->sc_flags |= RTK_ENABLED; 936 } 937 return 0; 938 } 939 940 /* 941 * re_disable: 942 * Disable the RTL81X9 chip. 943 */ 944 static void 945 re_disable(struct rtk_softc *sc) 946 { 947 948 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 949 (*sc->sc_disable)(sc); 950 sc->sc_flags &= ~RTK_ENABLED; 951 } 952 } 953 954 /* 955 * re_power: 956 * Power management (suspend/resume) hook. 957 */ 958 void 959 re_power(int why, void *arg) 960 { 961 struct rtk_softc *sc = (void *) arg; 962 struct ifnet *ifp = &sc->ethercom.ec_if; 963 int s; 964 965 s = splnet(); 966 switch (why) { 967 case PWR_SUSPEND: 968 case PWR_STANDBY: 969 re_stop(ifp, 0); 970 if (sc->sc_power != NULL) 971 (*sc->sc_power)(sc, why); 972 break; 973 case PWR_RESUME: 974 if (ifp->if_flags & IFF_UP) { 975 if (sc->sc_power != NULL) 976 (*sc->sc_power)(sc, why); 977 re_init(ifp); 978 } 979 break; 980 case PWR_SOFTSUSPEND: 981 case PWR_SOFTSTANDBY: 982 case PWR_SOFTRESUME: 983 break; 984 } 985 splx(s); 986 } 987 988 989 static int 990 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 991 { 992 struct mbuf *n = NULL; 993 bus_dmamap_t map; 994 struct rtk_desc *d; 995 u_int32_t cmdstat; 996 int error; 997 998 if (m == NULL) { 999 MGETHDR(n, M_DONTWAIT, MT_DATA); 1000 if (n == NULL) 1001 return ENOBUFS; 1002 m = n; 1003 1004 MCLGET(m, M_DONTWAIT); 1005 if (!(m->m_flags & M_EXT)) { 1006 m_freem(m); 1007 return ENOBUFS; 1008 } 1009 } else 1010 m->m_data = m->m_ext.ext_buf; 1011 1012 /* 1013 * Initialize mbuf length fields and fixup 1014 * alignment so that the frame payload is 1015 * longword aligned. 1016 */ 1017 m->m_len = m->m_pkthdr.len = MCLBYTES; 1018 m_adj(m, RTK_ETHER_ALIGN); 1019 1020 map = sc->rtk_ldata.rtk_rx_dmamap[idx]; 1021 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1022 1023 if (error) 1024 goto out; 1025 1026 d = &sc->rtk_ldata.rtk_rx_list[idx]; 1027 if (le32toh(d->rtk_cmdstat) & RTK_RDESC_STAT_OWN) 1028 goto out; 1029 1030 cmdstat = map->dm_segs[0].ds_len; 1031 d->rtk_bufaddr_lo = htole32(RTK_ADDR_LO(map->dm_segs[0].ds_addr)); 1032 d->rtk_bufaddr_hi = htole32(RTK_ADDR_HI(map->dm_segs[0].ds_addr)); 1033 cmdstat |= RTK_TDESC_CMD_SOF; 1034 if (idx == (RTK_RX_DESC_CNT - 1)) 1035 cmdstat |= RTK_TDESC_CMD_EOR; 1036 d->rtk_cmdstat = htole32(cmdstat); 1037 1038 d->rtk_cmdstat |= htole32(RTK_TDESC_CMD_EOF); 1039 1040 1041 sc->rtk_ldata.rtk_rx_list[idx].rtk_cmdstat |= 1042 htole32(RTK_RDESC_CMD_OWN); 1043 sc->rtk_ldata.rtk_rx_mbuf[idx] = m; 1044 1045 bus_dmamap_sync(sc->sc_dmat, sc->rtk_ldata.rtk_rx_dmamap[idx], 0, 1046 sc->rtk_ldata.rtk_rx_dmamap[idx]->dm_mapsize, 1047 BUS_DMASYNC_PREREAD); 1048 1049 return 0; 1050 out: 1051 if (n != NULL) 1052 m_freem(n); 1053 return ENOMEM; 1054 } 1055 1056 static int 1057 re_tx_list_init(struct rtk_softc *sc) 1058 { 1059 memset((char *)sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ); 1060 memset((char *)&sc->rtk_ldata.rtk_tx_mbuf, 0, 1061 (RTK_TX_DESC_CNT * sizeof(struct mbuf *))); 1062 1063 bus_dmamap_sync(sc->sc_dmat, 1064 sc->rtk_ldata.rtk_tx_list_map, 0, 1065 sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1066 sc->rtk_ldata.rtk_tx_prodidx = 0; 1067 sc->rtk_ldata.rtk_tx_considx = 0; 1068 sc->rtk_ldata.rtk_tx_free = RTK_TX_DESC_CNT; 1069 1070 return 0; 1071 } 1072 1073 static int 1074 re_rx_list_init(struct rtk_softc *sc) 1075 { 1076 int i; 1077 1078 memset((char *)sc->rtk_ldata.rtk_rx_list, 0, RTK_RX_LIST_SZ); 1079 memset((char *)&sc->rtk_ldata.rtk_rx_mbuf, 0, 1080 (RTK_RX_DESC_CNT * sizeof(struct mbuf *))); 1081 1082 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 1083 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1084 return ENOBUFS; 1085 } 1086 1087 /* Flush the RX descriptors */ 1088 1089 bus_dmamap_sync(sc->sc_dmat, 1090 sc->rtk_ldata.rtk_rx_list_map, 1091 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1092 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1093 1094 sc->rtk_ldata.rtk_rx_prodidx = 0; 1095 sc->rtk_head = sc->rtk_tail = NULL; 1096 1097 return 0; 1098 } 1099 1100 /* 1101 * RX handler for C+ and 8169. For the gigE chips, we support 1102 * the reception of jumbo frames that have been fragmented 1103 * across multiple 2K mbuf cluster buffers. 1104 */ 1105 static void 1106 re_rxeof(struct rtk_softc *sc) 1107 { 1108 struct mbuf *m; 1109 struct ifnet *ifp; 1110 int i, total_len; 1111 struct rtk_desc *cur_rx; 1112 u_int32_t rxstat, rxvlan; 1113 1114 ifp = &sc->ethercom.ec_if; 1115 i = sc->rtk_ldata.rtk_rx_prodidx; 1116 1117 /* Invalidate the descriptor memory */ 1118 1119 bus_dmamap_sync(sc->sc_dmat, 1120 sc->rtk_ldata.rtk_rx_list_map, 1121 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1122 BUS_DMASYNC_POSTREAD); 1123 1124 while (!RTK_OWN(&sc->rtk_ldata.rtk_rx_list[i])) { 1125 1126 cur_rx = &sc->rtk_ldata.rtk_rx_list[i]; 1127 m = sc->rtk_ldata.rtk_rx_mbuf[i]; 1128 total_len = RTK_RXBYTES(cur_rx); 1129 rxstat = le32toh(cur_rx->rtk_cmdstat); 1130 rxvlan = le32toh(cur_rx->rtk_vlanctl); 1131 1132 /* Invalidate the RX mbuf and unload its map */ 1133 1134 bus_dmamap_sync(sc->sc_dmat, 1135 sc->rtk_ldata.rtk_rx_dmamap[i], 1136 0, sc->rtk_ldata.rtk_rx_dmamap[i]->dm_mapsize, 1137 BUS_DMASYNC_POSTWRITE); 1138 bus_dmamap_unload(sc->sc_dmat, 1139 sc->rtk_ldata.rtk_rx_dmamap[i]); 1140 1141 if (!(rxstat & RTK_RDESC_STAT_EOF)) { 1142 m->m_len = MCLBYTES - RTK_ETHER_ALIGN; 1143 if (sc->rtk_head == NULL) 1144 sc->rtk_head = sc->rtk_tail = m; 1145 else { 1146 m->m_flags &= ~M_PKTHDR; 1147 sc->rtk_tail->m_next = m; 1148 sc->rtk_tail = m; 1149 } 1150 re_newbuf(sc, i, NULL); 1151 RTK_DESC_INC(i); 1152 continue; 1153 } 1154 1155 /* 1156 * NOTE: for the 8139C+, the frame length field 1157 * is always 12 bits in size, but for the gigE chips, 1158 * it is 13 bits (since the max RX frame length is 16K). 1159 * Unfortunately, all 32 bits in the status word 1160 * were already used, so to make room for the extra 1161 * length bit, RealTek took out the 'frame alignment 1162 * error' bit and shifted the other status bits 1163 * over one slot. The OWN, EOR, FS and LS bits are 1164 * still in the same places. We have already extracted 1165 * the frame length and checked the OWN bit, so rather 1166 * than using an alternate bit mapping, we shift the 1167 * status bits one space to the right so we can evaluate 1168 * them using the 8169 status as though it was in the 1169 * same format as that of the 8139C+. 1170 */ 1171 if (sc->rtk_type == RTK_8169) 1172 rxstat >>= 1; 1173 1174 if (rxstat & RTK_RDESC_STAT_RXERRSUM) { 1175 ifp->if_ierrors++; 1176 /* 1177 * If this is part of a multi-fragment packet, 1178 * discard all the pieces. 1179 */ 1180 if (sc->rtk_head != NULL) { 1181 m_freem(sc->rtk_head); 1182 sc->rtk_head = sc->rtk_tail = NULL; 1183 } 1184 re_newbuf(sc, i, m); 1185 RTK_DESC_INC(i); 1186 continue; 1187 } 1188 1189 /* 1190 * If allocating a replacement mbuf fails, 1191 * reload the current one. 1192 */ 1193 1194 if (re_newbuf(sc, i, NULL)) { 1195 ifp->if_ierrors++; 1196 if (sc->rtk_head != NULL) { 1197 m_freem(sc->rtk_head); 1198 sc->rtk_head = sc->rtk_tail = NULL; 1199 } 1200 re_newbuf(sc, i, m); 1201 RTK_DESC_INC(i); 1202 continue; 1203 } 1204 1205 RTK_DESC_INC(i); 1206 1207 if (sc->rtk_head != NULL) { 1208 m->m_len = total_len % (MCLBYTES - RTK_ETHER_ALIGN); 1209 /* 1210 * Special case: if there's 4 bytes or less 1211 * in this buffer, the mbuf can be discarded: 1212 * the last 4 bytes is the CRC, which we don't 1213 * care about anyway. 1214 */ 1215 if (m->m_len <= ETHER_CRC_LEN) { 1216 sc->rtk_tail->m_len -= 1217 (ETHER_CRC_LEN - m->m_len); 1218 m_freem(m); 1219 } else { 1220 m->m_len -= ETHER_CRC_LEN; 1221 m->m_flags &= ~M_PKTHDR; 1222 sc->rtk_tail->m_next = m; 1223 } 1224 m = sc->rtk_head; 1225 sc->rtk_head = sc->rtk_tail = NULL; 1226 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1227 } else 1228 m->m_pkthdr.len = m->m_len = 1229 (total_len - ETHER_CRC_LEN); 1230 1231 ifp->if_ipackets++; 1232 m->m_pkthdr.rcvif = ifp; 1233 1234 /* Do RX checksumming if enabled */ 1235 1236 if (ifp->if_capenable & IFCAP_CSUM_IPv4) { 1237 1238 /* Check IP header checksum */ 1239 if (rxstat & RTK_RDESC_STAT_PROTOID) 1240 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;; 1241 if (rxstat & RTK_RDESC_STAT_IPSUMBAD) 1242 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1243 } 1244 1245 /* Check TCP/UDP checksum */ 1246 if (RTK_TCPPKT(rxstat) && 1247 (ifp->if_capenable & IFCAP_CSUM_TCPv4)) { 1248 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1249 if (rxstat & RTK_RDESC_STAT_TCPSUMBAD) 1250 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1251 } 1252 if (RTK_UDPPKT(rxstat) && 1253 (ifp->if_capenable & IFCAP_CSUM_UDPv4)) { 1254 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1255 if (rxstat & RTK_RDESC_STAT_UDPSUMBAD) 1256 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1257 } 1258 1259 if (rxvlan & RTK_RDESC_VLANCTL_TAG) { 1260 VLAN_INPUT_TAG(ifp, m, 1261 be16toh(rxvlan & RTK_RDESC_VLANCTL_DATA), 1262 continue); 1263 } 1264 #if NBPFILTER > 0 1265 if (ifp->if_bpf) 1266 bpf_mtap(ifp->if_bpf, m); 1267 #endif 1268 (*ifp->if_input)(ifp, m); 1269 } 1270 1271 /* Flush the RX DMA ring */ 1272 1273 bus_dmamap_sync(sc->sc_dmat, 1274 sc->rtk_ldata.rtk_rx_list_map, 1275 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1276 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1277 1278 sc->rtk_ldata.rtk_rx_prodidx = i; 1279 1280 return; 1281 } 1282 1283 static void 1284 re_txeof(struct rtk_softc *sc) 1285 { 1286 struct ifnet *ifp; 1287 u_int32_t txstat; 1288 int idx; 1289 1290 ifp = &sc->ethercom.ec_if; 1291 idx = sc->rtk_ldata.rtk_tx_considx; 1292 1293 /* Invalidate the TX descriptor list */ 1294 1295 bus_dmamap_sync(sc->sc_dmat, 1296 sc->rtk_ldata.rtk_tx_list_map, 1297 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1298 BUS_DMASYNC_POSTREAD); 1299 1300 while (idx != sc->rtk_ldata.rtk_tx_prodidx) { 1301 1302 txstat = le32toh(sc->rtk_ldata.rtk_tx_list[idx].rtk_cmdstat); 1303 if (txstat & RTK_TDESC_CMD_OWN) 1304 break; 1305 1306 /* 1307 * We only stash mbufs in the last descriptor 1308 * in a fragment chain, which also happens to 1309 * be the only place where the TX status bits 1310 * are valid. 1311 */ 1312 1313 if (txstat & RTK_TDESC_CMD_EOF) { 1314 m_freem(sc->rtk_ldata.rtk_tx_mbuf[idx]); 1315 sc->rtk_ldata.rtk_tx_mbuf[idx] = NULL; 1316 bus_dmamap_unload(sc->sc_dmat, 1317 sc->rtk_ldata.rtk_tx_dmamap[idx]); 1318 if (txstat & (RTK_TDESC_STAT_EXCESSCOL | 1319 RTK_TDESC_STAT_COLCNT)) 1320 ifp->if_collisions++; 1321 if (txstat & RTK_TDESC_STAT_TXERRSUM) 1322 ifp->if_oerrors++; 1323 else 1324 ifp->if_opackets++; 1325 } 1326 sc->rtk_ldata.rtk_tx_free++; 1327 RTK_DESC_INC(idx); 1328 } 1329 1330 /* No changes made to the TX ring, so no flush needed */ 1331 1332 if (idx != sc->rtk_ldata.rtk_tx_considx) { 1333 sc->rtk_ldata.rtk_tx_considx = idx; 1334 ifp->if_flags &= ~IFF_OACTIVE; 1335 ifp->if_timer = 0; 1336 } 1337 1338 /* 1339 * If not all descriptors have been released reaped yet, 1340 * reload the timer so that we will eventually get another 1341 * interrupt that will cause us to re-enter this routine. 1342 * This is done in case the transmitter has gone idle. 1343 */ 1344 if (sc->rtk_ldata.rtk_tx_free != RTK_TX_DESC_CNT) 1345 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1346 1347 return; 1348 } 1349 1350 /* 1351 * Stop all chip I/O so that the kernel's probe routines don't 1352 * get confused by errant DMAs when rebooting. 1353 */ 1354 static void 1355 re_shutdown(void *vsc) 1356 1357 { 1358 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1359 1360 re_stop(&sc->ethercom.ec_if, 0); 1361 } 1362 1363 1364 static void 1365 re_tick(void *xsc) 1366 { 1367 struct rtk_softc *sc = xsc; 1368 int s; 1369 1370 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1371 s = splnet(); 1372 1373 mii_tick(&sc->mii); 1374 splx(s); 1375 1376 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1377 } 1378 1379 #ifdef DEVICE_POLLING 1380 static void 1381 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1382 { 1383 struct rtk_softc *sc = ifp->if_softc; 1384 1385 RTK_LOCK(sc); 1386 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1387 ether_poll_deregister(ifp); 1388 cmd = POLL_DEREGISTER; 1389 } 1390 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1391 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1392 goto done; 1393 } 1394 1395 sc->rxcycles = count; 1396 re_rxeof(sc); 1397 re_txeof(sc); 1398 1399 if (ifp->if_snd.ifq_head != NULL) 1400 (*ifp->if_start)(ifp); 1401 1402 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1403 u_int16_t status; 1404 1405 status = CSR_READ_2(sc, RTK_ISR); 1406 if (status == 0xffff) 1407 goto done; 1408 if (status) 1409 CSR_WRITE_2(sc, RTK_ISR, status); 1410 1411 /* 1412 * XXX check behaviour on receiver stalls. 1413 */ 1414 1415 if (status & RTK_ISR_SYSTEM_ERR) { 1416 re_reset(sc); 1417 re_init(sc); 1418 } 1419 } 1420 done: 1421 RTK_UNLOCK(sc); 1422 } 1423 #endif /* DEVICE_POLLING */ 1424 1425 int 1426 re_intr(void *arg) 1427 { 1428 struct rtk_softc *sc = arg; 1429 struct ifnet *ifp; 1430 u_int16_t status; 1431 int handled = 0; 1432 1433 ifp = &sc->ethercom.ec_if; 1434 1435 if (!(ifp->if_flags & IFF_UP)) 1436 return 0; 1437 1438 #ifdef DEVICE_POLLING 1439 if (ifp->if_flags & IFF_POLLING) 1440 goto done; 1441 if ((ifp->if_capenable & IFCAP_POLLING) && 1442 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1443 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1444 re_poll(ifp, 0, 1); 1445 goto done; 1446 } 1447 #endif /* DEVICE_POLLING */ 1448 1449 for (;;) { 1450 1451 status = CSR_READ_2(sc, RTK_ISR); 1452 /* If the card has gone away the read returns 0xffff. */ 1453 if (status == 0xffff) 1454 break; 1455 if (status) { 1456 handled = 1; 1457 CSR_WRITE_2(sc, RTK_ISR, status); 1458 } 1459 1460 if ((status & RTK_INTRS_CPLUS) == 0) 1461 break; 1462 1463 if ((status & RTK_ISR_RX_OK) || 1464 (status & RTK_ISR_RX_ERR)) 1465 re_rxeof(sc); 1466 1467 if ((status & RTK_ISR_TIMEOUT_EXPIRED) || 1468 (status & RTK_ISR_TX_ERR) || 1469 (status & RTK_ISR_TX_DESC_UNAVAIL)) 1470 re_txeof(sc); 1471 1472 if (status & RTK_ISR_SYSTEM_ERR) { 1473 re_reset(sc); 1474 re_init(ifp); 1475 } 1476 1477 if (status & RTK_ISR_LINKCHG) { 1478 callout_stop(&sc->rtk_tick_ch); 1479 re_tick(sc); 1480 } 1481 } 1482 1483 if (ifp->if_flags & IFF_UP) /* kludge for interrupt during re_init() */ 1484 if (ifp->if_snd.ifq_head != NULL) 1485 (*ifp->if_start)(ifp); 1486 1487 #ifdef DEVICE_POLLING 1488 done: 1489 #endif 1490 1491 return handled; 1492 } 1493 1494 static int 1495 re_encap(struct rtk_softc *sc, struct mbuf *m, int *idx) 1496 { 1497 bus_dmamap_t map; 1498 int error, i, curidx; 1499 struct m_tag *mtag; 1500 struct rtk_desc *d; 1501 u_int32_t cmdstat, rtk_flags; 1502 1503 if (sc->rtk_ldata.rtk_tx_free <= 4) 1504 return EFBIG; 1505 1506 /* 1507 * Set up checksum offload. Note: checksum offload bits must 1508 * appear in all descriptors of a multi-descriptor transmit 1509 * attempt. (This is according to testing done with an 8169 1510 * chip. I'm not sure if this is a requirement or a bug.) 1511 */ 1512 1513 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1514 u_int32_t segsz = m->m_pkthdr.segsz; 1515 1516 rtk_flags = RTK_TDESC_CMD_LGSEND | 1517 (segsz << RTK_TDESC_CMD_MSSVAL_SHIFT); 1518 } else { 1519 rtk_flags = 0; 1520 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1521 rtk_flags |= RTK_TDESC_CMD_IPCSUM; 1522 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1523 rtk_flags |= RTK_TDESC_CMD_TCPCSUM; 1524 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1525 rtk_flags |= RTK_TDESC_CMD_UDPCSUM; 1526 } 1527 1528 map = sc->rtk_ldata.rtk_tx_dmamap[*idx]; 1529 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1530 1531 if (error) { 1532 /* XXX try to defrag if EFBIG? */ 1533 1534 aprint_error("%s: can't map mbuf (error %d)\n", 1535 sc->sc_dev.dv_xname, error); 1536 1537 if (error == EFBIG && 1538 sc->rtk_ldata.rtk_tx_free == RTK_TX_DESC_CNT) { 1539 return error; 1540 } 1541 1542 return ENOBUFS; 1543 } 1544 1545 if (map->dm_nsegs > sc->rtk_ldata.rtk_tx_free - 4) { 1546 error = ENOBUFS; 1547 goto fail_unload; 1548 } 1549 /* 1550 * Map the segment array into descriptors. Note that we set the 1551 * start-of-frame and end-of-frame markers for either TX or RX, but 1552 * they really only have meaning in the TX case. (In the RX case, 1553 * it's the chip that tells us where packets begin and end.) 1554 * We also keep track of the end of the ring and set the 1555 * end-of-ring bits as needed, and we set the ownership bits 1556 * in all except the very first descriptor. (The caller will 1557 * set this descriptor later when it start transmission or 1558 * reception.) 1559 */ 1560 i = 0; 1561 curidx = *idx; 1562 while (1) { 1563 d = &sc->rtk_ldata.rtk_tx_list[curidx]; 1564 if (le32toh(d->rtk_cmdstat) & RTK_RDESC_STAT_OWN) { 1565 while (i > 0) { 1566 sc->rtk_ldata.rtk_tx_list[ 1567 (curidx + RTK_TX_DESC_CNT - i) % 1568 RTK_TX_DESC_CNT].rtk_cmdstat = 0; 1569 i--; 1570 } 1571 error = ENOBUFS; 1572 goto fail_unload; 1573 } 1574 1575 cmdstat = map->dm_segs[i].ds_len; 1576 d->rtk_bufaddr_lo = 1577 htole32(RTK_ADDR_LO(map->dm_segs[i].ds_addr)); 1578 d->rtk_bufaddr_hi = 1579 htole32(RTK_ADDR_HI(map->dm_segs[i].ds_addr)); 1580 if (i == 0) 1581 cmdstat |= RTK_TDESC_CMD_SOF; 1582 else 1583 cmdstat |= RTK_TDESC_CMD_OWN; 1584 if (curidx == (RTK_RX_DESC_CNT - 1)) 1585 cmdstat |= RTK_TDESC_CMD_EOR; 1586 d->rtk_cmdstat = htole32(cmdstat | rtk_flags); 1587 i++; 1588 if (i == map->dm_nsegs) 1589 break; 1590 RTK_DESC_INC(curidx); 1591 } 1592 1593 d->rtk_cmdstat |= htole32(RTK_TDESC_CMD_EOF); 1594 1595 /* 1596 * Insure that the map for this transmission 1597 * is placed at the array index of the last descriptor 1598 * in this chain. 1599 */ 1600 sc->rtk_ldata.rtk_tx_dmamap[*idx] = 1601 sc->rtk_ldata.rtk_tx_dmamap[curidx]; 1602 sc->rtk_ldata.rtk_tx_dmamap[curidx] = map; 1603 sc->rtk_ldata.rtk_tx_mbuf[curidx] = m; 1604 sc->rtk_ldata.rtk_tx_free -= map->dm_nsegs; 1605 1606 /* 1607 * Set up hardware VLAN tagging. Note: vlan tag info must 1608 * appear in the first descriptor of a multi-descriptor 1609 * transmission attempt. 1610 */ 1611 1612 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) { 1613 sc->rtk_ldata.rtk_tx_list[*idx].rtk_vlanctl = 1614 htole32(htons(VLAN_TAG_VALUE(mtag)) | 1615 RTK_TDESC_VLANCTL_TAG); 1616 } 1617 1618 /* Transfer ownership of packet to the chip. */ 1619 1620 sc->rtk_ldata.rtk_tx_list[curidx].rtk_cmdstat |= 1621 htole32(RTK_TDESC_CMD_OWN); 1622 if (*idx != curidx) 1623 sc->rtk_ldata.rtk_tx_list[*idx].rtk_cmdstat |= 1624 htole32(RTK_TDESC_CMD_OWN); 1625 1626 RTK_DESC_INC(curidx); 1627 *idx = curidx; 1628 1629 return 0; 1630 1631 fail_unload: 1632 bus_dmamap_unload(sc->sc_dmat, map); 1633 1634 return error; 1635 } 1636 1637 /* 1638 * Main transmit routine for C+ and gigE NICs. 1639 */ 1640 1641 static void 1642 re_start(struct ifnet *ifp) 1643 { 1644 struct rtk_softc *sc; 1645 struct mbuf *m_head = NULL; 1646 int idx; 1647 1648 sc = ifp->if_softc; 1649 1650 idx = sc->rtk_ldata.rtk_tx_prodidx; 1651 while (sc->rtk_ldata.rtk_tx_mbuf[idx] == NULL) { 1652 int error; 1653 1654 IF_DEQUEUE(&ifp->if_snd, m_head); 1655 if (m_head == NULL) 1656 break; 1657 1658 error = re_encap(sc, m_head, &idx); 1659 if (error == EFBIG) { 1660 ifp->if_oerrors++; 1661 m_freem(m_head); 1662 continue; 1663 } 1664 if (error) { 1665 IF_PREPEND(&ifp->if_snd, m_head); 1666 ifp->if_flags |= IFF_OACTIVE; 1667 break; 1668 } 1669 #if NBPFILTER > 0 1670 /* 1671 * If there's a BPF listener, bounce a copy of this frame 1672 * to him. 1673 */ 1674 if (ifp->if_bpf) 1675 bpf_mtap(ifp->if_bpf, m_head); 1676 #endif 1677 } 1678 1679 /* Flush the TX descriptors */ 1680 1681 bus_dmamap_sync(sc->sc_dmat, 1682 sc->rtk_ldata.rtk_tx_list_map, 1683 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1684 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1685 1686 sc->rtk_ldata.rtk_tx_prodidx = idx; 1687 1688 /* 1689 * RealTek put the TX poll request register in a different 1690 * location on the 8169 gigE chip. I don't know why. 1691 */ 1692 1693 if (sc->rtk_type == RTK_8169) 1694 CSR_WRITE_2(sc, RTK_GTXSTART, RTK_TXSTART_START); 1695 else 1696 CSR_WRITE_2(sc, RTK_TXSTART, RTK_TXSTART_START); 1697 1698 /* 1699 * Use the countdown timer for interrupt moderation. 1700 * 'TX done' interrupts are disabled. Instead, we reset the 1701 * countdown timer, which will begin counting until it hits 1702 * the value in the TIMERINT register, and then trigger an 1703 * interrupt. Each time we write to the TIMERCNT register, 1704 * the timer count is reset to 0. 1705 */ 1706 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1707 1708 /* 1709 * Set a timeout in case the chip goes out to lunch. 1710 */ 1711 ifp->if_timer = 5; 1712 1713 return; 1714 } 1715 1716 static int 1717 re_init(struct ifnet *ifp) 1718 { 1719 struct rtk_softc *sc = ifp->if_softc; 1720 u_int32_t rxcfg = 0; 1721 u_int32_t reg; 1722 int error; 1723 1724 if ((error = re_enable(sc)) != 0) 1725 goto out; 1726 1727 /* 1728 * Cancel pending I/O and free all RX/TX buffers. 1729 */ 1730 re_stop(ifp, 0); 1731 1732 /* 1733 * Enable C+ RX and TX mode, as well as VLAN stripping and 1734 * RX checksum offload. We must configure the C+ register 1735 * before all others. 1736 */ 1737 reg = 0; 1738 1739 /* 1740 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S. 1741 * FreeBSD drivers set these bits anyway (for 8139C+?). 1742 * So far, it works. 1743 */ 1744 1745 /* 1746 * XXX: For 8169 and 8196S revs below 2, set bit 14. 1747 * For 8169S/8110S rev 2 and above, do not set bit 14. 1748 */ 1749 if (sc->rtk_type == RTK_8169 && sc->sc_rev == 1) 1750 reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW;; 1751 1752 if (1) {/* not for 8169S ? */ 1753 reg |= RTK_CPLUSCMD_VLANSTRIP | 1754 (ifp->if_capenable & 1755 (IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4) ? 1756 RTK_CPLUSCMD_RXCSUM_ENB : 0); 1757 } 1758 1759 CSR_WRITE_2(sc, RTK_CPLUS_CMD, 1760 reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB); 1761 1762 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1763 if (sc->rtk_type == RTK_8169) 1764 CSR_WRITE_2(sc, RTK_CPLUS_CMD+0x2, 0x0000); 1765 1766 DELAY(10000); 1767 1768 /* 1769 * Init our MAC address. Even though the chipset 1770 * documentation doesn't mention it, we need to enter "Config 1771 * register write enable" mode to modify the ID registers. 1772 */ 1773 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1774 memcpy(®, LLADDR(ifp->if_sadl), 4); 1775 CSR_WRITE_STREAM_4(sc, RTK_IDR0, reg); 1776 reg = 0; 1777 memcpy(®, LLADDR(ifp->if_sadl) + 4, 4); 1778 CSR_WRITE_STREAM_4(sc, RTK_IDR4, reg); 1779 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1780 1781 /* 1782 * For C+ mode, initialize the RX descriptors and mbufs. 1783 */ 1784 re_rx_list_init(sc); 1785 re_tx_list_init(sc); 1786 1787 /* 1788 * Enable transmit and receive. 1789 */ 1790 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1791 1792 /* 1793 * Set the initial TX and RX configuration. 1794 */ 1795 if (sc->rtk_testmode) { 1796 if (sc->rtk_type == RTK_8169) 1797 CSR_WRITE_4(sc, RTK_TXCFG, 1798 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1799 else 1800 CSR_WRITE_4(sc, RTK_TXCFG, 1801 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON_CPLUS); 1802 } else 1803 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1804 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1805 1806 /* Set the individual bit to receive frames for this host only. */ 1807 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1808 rxcfg |= RTK_RXCFG_RX_INDIV; 1809 1810 /* If we want promiscuous mode, set the allframes bit. */ 1811 if (ifp->if_flags & IFF_PROMISC) 1812 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1813 else 1814 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1815 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1816 1817 /* 1818 * Set capture broadcast bit to capture broadcast frames. 1819 */ 1820 if (ifp->if_flags & IFF_BROADCAST) 1821 rxcfg |= RTK_RXCFG_RX_BROAD; 1822 else 1823 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1824 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1825 1826 /* 1827 * Program the multicast filter, if necessary. 1828 */ 1829 rtk_setmulti(sc); 1830 1831 #ifdef DEVICE_POLLING 1832 /* 1833 * Disable interrupts if we are polling. 1834 */ 1835 if (ifp->if_flags & IFF_POLLING) 1836 CSR_WRITE_2(sc, RTK_IMR, 0); 1837 else /* otherwise ... */ 1838 #endif /* DEVICE_POLLING */ 1839 /* 1840 * Enable interrupts. 1841 */ 1842 if (sc->rtk_testmode) 1843 CSR_WRITE_2(sc, RTK_IMR, 0); 1844 else 1845 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1846 1847 /* Start RX/TX process. */ 1848 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1849 #ifdef notdef 1850 /* Enable receiver and transmitter. */ 1851 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1852 #endif 1853 /* 1854 * Load the addresses of the RX and TX lists into the chip. 1855 */ 1856 1857 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1858 RTK_ADDR_HI(sc->rtk_ldata.rtk_rx_list_map->dm_segs[0].ds_addr)); 1859 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1860 RTK_ADDR_LO(sc->rtk_ldata.rtk_rx_list_map->dm_segs[0].ds_addr)); 1861 1862 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1863 RTK_ADDR_HI(sc->rtk_ldata.rtk_tx_list_map->dm_segs[0].ds_addr)); 1864 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1865 RTK_ADDR_LO(sc->rtk_ldata.rtk_tx_list_map->dm_segs[0].ds_addr)); 1866 1867 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1868 1869 /* 1870 * Initialize the timer interrupt register so that 1871 * a timer interrupt will be generated once the timer 1872 * reaches a certain number of ticks. The timer is 1873 * reloaded on each transmit. This gives us TX interrupt 1874 * moderation, which dramatically improves TX frame rate. 1875 */ 1876 1877 if (sc->rtk_type == RTK_8169) 1878 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1879 else 1880 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1881 1882 /* 1883 * For 8169 gigE NICs, set the max allowed RX packet 1884 * size so we can receive jumbo frames. 1885 */ 1886 if (sc->rtk_type == RTK_8169) 1887 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1888 1889 if (sc->rtk_testmode) 1890 return 0; 1891 1892 mii_mediachg(&sc->mii); 1893 1894 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD | RTK_CFG1_FULLDUPLEX); 1895 1896 ifp->if_flags |= IFF_RUNNING; 1897 ifp->if_flags &= ~IFF_OACTIVE; 1898 1899 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1900 1901 out: 1902 if (error) { 1903 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1904 ifp->if_timer = 0; 1905 aprint_error("%s: interface not running\n", 1906 sc->sc_dev.dv_xname); 1907 } 1908 1909 return error; 1910 1911 } 1912 1913 /* 1914 * Set media options. 1915 */ 1916 static int 1917 re_ifmedia_upd(struct ifnet *ifp) 1918 { 1919 struct rtk_softc *sc; 1920 1921 sc = ifp->if_softc; 1922 1923 return mii_mediachg(&sc->mii); 1924 } 1925 1926 /* 1927 * Report current media status. 1928 */ 1929 static void 1930 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1931 { 1932 struct rtk_softc *sc; 1933 1934 sc = ifp->if_softc; 1935 1936 mii_pollstat(&sc->mii); 1937 ifmr->ifm_active = sc->mii.mii_media_active; 1938 ifmr->ifm_status = sc->mii.mii_media_status; 1939 1940 return; 1941 } 1942 1943 static int 1944 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1945 { 1946 struct rtk_softc *sc = ifp->if_softc; 1947 struct ifreq *ifr = (struct ifreq *) data; 1948 int s, error = 0; 1949 1950 s = splnet(); 1951 1952 switch (command) { 1953 case SIOCSIFMTU: 1954 if (ifr->ifr_mtu > RTK_JUMBO_MTU) 1955 error = EINVAL; 1956 ifp->if_mtu = ifr->ifr_mtu; 1957 break; 1958 case SIOCGIFMEDIA: 1959 case SIOCSIFMEDIA: 1960 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1961 break; 1962 default: 1963 error = ether_ioctl(ifp, command, data); 1964 if (error == ENETRESET) { 1965 if (ifp->if_flags & IFF_RUNNING) 1966 rtk_setmulti(sc); 1967 error = 0; 1968 } 1969 break; 1970 } 1971 1972 splx(s); 1973 1974 return error; 1975 } 1976 1977 static void 1978 re_watchdog(struct ifnet *ifp) 1979 { 1980 struct rtk_softc *sc; 1981 int s; 1982 1983 sc = ifp->if_softc; 1984 s = splnet(); 1985 aprint_error("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1986 ifp->if_oerrors++; 1987 1988 re_txeof(sc); 1989 re_rxeof(sc); 1990 1991 re_init(ifp); 1992 1993 splx(s); 1994 } 1995 1996 /* 1997 * Stop the adapter and free any mbufs allocated to the 1998 * RX and TX lists. 1999 */ 2000 static void 2001 re_stop(struct ifnet *ifp, int disable) 2002 { 2003 register int i; 2004 struct rtk_softc *sc = ifp->if_softc; 2005 2006 callout_stop(&sc->rtk_tick_ch); 2007 2008 #ifdef DEVICE_POLLING 2009 ether_poll_deregister(ifp); 2010 #endif /* DEVICE_POLLING */ 2011 2012 mii_down(&sc->mii); 2013 2014 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2015 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2016 2017 if (sc->rtk_head != NULL) { 2018 m_freem(sc->rtk_head); 2019 sc->rtk_head = sc->rtk_tail = NULL; 2020 } 2021 2022 /* Free the TX list buffers. */ 2023 for (i = 0; i < RTK_TX_DESC_CNT; i++) { 2024 if (sc->rtk_ldata.rtk_tx_mbuf[i] != NULL) { 2025 bus_dmamap_unload(sc->sc_dmat, 2026 sc->rtk_ldata.rtk_tx_dmamap[i]); 2027 m_freem(sc->rtk_ldata.rtk_tx_mbuf[i]); 2028 sc->rtk_ldata.rtk_tx_mbuf[i] = NULL; 2029 } 2030 } 2031 2032 /* Free the RX list buffers. */ 2033 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 2034 if (sc->rtk_ldata.rtk_rx_mbuf[i] != NULL) { 2035 bus_dmamap_unload(sc->sc_dmat, 2036 sc->rtk_ldata.rtk_rx_dmamap[i]); 2037 m_freem(sc->rtk_ldata.rtk_rx_mbuf[i]); 2038 sc->rtk_ldata.rtk_rx_mbuf[i] = NULL; 2039 } 2040 } 2041 2042 if (disable) 2043 re_disable(sc); 2044 2045 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2046 ifp->if_timer = 0; 2047 2048 return; 2049 } 2050
Indexes created Tue Sep 23 14:10:03 GMT 2025