rtl8169.c revision 1.134.4.2 1 /* $NetBSD: rtl8169.c,v 1.134.4.2 2013/07/29 08:11:53 msaitoh Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998-2003
5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.134.4.2 2013/07/29 08:11:53 msaitoh Exp $");
37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
38
39 /*
40 * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver
41 *
42 * Written by Bill Paul <wpaul (at) windriver.com>
43 * Senior Networking Software Engineer
44 * Wind River Systems
45 */
46
47 /*
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * six devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168 and the RTL8111.
52 *
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
57 *
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
60 * any byte boundary.
61 *
62 * o 64-bit DMA
63 *
64 * o TCP/IP checksum offload for both RX and TX
65 *
66 * o High and normal priority transmit DMA rings
67 *
68 * o VLAN tag insertion and extraction
69 *
70 * o TCP large send (segmentation offload)
71 *
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
75 * chips.
76 *
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
80 *
81 * o 1000Mbps mode
82 *
83 * o Jumbo frames
84 *
85 * o GMII and TBI ports/registers for interfacing with copper
86 * or fiber PHYs
87 *
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
90 *
91 * o Slight differences in register layout from the 8139C+
92 *
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
97 * copper gigE PHY.
98 *
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
104 *
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7.5K, so the max MTU possible with this
111 * driver is 7500 bytes.
112 */
113
114
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/kernel.h>
122 #include <sys/socket.h>
123 #include <sys/device.h>
124
125 #include <net/if.h>
126 #include <net/if_arp.h>
127 #include <net/if_dl.h>
128 #include <net/if_ether.h>
129 #include <net/if_media.h>
130 #include <net/if_vlanvar.h>
131
132 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */
133 #include <netinet/in.h> /* XXX for IP_MAXPACKET */
134 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */
135
136 #include <net/bpf.h>
137
138 #include <sys/bus.h>
139
140 #include <dev/mii/mii.h>
141 #include <dev/mii/miivar.h>
142
143 #include <dev/ic/rtl81x9reg.h>
144 #include <dev/ic/rtl81x9var.h>
145
146 #include <dev/ic/rtl8169var.h>
147
148 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t);
149
150 static int re_newbuf(struct rtk_softc *, int, struct mbuf *);
151 static int re_rx_list_init(struct rtk_softc *);
152 static int re_tx_list_init(struct rtk_softc *);
153 static void re_rxeof(struct rtk_softc *);
154 static void re_txeof(struct rtk_softc *);
155 static void re_tick(void *);
156 static void re_start(struct ifnet *);
157 static int re_ioctl(struct ifnet *, u_long, void *);
158 static int re_init(struct ifnet *);
159 static void re_stop(struct ifnet *, int);
160 static void re_watchdog(struct ifnet *);
161
162 static int re_enable(struct rtk_softc *);
163 static void re_disable(struct rtk_softc *);
164
165 static int re_gmii_readreg(device_t, int, int);
166 static void re_gmii_writereg(device_t, int, int, int);
167
168 static int re_miibus_readreg(device_t, int, int);
169 static void re_miibus_writereg(device_t, int, int, int);
170 static void re_miibus_statchg(device_t);
171
172 static void re_reset(struct rtk_softc *);
173
174 static inline void
175 re_set_bufaddr(struct re_desc *d, bus_addr_t addr)
176 {
177
178 d->re_bufaddr_lo = htole32((uint32_t)addr);
179 if (sizeof(bus_addr_t) == sizeof(uint64_t))
180 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32);
181 else
182 d->re_bufaddr_hi = 0;
183 }
184
185 static int
186 re_gmii_readreg(device_t dev, int phy, int reg)
187 {
188 struct rtk_softc *sc = device_private(dev);
189 uint32_t rval;
190 int i;
191
192 if (phy != 7)
193 return 0;
194
195 /* Let the rgephy driver read the GMEDIASTAT register */
196
197 if (reg == RTK_GMEDIASTAT) {
198 rval = CSR_READ_1(sc, RTK_GMEDIASTAT);
199 return rval;
200 }
201
202 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16);
203 DELAY(1000);
204
205 for (i = 0; i < RTK_TIMEOUT; i++) {
206 rval = CSR_READ_4(sc, RTK_PHYAR);
207 if (rval & RTK_PHYAR_BUSY)
208 break;
209 DELAY(100);
210 }
211
212 if (i == RTK_TIMEOUT) {
213 printf("%s: PHY read failed\n", device_xname(sc->sc_dev));
214 return 0;
215 }
216
217 return rval & RTK_PHYAR_PHYDATA;
218 }
219
220 static void
221 re_gmii_writereg(device_t dev, int phy, int reg, int data)
222 {
223 struct rtk_softc *sc = device_private(dev);
224 uint32_t rval;
225 int i;
226
227 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) |
228 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY);
229 DELAY(1000);
230
231 for (i = 0; i < RTK_TIMEOUT; i++) {
232 rval = CSR_READ_4(sc, RTK_PHYAR);
233 if (!(rval & RTK_PHYAR_BUSY))
234 break;
235 DELAY(100);
236 }
237
238 if (i == RTK_TIMEOUT) {
239 printf("%s: PHY write reg %x <- %x failed\n",
240 device_xname(sc->sc_dev), reg, data);
241 }
242 }
243
244 static int
245 re_miibus_readreg(device_t dev, int phy, int reg)
246 {
247 struct rtk_softc *sc = device_private(dev);
248 uint16_t rval = 0;
249 uint16_t re8139_reg = 0;
250 int s;
251
252 s = splnet();
253
254 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
255 rval = re_gmii_readreg(dev, phy, reg);
256 splx(s);
257 return rval;
258 }
259
260 /* Pretend the internal PHY is only at address 0 */
261 if (phy) {
262 splx(s);
263 return 0;
264 }
265 switch (reg) {
266 case MII_BMCR:
267 re8139_reg = RTK_BMCR;
268 break;
269 case MII_BMSR:
270 re8139_reg = RTK_BMSR;
271 break;
272 case MII_ANAR:
273 re8139_reg = RTK_ANAR;
274 break;
275 case MII_ANER:
276 re8139_reg = RTK_ANER;
277 break;
278 case MII_ANLPAR:
279 re8139_reg = RTK_LPAR;
280 break;
281 case MII_PHYIDR1:
282 case MII_PHYIDR2:
283 splx(s);
284 return 0;
285 /*
286 * Allow the rlphy driver to read the media status
287 * register. If we have a link partner which does not
288 * support NWAY, this is the register which will tell
289 * us the results of parallel detection.
290 */
291 case RTK_MEDIASTAT:
292 rval = CSR_READ_1(sc, RTK_MEDIASTAT);
293 splx(s);
294 return rval;
295 default:
296 printf("%s: bad phy register\n", device_xname(sc->sc_dev));
297 splx(s);
298 return 0;
299 }
300 rval = CSR_READ_2(sc, re8139_reg);
301 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) {
302 /* 8139C+ has different bit layout. */
303 rval &= ~(BMCR_LOOP | BMCR_ISO);
304 }
305 splx(s);
306 return rval;
307 }
308
309 static void
310 re_miibus_writereg(device_t dev, int phy, int reg, int data)
311 {
312 struct rtk_softc *sc = device_private(dev);
313 uint16_t re8139_reg = 0;
314 int s;
315
316 s = splnet();
317
318 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
319 re_gmii_writereg(dev, phy, reg, data);
320 splx(s);
321 return;
322 }
323
324 /* Pretend the internal PHY is only at address 0 */
325 if (phy) {
326 splx(s);
327 return;
328 }
329 switch (reg) {
330 case MII_BMCR:
331 re8139_reg = RTK_BMCR;
332 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) {
333 /* 8139C+ has different bit layout. */
334 data &= ~(BMCR_LOOP | BMCR_ISO);
335 }
336 break;
337 case MII_BMSR:
338 re8139_reg = RTK_BMSR;
339 break;
340 case MII_ANAR:
341 re8139_reg = RTK_ANAR;
342 break;
343 case MII_ANER:
344 re8139_reg = RTK_ANER;
345 break;
346 case MII_ANLPAR:
347 re8139_reg = RTK_LPAR;
348 break;
349 case MII_PHYIDR1:
350 case MII_PHYIDR2:
351 splx(s);
352 return;
353 break;
354 default:
355 printf("%s: bad phy register\n", device_xname(sc->sc_dev));
356 splx(s);
357 return;
358 }
359 CSR_WRITE_2(sc, re8139_reg, data);
360 splx(s);
361 return;
362 }
363
364 static void
365 re_miibus_statchg(device_t dev)
366 {
367
368 return;
369 }
370
371 static void
372 re_reset(struct rtk_softc *sc)
373 {
374 int i;
375
376 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET);
377
378 for (i = 0; i < RTK_TIMEOUT; i++) {
379 DELAY(10);
380 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
381 break;
382 }
383 if (i == RTK_TIMEOUT)
384 printf("%s: reset never completed!\n",
385 device_xname(sc->sc_dev));
386
387 /*
388 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3,
389 * but also says "Rtl8169s sigle chip detected".
390 */
391 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0)
392 CSR_WRITE_1(sc, RTK_LDPS, 1);
393
394 }
395
396 /*
397 * The following routine is designed to test for a defect on some
398 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
399 * lines connected to the bus, however for a 32-bit only card, they
400 * should be pulled high. The result of this defect is that the
401 * NIC will not work right if you plug it into a 64-bit slot: DMA
402 * operations will be done with 64-bit transfers, which will fail
403 * because the 64-bit data lines aren't connected.
404 *
405 * There's no way to work around this (short of talking a soldering
406 * iron to the board), however we can detect it. The method we use
407 * here is to put the NIC into digital loopback mode, set the receiver
408 * to promiscuous mode, and then try to send a frame. We then compare
409 * the frame data we sent to what was received. If the data matches,
410 * then the NIC is working correctly, otherwise we know the user has
411 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
412 * slot. In the latter case, there's no way the NIC can work correctly,
413 * so we print out a message on the console and abort the device attach.
414 */
415
416 int
417 re_diag(struct rtk_softc *sc)
418 {
419 struct ifnet *ifp = &sc->ethercom.ec_if;
420 struct mbuf *m0;
421 struct ether_header *eh;
422 struct re_rxsoft *rxs;
423 struct re_desc *cur_rx;
424 bus_dmamap_t dmamap;
425 uint16_t status;
426 uint32_t rxstat;
427 int total_len, i, s, error = 0;
428 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
429 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
430
431 /* Allocate a single mbuf */
432
433 MGETHDR(m0, M_DONTWAIT, MT_DATA);
434 if (m0 == NULL)
435 return ENOBUFS;
436
437 /*
438 * Initialize the NIC in test mode. This sets the chip up
439 * so that it can send and receive frames, but performs the
440 * following special functions:
441 * - Puts receiver in promiscuous mode
442 * - Enables digital loopback mode
443 * - Leaves interrupts turned off
444 */
445
446 ifp->if_flags |= IFF_PROMISC;
447 sc->re_testmode = 1;
448 re_init(ifp);
449 re_stop(ifp, 0);
450 DELAY(100000);
451 re_init(ifp);
452
453 /* Put some data in the mbuf */
454
455 eh = mtod(m0, struct ether_header *);
456 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN);
457 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN);
458 eh->ether_type = htons(ETHERTYPE_IP);
459 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
460
461 /*
462 * Queue the packet, start transmission.
463 */
464
465 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
466 s = splnet();
467 IF_ENQUEUE(&ifp->if_snd, m0);
468 re_start(ifp);
469 splx(s);
470 m0 = NULL;
471
472 /* Wait for it to propagate through the chip */
473
474 DELAY(100000);
475 for (i = 0; i < RTK_TIMEOUT; i++) {
476 status = CSR_READ_2(sc, RTK_ISR);
477 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) ==
478 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK))
479 break;
480 DELAY(10);
481 }
482 if (i == RTK_TIMEOUT) {
483 aprint_error_dev(sc->sc_dev,
484 "diagnostic failed, failed to receive packet "
485 "in loopback mode\n");
486 error = EIO;
487 goto done;
488 }
489
490 /*
491 * The packet should have been dumped into the first
492 * entry in the RX DMA ring. Grab it from there.
493 */
494
495 rxs = &sc->re_ldata.re_rxsoft[0];
496 dmamap = rxs->rxs_dmamap;
497 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
498 BUS_DMASYNC_POSTREAD);
499 bus_dmamap_unload(sc->sc_dmat, dmamap);
500
501 m0 = rxs->rxs_mbuf;
502 rxs->rxs_mbuf = NULL;
503 eh = mtod(m0, struct ether_header *);
504
505 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
506 cur_rx = &sc->re_ldata.re_rx_list[0];
507 rxstat = le32toh(cur_rx->re_cmdstat);
508 total_len = rxstat & sc->re_rxlenmask;
509
510 if (total_len != ETHER_MIN_LEN) {
511 aprint_error_dev(sc->sc_dev,
512 "diagnostic failed, received short packet\n");
513 error = EIO;
514 goto done;
515 }
516
517 /* Test that the received packet data matches what we sent. */
518
519 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
520 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
521 ntohs(eh->ether_type) != ETHERTYPE_IP) {
522 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n"
523 "expected TX data: %s/%s/0x%x\n"
524 "received RX data: %s/%s/0x%x\n"
525 "You may have a defective 32-bit NIC plugged "
526 "into a 64-bit PCI slot.\n"
527 "Please re-install the NIC in a 32-bit slot "
528 "for proper operation.\n"
529 "Read the re(4) man page for more details.\n" ,
530 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP,
531 ether_sprintf(eh->ether_dhost),
532 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type));
533 error = EIO;
534 }
535
536 done:
537 /* Turn interface off, release resources */
538
539 sc->re_testmode = 0;
540 ifp->if_flags &= ~IFF_PROMISC;
541 re_stop(ifp, 0);
542 if (m0 != NULL)
543 m_freem(m0);
544
545 return error;
546 }
547
548
549 /*
550 * Attach the interface. Allocate softc structures, do ifmedia
551 * setup and ethernet/BPF attach.
552 */
553 void
554 re_attach(struct rtk_softc *sc)
555 {
556 uint8_t eaddr[ETHER_ADDR_LEN];
557 uint16_t val;
558 struct ifnet *ifp;
559 int error = 0, i, addr_len;
560
561 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
562 uint32_t hwrev;
563
564 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */
565 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV;
566 switch (hwrev) {
567 case RTK_HWREV_8169:
568 sc->sc_quirk |= RTKQ_8169NONS;
569 break;
570 case RTK_HWREV_8169S:
571 case RTK_HWREV_8110S:
572 case RTK_HWREV_8169_8110SB:
573 case RTK_HWREV_8169_8110SBL:
574 case RTK_HWREV_8169_8110SC:
575 sc->sc_quirk |= RTKQ_MACLDPS;
576 break;
577 case RTK_HWREV_8168_SPIN1:
578 case RTK_HWREV_8168_SPIN2:
579 case RTK_HWREV_8168_SPIN3:
580 sc->sc_quirk |= RTKQ_MACSTAT;
581 break;
582 case RTK_HWREV_8168C:
583 case RTK_HWREV_8168C_SPIN2:
584 case RTK_HWREV_8168CP:
585 case RTK_HWREV_8168D:
586 case RTK_HWREV_8168DP:
587 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
588 RTKQ_MACSTAT | RTKQ_CMDSTOP;
589 /*
590 * From FreeBSD driver:
591 *
592 * These (8168/8111) controllers support jumbo frame
593 * but it seems that enabling it requires touching
594 * additional magic registers. Depending on MAC
595 * revisions some controllers need to disable
596 * checksum offload. So disable jumbo frame until
597 * I have better idea what it really requires to
598 * make it support.
599 * RTL8168C/CP : supports up to 6KB jumbo frame.
600 * RTL8111C/CP : supports up to 9KB jumbo frame.
601 */
602 sc->sc_quirk |= RTKQ_NOJUMBO;
603 break;
604 case RTK_HWREV_8168E:
605 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
606 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM |
607 RTKQ_NOJUMBO;
608 break;
609 case RTK_HWREV_8168E_VL:
610 case RTK_HWREV_8168F:
611 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
612 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
613 break;
614 case RTK_HWREV_8100E:
615 case RTK_HWREV_8100E_SPIN2:
616 case RTK_HWREV_8101E:
617 sc->sc_quirk |= RTKQ_NOJUMBO;
618 break;
619 case RTK_HWREV_8102E:
620 case RTK_HWREV_8102EL:
621 case RTK_HWREV_8103E:
622 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
623 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
624 break;
625 default:
626 aprint_normal_dev(sc->sc_dev,
627 "Unknown revision (0x%08x)\n", hwrev);
628 /* assume the latest features */
629 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD;
630 sc->sc_quirk |= RTKQ_NOJUMBO;
631 }
632
633 /* Set RX length mask */
634 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
635 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169;
636 } else {
637 sc->sc_quirk |= RTKQ_NOJUMBO;
638
639 /* Set RX length mask */
640 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
641 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139;
642 }
643
644 /* Reset the adapter. */
645 re_reset(sc);
646
647 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) {
648 /*
649 * Get station address from ID registers.
650 */
651 for (i = 0; i < ETHER_ADDR_LEN; i++)
652 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
653 } else {
654 /*
655 * Get station address from the EEPROM.
656 */
657 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129)
658 addr_len = RTK_EEADDR_LEN1;
659 else
660 addr_len = RTK_EEADDR_LEN0;
661
662 /*
663 * Get station address from the EEPROM.
664 */
665 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
666 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len);
667 eaddr[(i * 2) + 0] = val & 0xff;
668 eaddr[(i * 2) + 1] = val >> 8;
669 }
670 }
671
672 /* Take PHY out of power down mode. */
673 if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0)
674 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80);
675
676 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
677 ether_sprintf(eaddr));
678
679 if (sc->re_ldata.re_tx_desc_cnt >
680 PAGE_SIZE / sizeof(struct re_desc)) {
681 sc->re_ldata.re_tx_desc_cnt =
682 PAGE_SIZE / sizeof(struct re_desc);
683 }
684
685 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n",
686 sc->re_ldata.re_tx_desc_cnt);
687 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0);
688
689 /* Allocate DMA'able memory for the TX ring */
690 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc),
691 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1,
692 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) {
693 aprint_error_dev(sc->sc_dev,
694 "can't allocate tx listseg, error = %d\n", error);
695 goto fail_0;
696 }
697
698 /* Load the map for the TX ring. */
699 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg,
700 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc),
701 (void **)&sc->re_ldata.re_tx_list,
702 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
703 aprint_error_dev(sc->sc_dev,
704 "can't map tx list, error = %d\n", error);
705 goto fail_1;
706 }
707 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc));
708
709 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1,
710 RE_TX_LIST_SZ(sc), 0, 0,
711 &sc->re_ldata.re_tx_list_map)) != 0) {
712 aprint_error_dev(sc->sc_dev,
713 "can't create tx list map, error = %d\n", error);
714 goto fail_2;
715 }
716
717
718 if ((error = bus_dmamap_load(sc->sc_dmat,
719 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
720 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) {
721 aprint_error_dev(sc->sc_dev,
722 "can't load tx list, error = %d\n", error);
723 goto fail_3;
724 }
725
726 /* Create DMA maps for TX buffers */
727 for (i = 0; i < RE_TX_QLEN; i++) {
728 error = bus_dmamap_create(sc->sc_dmat,
729 round_page(IP_MAXPACKET),
730 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN,
731 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap);
732 if (error) {
733 aprint_error_dev(sc->sc_dev,
734 "can't create DMA map for TX\n");
735 goto fail_4;
736 }
737 }
738
739 /* Allocate DMA'able memory for the RX ring */
740 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */
741 if ((error = bus_dmamem_alloc(sc->sc_dmat,
742 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1,
743 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) {
744 aprint_error_dev(sc->sc_dev,
745 "can't allocate rx listseg, error = %d\n", error);
746 goto fail_4;
747 }
748
749 /* Load the map for the RX ring. */
750 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg,
751 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ,
752 (void **)&sc->re_ldata.re_rx_list,
753 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
754 aprint_error_dev(sc->sc_dev,
755 "can't map rx list, error = %d\n", error);
756 goto fail_5;
757 }
758 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ);
759
760 if ((error = bus_dmamap_create(sc->sc_dmat,
761 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0,
762 &sc->re_ldata.re_rx_list_map)) != 0) {
763 aprint_error_dev(sc->sc_dev,
764 "can't create rx list map, error = %d\n", error);
765 goto fail_6;
766 }
767
768 if ((error = bus_dmamap_load(sc->sc_dmat,
769 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
770 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) {
771 aprint_error_dev(sc->sc_dev,
772 "can't load rx list, error = %d\n", error);
773 goto fail_7;
774 }
775
776 /* Create DMA maps for RX buffers */
777 for (i = 0; i < RE_RX_DESC_CNT; i++) {
778 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
779 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap);
780 if (error) {
781 aprint_error_dev(sc->sc_dev,
782 "can't create DMA map for RX\n");
783 goto fail_8;
784 }
785 }
786
787 /*
788 * Record interface as attached. From here, we should not fail.
789 */
790 sc->sc_flags |= RTK_ATTACHED;
791
792 ifp = &sc->ethercom.ec_if;
793 ifp->if_softc = sc;
794 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
795 ifp->if_mtu = ETHERMTU;
796 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
797 ifp->if_ioctl = re_ioctl;
798 sc->ethercom.ec_capabilities |=
799 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
800 ifp->if_start = re_start;
801 ifp->if_stop = re_stop;
802
803 /*
804 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets,
805 * so we have a workaround to handle the bug by padding
806 * such packets manually.
807 */
808 ifp->if_capabilities |=
809 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
810 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
811 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
812 IFCAP_TSOv4;
813
814 /*
815 * XXX
816 * Still have no idea how to make TSO work on 8168C, 8168CP,
817 * 8102E, 8111C and 8111CP.
818 */
819 if ((sc->sc_quirk & RTKQ_DESCV2) != 0)
820 ifp->if_capabilities &= ~IFCAP_TSOv4;
821
822 ifp->if_watchdog = re_watchdog;
823 ifp->if_init = re_init;
824 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN;
825 ifp->if_capenable = ifp->if_capabilities;
826 IFQ_SET_READY(&ifp->if_snd);
827
828 callout_init(&sc->rtk_tick_ch, 0);
829
830 /* Do MII setup */
831 sc->mii.mii_ifp = ifp;
832 sc->mii.mii_readreg = re_miibus_readreg;
833 sc->mii.mii_writereg = re_miibus_writereg;
834 sc->mii.mii_statchg = re_miibus_statchg;
835 sc->ethercom.ec_mii = &sc->mii;
836 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange,
837 ether_mediastatus);
838 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY,
839 MII_OFFSET_ANY, 0);
840 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO);
841
842 /*
843 * Call MI attach routine.
844 */
845 if_attach(ifp);
846 ether_ifattach(ifp, eaddr);
847
848 if (pmf_device_register(sc->sc_dev, NULL, NULL))
849 pmf_class_network_register(sc->sc_dev, ifp);
850 else
851 aprint_error_dev(sc->sc_dev,
852 "couldn't establish power handler\n");
853
854 return;
855
856 fail_8:
857 /* Destroy DMA maps for RX buffers. */
858 for (i = 0; i < RE_RX_DESC_CNT; i++)
859 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL)
860 bus_dmamap_destroy(sc->sc_dmat,
861 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
862
863 /* Free DMA'able memory for the RX ring. */
864 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
865 fail_7:
866 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
867 fail_6:
868 bus_dmamem_unmap(sc->sc_dmat,
869 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ);
870 fail_5:
871 bus_dmamem_free(sc->sc_dmat,
872 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg);
873
874 fail_4:
875 /* Destroy DMA maps for TX buffers. */
876 for (i = 0; i < RE_TX_QLEN; i++)
877 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL)
878 bus_dmamap_destroy(sc->sc_dmat,
879 sc->re_ldata.re_txq[i].txq_dmamap);
880
881 /* Free DMA'able memory for the TX ring. */
882 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
883 fail_3:
884 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
885 fail_2:
886 bus_dmamem_unmap(sc->sc_dmat,
887 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
888 fail_1:
889 bus_dmamem_free(sc->sc_dmat,
890 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg);
891 fail_0:
892 return;
893 }
894
895
896 /*
897 * re_activate:
898 * Handle device activation/deactivation requests.
899 */
900 int
901 re_activate(device_t self, enum devact act)
902 {
903 struct rtk_softc *sc = device_private(self);
904
905 switch (act) {
906 case DVACT_DEACTIVATE:
907 if_deactivate(&sc->ethercom.ec_if);
908 return 0;
909 default:
910 return EOPNOTSUPP;
911 }
912 }
913
914 /*
915 * re_detach:
916 * Detach a rtk interface.
917 */
918 int
919 re_detach(struct rtk_softc *sc)
920 {
921 struct ifnet *ifp = &sc->ethercom.ec_if;
922 int i;
923
924 /*
925 * Succeed now if there isn't any work to do.
926 */
927 if ((sc->sc_flags & RTK_ATTACHED) == 0)
928 return 0;
929
930 /* Unhook our tick handler. */
931 callout_stop(&sc->rtk_tick_ch);
932
933 /* Detach all PHYs. */
934 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY);
935
936 /* Delete all remaining media. */
937 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY);
938
939 ether_ifdetach(ifp);
940 if_detach(ifp);
941
942 /* Destroy DMA maps for RX buffers. */
943 for (i = 0; i < RE_RX_DESC_CNT; i++)
944 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL)
945 bus_dmamap_destroy(sc->sc_dmat,
946 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
947
948 /* Free DMA'able memory for the RX ring. */
949 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
950 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
951 bus_dmamem_unmap(sc->sc_dmat,
952 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ);
953 bus_dmamem_free(sc->sc_dmat,
954 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg);
955
956 /* Destroy DMA maps for TX buffers. */
957 for (i = 0; i < RE_TX_QLEN; i++)
958 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL)
959 bus_dmamap_destroy(sc->sc_dmat,
960 sc->re_ldata.re_txq[i].txq_dmamap);
961
962 /* Free DMA'able memory for the TX ring. */
963 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
964 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
965 bus_dmamem_unmap(sc->sc_dmat,
966 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
967 bus_dmamem_free(sc->sc_dmat,
968 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg);
969
970 pmf_device_deregister(sc->sc_dev);
971
972 /* we don't want to run again */
973 sc->sc_flags &= ~RTK_ATTACHED;
974
975 return 0;
976 }
977
978 /*
979 * re_enable:
980 * Enable the RTL81X9 chip.
981 */
982 static int
983 re_enable(struct rtk_softc *sc)
984 {
985
986 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) {
987 if ((*sc->sc_enable)(sc) != 0) {
988 printf("%s: device enable failed\n",
989 device_xname(sc->sc_dev));
990 return EIO;
991 }
992 sc->sc_flags |= RTK_ENABLED;
993 }
994 return 0;
995 }
996
997 /*
998 * re_disable:
999 * Disable the RTL81X9 chip.
1000 */
1001 static void
1002 re_disable(struct rtk_softc *sc)
1003 {
1004
1005 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) {
1006 (*sc->sc_disable)(sc);
1007 sc->sc_flags &= ~RTK_ENABLED;
1008 }
1009 }
1010
1011 static int
1012 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m)
1013 {
1014 struct mbuf *n = NULL;
1015 bus_dmamap_t map;
1016 struct re_desc *d;
1017 struct re_rxsoft *rxs;
1018 uint32_t cmdstat;
1019 int error;
1020
1021 if (m == NULL) {
1022 MGETHDR(n, M_DONTWAIT, MT_DATA);
1023 if (n == NULL)
1024 return ENOBUFS;
1025
1026 MCLGET(n, M_DONTWAIT);
1027 if ((n->m_flags & M_EXT) == 0) {
1028 m_freem(n);
1029 return ENOBUFS;
1030 }
1031 m = n;
1032 } else
1033 m->m_data = m->m_ext.ext_buf;
1034
1035 /*
1036 * Initialize mbuf length fields and fixup
1037 * alignment so that the frame payload is
1038 * longword aligned.
1039 */
1040 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN;
1041 m->m_data += RE_ETHER_ALIGN;
1042
1043 rxs = &sc->re_ldata.re_rxsoft[idx];
1044 map = rxs->rxs_dmamap;
1045 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
1046 BUS_DMA_READ|BUS_DMA_NOWAIT);
1047
1048 if (error)
1049 goto out;
1050
1051 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1052 BUS_DMASYNC_PREREAD);
1053
1054 d = &sc->re_ldata.re_rx_list[idx];
1055 #ifdef DIAGNOSTIC
1056 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1057 cmdstat = le32toh(d->re_cmdstat);
1058 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1059 if (cmdstat & RE_RDESC_STAT_OWN) {
1060 panic("%s: tried to map busy RX descriptor",
1061 device_xname(sc->sc_dev));
1062 }
1063 #endif
1064
1065 rxs->rxs_mbuf = m;
1066
1067 d->re_vlanctl = 0;
1068 cmdstat = map->dm_segs[0].ds_len;
1069 if (idx == (RE_RX_DESC_CNT - 1))
1070 cmdstat |= RE_RDESC_CMD_EOR;
1071 re_set_bufaddr(d, map->dm_segs[0].ds_addr);
1072 d->re_cmdstat = htole32(cmdstat);
1073 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1074 cmdstat |= RE_RDESC_CMD_OWN;
1075 d->re_cmdstat = htole32(cmdstat);
1076 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1077
1078 return 0;
1079 out:
1080 if (n != NULL)
1081 m_freem(n);
1082 return ENOMEM;
1083 }
1084
1085 static int
1086 re_tx_list_init(struct rtk_softc *sc)
1087 {
1088 int i;
1089
1090 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc));
1091 for (i = 0; i < RE_TX_QLEN; i++) {
1092 sc->re_ldata.re_txq[i].txq_mbuf = NULL;
1093 }
1094
1095 bus_dmamap_sync(sc->sc_dmat,
1096 sc->re_ldata.re_tx_list_map, 0,
1097 sc->re_ldata.re_tx_list_map->dm_mapsize,
1098 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1099 sc->re_ldata.re_txq_prodidx = 0;
1100 sc->re_ldata.re_txq_considx = 0;
1101 sc->re_ldata.re_txq_free = RE_TX_QLEN;
1102 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc);
1103 sc->re_ldata.re_tx_nextfree = 0;
1104
1105 return 0;
1106 }
1107
1108 static int
1109 re_rx_list_init(struct rtk_softc *sc)
1110 {
1111 int i;
1112
1113 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ);
1114
1115 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1116 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1117 return ENOBUFS;
1118 }
1119
1120 sc->re_ldata.re_rx_prodidx = 0;
1121 sc->re_head = sc->re_tail = NULL;
1122
1123 return 0;
1124 }
1125
1126 /*
1127 * RX handler for C+ and 8169. For the gigE chips, we support
1128 * the reception of jumbo frames that have been fragmented
1129 * across multiple 2K mbuf cluster buffers.
1130 */
1131 static void
1132 re_rxeof(struct rtk_softc *sc)
1133 {
1134 struct mbuf *m;
1135 struct ifnet *ifp;
1136 int i, total_len;
1137 struct re_desc *cur_rx;
1138 struct re_rxsoft *rxs;
1139 uint32_t rxstat, rxvlan;
1140
1141 ifp = &sc->ethercom.ec_if;
1142
1143 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) {
1144 cur_rx = &sc->re_ldata.re_rx_list[i];
1145 RE_RXDESCSYNC(sc, i,
1146 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1147 rxstat = le32toh(cur_rx->re_cmdstat);
1148 rxvlan = le32toh(cur_rx->re_vlanctl);
1149 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD);
1150 if ((rxstat & RE_RDESC_STAT_OWN) != 0) {
1151 break;
1152 }
1153 total_len = rxstat & sc->re_rxlenmask;
1154 rxs = &sc->re_ldata.re_rxsoft[i];
1155 m = rxs->rxs_mbuf;
1156
1157 /* Invalidate the RX mbuf and unload its map */
1158
1159 bus_dmamap_sync(sc->sc_dmat,
1160 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize,
1161 BUS_DMASYNC_POSTREAD);
1162 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
1163
1164 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1165 m->m_len = MCLBYTES - RE_ETHER_ALIGN;
1166 if (sc->re_head == NULL)
1167 sc->re_head = sc->re_tail = m;
1168 else {
1169 m->m_flags &= ~M_PKTHDR;
1170 sc->re_tail->m_next = m;
1171 sc->re_tail = m;
1172 }
1173 re_newbuf(sc, i, NULL);
1174 continue;
1175 }
1176
1177 /*
1178 * NOTE: for the 8139C+, the frame length field
1179 * is always 12 bits in size, but for the gigE chips,
1180 * it is 13 bits (since the max RX frame length is 16K).
1181 * Unfortunately, all 32 bits in the status word
1182 * were already used, so to make room for the extra
1183 * length bit, RealTek took out the 'frame alignment
1184 * error' bit and shifted the other status bits
1185 * over one slot. The OWN, EOR, FS and LS bits are
1186 * still in the same places. We have already extracted
1187 * the frame length and checked the OWN bit, so rather
1188 * than using an alternate bit mapping, we shift the
1189 * status bits one space to the right so we can evaluate
1190 * them using the 8169 status as though it was in the
1191 * same format as that of the 8139C+.
1192 */
1193 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
1194 rxstat >>= 1;
1195
1196 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) {
1197 #ifdef RE_DEBUG
1198 printf("%s: RX error (rxstat = 0x%08x)",
1199 device_xname(sc->sc_dev), rxstat);
1200 if (rxstat & RE_RDESC_STAT_FRALIGN)
1201 printf(", frame alignment error");
1202 if (rxstat & RE_RDESC_STAT_BUFOFLOW)
1203 printf(", out of buffer space");
1204 if (rxstat & RE_RDESC_STAT_FIFOOFLOW)
1205 printf(", FIFO overrun");
1206 if (rxstat & RE_RDESC_STAT_GIANT)
1207 printf(", giant packet");
1208 if (rxstat & RE_RDESC_STAT_RUNT)
1209 printf(", runt packet");
1210 if (rxstat & RE_RDESC_STAT_CRCERR)
1211 printf(", CRC error");
1212 printf("\n");
1213 #endif
1214 ifp->if_ierrors++;
1215 /*
1216 * If this is part of a multi-fragment packet,
1217 * discard all the pieces.
1218 */
1219 if (sc->re_head != NULL) {
1220 m_freem(sc->re_head);
1221 sc->re_head = sc->re_tail = NULL;
1222 }
1223 re_newbuf(sc, i, m);
1224 continue;
1225 }
1226
1227 /*
1228 * If allocating a replacement mbuf fails,
1229 * reload the current one.
1230 */
1231
1232 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) {
1233 ifp->if_ierrors++;
1234 if (sc->re_head != NULL) {
1235 m_freem(sc->re_head);
1236 sc->re_head = sc->re_tail = NULL;
1237 }
1238 re_newbuf(sc, i, m);
1239 continue;
1240 }
1241
1242 if (sc->re_head != NULL) {
1243 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN);
1244 /*
1245 * Special case: if there's 4 bytes or less
1246 * in this buffer, the mbuf can be discarded:
1247 * the last 4 bytes is the CRC, which we don't
1248 * care about anyway.
1249 */
1250 if (m->m_len <= ETHER_CRC_LEN) {
1251 sc->re_tail->m_len -=
1252 (ETHER_CRC_LEN - m->m_len);
1253 m_freem(m);
1254 } else {
1255 m->m_len -= ETHER_CRC_LEN;
1256 m->m_flags &= ~M_PKTHDR;
1257 sc->re_tail->m_next = m;
1258 }
1259 m = sc->re_head;
1260 sc->re_head = sc->re_tail = NULL;
1261 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1262 } else
1263 m->m_pkthdr.len = m->m_len =
1264 (total_len - ETHER_CRC_LEN);
1265
1266 ifp->if_ipackets++;
1267 m->m_pkthdr.rcvif = ifp;
1268
1269 /* Do RX checksumming */
1270 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
1271 /* Check IP header checksum */
1272 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) {
1273 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1274 if (rxstat & RE_RDESC_STAT_IPSUMBAD)
1275 m->m_pkthdr.csum_flags |=
1276 M_CSUM_IPv4_BAD;
1277
1278 /* Check TCP/UDP checksum */
1279 if (RE_TCPPKT(rxstat)) {
1280 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1281 if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
1282 m->m_pkthdr.csum_flags |=
1283 M_CSUM_TCP_UDP_BAD;
1284 } else if (RE_UDPPKT(rxstat)) {
1285 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1286 if (rxstat & RE_RDESC_STAT_UDPSUMBAD)
1287 m->m_pkthdr.csum_flags |=
1288 M_CSUM_TCP_UDP_BAD;
1289 }
1290 }
1291 } else {
1292 /* Check IPv4 header checksum */
1293 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) {
1294 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1295 if (rxstat & RE_RDESC_STAT_IPSUMBAD)
1296 m->m_pkthdr.csum_flags |=
1297 M_CSUM_IPv4_BAD;
1298
1299 /* Check TCPv4/UDPv4 checksum */
1300 if (RE_TCPPKT(rxstat)) {
1301 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1302 if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
1303 m->m_pkthdr.csum_flags |=
1304 M_CSUM_TCP_UDP_BAD;
1305 } else if (RE_UDPPKT(rxstat)) {
1306 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1307 if (rxstat & RE_RDESC_STAT_UDPSUMBAD)
1308 m->m_pkthdr.csum_flags |=
1309 M_CSUM_TCP_UDP_BAD;
1310 }
1311 }
1312 /* XXX Check TCPv6/UDPv6 checksum? */
1313 }
1314
1315 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1316 VLAN_INPUT_TAG(ifp, m,
1317 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA),
1318 continue);
1319 }
1320 bpf_mtap(ifp, m);
1321 (*ifp->if_input)(ifp, m);
1322 }
1323
1324 sc->re_ldata.re_rx_prodidx = i;
1325 }
1326
1327 static void
1328 re_txeof(struct rtk_softc *sc)
1329 {
1330 struct ifnet *ifp;
1331 struct re_txq *txq;
1332 uint32_t txstat;
1333 int idx, descidx;
1334
1335 ifp = &sc->ethercom.ec_if;
1336
1337 for (idx = sc->re_ldata.re_txq_considx;
1338 sc->re_ldata.re_txq_free < RE_TX_QLEN;
1339 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) {
1340 txq = &sc->re_ldata.re_txq[idx];
1341 KASSERT(txq->txq_mbuf != NULL);
1342
1343 descidx = txq->txq_descidx;
1344 RE_TXDESCSYNC(sc, descidx,
1345 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1346 txstat =
1347 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat);
1348 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD);
1349 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0);
1350 if (txstat & RE_TDESC_CMD_OWN) {
1351 break;
1352 }
1353
1354 sc->re_ldata.re_tx_free += txq->txq_nsegs;
1355 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc));
1356 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap,
1357 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1358 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap);
1359 m_freem(txq->txq_mbuf);
1360 txq->txq_mbuf = NULL;
1361
1362 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT))
1363 ifp->if_collisions++;
1364 if (txstat & RE_TDESC_STAT_TXERRSUM)
1365 ifp->if_oerrors++;
1366 else
1367 ifp->if_opackets++;
1368 }
1369
1370 sc->re_ldata.re_txq_considx = idx;
1371
1372 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD)
1373 ifp->if_flags &= ~IFF_OACTIVE;
1374
1375 /*
1376 * If not all descriptors have been released reaped yet,
1377 * reload the timer so that we will eventually get another
1378 * interrupt that will cause us to re-enter this routine.
1379 * This is done in case the transmitter has gone idle.
1380 */
1381 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) {
1382 CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
1383 if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
1384 /*
1385 * Some chips will ignore a second TX request
1386 * issued while an existing transmission is in
1387 * progress. If the transmitter goes idle but
1388 * there are still packets waiting to be sent,
1389 * we need to restart the channel here to flush
1390 * them out. This only seems to be required with
1391 * the PCIe devices.
1392 */
1393 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
1394 }
1395 } else
1396 ifp->if_timer = 0;
1397 }
1398
1399 static void
1400 re_tick(void *arg)
1401 {
1402 struct rtk_softc *sc = arg;
1403 int s;
1404
1405 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */
1406 s = splnet();
1407
1408 mii_tick(&sc->mii);
1409 splx(s);
1410
1411 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc);
1412 }
1413
1414 int
1415 re_intr(void *arg)
1416 {
1417 struct rtk_softc *sc = arg;
1418 struct ifnet *ifp;
1419 uint16_t status;
1420 int handled = 0;
1421
1422 if (!device_has_power(sc->sc_dev))
1423 return 0;
1424
1425 ifp = &sc->ethercom.ec_if;
1426
1427 if ((ifp->if_flags & IFF_UP) == 0)
1428 return 0;
1429
1430 for (;;) {
1431
1432 status = CSR_READ_2(sc, RTK_ISR);
1433 /* If the card has gone away the read returns 0xffff. */
1434 if (status == 0xffff)
1435 break;
1436 if (status) {
1437 handled = 1;
1438 CSR_WRITE_2(sc, RTK_ISR, status);
1439 }
1440
1441 if ((status & RTK_INTRS_CPLUS) == 0)
1442 break;
1443
1444 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR))
1445 re_rxeof(sc);
1446
1447 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR |
1448 RTK_ISR_TX_DESC_UNAVAIL))
1449 re_txeof(sc);
1450
1451 if (status & RTK_ISR_SYSTEM_ERR) {
1452 re_init(ifp);
1453 }
1454
1455 if (status & RTK_ISR_LINKCHG) {
1456 callout_stop(&sc->rtk_tick_ch);
1457 re_tick(sc);
1458 }
1459 }
1460
1461 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd))
1462 re_start(ifp);
1463
1464 return handled;
1465 }
1466
1467
1468
1469 /*
1470 * Main transmit routine for C+ and gigE NICs.
1471 */
1472
1473 static void
1474 re_start(struct ifnet *ifp)
1475 {
1476 struct rtk_softc *sc;
1477 struct mbuf *m;
1478 bus_dmamap_t map;
1479 struct re_txq *txq;
1480 struct re_desc *d;
1481 struct m_tag *mtag;
1482 uint32_t cmdstat, re_flags, vlanctl;
1483 int ofree, idx, error, nsegs, seg;
1484 int startdesc, curdesc, lastdesc;
1485 bool pad;
1486
1487 sc = ifp->if_softc;
1488 ofree = sc->re_ldata.re_txq_free;
1489
1490 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) {
1491
1492 IFQ_POLL(&ifp->if_snd, m);
1493 if (m == NULL)
1494 break;
1495
1496 if (sc->re_ldata.re_txq_free == 0 ||
1497 sc->re_ldata.re_tx_free == 0) {
1498 /* no more free slots left */
1499 ifp->if_flags |= IFF_OACTIVE;
1500 break;
1501 }
1502
1503 /*
1504 * Set up checksum offload. Note: checksum offload bits must
1505 * appear in all descriptors of a multi-descriptor transmit
1506 * attempt. (This is according to testing done with an 8169
1507 * chip. I'm not sure if this is a requirement or a bug.)
1508 */
1509
1510 vlanctl = 0;
1511 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) {
1512 uint32_t segsz = m->m_pkthdr.segsz;
1513
1514 re_flags = RE_TDESC_CMD_LGSEND |
1515 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT);
1516 } else {
1517 /*
1518 * set RE_TDESC_CMD_IPCSUM if any checksum offloading
1519 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/
1520 * RE_TDESC_CMD_UDPCSUM doesn't make effects.
1521 */
1522 re_flags = 0;
1523 if ((m->m_pkthdr.csum_flags &
1524 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4))
1525 != 0) {
1526 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
1527 re_flags |= RE_TDESC_CMD_IPCSUM;
1528 if (m->m_pkthdr.csum_flags &
1529 M_CSUM_TCPv4) {
1530 re_flags |=
1531 RE_TDESC_CMD_TCPCSUM;
1532 } else if (m->m_pkthdr.csum_flags &
1533 M_CSUM_UDPv4) {
1534 re_flags |=
1535 RE_TDESC_CMD_UDPCSUM;
1536 }
1537 } else {
1538 vlanctl |= RE_TDESC_VLANCTL_IPCSUM;
1539 if (m->m_pkthdr.csum_flags &
1540 M_CSUM_TCPv4) {
1541 vlanctl |=
1542 RE_TDESC_VLANCTL_TCPCSUM;
1543 } else if (m->m_pkthdr.csum_flags &
1544 M_CSUM_UDPv4) {
1545 vlanctl |=
1546 RE_TDESC_VLANCTL_UDPCSUM;
1547 }
1548 }
1549 }
1550 }
1551
1552 txq = &sc->re_ldata.re_txq[idx];
1553 map = txq->txq_dmamap;
1554 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
1555 BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1556
1557 if (__predict_false(error)) {
1558 /* XXX try to defrag if EFBIG? */
1559 printf("%s: can't map mbuf (error %d)\n",
1560 device_xname(sc->sc_dev), error);
1561
1562 IFQ_DEQUEUE(&ifp->if_snd, m);
1563 m_freem(m);
1564 ifp->if_oerrors++;
1565 continue;
1566 }
1567
1568 nsegs = map->dm_nsegs;
1569 pad = false;
1570 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN &&
1571 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 &&
1572 (sc->sc_quirk & RTKQ_DESCV2) == 0)) {
1573 pad = true;
1574 nsegs++;
1575 }
1576
1577 if (nsegs > sc->re_ldata.re_tx_free) {
1578 /*
1579 * Not enough free descriptors to transmit this packet.
1580 */
1581 ifp->if_flags |= IFF_OACTIVE;
1582 bus_dmamap_unload(sc->sc_dmat, map);
1583 break;
1584 }
1585
1586 IFQ_DEQUEUE(&ifp->if_snd, m);
1587
1588 /*
1589 * Make sure that the caches are synchronized before we
1590 * ask the chip to start DMA for the packet data.
1591 */
1592 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1593 BUS_DMASYNC_PREWRITE);
1594
1595 /*
1596 * Set up hardware VLAN tagging. Note: vlan tag info must
1597 * appear in all descriptors of a multi-descriptor
1598 * transmission attempt.
1599 */
1600 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL)
1601 vlanctl |= bswap16(VLAN_TAG_VALUE(mtag)) |
1602 RE_TDESC_VLANCTL_TAG;
1603
1604 /*
1605 * Map the segment array into descriptors.
1606 * Note that we set the start-of-frame and
1607 * end-of-frame markers for either TX or RX,
1608 * but they really only have meaning in the TX case.
1609 * (In the RX case, it's the chip that tells us
1610 * where packets begin and end.)
1611 * We also keep track of the end of the ring
1612 * and set the end-of-ring bits as needed,
1613 * and we set the ownership bits in all except
1614 * the very first descriptor. (The caller will
1615 * set this descriptor later when it start
1616 * transmission or reception.)
1617 */
1618 curdesc = startdesc = sc->re_ldata.re_tx_nextfree;
1619 lastdesc = -1;
1620 for (seg = 0; seg < map->dm_nsegs;
1621 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) {
1622 d = &sc->re_ldata.re_tx_list[curdesc];
1623 #ifdef DIAGNOSTIC
1624 RE_TXDESCSYNC(sc, curdesc,
1625 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1626 cmdstat = le32toh(d->re_cmdstat);
1627 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD);
1628 if (cmdstat & RE_TDESC_STAT_OWN) {
1629 panic("%s: tried to map busy TX descriptor",
1630 device_xname(sc->sc_dev));
1631 }
1632 #endif
1633
1634 d->re_vlanctl = htole32(vlanctl);
1635 re_set_bufaddr(d, map->dm_segs[seg].ds_addr);
1636 cmdstat = re_flags | map->dm_segs[seg].ds_len;
1637 if (seg == 0)
1638 cmdstat |= RE_TDESC_CMD_SOF;
1639 else
1640 cmdstat |= RE_TDESC_CMD_OWN;
1641 if (curdesc == (RE_TX_DESC_CNT(sc) - 1))
1642 cmdstat |= RE_TDESC_CMD_EOR;
1643 if (seg == nsegs - 1) {
1644 cmdstat |= RE_TDESC_CMD_EOF;
1645 lastdesc = curdesc;
1646 }
1647 d->re_cmdstat = htole32(cmdstat);
1648 RE_TXDESCSYNC(sc, curdesc,
1649 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1650 }
1651 if (__predict_false(pad)) {
1652 d = &sc->re_ldata.re_tx_list[curdesc];
1653 d->re_vlanctl = htole32(vlanctl);
1654 re_set_bufaddr(d, RE_TXPADDADDR(sc));
1655 cmdstat = re_flags |
1656 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF |
1657 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len);
1658 if (curdesc == (RE_TX_DESC_CNT(sc) - 1))
1659 cmdstat |= RE_TDESC_CMD_EOR;
1660 d->re_cmdstat = htole32(cmdstat);
1661 RE_TXDESCSYNC(sc, curdesc,
1662 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1663 lastdesc = curdesc;
1664 curdesc = RE_NEXT_TX_DESC(sc, curdesc);
1665 }
1666 KASSERT(lastdesc != -1);
1667
1668 /* Transfer ownership of packet to the chip. */
1669
1670 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |=
1671 htole32(RE_TDESC_CMD_OWN);
1672 RE_TXDESCSYNC(sc, startdesc,
1673 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1674
1675 /* update info of TX queue and descriptors */
1676 txq->txq_mbuf = m;
1677 txq->txq_descidx = lastdesc;
1678 txq->txq_nsegs = nsegs;
1679
1680 sc->re_ldata.re_txq_free--;
1681 sc->re_ldata.re_tx_free -= nsegs;
1682 sc->re_ldata.re_tx_nextfree = curdesc;
1683
1684 /*
1685 * If there's a BPF listener, bounce a copy of this frame
1686 * to him.
1687 */
1688 bpf_mtap(ifp, m);
1689 }
1690
1691 if (sc->re_ldata.re_txq_free < ofree) {
1692 /*
1693 * TX packets are enqueued.
1694 */
1695 sc->re_ldata.re_txq_prodidx = idx;
1696
1697 /*
1698 * Start the transmitter to poll.
1699 *
1700 * RealTek put the TX poll request register in a different
1701 * location on the 8169 gigE chip. I don't know why.
1702 */
1703 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
1704 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START);
1705 else
1706 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
1707
1708 /*
1709 * Use the countdown timer for interrupt moderation.
1710 * 'TX done' interrupts are disabled. Instead, we reset the
1711 * countdown timer, which will begin counting until it hits
1712 * the value in the TIMERINT register, and then trigger an
1713 * interrupt. Each time we write to the TIMERCNT register,
1714 * the timer count is reset to 0.
1715 */
1716 CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
1717
1718 /*
1719 * Set a timeout in case the chip goes out to lunch.
1720 */
1721 ifp->if_timer = 5;
1722 }
1723 }
1724
1725 static int
1726 re_init(struct ifnet *ifp)
1727 {
1728 struct rtk_softc *sc = ifp->if_softc;
1729 const uint8_t *enaddr;
1730 uint32_t rxcfg = 0;
1731 uint32_t reg;
1732 uint16_t cfg;
1733 int error;
1734
1735 if ((error = re_enable(sc)) != 0)
1736 goto out;
1737
1738 /*
1739 * Cancel pending I/O and free all RX/TX buffers.
1740 */
1741 re_stop(ifp, 0);
1742
1743 re_reset(sc);
1744
1745 /*
1746 * Enable C+ RX and TX mode, as well as VLAN stripping and
1747 * RX checksum offload. We must configure the C+ register
1748 * before all others.
1749 */
1750 cfg = RE_CPLUSCMD_PCI_MRW;
1751
1752 /*
1753 * XXX: For old 8169 set bit 14.
1754 * For 8169S/8110S and above, do not set bit 14.
1755 */
1756 if ((sc->sc_quirk & RTKQ_8169NONS) != 0)
1757 cfg |= (0x1 << 14);
1758
1759 if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0)
1760 cfg |= RE_CPLUSCMD_VLANSTRIP;
1761 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx |
1762 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0)
1763 cfg |= RE_CPLUSCMD_RXCSUM_ENB;
1764 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) {
1765 cfg |= RE_CPLUSCMD_MACSTAT_DIS;
1766 cfg |= RE_CPLUSCMD_TXENB;
1767 } else
1768 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB;
1769
1770 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
1771
1772 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */
1773 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
1774 CSR_WRITE_2(sc, RTK_IM, 0x0000);
1775
1776 DELAY(10000);
1777
1778 /*
1779 * Init our MAC address. Even though the chipset
1780 * documentation doesn't mention it, we need to enter "Config
1781 * register write enable" mode to modify the ID registers.
1782 */
1783 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG);
1784 enaddr = CLLADDR(ifp->if_sadl);
1785 reg = enaddr[0] | (enaddr[1] << 8) |
1786 (enaddr[2] << 16) | (enaddr[3] << 24);
1787 CSR_WRITE_4(sc, RTK_IDR0, reg);
1788 reg = enaddr[4] | (enaddr[5] << 8);
1789 CSR_WRITE_4(sc, RTK_IDR4, reg);
1790 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
1791
1792 /*
1793 * For C+ mode, initialize the RX descriptors and mbufs.
1794 */
1795 re_rx_list_init(sc);
1796 re_tx_list_init(sc);
1797
1798 /*
1799 * Load the addresses of the RX and TX lists into the chip.
1800 */
1801 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI,
1802 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr));
1803 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO,
1804 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr));
1805
1806 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI,
1807 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
1808 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO,
1809 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
1810
1811 /*
1812 * Enable transmit and receive.
1813 */
1814 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
1815
1816 /*
1817 * Set the initial TX and RX configuration.
1818 */
1819 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) {
1820 /* test mode is needed only for old 8169 */
1821 CSR_WRITE_4(sc, RTK_TXCFG,
1822 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON);
1823 } else
1824 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG);
1825
1826 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16);
1827
1828 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG);
1829
1830 /* Set the individual bit to receive frames for this host only. */
1831 rxcfg = CSR_READ_4(sc, RTK_RXCFG);
1832 rxcfg |= RTK_RXCFG_RX_INDIV;
1833
1834 /* If we want promiscuous mode, set the allframes bit. */
1835 if (ifp->if_flags & IFF_PROMISC)
1836 rxcfg |= RTK_RXCFG_RX_ALLPHYS;
1837 else
1838 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS;
1839 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1840
1841 /*
1842 * Set capture broadcast bit to capture broadcast frames.
1843 */
1844 if (ifp->if_flags & IFF_BROADCAST)
1845 rxcfg |= RTK_RXCFG_RX_BROAD;
1846 else
1847 rxcfg &= ~RTK_RXCFG_RX_BROAD;
1848 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1849
1850 /*
1851 * Program the multicast filter, if necessary.
1852 */
1853 rtk_setmulti(sc);
1854
1855 /*
1856 * Enable interrupts.
1857 */
1858 if (sc->re_testmode)
1859 CSR_WRITE_2(sc, RTK_IMR, 0);
1860 else
1861 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS);
1862
1863 /* Start RX/TX process. */
1864 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0);
1865 #ifdef notdef
1866 /* Enable receiver and transmitter. */
1867 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
1868 #endif
1869
1870 /*
1871 * Initialize the timer interrupt register so that
1872 * a timer interrupt will be generated once the timer
1873 * reaches a certain number of ticks. The timer is
1874 * reloaded on each transmit. This gives us TX interrupt
1875 * moderation, which dramatically improves TX frame rate.
1876 */
1877
1878 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
1879 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400);
1880 else {
1881 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800);
1882
1883 /*
1884 * For 8169 gigE NICs, set the max allowed RX packet
1885 * size so we can receive jumbo frames.
1886 */
1887 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383);
1888 }
1889
1890 if (sc->re_testmode)
1891 return 0;
1892
1893 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD);
1894
1895 ifp->if_flags |= IFF_RUNNING;
1896 ifp->if_flags &= ~IFF_OACTIVE;
1897
1898 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc);
1899
1900 out:
1901 if (error) {
1902 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1903 ifp->if_timer = 0;
1904 printf("%s: interface not running\n",
1905 device_xname(sc->sc_dev));
1906 }
1907
1908 return error;
1909 }
1910
1911 static int
1912 re_ioctl(struct ifnet *ifp, u_long command, void *data)
1913 {
1914 struct rtk_softc *sc = ifp->if_softc;
1915 struct ifreq *ifr = data;
1916 int s, error = 0;
1917
1918 s = splnet();
1919
1920 switch (command) {
1921 case SIOCSIFMTU:
1922 /*
1923 * Disable jumbo frames if it's not supported.
1924 */
1925 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 &&
1926 ifr->ifr_mtu > ETHERMTU) {
1927 error = EINVAL;
1928 break;
1929 }
1930
1931 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO)
1932 error = EINVAL;
1933 else if ((error = ifioctl_common(ifp, command, data)) ==
1934 ENETRESET)
1935 error = 0;
1936 break;
1937 default:
1938 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
1939 break;
1940
1941 error = 0;
1942
1943 if (command == SIOCSIFCAP)
1944 error = (*ifp->if_init)(ifp);
1945 else if (command != SIOCADDMULTI && command != SIOCDELMULTI)
1946 ;
1947 else if (ifp->if_flags & IFF_RUNNING)
1948 rtk_setmulti(sc);
1949 break;
1950 }
1951
1952 splx(s);
1953
1954 return error;
1955 }
1956
1957 static void
1958 re_watchdog(struct ifnet *ifp)
1959 {
1960 struct rtk_softc *sc;
1961 int s;
1962
1963 sc = ifp->if_softc;
1964 s = splnet();
1965 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
1966 ifp->if_oerrors++;
1967
1968 re_txeof(sc);
1969 re_rxeof(sc);
1970
1971 re_init(ifp);
1972
1973 splx(s);
1974 }
1975
1976 /*
1977 * Stop the adapter and free any mbufs allocated to the
1978 * RX and TX lists.
1979 */
1980 static void
1981 re_stop(struct ifnet *ifp, int disable)
1982 {
1983 int i;
1984 struct rtk_softc *sc = ifp->if_softc;
1985
1986 callout_stop(&sc->rtk_tick_ch);
1987
1988 mii_down(&sc->mii);
1989
1990 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0)
1991 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB |
1992 RTK_CMD_RX_ENB);
1993 else
1994 CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
1995 DELAY(1000);
1996 CSR_WRITE_2(sc, RTK_IMR, 0x0000);
1997 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
1998
1999 if (sc->re_head != NULL) {
2000 m_freem(sc->re_head);
2001 sc->re_head = sc->re_tail = NULL;
2002 }
2003
2004 /* Free the TX list buffers. */
2005 for (i = 0; i < RE_TX_QLEN; i++) {
2006 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) {
2007 bus_dmamap_unload(sc->sc_dmat,
2008 sc->re_ldata.re_txq[i].txq_dmamap);
2009 m_freem(sc->re_ldata.re_txq[i].txq_mbuf);
2010 sc->re_ldata.re_txq[i].txq_mbuf = NULL;
2011 }
2012 }
2013
2014 /* Free the RX list buffers. */
2015 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2016 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) {
2017 bus_dmamap_unload(sc->sc_dmat,
2018 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
2019 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf);
2020 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL;
2021 }
2022 }
2023
2024 if (disable)
2025 re_disable(sc);
2026
2027 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2028 ifp->if_timer = 0;
2029 }
2030