rtl8169.c revision 1.134.4.3
1 /* $NetBSD: rtl8169.c,v 1.134.4.3 2013/09/18 20:00:53 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.134.4.3 2013/09/18 20:00:53 bouyer Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul (at) windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * six devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168 and the RTL8111. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/kernel.h> 122 #include <sys/socket.h> 123 #include <sys/device.h> 124 125 #include <net/if.h> 126 #include <net/if_arp.h> 127 #include <net/if_dl.h> 128 #include <net/if_ether.h> 129 #include <net/if_media.h> 130 #include <net/if_vlanvar.h> 131 132 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 133 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 134 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 135 136 #include <net/bpf.h> 137 138 #include <sys/bus.h> 139 140 #include <dev/mii/mii.h> 141 #include <dev/mii/miivar.h> 142 143 #include <dev/ic/rtl81x9reg.h> 144 #include <dev/ic/rtl81x9var.h> 145 146 #include <dev/ic/rtl8169var.h> 147 148 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 149 150 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 151 static int re_rx_list_init(struct rtk_softc *); 152 static int re_tx_list_init(struct rtk_softc *); 153 static void re_rxeof(struct rtk_softc *); 154 static void re_txeof(struct rtk_softc *); 155 static void re_tick(void *); 156 static void re_start(struct ifnet *); 157 static int re_ioctl(struct ifnet *, u_long, void *); 158 static int re_init(struct ifnet *); 159 static void re_stop(struct ifnet *, int); 160 static void re_watchdog(struct ifnet *); 161 162 static int re_enable(struct rtk_softc *); 163 static void re_disable(struct rtk_softc *); 164 165 static int re_gmii_readreg(device_t, int, int); 166 static void re_gmii_writereg(device_t, int, int, int); 167 168 static int re_miibus_readreg(device_t, int, int); 169 static void re_miibus_writereg(device_t, int, int, int); 170 static void re_miibus_statchg(device_t); 171 172 static void re_reset(struct rtk_softc *); 173 174 static inline void 175 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 176 { 177 178 d->re_bufaddr_lo = htole32((uint32_t)addr); 179 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 180 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32); 181 else 182 d->re_bufaddr_hi = 0; 183 } 184 185 static int 186 re_gmii_readreg(device_t dev, int phy, int reg) 187 { 188 struct rtk_softc *sc = device_private(dev); 189 uint32_t rval; 190 int i; 191 192 if (phy != 7) 193 return 0; 194 195 /* Let the rgephy driver read the GMEDIASTAT register */ 196 197 if (reg == RTK_GMEDIASTAT) { 198 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 199 return rval; 200 } 201 202 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 203 DELAY(1000); 204 205 for (i = 0; i < RTK_TIMEOUT; i++) { 206 rval = CSR_READ_4(sc, RTK_PHYAR); 207 if (rval & RTK_PHYAR_BUSY) 208 break; 209 DELAY(100); 210 } 211 212 if (i == RTK_TIMEOUT) { 213 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 214 return 0; 215 } 216 217 return rval & RTK_PHYAR_PHYDATA; 218 } 219 220 static void 221 re_gmii_writereg(device_t dev, int phy, int reg, int data) 222 { 223 struct rtk_softc *sc = device_private(dev); 224 uint32_t rval; 225 int i; 226 227 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 228 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 229 DELAY(1000); 230 231 for (i = 0; i < RTK_TIMEOUT; i++) { 232 rval = CSR_READ_4(sc, RTK_PHYAR); 233 if (!(rval & RTK_PHYAR_BUSY)) 234 break; 235 DELAY(100); 236 } 237 238 if (i == RTK_TIMEOUT) { 239 printf("%s: PHY write reg %x <- %x failed\n", 240 device_xname(sc->sc_dev), reg, data); 241 } 242 } 243 244 static int 245 re_miibus_readreg(device_t dev, int phy, int reg) 246 { 247 struct rtk_softc *sc = device_private(dev); 248 uint16_t rval = 0; 249 uint16_t re8139_reg = 0; 250 int s; 251 252 s = splnet(); 253 254 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 255 rval = re_gmii_readreg(dev, phy, reg); 256 splx(s); 257 return rval; 258 } 259 260 /* Pretend the internal PHY is only at address 0 */ 261 if (phy) { 262 splx(s); 263 return 0; 264 } 265 switch (reg) { 266 case MII_BMCR: 267 re8139_reg = RTK_BMCR; 268 break; 269 case MII_BMSR: 270 re8139_reg = RTK_BMSR; 271 break; 272 case MII_ANAR: 273 re8139_reg = RTK_ANAR; 274 break; 275 case MII_ANER: 276 re8139_reg = RTK_ANER; 277 break; 278 case MII_ANLPAR: 279 re8139_reg = RTK_LPAR; 280 break; 281 case MII_PHYIDR1: 282 case MII_PHYIDR2: 283 splx(s); 284 return 0; 285 /* 286 * Allow the rlphy driver to read the media status 287 * register. If we have a link partner which does not 288 * support NWAY, this is the register which will tell 289 * us the results of parallel detection. 290 */ 291 case RTK_MEDIASTAT: 292 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 293 splx(s); 294 return rval; 295 default: 296 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 297 splx(s); 298 return 0; 299 } 300 rval = CSR_READ_2(sc, re8139_reg); 301 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 302 /* 8139C+ has different bit layout. */ 303 rval &= ~(BMCR_LOOP | BMCR_ISO); 304 } 305 splx(s); 306 return rval; 307 } 308 309 static void 310 re_miibus_writereg(device_t dev, int phy, int reg, int data) 311 { 312 struct rtk_softc *sc = device_private(dev); 313 uint16_t re8139_reg = 0; 314 int s; 315 316 s = splnet(); 317 318 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 319 re_gmii_writereg(dev, phy, reg, data); 320 splx(s); 321 return; 322 } 323 324 /* Pretend the internal PHY is only at address 0 */ 325 if (phy) { 326 splx(s); 327 return; 328 } 329 switch (reg) { 330 case MII_BMCR: 331 re8139_reg = RTK_BMCR; 332 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 333 /* 8139C+ has different bit layout. */ 334 data &= ~(BMCR_LOOP | BMCR_ISO); 335 } 336 break; 337 case MII_BMSR: 338 re8139_reg = RTK_BMSR; 339 break; 340 case MII_ANAR: 341 re8139_reg = RTK_ANAR; 342 break; 343 case MII_ANER: 344 re8139_reg = RTK_ANER; 345 break; 346 case MII_ANLPAR: 347 re8139_reg = RTK_LPAR; 348 break; 349 case MII_PHYIDR1: 350 case MII_PHYIDR2: 351 splx(s); 352 return; 353 break; 354 default: 355 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 356 splx(s); 357 return; 358 } 359 CSR_WRITE_2(sc, re8139_reg, data); 360 splx(s); 361 return; 362 } 363 364 static void 365 re_miibus_statchg(device_t dev) 366 { 367 368 return; 369 } 370 371 static void 372 re_reset(struct rtk_softc *sc) 373 { 374 int i; 375 376 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 377 378 for (i = 0; i < RTK_TIMEOUT; i++) { 379 DELAY(10); 380 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 381 break; 382 } 383 if (i == RTK_TIMEOUT) 384 printf("%s: reset never completed!\n", 385 device_xname(sc->sc_dev)); 386 387 /* 388 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 389 * but also says "Rtl8169s sigle chip detected". 390 */ 391 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 392 CSR_WRITE_1(sc, RTK_LDPS, 1); 393 394 } 395 396 /* 397 * The following routine is designed to test for a defect on some 398 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 399 * lines connected to the bus, however for a 32-bit only card, they 400 * should be pulled high. The result of this defect is that the 401 * NIC will not work right if you plug it into a 64-bit slot: DMA 402 * operations will be done with 64-bit transfers, which will fail 403 * because the 64-bit data lines aren't connected. 404 * 405 * There's no way to work around this (short of talking a soldering 406 * iron to the board), however we can detect it. The method we use 407 * here is to put the NIC into digital loopback mode, set the receiver 408 * to promiscuous mode, and then try to send a frame. We then compare 409 * the frame data we sent to what was received. If the data matches, 410 * then the NIC is working correctly, otherwise we know the user has 411 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 412 * slot. In the latter case, there's no way the NIC can work correctly, 413 * so we print out a message on the console and abort the device attach. 414 */ 415 416 int 417 re_diag(struct rtk_softc *sc) 418 { 419 struct ifnet *ifp = &sc->ethercom.ec_if; 420 struct mbuf *m0; 421 struct ether_header *eh; 422 struct re_rxsoft *rxs; 423 struct re_desc *cur_rx; 424 bus_dmamap_t dmamap; 425 uint16_t status; 426 uint32_t rxstat; 427 int total_len, i, s, error = 0; 428 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 429 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 430 431 /* Allocate a single mbuf */ 432 433 MGETHDR(m0, M_DONTWAIT, MT_DATA); 434 if (m0 == NULL) 435 return ENOBUFS; 436 437 /* 438 * Initialize the NIC in test mode. This sets the chip up 439 * so that it can send and receive frames, but performs the 440 * following special functions: 441 * - Puts receiver in promiscuous mode 442 * - Enables digital loopback mode 443 * - Leaves interrupts turned off 444 */ 445 446 ifp->if_flags |= IFF_PROMISC; 447 sc->re_testmode = 1; 448 re_init(ifp); 449 re_stop(ifp, 0); 450 DELAY(100000); 451 re_init(ifp); 452 453 /* Put some data in the mbuf */ 454 455 eh = mtod(m0, struct ether_header *); 456 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN); 457 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN); 458 eh->ether_type = htons(ETHERTYPE_IP); 459 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 460 461 /* 462 * Queue the packet, start transmission. 463 */ 464 465 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 466 s = splnet(); 467 IF_ENQUEUE(&ifp->if_snd, m0); 468 re_start(ifp); 469 splx(s); 470 m0 = NULL; 471 472 /* Wait for it to propagate through the chip */ 473 474 DELAY(100000); 475 for (i = 0; i < RTK_TIMEOUT; i++) { 476 status = CSR_READ_2(sc, RTK_ISR); 477 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 478 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 479 break; 480 DELAY(10); 481 } 482 if (i == RTK_TIMEOUT) { 483 aprint_error_dev(sc->sc_dev, 484 "diagnostic failed, failed to receive packet " 485 "in loopback mode\n"); 486 error = EIO; 487 goto done; 488 } 489 490 /* 491 * The packet should have been dumped into the first 492 * entry in the RX DMA ring. Grab it from there. 493 */ 494 495 rxs = &sc->re_ldata.re_rxsoft[0]; 496 dmamap = rxs->rxs_dmamap; 497 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 498 BUS_DMASYNC_POSTREAD); 499 bus_dmamap_unload(sc->sc_dmat, dmamap); 500 501 m0 = rxs->rxs_mbuf; 502 rxs->rxs_mbuf = NULL; 503 eh = mtod(m0, struct ether_header *); 504 505 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 506 cur_rx = &sc->re_ldata.re_rx_list[0]; 507 rxstat = le32toh(cur_rx->re_cmdstat); 508 total_len = rxstat & sc->re_rxlenmask; 509 510 if (total_len != ETHER_MIN_LEN) { 511 aprint_error_dev(sc->sc_dev, 512 "diagnostic failed, received short packet\n"); 513 error = EIO; 514 goto done; 515 } 516 517 /* Test that the received packet data matches what we sent. */ 518 519 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 520 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 521 ntohs(eh->ether_type) != ETHERTYPE_IP) { 522 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 523 "expected TX data: %s/%s/0x%x\n" 524 "received RX data: %s/%s/0x%x\n" 525 "You may have a defective 32-bit NIC plugged " 526 "into a 64-bit PCI slot.\n" 527 "Please re-install the NIC in a 32-bit slot " 528 "for proper operation.\n" 529 "Read the re(4) man page for more details.\n" , 530 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 531 ether_sprintf(eh->ether_dhost), 532 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 533 error = EIO; 534 } 535 536 done: 537 /* Turn interface off, release resources */ 538 539 sc->re_testmode = 0; 540 ifp->if_flags &= ~IFF_PROMISC; 541 re_stop(ifp, 0); 542 if (m0 != NULL) 543 m_freem(m0); 544 545 return error; 546 } 547 548 549 /* 550 * Attach the interface. Allocate softc structures, do ifmedia 551 * setup and ethernet/BPF attach. 552 */ 553 void 554 re_attach(struct rtk_softc *sc) 555 { 556 uint8_t eaddr[ETHER_ADDR_LEN]; 557 struct ifnet *ifp; 558 int error = 0, i; 559 560 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 561 uint32_t hwrev; 562 563 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 564 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 565 switch (hwrev) { 566 case RTK_HWREV_8169: 567 sc->sc_quirk |= RTKQ_8169NONS; 568 break; 569 case RTK_HWREV_8169S: 570 case RTK_HWREV_8110S: 571 case RTK_HWREV_8169_8110SB: 572 case RTK_HWREV_8169_8110SBL: 573 case RTK_HWREV_8169_8110SC: 574 sc->sc_quirk |= RTKQ_MACLDPS; 575 break; 576 case RTK_HWREV_8168_SPIN1: 577 case RTK_HWREV_8168_SPIN2: 578 case RTK_HWREV_8168_SPIN3: 579 sc->sc_quirk |= RTKQ_MACSTAT; 580 break; 581 case RTK_HWREV_8168C: 582 case RTK_HWREV_8168C_SPIN2: 583 case RTK_HWREV_8168CP: 584 case RTK_HWREV_8168D: 585 case RTK_HWREV_8168DP: 586 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 587 RTKQ_MACSTAT | RTKQ_CMDSTOP; 588 /* 589 * From FreeBSD driver: 590 * 591 * These (8168/8111) controllers support jumbo frame 592 * but it seems that enabling it requires touching 593 * additional magic registers. Depending on MAC 594 * revisions some controllers need to disable 595 * checksum offload. So disable jumbo frame until 596 * I have better idea what it really requires to 597 * make it support. 598 * RTL8168C/CP : supports up to 6KB jumbo frame. 599 * RTL8111C/CP : supports up to 9KB jumbo frame. 600 */ 601 sc->sc_quirk |= RTKQ_NOJUMBO; 602 break; 603 case RTK_HWREV_8168E: 604 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 605 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM | 606 RTKQ_NOJUMBO; 607 break; 608 case RTK_HWREV_8168E_VL: 609 case RTK_HWREV_8168F: 610 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 611 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 612 break; 613 case RTK_HWREV_8100E: 614 case RTK_HWREV_8100E_SPIN2: 615 case RTK_HWREV_8101E: 616 sc->sc_quirk |= RTKQ_NOJUMBO; 617 break; 618 case RTK_HWREV_8102E: 619 case RTK_HWREV_8102EL: 620 case RTK_HWREV_8103E: 621 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 622 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 623 break; 624 default: 625 aprint_normal_dev(sc->sc_dev, 626 "Unknown revision (0x%08x)\n", hwrev); 627 /* assume the latest features */ 628 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 629 sc->sc_quirk |= RTKQ_NOJUMBO; 630 } 631 632 /* Set RX length mask */ 633 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 634 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 635 } else { 636 sc->sc_quirk |= RTKQ_NOJUMBO; 637 638 /* Set RX length mask */ 639 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 640 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 641 } 642 643 /* Reset the adapter. */ 644 re_reset(sc); 645 646 /* 647 * RTL81x9 chips automatically read EEPROM to init MAC address, 648 * and some NAS override its MAC address per own configuration, 649 * so no need to explicitely read EEPROM and set ID registers. 650 */ 651 #ifdef RE_USE_EECMD 652 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 653 /* 654 * Get station address from ID registers. 655 */ 656 for (i = 0; i < ETHER_ADDR_LEN; i++) 657 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 658 } else { 659 uint16_t val; 660 int addr_len; 661 662 /* 663 * Get station address from the EEPROM. 664 */ 665 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 666 addr_len = RTK_EEADDR_LEN1; 667 else 668 addr_len = RTK_EEADDR_LEN0; 669 670 /* 671 * Get station address from the EEPROM. 672 */ 673 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 674 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 675 eaddr[(i * 2) + 0] = val & 0xff; 676 eaddr[(i * 2) + 1] = val >> 8; 677 } 678 } 679 #else 680 /* 681 * Get station address from ID registers. 682 */ 683 for (i = 0; i < ETHER_ADDR_LEN; i++) 684 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 685 #endif 686 687 /* Take PHY out of power down mode. */ 688 if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0) 689 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80); 690 691 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 692 ether_sprintf(eaddr)); 693 694 if (sc->re_ldata.re_tx_desc_cnt > 695 PAGE_SIZE / sizeof(struct re_desc)) { 696 sc->re_ldata.re_tx_desc_cnt = 697 PAGE_SIZE / sizeof(struct re_desc); 698 } 699 700 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 701 sc->re_ldata.re_tx_desc_cnt); 702 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 703 704 /* Allocate DMA'able memory for the TX ring */ 705 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 706 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 707 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 708 aprint_error_dev(sc->sc_dev, 709 "can't allocate tx listseg, error = %d\n", error); 710 goto fail_0; 711 } 712 713 /* Load the map for the TX ring. */ 714 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 715 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 716 (void **)&sc->re_ldata.re_tx_list, 717 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 718 aprint_error_dev(sc->sc_dev, 719 "can't map tx list, error = %d\n", error); 720 goto fail_1; 721 } 722 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 723 724 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 725 RE_TX_LIST_SZ(sc), 0, 0, 726 &sc->re_ldata.re_tx_list_map)) != 0) { 727 aprint_error_dev(sc->sc_dev, 728 "can't create tx list map, error = %d\n", error); 729 goto fail_2; 730 } 731 732 733 if ((error = bus_dmamap_load(sc->sc_dmat, 734 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 735 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 736 aprint_error_dev(sc->sc_dev, 737 "can't load tx list, error = %d\n", error); 738 goto fail_3; 739 } 740 741 /* Create DMA maps for TX buffers */ 742 for (i = 0; i < RE_TX_QLEN; i++) { 743 error = bus_dmamap_create(sc->sc_dmat, 744 round_page(IP_MAXPACKET), 745 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 746 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 747 if (error) { 748 aprint_error_dev(sc->sc_dev, 749 "can't create DMA map for TX\n"); 750 goto fail_4; 751 } 752 } 753 754 /* Allocate DMA'able memory for the RX ring */ 755 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 756 if ((error = bus_dmamem_alloc(sc->sc_dmat, 757 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 758 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 759 aprint_error_dev(sc->sc_dev, 760 "can't allocate rx listseg, error = %d\n", error); 761 goto fail_4; 762 } 763 764 /* Load the map for the RX ring. */ 765 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 766 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 767 (void **)&sc->re_ldata.re_rx_list, 768 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 769 aprint_error_dev(sc->sc_dev, 770 "can't map rx list, error = %d\n", error); 771 goto fail_5; 772 } 773 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 774 775 if ((error = bus_dmamap_create(sc->sc_dmat, 776 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 777 &sc->re_ldata.re_rx_list_map)) != 0) { 778 aprint_error_dev(sc->sc_dev, 779 "can't create rx list map, error = %d\n", error); 780 goto fail_6; 781 } 782 783 if ((error = bus_dmamap_load(sc->sc_dmat, 784 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 785 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 786 aprint_error_dev(sc->sc_dev, 787 "can't load rx list, error = %d\n", error); 788 goto fail_7; 789 } 790 791 /* Create DMA maps for RX buffers */ 792 for (i = 0; i < RE_RX_DESC_CNT; i++) { 793 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 794 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 795 if (error) { 796 aprint_error_dev(sc->sc_dev, 797 "can't create DMA map for RX\n"); 798 goto fail_8; 799 } 800 } 801 802 /* 803 * Record interface as attached. From here, we should not fail. 804 */ 805 sc->sc_flags |= RTK_ATTACHED; 806 807 ifp = &sc->ethercom.ec_if; 808 ifp->if_softc = sc; 809 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 810 ifp->if_mtu = ETHERMTU; 811 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 812 ifp->if_ioctl = re_ioctl; 813 sc->ethercom.ec_capabilities |= 814 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 815 ifp->if_start = re_start; 816 ifp->if_stop = re_stop; 817 818 /* 819 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 820 * so we have a workaround to handle the bug by padding 821 * such packets manually. 822 */ 823 ifp->if_capabilities |= 824 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 825 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 826 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 827 IFCAP_TSOv4; 828 829 /* 830 * XXX 831 * Still have no idea how to make TSO work on 8168C, 8168CP, 832 * 8102E, 8111C and 8111CP. 833 */ 834 if ((sc->sc_quirk & RTKQ_DESCV2) != 0) 835 ifp->if_capabilities &= ~IFCAP_TSOv4; 836 837 ifp->if_watchdog = re_watchdog; 838 ifp->if_init = re_init; 839 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 840 ifp->if_capenable = ifp->if_capabilities; 841 IFQ_SET_READY(&ifp->if_snd); 842 843 callout_init(&sc->rtk_tick_ch, 0); 844 845 /* Do MII setup */ 846 sc->mii.mii_ifp = ifp; 847 sc->mii.mii_readreg = re_miibus_readreg; 848 sc->mii.mii_writereg = re_miibus_writereg; 849 sc->mii.mii_statchg = re_miibus_statchg; 850 sc->ethercom.ec_mii = &sc->mii; 851 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 852 ether_mediastatus); 853 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 854 MII_OFFSET_ANY, 0); 855 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 856 857 /* 858 * Call MI attach routine. 859 */ 860 if_attach(ifp); 861 ether_ifattach(ifp, eaddr); 862 863 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 864 pmf_class_network_register(sc->sc_dev, ifp); 865 else 866 aprint_error_dev(sc->sc_dev, 867 "couldn't establish power handler\n"); 868 869 return; 870 871 fail_8: 872 /* Destroy DMA maps for RX buffers. */ 873 for (i = 0; i < RE_RX_DESC_CNT; i++) 874 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 875 bus_dmamap_destroy(sc->sc_dmat, 876 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 877 878 /* Free DMA'able memory for the RX ring. */ 879 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 880 fail_7: 881 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 882 fail_6: 883 bus_dmamem_unmap(sc->sc_dmat, 884 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 885 fail_5: 886 bus_dmamem_free(sc->sc_dmat, 887 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 888 889 fail_4: 890 /* Destroy DMA maps for TX buffers. */ 891 for (i = 0; i < RE_TX_QLEN; i++) 892 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 893 bus_dmamap_destroy(sc->sc_dmat, 894 sc->re_ldata.re_txq[i].txq_dmamap); 895 896 /* Free DMA'able memory for the TX ring. */ 897 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 898 fail_3: 899 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 900 fail_2: 901 bus_dmamem_unmap(sc->sc_dmat, 902 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 903 fail_1: 904 bus_dmamem_free(sc->sc_dmat, 905 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 906 fail_0: 907 return; 908 } 909 910 911 /* 912 * re_activate: 913 * Handle device activation/deactivation requests. 914 */ 915 int 916 re_activate(device_t self, enum devact act) 917 { 918 struct rtk_softc *sc = device_private(self); 919 920 switch (act) { 921 case DVACT_DEACTIVATE: 922 if_deactivate(&sc->ethercom.ec_if); 923 return 0; 924 default: 925 return EOPNOTSUPP; 926 } 927 } 928 929 /* 930 * re_detach: 931 * Detach a rtk interface. 932 */ 933 int 934 re_detach(struct rtk_softc *sc) 935 { 936 struct ifnet *ifp = &sc->ethercom.ec_if; 937 int i; 938 939 /* 940 * Succeed now if there isn't any work to do. 941 */ 942 if ((sc->sc_flags & RTK_ATTACHED) == 0) 943 return 0; 944 945 /* Unhook our tick handler. */ 946 callout_stop(&sc->rtk_tick_ch); 947 948 /* Detach all PHYs. */ 949 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 950 951 /* Delete all remaining media. */ 952 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 953 954 ether_ifdetach(ifp); 955 if_detach(ifp); 956 957 /* Destroy DMA maps for RX buffers. */ 958 for (i = 0; i < RE_RX_DESC_CNT; i++) 959 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 960 bus_dmamap_destroy(sc->sc_dmat, 961 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 962 963 /* Free DMA'able memory for the RX ring. */ 964 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 965 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 966 bus_dmamem_unmap(sc->sc_dmat, 967 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 968 bus_dmamem_free(sc->sc_dmat, 969 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 970 971 /* Destroy DMA maps for TX buffers. */ 972 for (i = 0; i < RE_TX_QLEN; i++) 973 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 974 bus_dmamap_destroy(sc->sc_dmat, 975 sc->re_ldata.re_txq[i].txq_dmamap); 976 977 /* Free DMA'able memory for the TX ring. */ 978 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 979 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 980 bus_dmamem_unmap(sc->sc_dmat, 981 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 982 bus_dmamem_free(sc->sc_dmat, 983 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 984 985 pmf_device_deregister(sc->sc_dev); 986 987 /* we don't want to run again */ 988 sc->sc_flags &= ~RTK_ATTACHED; 989 990 return 0; 991 } 992 993 /* 994 * re_enable: 995 * Enable the RTL81X9 chip. 996 */ 997 static int 998 re_enable(struct rtk_softc *sc) 999 { 1000 1001 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 1002 if ((*sc->sc_enable)(sc) != 0) { 1003 printf("%s: device enable failed\n", 1004 device_xname(sc->sc_dev)); 1005 return EIO; 1006 } 1007 sc->sc_flags |= RTK_ENABLED; 1008 } 1009 return 0; 1010 } 1011 1012 /* 1013 * re_disable: 1014 * Disable the RTL81X9 chip. 1015 */ 1016 static void 1017 re_disable(struct rtk_softc *sc) 1018 { 1019 1020 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 1021 (*sc->sc_disable)(sc); 1022 sc->sc_flags &= ~RTK_ENABLED; 1023 } 1024 } 1025 1026 static int 1027 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1028 { 1029 struct mbuf *n = NULL; 1030 bus_dmamap_t map; 1031 struct re_desc *d; 1032 struct re_rxsoft *rxs; 1033 uint32_t cmdstat; 1034 int error; 1035 1036 if (m == NULL) { 1037 MGETHDR(n, M_DONTWAIT, MT_DATA); 1038 if (n == NULL) 1039 return ENOBUFS; 1040 1041 MCLGET(n, M_DONTWAIT); 1042 if ((n->m_flags & M_EXT) == 0) { 1043 m_freem(n); 1044 return ENOBUFS; 1045 } 1046 m = n; 1047 } else 1048 m->m_data = m->m_ext.ext_buf; 1049 1050 /* 1051 * Initialize mbuf length fields and fixup 1052 * alignment so that the frame payload is 1053 * longword aligned. 1054 */ 1055 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1056 m->m_data += RE_ETHER_ALIGN; 1057 1058 rxs = &sc->re_ldata.re_rxsoft[idx]; 1059 map = rxs->rxs_dmamap; 1060 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1061 BUS_DMA_READ|BUS_DMA_NOWAIT); 1062 1063 if (error) 1064 goto out; 1065 1066 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1067 BUS_DMASYNC_PREREAD); 1068 1069 d = &sc->re_ldata.re_rx_list[idx]; 1070 #ifdef DIAGNOSTIC 1071 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1072 cmdstat = le32toh(d->re_cmdstat); 1073 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1074 if (cmdstat & RE_RDESC_STAT_OWN) { 1075 panic("%s: tried to map busy RX descriptor", 1076 device_xname(sc->sc_dev)); 1077 } 1078 #endif 1079 1080 rxs->rxs_mbuf = m; 1081 1082 d->re_vlanctl = 0; 1083 cmdstat = map->dm_segs[0].ds_len; 1084 if (idx == (RE_RX_DESC_CNT - 1)) 1085 cmdstat |= RE_RDESC_CMD_EOR; 1086 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1087 d->re_cmdstat = htole32(cmdstat); 1088 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1089 cmdstat |= RE_RDESC_CMD_OWN; 1090 d->re_cmdstat = htole32(cmdstat); 1091 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1092 1093 return 0; 1094 out: 1095 if (n != NULL) 1096 m_freem(n); 1097 return ENOMEM; 1098 } 1099 1100 static int 1101 re_tx_list_init(struct rtk_softc *sc) 1102 { 1103 int i; 1104 1105 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1106 for (i = 0; i < RE_TX_QLEN; i++) { 1107 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1108 } 1109 1110 bus_dmamap_sync(sc->sc_dmat, 1111 sc->re_ldata.re_tx_list_map, 0, 1112 sc->re_ldata.re_tx_list_map->dm_mapsize, 1113 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1114 sc->re_ldata.re_txq_prodidx = 0; 1115 sc->re_ldata.re_txq_considx = 0; 1116 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1117 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1118 sc->re_ldata.re_tx_nextfree = 0; 1119 1120 return 0; 1121 } 1122 1123 static int 1124 re_rx_list_init(struct rtk_softc *sc) 1125 { 1126 int i; 1127 1128 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1129 1130 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1131 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1132 return ENOBUFS; 1133 } 1134 1135 sc->re_ldata.re_rx_prodidx = 0; 1136 sc->re_head = sc->re_tail = NULL; 1137 1138 return 0; 1139 } 1140 1141 /* 1142 * RX handler for C+ and 8169. For the gigE chips, we support 1143 * the reception of jumbo frames that have been fragmented 1144 * across multiple 2K mbuf cluster buffers. 1145 */ 1146 static void 1147 re_rxeof(struct rtk_softc *sc) 1148 { 1149 struct mbuf *m; 1150 struct ifnet *ifp; 1151 int i, total_len; 1152 struct re_desc *cur_rx; 1153 struct re_rxsoft *rxs; 1154 uint32_t rxstat, rxvlan; 1155 1156 ifp = &sc->ethercom.ec_if; 1157 1158 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1159 cur_rx = &sc->re_ldata.re_rx_list[i]; 1160 RE_RXDESCSYNC(sc, i, 1161 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1162 rxstat = le32toh(cur_rx->re_cmdstat); 1163 rxvlan = le32toh(cur_rx->re_vlanctl); 1164 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1165 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1166 break; 1167 } 1168 total_len = rxstat & sc->re_rxlenmask; 1169 rxs = &sc->re_ldata.re_rxsoft[i]; 1170 m = rxs->rxs_mbuf; 1171 1172 /* Invalidate the RX mbuf and unload its map */ 1173 1174 bus_dmamap_sync(sc->sc_dmat, 1175 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1176 BUS_DMASYNC_POSTREAD); 1177 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1178 1179 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1180 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1181 if (sc->re_head == NULL) 1182 sc->re_head = sc->re_tail = m; 1183 else { 1184 m->m_flags &= ~M_PKTHDR; 1185 sc->re_tail->m_next = m; 1186 sc->re_tail = m; 1187 } 1188 re_newbuf(sc, i, NULL); 1189 continue; 1190 } 1191 1192 /* 1193 * NOTE: for the 8139C+, the frame length field 1194 * is always 12 bits in size, but for the gigE chips, 1195 * it is 13 bits (since the max RX frame length is 16K). 1196 * Unfortunately, all 32 bits in the status word 1197 * were already used, so to make room for the extra 1198 * length bit, RealTek took out the 'frame alignment 1199 * error' bit and shifted the other status bits 1200 * over one slot. The OWN, EOR, FS and LS bits are 1201 * still in the same places. We have already extracted 1202 * the frame length and checked the OWN bit, so rather 1203 * than using an alternate bit mapping, we shift the 1204 * status bits one space to the right so we can evaluate 1205 * them using the 8169 status as though it was in the 1206 * same format as that of the 8139C+. 1207 */ 1208 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1209 rxstat >>= 1; 1210 1211 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1212 #ifdef RE_DEBUG 1213 printf("%s: RX error (rxstat = 0x%08x)", 1214 device_xname(sc->sc_dev), rxstat); 1215 if (rxstat & RE_RDESC_STAT_FRALIGN) 1216 printf(", frame alignment error"); 1217 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1218 printf(", out of buffer space"); 1219 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1220 printf(", FIFO overrun"); 1221 if (rxstat & RE_RDESC_STAT_GIANT) 1222 printf(", giant packet"); 1223 if (rxstat & RE_RDESC_STAT_RUNT) 1224 printf(", runt packet"); 1225 if (rxstat & RE_RDESC_STAT_CRCERR) 1226 printf(", CRC error"); 1227 printf("\n"); 1228 #endif 1229 ifp->if_ierrors++; 1230 /* 1231 * If this is part of a multi-fragment packet, 1232 * discard all the pieces. 1233 */ 1234 if (sc->re_head != NULL) { 1235 m_freem(sc->re_head); 1236 sc->re_head = sc->re_tail = NULL; 1237 } 1238 re_newbuf(sc, i, m); 1239 continue; 1240 } 1241 1242 /* 1243 * If allocating a replacement mbuf fails, 1244 * reload the current one. 1245 */ 1246 1247 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1248 ifp->if_ierrors++; 1249 if (sc->re_head != NULL) { 1250 m_freem(sc->re_head); 1251 sc->re_head = sc->re_tail = NULL; 1252 } 1253 re_newbuf(sc, i, m); 1254 continue; 1255 } 1256 1257 if (sc->re_head != NULL) { 1258 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1259 /* 1260 * Special case: if there's 4 bytes or less 1261 * in this buffer, the mbuf can be discarded: 1262 * the last 4 bytes is the CRC, which we don't 1263 * care about anyway. 1264 */ 1265 if (m->m_len <= ETHER_CRC_LEN) { 1266 sc->re_tail->m_len -= 1267 (ETHER_CRC_LEN - m->m_len); 1268 m_freem(m); 1269 } else { 1270 m->m_len -= ETHER_CRC_LEN; 1271 m->m_flags &= ~M_PKTHDR; 1272 sc->re_tail->m_next = m; 1273 } 1274 m = sc->re_head; 1275 sc->re_head = sc->re_tail = NULL; 1276 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1277 } else 1278 m->m_pkthdr.len = m->m_len = 1279 (total_len - ETHER_CRC_LEN); 1280 1281 ifp->if_ipackets++; 1282 m->m_pkthdr.rcvif = ifp; 1283 1284 /* Do RX checksumming */ 1285 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1286 /* Check IP header checksum */ 1287 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) { 1288 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1289 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1290 m->m_pkthdr.csum_flags |= 1291 M_CSUM_IPv4_BAD; 1292 1293 /* Check TCP/UDP checksum */ 1294 if (RE_TCPPKT(rxstat)) { 1295 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1296 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1297 m->m_pkthdr.csum_flags |= 1298 M_CSUM_TCP_UDP_BAD; 1299 } else if (RE_UDPPKT(rxstat)) { 1300 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1301 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1302 m->m_pkthdr.csum_flags |= 1303 M_CSUM_TCP_UDP_BAD; 1304 } 1305 } 1306 } else { 1307 /* Check IPv4 header checksum */ 1308 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) { 1309 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1310 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1311 m->m_pkthdr.csum_flags |= 1312 M_CSUM_IPv4_BAD; 1313 1314 /* Check TCPv4/UDPv4 checksum */ 1315 if (RE_TCPPKT(rxstat)) { 1316 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1317 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1318 m->m_pkthdr.csum_flags |= 1319 M_CSUM_TCP_UDP_BAD; 1320 } else if (RE_UDPPKT(rxstat)) { 1321 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1322 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1323 m->m_pkthdr.csum_flags |= 1324 M_CSUM_TCP_UDP_BAD; 1325 } 1326 } 1327 /* XXX Check TCPv6/UDPv6 checksum? */ 1328 } 1329 1330 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1331 VLAN_INPUT_TAG(ifp, m, 1332 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA), 1333 continue); 1334 } 1335 bpf_mtap(ifp, m); 1336 (*ifp->if_input)(ifp, m); 1337 } 1338 1339 sc->re_ldata.re_rx_prodidx = i; 1340 } 1341 1342 static void 1343 re_txeof(struct rtk_softc *sc) 1344 { 1345 struct ifnet *ifp; 1346 struct re_txq *txq; 1347 uint32_t txstat; 1348 int idx, descidx; 1349 1350 ifp = &sc->ethercom.ec_if; 1351 1352 for (idx = sc->re_ldata.re_txq_considx; 1353 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1354 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1355 txq = &sc->re_ldata.re_txq[idx]; 1356 KASSERT(txq->txq_mbuf != NULL); 1357 1358 descidx = txq->txq_descidx; 1359 RE_TXDESCSYNC(sc, descidx, 1360 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1361 txstat = 1362 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1363 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1364 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1365 if (txstat & RE_TDESC_CMD_OWN) { 1366 break; 1367 } 1368 1369 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1370 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1371 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1372 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1373 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1374 m_freem(txq->txq_mbuf); 1375 txq->txq_mbuf = NULL; 1376 1377 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1378 ifp->if_collisions++; 1379 if (txstat & RE_TDESC_STAT_TXERRSUM) 1380 ifp->if_oerrors++; 1381 else 1382 ifp->if_opackets++; 1383 } 1384 1385 sc->re_ldata.re_txq_considx = idx; 1386 1387 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1388 ifp->if_flags &= ~IFF_OACTIVE; 1389 1390 /* 1391 * If not all descriptors have been released reaped yet, 1392 * reload the timer so that we will eventually get another 1393 * interrupt that will cause us to re-enter this routine. 1394 * This is done in case the transmitter has gone idle. 1395 */ 1396 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1397 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1398 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1399 /* 1400 * Some chips will ignore a second TX request 1401 * issued while an existing transmission is in 1402 * progress. If the transmitter goes idle but 1403 * there are still packets waiting to be sent, 1404 * we need to restart the channel here to flush 1405 * them out. This only seems to be required with 1406 * the PCIe devices. 1407 */ 1408 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1409 } 1410 } else 1411 ifp->if_timer = 0; 1412 } 1413 1414 static void 1415 re_tick(void *arg) 1416 { 1417 struct rtk_softc *sc = arg; 1418 int s; 1419 1420 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1421 s = splnet(); 1422 1423 mii_tick(&sc->mii); 1424 splx(s); 1425 1426 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1427 } 1428 1429 int 1430 re_intr(void *arg) 1431 { 1432 struct rtk_softc *sc = arg; 1433 struct ifnet *ifp; 1434 uint16_t status; 1435 int handled = 0; 1436 1437 if (!device_has_power(sc->sc_dev)) 1438 return 0; 1439 1440 ifp = &sc->ethercom.ec_if; 1441 1442 if ((ifp->if_flags & IFF_UP) == 0) 1443 return 0; 1444 1445 for (;;) { 1446 1447 status = CSR_READ_2(sc, RTK_ISR); 1448 /* If the card has gone away the read returns 0xffff. */ 1449 if (status == 0xffff) 1450 break; 1451 if (status) { 1452 handled = 1; 1453 CSR_WRITE_2(sc, RTK_ISR, status); 1454 } 1455 1456 if ((status & RTK_INTRS_CPLUS) == 0) 1457 break; 1458 1459 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1460 re_rxeof(sc); 1461 1462 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1463 RTK_ISR_TX_DESC_UNAVAIL)) 1464 re_txeof(sc); 1465 1466 if (status & RTK_ISR_SYSTEM_ERR) { 1467 re_init(ifp); 1468 } 1469 1470 if (status & RTK_ISR_LINKCHG) { 1471 callout_stop(&sc->rtk_tick_ch); 1472 re_tick(sc); 1473 } 1474 } 1475 1476 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd)) 1477 re_start(ifp); 1478 1479 return handled; 1480 } 1481 1482 1483 1484 /* 1485 * Main transmit routine for C+ and gigE NICs. 1486 */ 1487 1488 static void 1489 re_start(struct ifnet *ifp) 1490 { 1491 struct rtk_softc *sc; 1492 struct mbuf *m; 1493 bus_dmamap_t map; 1494 struct re_txq *txq; 1495 struct re_desc *d; 1496 struct m_tag *mtag; 1497 uint32_t cmdstat, re_flags, vlanctl; 1498 int ofree, idx, error, nsegs, seg; 1499 int startdesc, curdesc, lastdesc; 1500 bool pad; 1501 1502 sc = ifp->if_softc; 1503 ofree = sc->re_ldata.re_txq_free; 1504 1505 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1506 1507 IFQ_POLL(&ifp->if_snd, m); 1508 if (m == NULL) 1509 break; 1510 1511 if (sc->re_ldata.re_txq_free == 0 || 1512 sc->re_ldata.re_tx_free == 0) { 1513 /* no more free slots left */ 1514 ifp->if_flags |= IFF_OACTIVE; 1515 break; 1516 } 1517 1518 /* 1519 * Set up checksum offload. Note: checksum offload bits must 1520 * appear in all descriptors of a multi-descriptor transmit 1521 * attempt. (This is according to testing done with an 8169 1522 * chip. I'm not sure if this is a requirement or a bug.) 1523 */ 1524 1525 vlanctl = 0; 1526 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1527 uint32_t segsz = m->m_pkthdr.segsz; 1528 1529 re_flags = RE_TDESC_CMD_LGSEND | 1530 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1531 } else { 1532 /* 1533 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1534 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1535 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1536 */ 1537 re_flags = 0; 1538 if ((m->m_pkthdr.csum_flags & 1539 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1540 != 0) { 1541 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1542 re_flags |= RE_TDESC_CMD_IPCSUM; 1543 if (m->m_pkthdr.csum_flags & 1544 M_CSUM_TCPv4) { 1545 re_flags |= 1546 RE_TDESC_CMD_TCPCSUM; 1547 } else if (m->m_pkthdr.csum_flags & 1548 M_CSUM_UDPv4) { 1549 re_flags |= 1550 RE_TDESC_CMD_UDPCSUM; 1551 } 1552 } else { 1553 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1554 if (m->m_pkthdr.csum_flags & 1555 M_CSUM_TCPv4) { 1556 vlanctl |= 1557 RE_TDESC_VLANCTL_TCPCSUM; 1558 } else if (m->m_pkthdr.csum_flags & 1559 M_CSUM_UDPv4) { 1560 vlanctl |= 1561 RE_TDESC_VLANCTL_UDPCSUM; 1562 } 1563 } 1564 } 1565 } 1566 1567 txq = &sc->re_ldata.re_txq[idx]; 1568 map = txq->txq_dmamap; 1569 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1570 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1571 1572 if (__predict_false(error)) { 1573 /* XXX try to defrag if EFBIG? */ 1574 printf("%s: can't map mbuf (error %d)\n", 1575 device_xname(sc->sc_dev), error); 1576 1577 IFQ_DEQUEUE(&ifp->if_snd, m); 1578 m_freem(m); 1579 ifp->if_oerrors++; 1580 continue; 1581 } 1582 1583 nsegs = map->dm_nsegs; 1584 pad = false; 1585 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1586 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1587 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1588 pad = true; 1589 nsegs++; 1590 } 1591 1592 if (nsegs > sc->re_ldata.re_tx_free) { 1593 /* 1594 * Not enough free descriptors to transmit this packet. 1595 */ 1596 ifp->if_flags |= IFF_OACTIVE; 1597 bus_dmamap_unload(sc->sc_dmat, map); 1598 break; 1599 } 1600 1601 IFQ_DEQUEUE(&ifp->if_snd, m); 1602 1603 /* 1604 * Make sure that the caches are synchronized before we 1605 * ask the chip to start DMA for the packet data. 1606 */ 1607 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1608 BUS_DMASYNC_PREWRITE); 1609 1610 /* 1611 * Set up hardware VLAN tagging. Note: vlan tag info must 1612 * appear in all descriptors of a multi-descriptor 1613 * transmission attempt. 1614 */ 1615 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) 1616 vlanctl |= bswap16(VLAN_TAG_VALUE(mtag)) | 1617 RE_TDESC_VLANCTL_TAG; 1618 1619 /* 1620 * Map the segment array into descriptors. 1621 * Note that we set the start-of-frame and 1622 * end-of-frame markers for either TX or RX, 1623 * but they really only have meaning in the TX case. 1624 * (In the RX case, it's the chip that tells us 1625 * where packets begin and end.) 1626 * We also keep track of the end of the ring 1627 * and set the end-of-ring bits as needed, 1628 * and we set the ownership bits in all except 1629 * the very first descriptor. (The caller will 1630 * set this descriptor later when it start 1631 * transmission or reception.) 1632 */ 1633 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1634 lastdesc = -1; 1635 for (seg = 0; seg < map->dm_nsegs; 1636 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1637 d = &sc->re_ldata.re_tx_list[curdesc]; 1638 #ifdef DIAGNOSTIC 1639 RE_TXDESCSYNC(sc, curdesc, 1640 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1641 cmdstat = le32toh(d->re_cmdstat); 1642 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1643 if (cmdstat & RE_TDESC_STAT_OWN) { 1644 panic("%s: tried to map busy TX descriptor", 1645 device_xname(sc->sc_dev)); 1646 } 1647 #endif 1648 1649 d->re_vlanctl = htole32(vlanctl); 1650 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1651 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1652 if (seg == 0) 1653 cmdstat |= RE_TDESC_CMD_SOF; 1654 else 1655 cmdstat |= RE_TDESC_CMD_OWN; 1656 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1657 cmdstat |= RE_TDESC_CMD_EOR; 1658 if (seg == nsegs - 1) { 1659 cmdstat |= RE_TDESC_CMD_EOF; 1660 lastdesc = curdesc; 1661 } 1662 d->re_cmdstat = htole32(cmdstat); 1663 RE_TXDESCSYNC(sc, curdesc, 1664 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1665 } 1666 if (__predict_false(pad)) { 1667 d = &sc->re_ldata.re_tx_list[curdesc]; 1668 d->re_vlanctl = htole32(vlanctl); 1669 re_set_bufaddr(d, RE_TXPADDADDR(sc)); 1670 cmdstat = re_flags | 1671 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1672 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1673 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1674 cmdstat |= RE_TDESC_CMD_EOR; 1675 d->re_cmdstat = htole32(cmdstat); 1676 RE_TXDESCSYNC(sc, curdesc, 1677 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1678 lastdesc = curdesc; 1679 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1680 } 1681 KASSERT(lastdesc != -1); 1682 1683 /* Transfer ownership of packet to the chip. */ 1684 1685 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1686 htole32(RE_TDESC_CMD_OWN); 1687 RE_TXDESCSYNC(sc, startdesc, 1688 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1689 1690 /* update info of TX queue and descriptors */ 1691 txq->txq_mbuf = m; 1692 txq->txq_descidx = lastdesc; 1693 txq->txq_nsegs = nsegs; 1694 1695 sc->re_ldata.re_txq_free--; 1696 sc->re_ldata.re_tx_free -= nsegs; 1697 sc->re_ldata.re_tx_nextfree = curdesc; 1698 1699 /* 1700 * If there's a BPF listener, bounce a copy of this frame 1701 * to him. 1702 */ 1703 bpf_mtap(ifp, m); 1704 } 1705 1706 if (sc->re_ldata.re_txq_free < ofree) { 1707 /* 1708 * TX packets are enqueued. 1709 */ 1710 sc->re_ldata.re_txq_prodidx = idx; 1711 1712 /* 1713 * Start the transmitter to poll. 1714 * 1715 * RealTek put the TX poll request register in a different 1716 * location on the 8169 gigE chip. I don't know why. 1717 */ 1718 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1719 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1720 else 1721 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1722 1723 /* 1724 * Use the countdown timer for interrupt moderation. 1725 * 'TX done' interrupts are disabled. Instead, we reset the 1726 * countdown timer, which will begin counting until it hits 1727 * the value in the TIMERINT register, and then trigger an 1728 * interrupt. Each time we write to the TIMERCNT register, 1729 * the timer count is reset to 0. 1730 */ 1731 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1732 1733 /* 1734 * Set a timeout in case the chip goes out to lunch. 1735 */ 1736 ifp->if_timer = 5; 1737 } 1738 } 1739 1740 static int 1741 re_init(struct ifnet *ifp) 1742 { 1743 struct rtk_softc *sc = ifp->if_softc; 1744 uint32_t rxcfg = 0; 1745 uint16_t cfg; 1746 int error; 1747 #ifdef RE_USE_EECMD 1748 const uint8_t *enaddr; 1749 uint32_t reg; 1750 #endif 1751 1752 if ((error = re_enable(sc)) != 0) 1753 goto out; 1754 1755 /* 1756 * Cancel pending I/O and free all RX/TX buffers. 1757 */ 1758 re_stop(ifp, 0); 1759 1760 re_reset(sc); 1761 1762 /* 1763 * Enable C+ RX and TX mode, as well as VLAN stripping and 1764 * RX checksum offload. We must configure the C+ register 1765 * before all others. 1766 */ 1767 cfg = RE_CPLUSCMD_PCI_MRW; 1768 1769 /* 1770 * XXX: For old 8169 set bit 14. 1771 * For 8169S/8110S and above, do not set bit 14. 1772 */ 1773 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1774 cfg |= (0x1 << 14); 1775 1776 if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0) 1777 cfg |= RE_CPLUSCMD_VLANSTRIP; 1778 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx | 1779 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0) 1780 cfg |= RE_CPLUSCMD_RXCSUM_ENB; 1781 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) { 1782 cfg |= RE_CPLUSCMD_MACSTAT_DIS; 1783 cfg |= RE_CPLUSCMD_TXENB; 1784 } else 1785 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB; 1786 1787 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg); 1788 1789 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1790 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1791 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1792 1793 DELAY(10000); 1794 1795 #ifdef RE_USE_EECMD 1796 /* 1797 * Init our MAC address. Even though the chipset 1798 * documentation doesn't mention it, we need to enter "Config 1799 * register write enable" mode to modify the ID registers. 1800 */ 1801 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1802 enaddr = CLLADDR(ifp->if_sadl); 1803 reg = enaddr[0] | (enaddr[1] << 8) | 1804 (enaddr[2] << 16) | (enaddr[3] << 24); 1805 CSR_WRITE_4(sc, RTK_IDR0, reg); 1806 reg = enaddr[4] | (enaddr[5] << 8); 1807 CSR_WRITE_4(sc, RTK_IDR4, reg); 1808 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1809 #endif 1810 1811 /* 1812 * For C+ mode, initialize the RX descriptors and mbufs. 1813 */ 1814 re_rx_list_init(sc); 1815 re_tx_list_init(sc); 1816 1817 /* 1818 * Load the addresses of the RX and TX lists into the chip. 1819 */ 1820 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1821 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1822 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1823 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1824 1825 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1826 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1827 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1828 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1829 1830 /* 1831 * Enable transmit and receive. 1832 */ 1833 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1834 1835 /* 1836 * Set the initial TX and RX configuration. 1837 */ 1838 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1839 /* test mode is needed only for old 8169 */ 1840 CSR_WRITE_4(sc, RTK_TXCFG, 1841 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1842 } else 1843 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1844 1845 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1846 1847 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1848 1849 /* Set the individual bit to receive frames for this host only. */ 1850 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1851 rxcfg |= RTK_RXCFG_RX_INDIV; 1852 1853 /* If we want promiscuous mode, set the allframes bit. */ 1854 if (ifp->if_flags & IFF_PROMISC) 1855 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1856 else 1857 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1858 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1859 1860 /* 1861 * Set capture broadcast bit to capture broadcast frames. 1862 */ 1863 if (ifp->if_flags & IFF_BROADCAST) 1864 rxcfg |= RTK_RXCFG_RX_BROAD; 1865 else 1866 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1867 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1868 1869 /* 1870 * Program the multicast filter, if necessary. 1871 */ 1872 rtk_setmulti(sc); 1873 1874 /* 1875 * Enable interrupts. 1876 */ 1877 if (sc->re_testmode) 1878 CSR_WRITE_2(sc, RTK_IMR, 0); 1879 else 1880 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1881 1882 /* Start RX/TX process. */ 1883 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1884 #ifdef notdef 1885 /* Enable receiver and transmitter. */ 1886 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1887 #endif 1888 1889 /* 1890 * Initialize the timer interrupt register so that 1891 * a timer interrupt will be generated once the timer 1892 * reaches a certain number of ticks. The timer is 1893 * reloaded on each transmit. This gives us TX interrupt 1894 * moderation, which dramatically improves TX frame rate. 1895 */ 1896 1897 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1898 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1899 else { 1900 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1901 1902 /* 1903 * For 8169 gigE NICs, set the max allowed RX packet 1904 * size so we can receive jumbo frames. 1905 */ 1906 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1907 } 1908 1909 if (sc->re_testmode) 1910 return 0; 1911 1912 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 1913 1914 ifp->if_flags |= IFF_RUNNING; 1915 ifp->if_flags &= ~IFF_OACTIVE; 1916 1917 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1918 1919 out: 1920 if (error) { 1921 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1922 ifp->if_timer = 0; 1923 printf("%s: interface not running\n", 1924 device_xname(sc->sc_dev)); 1925 } 1926 1927 return error; 1928 } 1929 1930 static int 1931 re_ioctl(struct ifnet *ifp, u_long command, void *data) 1932 { 1933 struct rtk_softc *sc = ifp->if_softc; 1934 struct ifreq *ifr = data; 1935 int s, error = 0; 1936 1937 s = splnet(); 1938 1939 switch (command) { 1940 case SIOCSIFMTU: 1941 /* 1942 * Disable jumbo frames if it's not supported. 1943 */ 1944 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 1945 ifr->ifr_mtu > ETHERMTU) { 1946 error = EINVAL; 1947 break; 1948 } 1949 1950 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 1951 error = EINVAL; 1952 else if ((error = ifioctl_common(ifp, command, data)) == 1953 ENETRESET) 1954 error = 0; 1955 break; 1956 default: 1957 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1958 break; 1959 1960 error = 0; 1961 1962 if (command == SIOCSIFCAP) 1963 error = (*ifp->if_init)(ifp); 1964 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1965 ; 1966 else if (ifp->if_flags & IFF_RUNNING) 1967 rtk_setmulti(sc); 1968 break; 1969 } 1970 1971 splx(s); 1972 1973 return error; 1974 } 1975 1976 static void 1977 re_watchdog(struct ifnet *ifp) 1978 { 1979 struct rtk_softc *sc; 1980 int s; 1981 1982 sc = ifp->if_softc; 1983 s = splnet(); 1984 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1985 ifp->if_oerrors++; 1986 1987 re_txeof(sc); 1988 re_rxeof(sc); 1989 1990 re_init(ifp); 1991 1992 splx(s); 1993 } 1994 1995 /* 1996 * Stop the adapter and free any mbufs allocated to the 1997 * RX and TX lists. 1998 */ 1999 static void 2000 re_stop(struct ifnet *ifp, int disable) 2001 { 2002 int i; 2003 struct rtk_softc *sc = ifp->if_softc; 2004 2005 callout_stop(&sc->rtk_tick_ch); 2006 2007 mii_down(&sc->mii); 2008 2009 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0) 2010 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB | 2011 RTK_CMD_RX_ENB); 2012 else 2013 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2014 DELAY(1000); 2015 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2016 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 2017 2018 if (sc->re_head != NULL) { 2019 m_freem(sc->re_head); 2020 sc->re_head = sc->re_tail = NULL; 2021 } 2022 2023 /* Free the TX list buffers. */ 2024 for (i = 0; i < RE_TX_QLEN; i++) { 2025 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 2026 bus_dmamap_unload(sc->sc_dmat, 2027 sc->re_ldata.re_txq[i].txq_dmamap); 2028 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 2029 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 2030 } 2031 } 2032 2033 /* Free the RX list buffers. */ 2034 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2035 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 2036 bus_dmamap_unload(sc->sc_dmat, 2037 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2038 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2039 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2040 } 2041 } 2042 2043 if (disable) 2044 re_disable(sc); 2045 2046 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2047 ifp->if_timer = 0; 2048 } 2049
Indexes created Wed Oct 22 00:09:40 GMT 2025