rtl8169.c revision 1.160
1 /* $NetBSD: rtl8169.c,v 1.160 2019/09/22 16:41:19 ryo Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.160 2019/09/22 16:41:19 ryo Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul (at) windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * six devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168 and the RTL8111. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/kernel.h> 122 #include <sys/socket.h> 123 #include <sys/device.h> 124 125 #include <net/if.h> 126 #include <net/if_arp.h> 127 #include <net/if_dl.h> 128 #include <net/if_ether.h> 129 #include <net/if_media.h> 130 #include <net/if_vlanvar.h> 131 132 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 133 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 134 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 135 136 #include <net/bpf.h> 137 #include <sys/rndsource.h> 138 139 #include <sys/bus.h> 140 141 #include <dev/mii/mii.h> 142 #include <dev/mii/miivar.h> 143 144 #include <dev/ic/rtl81x9reg.h> 145 #include <dev/ic/rtl81x9var.h> 146 147 #include <dev/ic/rtl8169var.h> 148 149 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 150 151 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 152 static int re_rx_list_init(struct rtk_softc *); 153 static int re_tx_list_init(struct rtk_softc *); 154 static void re_rxeof(struct rtk_softc *); 155 static void re_txeof(struct rtk_softc *); 156 static void re_tick(void *); 157 static void re_start(struct ifnet *); 158 static int re_ioctl(struct ifnet *, u_long, void *); 159 static int re_init(struct ifnet *); 160 static void re_stop(struct ifnet *, int); 161 static void re_watchdog(struct ifnet *); 162 163 static int re_enable(struct rtk_softc *); 164 static void re_disable(struct rtk_softc *); 165 166 static int re_gmii_readreg(device_t, int, int, uint16_t *); 167 static int re_gmii_writereg(device_t, int, int, uint16_t); 168 169 static int re_miibus_readreg(device_t, int, int, uint16_t *); 170 static int re_miibus_writereg(device_t, int, int, uint16_t); 171 static void re_miibus_statchg(struct ifnet *); 172 173 static void re_reset(struct rtk_softc *); 174 175 static inline void 176 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 177 { 178 179 d->re_bufaddr_lo = htole32((uint32_t)addr); 180 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 181 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32); 182 else 183 d->re_bufaddr_hi = 0; 184 } 185 186 static int 187 re_gmii_readreg(device_t dev, int phy, int reg, uint16_t *val) 188 { 189 struct rtk_softc *sc = device_private(dev); 190 uint32_t data; 191 int i; 192 193 if (phy != 7) 194 return -1; 195 196 /* Let the rgephy driver read the GMEDIASTAT register */ 197 198 if (reg == RTK_GMEDIASTAT) { 199 *val = CSR_READ_1(sc, RTK_GMEDIASTAT); 200 return 0; 201 } 202 203 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 204 DELAY(1000); 205 206 for (i = 0; i < RTK_TIMEOUT; i++) { 207 data = CSR_READ_4(sc, RTK_PHYAR); 208 if (data & RTK_PHYAR_BUSY) 209 break; 210 DELAY(100); 211 } 212 213 if (i == RTK_TIMEOUT) { 214 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 215 return ETIMEDOUT; 216 } 217 218 *val = data & RTK_PHYAR_PHYDATA; 219 return 0; 220 } 221 222 static int 223 re_gmii_writereg(device_t dev, int phy, int reg, uint16_t val) 224 { 225 struct rtk_softc *sc = device_private(dev); 226 uint32_t data; 227 int i; 228 229 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 230 (val & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 231 DELAY(1000); 232 233 for (i = 0; i < RTK_TIMEOUT; i++) { 234 data = CSR_READ_4(sc, RTK_PHYAR); 235 if (!(data & RTK_PHYAR_BUSY)) 236 break; 237 DELAY(100); 238 } 239 240 if (i == RTK_TIMEOUT) { 241 printf("%s: PHY write reg %x <- %hx failed\n", 242 device_xname(sc->sc_dev), reg, val); 243 return ETIMEDOUT; 244 } 245 246 return 0; 247 } 248 249 static int 250 re_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 251 { 252 struct rtk_softc *sc = device_private(dev); 253 uint16_t re8139_reg = 0; 254 int s, rv = 0; 255 256 s = splnet(); 257 258 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 259 rv = re_gmii_readreg(dev, phy, reg, val); 260 splx(s); 261 return rv; 262 } 263 264 /* Pretend the internal PHY is only at address 0 */ 265 if (phy) { 266 splx(s); 267 return -1; 268 } 269 switch (reg) { 270 case MII_BMCR: 271 re8139_reg = RTK_BMCR; 272 break; 273 case MII_BMSR: 274 re8139_reg = RTK_BMSR; 275 break; 276 case MII_ANAR: 277 re8139_reg = RTK_ANAR; 278 break; 279 case MII_ANER: 280 re8139_reg = RTK_ANER; 281 break; 282 case MII_ANLPAR: 283 re8139_reg = RTK_LPAR; 284 break; 285 case MII_PHYIDR1: 286 case MII_PHYIDR2: 287 *val = 0; 288 splx(s); 289 return 0; 290 /* 291 * Allow the rlphy driver to read the media status 292 * register. If we have a link partner which does not 293 * support NWAY, this is the register which will tell 294 * us the results of parallel detection. 295 */ 296 case RTK_MEDIASTAT: 297 *val = CSR_READ_1(sc, RTK_MEDIASTAT); 298 splx(s); 299 return 0; 300 default: 301 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 302 splx(s); 303 return -1; 304 } 305 *val = CSR_READ_2(sc, re8139_reg); 306 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 307 /* 8139C+ has different bit layout. */ 308 *val &= ~(BMCR_LOOP | BMCR_ISO); 309 } 310 splx(s); 311 return 0; 312 } 313 314 static int 315 re_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 316 { 317 struct rtk_softc *sc = device_private(dev); 318 uint16_t re8139_reg = 0; 319 int s, rv; 320 321 s = splnet(); 322 323 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 324 rv = re_gmii_writereg(dev, phy, reg, val); 325 splx(s); 326 return rv; 327 } 328 329 /* Pretend the internal PHY is only at address 0 */ 330 if (phy) { 331 splx(s); 332 return -1; 333 } 334 switch (reg) { 335 case MII_BMCR: 336 re8139_reg = RTK_BMCR; 337 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 338 /* 8139C+ has different bit layout. */ 339 val &= ~(BMCR_LOOP | BMCR_ISO); 340 } 341 break; 342 case MII_BMSR: 343 re8139_reg = RTK_BMSR; 344 break; 345 case MII_ANAR: 346 re8139_reg = RTK_ANAR; 347 break; 348 case MII_ANER: 349 re8139_reg = RTK_ANER; 350 break; 351 case MII_ANLPAR: 352 re8139_reg = RTK_LPAR; 353 break; 354 case MII_PHYIDR1: 355 case MII_PHYIDR2: 356 splx(s); 357 return 0; 358 break; 359 default: 360 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 361 splx(s); 362 return -1; 363 } 364 CSR_WRITE_2(sc, re8139_reg, val); 365 splx(s); 366 return 0; 367 } 368 369 static void 370 re_miibus_statchg(struct ifnet *ifp) 371 { 372 373 return; 374 } 375 376 static void 377 re_reset(struct rtk_softc *sc) 378 { 379 int i; 380 381 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 382 383 for (i = 0; i < RTK_TIMEOUT; i++) { 384 DELAY(10); 385 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 386 break; 387 } 388 if (i == RTK_TIMEOUT) 389 printf("%s: reset never completed!\n", 390 device_xname(sc->sc_dev)); 391 392 /* 393 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 394 * but also says "Rtl8169s sigle chip detected". 395 */ 396 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 397 CSR_WRITE_1(sc, RTK_LDPS, 1); 398 399 } 400 401 /* 402 * The following routine is designed to test for a defect on some 403 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 404 * lines connected to the bus, however for a 32-bit only card, they 405 * should be pulled high. The result of this defect is that the 406 * NIC will not work right if you plug it into a 64-bit slot: DMA 407 * operations will be done with 64-bit transfers, which will fail 408 * because the 64-bit data lines aren't connected. 409 * 410 * There's no way to work around this (short of talking a soldering 411 * iron to the board), however we can detect it. The method we use 412 * here is to put the NIC into digital loopback mode, set the receiver 413 * to promiscuous mode, and then try to send a frame. We then compare 414 * the frame data we sent to what was received. If the data matches, 415 * then the NIC is working correctly, otherwise we know the user has 416 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 417 * slot. In the latter case, there's no way the NIC can work correctly, 418 * so we print out a message on the console and abort the device attach. 419 */ 420 421 int 422 re_diag(struct rtk_softc *sc) 423 { 424 struct ifnet *ifp = &sc->ethercom.ec_if; 425 struct mbuf *m0; 426 struct ether_header *eh; 427 struct re_rxsoft *rxs; 428 struct re_desc *cur_rx; 429 bus_dmamap_t dmamap; 430 uint16_t status; 431 uint32_t rxstat; 432 int total_len, i, s, error = 0; 433 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 434 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 435 436 /* Allocate a single mbuf */ 437 438 MGETHDR(m0, M_DONTWAIT, MT_DATA); 439 if (m0 == NULL) 440 return ENOBUFS; 441 442 /* 443 * Initialize the NIC in test mode. This sets the chip up 444 * so that it can send and receive frames, but performs the 445 * following special functions: 446 * - Puts receiver in promiscuous mode 447 * - Enables digital loopback mode 448 * - Leaves interrupts turned off 449 */ 450 451 ifp->if_flags |= IFF_PROMISC; 452 sc->re_testmode = 1; 453 re_init(ifp); 454 re_stop(ifp, 0); 455 DELAY(100000); 456 re_init(ifp); 457 458 /* Put some data in the mbuf */ 459 460 eh = mtod(m0, struct ether_header *); 461 memcpy(eh->ether_dhost, &dst, ETHER_ADDR_LEN); 462 memcpy(eh->ether_shost, &src, ETHER_ADDR_LEN); 463 eh->ether_type = htons(ETHERTYPE_IP); 464 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 465 466 /* 467 * Queue the packet, start transmission. 468 */ 469 470 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 471 s = splnet(); 472 IF_ENQUEUE(&ifp->if_snd, m0); 473 re_start(ifp); 474 splx(s); 475 m0 = NULL; 476 477 /* Wait for it to propagate through the chip */ 478 479 DELAY(100000); 480 for (i = 0; i < RTK_TIMEOUT; i++) { 481 status = CSR_READ_2(sc, RTK_ISR); 482 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 483 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 484 break; 485 DELAY(10); 486 } 487 if (i == RTK_TIMEOUT) { 488 aprint_error_dev(sc->sc_dev, 489 "diagnostic failed, failed to receive packet " 490 "in loopback mode\n"); 491 error = EIO; 492 goto done; 493 } 494 495 /* 496 * The packet should have been dumped into the first 497 * entry in the RX DMA ring. Grab it from there. 498 */ 499 500 rxs = &sc->re_ldata.re_rxsoft[0]; 501 dmamap = rxs->rxs_dmamap; 502 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 503 BUS_DMASYNC_POSTREAD); 504 bus_dmamap_unload(sc->sc_dmat, dmamap); 505 506 m0 = rxs->rxs_mbuf; 507 rxs->rxs_mbuf = NULL; 508 eh = mtod(m0, struct ether_header *); 509 510 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 511 cur_rx = &sc->re_ldata.re_rx_list[0]; 512 rxstat = le32toh(cur_rx->re_cmdstat); 513 total_len = rxstat & sc->re_rxlenmask; 514 515 if (total_len != ETHER_MIN_LEN) { 516 aprint_error_dev(sc->sc_dev, 517 "diagnostic failed, received short packet\n"); 518 error = EIO; 519 goto done; 520 } 521 522 /* Test that the received packet data matches what we sent. */ 523 524 if (memcmp(&eh->ether_dhost, &dst, ETHER_ADDR_LEN) || 525 memcmp(&eh->ether_shost, &src, ETHER_ADDR_LEN) || 526 ntohs(eh->ether_type) != ETHERTYPE_IP) { 527 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 528 "expected TX data: %s/%s/0x%x\n" 529 "received RX data: %s/%s/0x%x\n" 530 "You may have a defective 32-bit NIC plugged " 531 "into a 64-bit PCI slot.\n" 532 "Please re-install the NIC in a 32-bit slot " 533 "for proper operation.\n" 534 "Read the re(4) man page for more details.\n" , 535 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 536 ether_sprintf(eh->ether_dhost), 537 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 538 error = EIO; 539 } 540 541 done: 542 /* Turn interface off, release resources */ 543 544 sc->re_testmode = 0; 545 ifp->if_flags &= ~IFF_PROMISC; 546 re_stop(ifp, 0); 547 if (m0 != NULL) 548 m_freem(m0); 549 550 return error; 551 } 552 553 554 /* 555 * Attach the interface. Allocate softc structures, do ifmedia 556 * setup and ethernet/BPF attach. 557 */ 558 void 559 re_attach(struct rtk_softc *sc) 560 { 561 uint8_t eaddr[ETHER_ADDR_LEN]; 562 struct ifnet *ifp; 563 struct mii_data *mii = &sc->mii; 564 int error = 0, i; 565 566 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 567 uint32_t hwrev; 568 569 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 570 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 571 switch (hwrev) { 572 case RTK_HWREV_8169: 573 sc->sc_quirk |= RTKQ_8169NONS; 574 break; 575 case RTK_HWREV_8169S: 576 case RTK_HWREV_8110S: 577 case RTK_HWREV_8169_8110SB: 578 case RTK_HWREV_8169_8110SBL: 579 case RTK_HWREV_8169_8110SC: 580 sc->sc_quirk |= RTKQ_MACLDPS; 581 break; 582 case RTK_HWREV_8168_SPIN1: 583 case RTK_HWREV_8168_SPIN2: 584 case RTK_HWREV_8168_SPIN3: 585 sc->sc_quirk |= RTKQ_MACSTAT; 586 break; 587 case RTK_HWREV_8168C: 588 case RTK_HWREV_8168C_SPIN2: 589 case RTK_HWREV_8168CP: 590 case RTK_HWREV_8168D: 591 case RTK_HWREV_8168DP: 592 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 593 RTKQ_MACSTAT | RTKQ_CMDSTOP; 594 /* 595 * From FreeBSD driver: 596 * 597 * These (8168/8111) controllers support jumbo frame 598 * but it seems that enabling it requires touching 599 * additional magic registers. Depending on MAC 600 * revisions some controllers need to disable 601 * checksum offload. So disable jumbo frame until 602 * I have better idea what it really requires to 603 * make it support. 604 * RTL8168C/CP : supports up to 6KB jumbo frame. 605 * RTL8111C/CP : supports up to 9KB jumbo frame. 606 */ 607 sc->sc_quirk |= RTKQ_NOJUMBO; 608 break; 609 case RTK_HWREV_8168E: 610 case RTK_HWREV_8168H_SPIN1: 611 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 612 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM | 613 RTKQ_NOJUMBO; 614 break; 615 case RTK_HWREV_8168H: 616 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 617 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM | 618 RTKQ_NOJUMBO | RTKQ_RXDV_GATED | RTKQ_TXRXEN_LATER; 619 break; 620 case RTK_HWREV_8168E_VL: 621 case RTK_HWREV_8168F: 622 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 623 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 624 break; 625 case RTK_HWREV_8168G: 626 case RTK_HWREV_8168G_SPIN1: 627 case RTK_HWREV_8168G_SPIN2: 628 case RTK_HWREV_8168G_SPIN4: 629 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 630 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO | 631 RTKQ_RXDV_GATED; 632 break; 633 case RTK_HWREV_8100E: 634 case RTK_HWREV_8100E_SPIN2: 635 case RTK_HWREV_8101E: 636 sc->sc_quirk |= RTKQ_NOJUMBO; 637 break; 638 case RTK_HWREV_8102E: 639 case RTK_HWREV_8102EL: 640 case RTK_HWREV_8103E: 641 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 642 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 643 break; 644 default: 645 aprint_normal_dev(sc->sc_dev, 646 "Unknown revision (0x%08x)\n", hwrev); 647 /* assume the latest features */ 648 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 649 sc->sc_quirk |= RTKQ_NOJUMBO; 650 } 651 652 /* Set RX length mask */ 653 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 654 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 655 } else { 656 sc->sc_quirk |= RTKQ_NOJUMBO; 657 658 /* Set RX length mask */ 659 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 660 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 661 } 662 663 /* Reset the adapter. */ 664 re_reset(sc); 665 666 /* 667 * RTL81x9 chips automatically read EEPROM to init MAC address, 668 * and some NAS override its MAC address per own configuration, 669 * so no need to explicitely read EEPROM and set ID registers. 670 */ 671 #ifdef RE_USE_EECMD 672 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 673 /* 674 * Get station address from ID registers. 675 */ 676 for (i = 0; i < ETHER_ADDR_LEN; i++) 677 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 678 } else { 679 uint16_t val; 680 int addr_len; 681 682 /* 683 * Get station address from the EEPROM. 684 */ 685 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 686 addr_len = RTK_EEADDR_LEN1; 687 else 688 addr_len = RTK_EEADDR_LEN0; 689 690 /* 691 * Get station address from the EEPROM. 692 */ 693 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 694 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 695 eaddr[(i * 2) + 0] = val & 0xff; 696 eaddr[(i * 2) + 1] = val >> 8; 697 } 698 } 699 #else 700 /* 701 * Get station address from ID registers. 702 */ 703 for (i = 0; i < ETHER_ADDR_LEN; i++) 704 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 705 #endif 706 707 /* Take PHY out of power down mode. */ 708 if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0) 709 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80); 710 711 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 712 ether_sprintf(eaddr)); 713 714 if (sc->re_ldata.re_tx_desc_cnt > 715 PAGE_SIZE / sizeof(struct re_desc)) { 716 sc->re_ldata.re_tx_desc_cnt = 717 PAGE_SIZE / sizeof(struct re_desc); 718 } 719 720 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 721 sc->re_ldata.re_tx_desc_cnt); 722 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 723 724 /* Allocate DMA'able memory for the TX ring */ 725 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 726 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 727 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 728 aprint_error_dev(sc->sc_dev, 729 "can't allocate tx listseg, error = %d\n", error); 730 goto fail_0; 731 } 732 733 /* Load the map for the TX ring. */ 734 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 735 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 736 (void **)&sc->re_ldata.re_tx_list, 737 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 738 aprint_error_dev(sc->sc_dev, 739 "can't map tx list, error = %d\n", error); 740 goto fail_1; 741 } 742 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 743 744 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 745 RE_TX_LIST_SZ(sc), 0, 0, 746 &sc->re_ldata.re_tx_list_map)) != 0) { 747 aprint_error_dev(sc->sc_dev, 748 "can't create tx list map, error = %d\n", error); 749 goto fail_2; 750 } 751 752 753 if ((error = bus_dmamap_load(sc->sc_dmat, 754 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 755 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 756 aprint_error_dev(sc->sc_dev, 757 "can't load tx list, error = %d\n", error); 758 goto fail_3; 759 } 760 761 /* Create DMA maps for TX buffers */ 762 for (i = 0; i < RE_TX_QLEN; i++) { 763 error = bus_dmamap_create(sc->sc_dmat, 764 round_page(IP_MAXPACKET), 765 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 766 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 767 if (error) { 768 aprint_error_dev(sc->sc_dev, 769 "can't create DMA map for TX\n"); 770 goto fail_4; 771 } 772 } 773 774 /* Allocate DMA'able memory for the RX ring */ 775 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 776 if ((error = bus_dmamem_alloc(sc->sc_dmat, 777 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 778 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 779 aprint_error_dev(sc->sc_dev, 780 "can't allocate rx listseg, error = %d\n", error); 781 goto fail_4; 782 } 783 784 /* Load the map for the RX ring. */ 785 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 786 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 787 (void **)&sc->re_ldata.re_rx_list, 788 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 789 aprint_error_dev(sc->sc_dev, 790 "can't map rx list, error = %d\n", error); 791 goto fail_5; 792 } 793 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 794 795 if ((error = bus_dmamap_create(sc->sc_dmat, 796 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 797 &sc->re_ldata.re_rx_list_map)) != 0) { 798 aprint_error_dev(sc->sc_dev, 799 "can't create rx list map, error = %d\n", error); 800 goto fail_6; 801 } 802 803 if ((error = bus_dmamap_load(sc->sc_dmat, 804 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 805 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 806 aprint_error_dev(sc->sc_dev, 807 "can't load rx list, error = %d\n", error); 808 goto fail_7; 809 } 810 811 /* Create DMA maps for RX buffers */ 812 for (i = 0; i < RE_RX_DESC_CNT; i++) { 813 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 814 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 815 if (error) { 816 aprint_error_dev(sc->sc_dev, 817 "can't create DMA map for RX\n"); 818 goto fail_8; 819 } 820 } 821 822 /* 823 * Record interface as attached. From here, we should not fail. 824 */ 825 sc->sc_flags |= RTK_ATTACHED; 826 827 ifp = &sc->ethercom.ec_if; 828 ifp->if_softc = sc; 829 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 830 ifp->if_mtu = ETHERMTU; 831 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 832 ifp->if_ioctl = re_ioctl; 833 sc->ethercom.ec_capabilities |= 834 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 835 ifp->if_start = re_start; 836 ifp->if_stop = re_stop; 837 838 /* 839 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 840 * so we have a workaround to handle the bug by padding 841 * such packets manually. 842 */ 843 ifp->if_capabilities |= 844 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 845 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 846 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 847 IFCAP_TSOv4; 848 849 ifp->if_watchdog = re_watchdog; 850 ifp->if_init = re_init; 851 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 852 ifp->if_capenable = ifp->if_capabilities; 853 IFQ_SET_READY(&ifp->if_snd); 854 855 callout_init(&sc->rtk_tick_ch, 0); 856 857 /* Do MII setup */ 858 mii->mii_ifp = ifp; 859 mii->mii_readreg = re_miibus_readreg; 860 mii->mii_writereg = re_miibus_writereg; 861 mii->mii_statchg = re_miibus_statchg; 862 sc->ethercom.ec_mii = mii; 863 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 864 ether_mediastatus); 865 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 866 MII_OFFSET_ANY, 0); 867 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 868 869 /* 870 * Call MI attach routine. 871 */ 872 if_attach(ifp); 873 if_deferred_start_init(ifp, NULL); 874 ether_ifattach(ifp, eaddr); 875 876 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 877 RND_TYPE_NET, RND_FLAG_DEFAULT); 878 879 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 880 pmf_class_network_register(sc->sc_dev, ifp); 881 else 882 aprint_error_dev(sc->sc_dev, 883 "couldn't establish power handler\n"); 884 885 return; 886 887 fail_8: 888 /* Destroy DMA maps for RX buffers. */ 889 for (i = 0; i < RE_RX_DESC_CNT; i++) 890 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 891 bus_dmamap_destroy(sc->sc_dmat, 892 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 893 894 /* Free DMA'able memory for the RX ring. */ 895 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 896 fail_7: 897 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 898 fail_6: 899 bus_dmamem_unmap(sc->sc_dmat, 900 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 901 fail_5: 902 bus_dmamem_free(sc->sc_dmat, 903 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 904 905 fail_4: 906 /* Destroy DMA maps for TX buffers. */ 907 for (i = 0; i < RE_TX_QLEN; i++) 908 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 909 bus_dmamap_destroy(sc->sc_dmat, 910 sc->re_ldata.re_txq[i].txq_dmamap); 911 912 /* Free DMA'able memory for the TX ring. */ 913 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 914 fail_3: 915 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 916 fail_2: 917 bus_dmamem_unmap(sc->sc_dmat, 918 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 919 fail_1: 920 bus_dmamem_free(sc->sc_dmat, 921 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 922 fail_0: 923 return; 924 } 925 926 927 /* 928 * re_activate: 929 * Handle device activation/deactivation requests. 930 */ 931 int 932 re_activate(device_t self, enum devact act) 933 { 934 struct rtk_softc *sc = device_private(self); 935 936 switch (act) { 937 case DVACT_DEACTIVATE: 938 if_deactivate(&sc->ethercom.ec_if); 939 return 0; 940 default: 941 return EOPNOTSUPP; 942 } 943 } 944 945 /* 946 * re_detach: 947 * Detach a rtk interface. 948 */ 949 int 950 re_detach(struct rtk_softc *sc) 951 { 952 struct ifnet *ifp = &sc->ethercom.ec_if; 953 int i; 954 955 /* 956 * Succeed now if there isn't any work to do. 957 */ 958 if ((sc->sc_flags & RTK_ATTACHED) == 0) 959 return 0; 960 961 /* Unhook our tick handler. */ 962 callout_stop(&sc->rtk_tick_ch); 963 964 /* Detach all PHYs. */ 965 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 966 967 /* Delete all remaining media. */ 968 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 969 970 rnd_detach_source(&sc->rnd_source); 971 ether_ifdetach(ifp); 972 if_detach(ifp); 973 974 /* Destroy DMA maps for RX buffers. */ 975 for (i = 0; i < RE_RX_DESC_CNT; i++) 976 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 977 bus_dmamap_destroy(sc->sc_dmat, 978 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 979 980 /* Free DMA'able memory for the RX ring. */ 981 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 982 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 983 bus_dmamem_unmap(sc->sc_dmat, 984 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 985 bus_dmamem_free(sc->sc_dmat, 986 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 987 988 /* Destroy DMA maps for TX buffers. */ 989 for (i = 0; i < RE_TX_QLEN; i++) 990 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 991 bus_dmamap_destroy(sc->sc_dmat, 992 sc->re_ldata.re_txq[i].txq_dmamap); 993 994 /* Free DMA'able memory for the TX ring. */ 995 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 996 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 997 bus_dmamem_unmap(sc->sc_dmat, 998 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 999 bus_dmamem_free(sc->sc_dmat, 1000 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 1001 1002 pmf_device_deregister(sc->sc_dev); 1003 1004 /* we don't want to run again */ 1005 sc->sc_flags &= ~RTK_ATTACHED; 1006 1007 return 0; 1008 } 1009 1010 /* 1011 * re_enable: 1012 * Enable the RTL81X9 chip. 1013 */ 1014 static int 1015 re_enable(struct rtk_softc *sc) 1016 { 1017 1018 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 1019 if ((*sc->sc_enable)(sc) != 0) { 1020 printf("%s: device enable failed\n", 1021 device_xname(sc->sc_dev)); 1022 return EIO; 1023 } 1024 sc->sc_flags |= RTK_ENABLED; 1025 } 1026 return 0; 1027 } 1028 1029 /* 1030 * re_disable: 1031 * Disable the RTL81X9 chip. 1032 */ 1033 static void 1034 re_disable(struct rtk_softc *sc) 1035 { 1036 1037 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 1038 (*sc->sc_disable)(sc); 1039 sc->sc_flags &= ~RTK_ENABLED; 1040 } 1041 } 1042 1043 static int 1044 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1045 { 1046 struct mbuf *n = NULL; 1047 bus_dmamap_t map; 1048 struct re_desc *d; 1049 struct re_rxsoft *rxs; 1050 uint32_t cmdstat; 1051 int error; 1052 1053 if (m == NULL) { 1054 MGETHDR(n, M_DONTWAIT, MT_DATA); 1055 if (n == NULL) 1056 return ENOBUFS; 1057 1058 MCLGET(n, M_DONTWAIT); 1059 if ((n->m_flags & M_EXT) == 0) { 1060 m_freem(n); 1061 return ENOBUFS; 1062 } 1063 m = n; 1064 } else 1065 m->m_data = m->m_ext.ext_buf; 1066 1067 /* 1068 * Initialize mbuf length fields and fixup 1069 * alignment so that the frame payload is 1070 * longword aligned. 1071 */ 1072 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1073 m->m_data += RE_ETHER_ALIGN; 1074 1075 rxs = &sc->re_ldata.re_rxsoft[idx]; 1076 map = rxs->rxs_dmamap; 1077 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1078 BUS_DMA_READ|BUS_DMA_NOWAIT); 1079 1080 if (error) 1081 goto out; 1082 1083 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1084 BUS_DMASYNC_PREREAD); 1085 1086 d = &sc->re_ldata.re_rx_list[idx]; 1087 #ifdef DIAGNOSTIC 1088 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1089 cmdstat = le32toh(d->re_cmdstat); 1090 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1091 if (cmdstat & RE_RDESC_STAT_OWN) { 1092 panic("%s: tried to map busy RX descriptor", 1093 device_xname(sc->sc_dev)); 1094 } 1095 #endif 1096 1097 rxs->rxs_mbuf = m; 1098 1099 d->re_vlanctl = 0; 1100 cmdstat = map->dm_segs[0].ds_len; 1101 if (idx == (RE_RX_DESC_CNT - 1)) 1102 cmdstat |= RE_RDESC_CMD_EOR; 1103 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1104 d->re_cmdstat = htole32(cmdstat); 1105 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1106 cmdstat |= RE_RDESC_CMD_OWN; 1107 d->re_cmdstat = htole32(cmdstat); 1108 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1109 1110 return 0; 1111 out: 1112 if (n != NULL) 1113 m_freem(n); 1114 return ENOMEM; 1115 } 1116 1117 static int 1118 re_tx_list_init(struct rtk_softc *sc) 1119 { 1120 int i; 1121 1122 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1123 for (i = 0; i < RE_TX_QLEN; i++) { 1124 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1125 } 1126 1127 bus_dmamap_sync(sc->sc_dmat, 1128 sc->re_ldata.re_tx_list_map, 0, 1129 sc->re_ldata.re_tx_list_map->dm_mapsize, 1130 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1131 sc->re_ldata.re_txq_prodidx = 0; 1132 sc->re_ldata.re_txq_considx = 0; 1133 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1134 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1135 sc->re_ldata.re_tx_nextfree = 0; 1136 1137 return 0; 1138 } 1139 1140 static int 1141 re_rx_list_init(struct rtk_softc *sc) 1142 { 1143 int i; 1144 1145 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1146 1147 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1148 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1149 return ENOBUFS; 1150 } 1151 1152 sc->re_ldata.re_rx_prodidx = 0; 1153 sc->re_head = sc->re_tail = NULL; 1154 1155 return 0; 1156 } 1157 1158 /* 1159 * RX handler for C+ and 8169. For the gigE chips, we support 1160 * the reception of jumbo frames that have been fragmented 1161 * across multiple 2K mbuf cluster buffers. 1162 */ 1163 static void 1164 re_rxeof(struct rtk_softc *sc) 1165 { 1166 struct mbuf *m; 1167 struct ifnet *ifp; 1168 int i, total_len; 1169 struct re_desc *cur_rx; 1170 struct re_rxsoft *rxs; 1171 uint32_t rxstat, rxvlan; 1172 1173 ifp = &sc->ethercom.ec_if; 1174 1175 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1176 cur_rx = &sc->re_ldata.re_rx_list[i]; 1177 RE_RXDESCSYNC(sc, i, 1178 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1179 rxstat = le32toh(cur_rx->re_cmdstat); 1180 rxvlan = le32toh(cur_rx->re_vlanctl); 1181 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1182 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1183 break; 1184 } 1185 total_len = rxstat & sc->re_rxlenmask; 1186 rxs = &sc->re_ldata.re_rxsoft[i]; 1187 m = rxs->rxs_mbuf; 1188 1189 /* Invalidate the RX mbuf and unload its map */ 1190 1191 bus_dmamap_sync(sc->sc_dmat, 1192 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1193 BUS_DMASYNC_POSTREAD); 1194 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1195 1196 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1197 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1198 if (sc->re_head == NULL) 1199 sc->re_head = sc->re_tail = m; 1200 else { 1201 m_remove_pkthdr(m); 1202 sc->re_tail->m_next = m; 1203 sc->re_tail = m; 1204 } 1205 re_newbuf(sc, i, NULL); 1206 continue; 1207 } 1208 1209 /* 1210 * NOTE: for the 8139C+, the frame length field 1211 * is always 12 bits in size, but for the gigE chips, 1212 * it is 13 bits (since the max RX frame length is 16K). 1213 * Unfortunately, all 32 bits in the status word 1214 * were already used, so to make room for the extra 1215 * length bit, RealTek took out the 'frame alignment 1216 * error' bit and shifted the other status bits 1217 * over one slot. The OWN, EOR, FS and LS bits are 1218 * still in the same places. We have already extracted 1219 * the frame length and checked the OWN bit, so rather 1220 * than using an alternate bit mapping, we shift the 1221 * status bits one space to the right so we can evaluate 1222 * them using the 8169 status as though it was in the 1223 * same format as that of the 8139C+. 1224 */ 1225 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1226 rxstat >>= 1; 1227 1228 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1229 #ifdef RE_DEBUG 1230 printf("%s: RX error (rxstat = 0x%08x)", 1231 device_xname(sc->sc_dev), rxstat); 1232 if (rxstat & RE_RDESC_STAT_FRALIGN) 1233 printf(", frame alignment error"); 1234 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1235 printf(", out of buffer space"); 1236 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1237 printf(", FIFO overrun"); 1238 if (rxstat & RE_RDESC_STAT_GIANT) 1239 printf(", giant packet"); 1240 if (rxstat & RE_RDESC_STAT_RUNT) 1241 printf(", runt packet"); 1242 if (rxstat & RE_RDESC_STAT_CRCERR) 1243 printf(", CRC error"); 1244 printf("\n"); 1245 #endif 1246 ifp->if_ierrors++; 1247 /* 1248 * If this is part of a multi-fragment packet, 1249 * discard all the pieces. 1250 */ 1251 if (sc->re_head != NULL) { 1252 m_freem(sc->re_head); 1253 sc->re_head = sc->re_tail = NULL; 1254 } 1255 re_newbuf(sc, i, m); 1256 continue; 1257 } 1258 1259 /* 1260 * If allocating a replacement mbuf fails, 1261 * reload the current one. 1262 */ 1263 1264 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1265 ifp->if_ierrors++; 1266 if (sc->re_head != NULL) { 1267 m_freem(sc->re_head); 1268 sc->re_head = sc->re_tail = NULL; 1269 } 1270 re_newbuf(sc, i, m); 1271 continue; 1272 } 1273 1274 if (sc->re_head != NULL) { 1275 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1276 /* 1277 * Special case: if there's 4 bytes or less 1278 * in this buffer, the mbuf can be discarded: 1279 * the last 4 bytes is the CRC, which we don't 1280 * care about anyway. 1281 */ 1282 if (m->m_len <= ETHER_CRC_LEN) { 1283 sc->re_tail->m_len -= 1284 (ETHER_CRC_LEN - m->m_len); 1285 m_freem(m); 1286 } else { 1287 m->m_len -= ETHER_CRC_LEN; 1288 m_remove_pkthdr(m); 1289 sc->re_tail->m_next = m; 1290 } 1291 m = sc->re_head; 1292 sc->re_head = sc->re_tail = NULL; 1293 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1294 } else 1295 m->m_pkthdr.len = m->m_len = 1296 (total_len - ETHER_CRC_LEN); 1297 1298 m_set_rcvif(m, ifp); 1299 1300 /* Do RX checksumming */ 1301 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1302 /* Check IP header checksum */ 1303 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) { 1304 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1305 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1306 m->m_pkthdr.csum_flags |= 1307 M_CSUM_IPv4_BAD; 1308 1309 /* Check TCP/UDP checksum */ 1310 if (RE_TCPPKT(rxstat)) { 1311 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1312 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1313 m->m_pkthdr.csum_flags |= 1314 M_CSUM_TCP_UDP_BAD; 1315 } else if (RE_UDPPKT(rxstat)) { 1316 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1317 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) { 1318 /* 1319 * XXX: 8139C+ thinks UDP csum 1320 * 0xFFFF is bad, force software 1321 * calculation. 1322 */ 1323 if (sc->sc_quirk & RTKQ_8139CPLUS) 1324 m->m_pkthdr.csum_flags 1325 &= ~M_CSUM_UDPv4; 1326 else 1327 m->m_pkthdr.csum_flags 1328 |= M_CSUM_TCP_UDP_BAD; 1329 } 1330 } 1331 } 1332 } else { 1333 /* Check IPv4 header checksum */ 1334 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) { 1335 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1336 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1337 m->m_pkthdr.csum_flags |= 1338 M_CSUM_IPv4_BAD; 1339 1340 /* Check TCPv4/UDPv4 checksum */ 1341 if (RE_TCPPKT(rxstat)) { 1342 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1343 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1344 m->m_pkthdr.csum_flags |= 1345 M_CSUM_TCP_UDP_BAD; 1346 } else if (RE_UDPPKT(rxstat)) { 1347 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1348 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1349 m->m_pkthdr.csum_flags |= 1350 M_CSUM_TCP_UDP_BAD; 1351 } 1352 } 1353 /* XXX Check TCPv6/UDPv6 checksum? */ 1354 } 1355 1356 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1357 vlan_set_tag(m, 1358 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA)); 1359 } 1360 if_percpuq_enqueue(ifp->if_percpuq, m); 1361 } 1362 1363 sc->re_ldata.re_rx_prodidx = i; 1364 } 1365 1366 static void 1367 re_txeof(struct rtk_softc *sc) 1368 { 1369 struct ifnet *ifp; 1370 struct re_txq *txq; 1371 uint32_t txstat; 1372 int idx, descidx; 1373 1374 ifp = &sc->ethercom.ec_if; 1375 1376 for (idx = sc->re_ldata.re_txq_considx; 1377 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1378 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1379 txq = &sc->re_ldata.re_txq[idx]; 1380 KASSERT(txq->txq_mbuf != NULL); 1381 1382 descidx = txq->txq_descidx; 1383 RE_TXDESCSYNC(sc, descidx, 1384 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1385 txstat = 1386 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1387 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1388 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1389 if (txstat & RE_TDESC_CMD_OWN) { 1390 break; 1391 } 1392 1393 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1394 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1395 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1396 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1397 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1398 m_freem(txq->txq_mbuf); 1399 txq->txq_mbuf = NULL; 1400 1401 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1402 ifp->if_collisions++; 1403 if (txstat & RE_TDESC_STAT_TXERRSUM) 1404 ifp->if_oerrors++; 1405 else 1406 ifp->if_opackets++; 1407 } 1408 1409 sc->re_ldata.re_txq_considx = idx; 1410 1411 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1412 ifp->if_flags &= ~IFF_OACTIVE; 1413 1414 /* 1415 * If not all descriptors have been released reaped yet, 1416 * reload the timer so that we will eventually get another 1417 * interrupt that will cause us to re-enter this routine. 1418 * This is done in case the transmitter has gone idle. 1419 */ 1420 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1421 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) 1422 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1423 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1424 /* 1425 * Some chips will ignore a second TX request 1426 * issued while an existing transmission is in 1427 * progress. If the transmitter goes idle but 1428 * there are still packets waiting to be sent, 1429 * we need to restart the channel here to flush 1430 * them out. This only seems to be required with 1431 * the PCIe devices. 1432 */ 1433 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1434 } 1435 } else 1436 ifp->if_timer = 0; 1437 } 1438 1439 static void 1440 re_tick(void *arg) 1441 { 1442 struct rtk_softc *sc = arg; 1443 int s; 1444 1445 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1446 s = splnet(); 1447 1448 mii_tick(&sc->mii); 1449 splx(s); 1450 1451 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1452 } 1453 1454 int 1455 re_intr(void *arg) 1456 { 1457 struct rtk_softc *sc = arg; 1458 struct ifnet *ifp; 1459 uint16_t status; 1460 int handled = 0; 1461 1462 if (!device_has_power(sc->sc_dev)) 1463 return 0; 1464 1465 ifp = &sc->ethercom.ec_if; 1466 1467 if ((ifp->if_flags & IFF_UP) == 0) 1468 return 0; 1469 1470 const uint16_t status_mask = (sc->sc_quirk & RTKQ_IM_HW) ? 1471 RTK_INTRS_IM_HW : RTK_INTRS_CPLUS; 1472 1473 for (;;) { 1474 1475 status = CSR_READ_2(sc, RTK_ISR); 1476 /* If the card has gone away the read returns 0xffff. */ 1477 if (status == 0xffff) 1478 break; 1479 if (status) { 1480 handled = 1; 1481 CSR_WRITE_2(sc, RTK_ISR, status); 1482 } 1483 1484 if ((status & status_mask) == 0) 1485 break; 1486 1487 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1488 re_rxeof(sc); 1489 1490 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1491 RTK_ISR_TX_DESC_UNAVAIL | RTK_ISR_TX_OK)) 1492 re_txeof(sc); 1493 1494 if (status & RTK_ISR_SYSTEM_ERR) { 1495 re_init(ifp); 1496 } 1497 1498 if (status & RTK_ISR_LINKCHG) { 1499 callout_stop(&sc->rtk_tick_ch); 1500 re_tick(sc); 1501 } 1502 } 1503 1504 if (handled) 1505 if_schedule_deferred_start(ifp); 1506 1507 rnd_add_uint32(&sc->rnd_source, status); 1508 1509 return handled; 1510 } 1511 1512 1513 1514 /* 1515 * Main transmit routine for C+ and gigE NICs. 1516 */ 1517 1518 static void 1519 re_start(struct ifnet *ifp) 1520 { 1521 struct rtk_softc *sc; 1522 struct mbuf *m; 1523 bus_dmamap_t map; 1524 struct re_txq *txq; 1525 struct re_desc *d; 1526 uint32_t cmdstat, re_flags, vlanctl; 1527 int ofree, idx, error, nsegs, seg; 1528 int startdesc, curdesc, lastdesc; 1529 bool pad; 1530 1531 sc = ifp->if_softc; 1532 ofree = sc->re_ldata.re_txq_free; 1533 1534 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1535 1536 IFQ_POLL(&ifp->if_snd, m); 1537 if (m == NULL) 1538 break; 1539 1540 if (sc->re_ldata.re_txq_free == 0 || 1541 sc->re_ldata.re_tx_free == 0) { 1542 /* no more free slots left */ 1543 ifp->if_flags |= IFF_OACTIVE; 1544 break; 1545 } 1546 1547 /* 1548 * Set up checksum offload. Note: checksum offload bits must 1549 * appear in all descriptors of a multi-descriptor transmit 1550 * attempt. (This is according to testing done with an 8169 1551 * chip. I'm not sure if this is a requirement or a bug.) 1552 */ 1553 1554 vlanctl = 0; 1555 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1556 uint32_t segsz = m->m_pkthdr.segsz; 1557 1558 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1559 re_flags = RE_TDESC_CMD_LGSEND | 1560 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1561 } else { 1562 re_flags = RE_TDESC_CMD_LGSEND_V4; 1563 vlanctl |= 1564 (segsz << RE_TDESC_VLANCTL_MSSVAL_SHIFT); 1565 } 1566 } else { 1567 /* 1568 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1569 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1570 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1571 */ 1572 re_flags = 0; 1573 if ((m->m_pkthdr.csum_flags & 1574 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1575 != 0) { 1576 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1577 re_flags |= RE_TDESC_CMD_IPCSUM; 1578 if (m->m_pkthdr.csum_flags & 1579 M_CSUM_TCPv4) { 1580 re_flags |= 1581 RE_TDESC_CMD_TCPCSUM; 1582 } else if (m->m_pkthdr.csum_flags & 1583 M_CSUM_UDPv4) { 1584 re_flags |= 1585 RE_TDESC_CMD_UDPCSUM; 1586 } 1587 } else { 1588 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1589 if (m->m_pkthdr.csum_flags & 1590 M_CSUM_TCPv4) { 1591 vlanctl |= 1592 RE_TDESC_VLANCTL_TCPCSUM; 1593 } else if (m->m_pkthdr.csum_flags & 1594 M_CSUM_UDPv4) { 1595 vlanctl |= 1596 RE_TDESC_VLANCTL_UDPCSUM; 1597 } 1598 } 1599 } 1600 } 1601 1602 txq = &sc->re_ldata.re_txq[idx]; 1603 map = txq->txq_dmamap; 1604 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1605 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1606 1607 if (__predict_false(error)) { 1608 /* XXX try to defrag if EFBIG? */ 1609 printf("%s: can't map mbuf (error %d)\n", 1610 device_xname(sc->sc_dev), error); 1611 1612 IFQ_DEQUEUE(&ifp->if_snd, m); 1613 m_freem(m); 1614 ifp->if_oerrors++; 1615 continue; 1616 } 1617 1618 nsegs = map->dm_nsegs; 1619 pad = false; 1620 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1621 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1622 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1623 pad = true; 1624 nsegs++; 1625 } 1626 1627 if (nsegs > sc->re_ldata.re_tx_free) { 1628 /* 1629 * Not enough free descriptors to transmit this packet. 1630 */ 1631 ifp->if_flags |= IFF_OACTIVE; 1632 bus_dmamap_unload(sc->sc_dmat, map); 1633 break; 1634 } 1635 1636 IFQ_DEQUEUE(&ifp->if_snd, m); 1637 1638 /* 1639 * Make sure that the caches are synchronized before we 1640 * ask the chip to start DMA for the packet data. 1641 */ 1642 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1643 BUS_DMASYNC_PREWRITE); 1644 1645 /* 1646 * Set up hardware VLAN tagging. Note: vlan tag info must 1647 * appear in all descriptors of a multi-descriptor 1648 * transmission attempt. 1649 */ 1650 if (vlan_has_tag(m)) 1651 vlanctl |= bswap16(vlan_get_tag(m)) | 1652 RE_TDESC_VLANCTL_TAG; 1653 1654 /* 1655 * Map the segment array into descriptors. 1656 * Note that we set the start-of-frame and 1657 * end-of-frame markers for either TX or RX, 1658 * but they really only have meaning in the TX case. 1659 * (In the RX case, it's the chip that tells us 1660 * where packets begin and end.) 1661 * We also keep track of the end of the ring 1662 * and set the end-of-ring bits as needed, 1663 * and we set the ownership bits in all except 1664 * the very first descriptor. (The caller will 1665 * set this descriptor later when it start 1666 * transmission or reception.) 1667 */ 1668 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1669 lastdesc = -1; 1670 for (seg = 0; seg < map->dm_nsegs; 1671 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1672 d = &sc->re_ldata.re_tx_list[curdesc]; 1673 #ifdef DIAGNOSTIC 1674 RE_TXDESCSYNC(sc, curdesc, 1675 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1676 cmdstat = le32toh(d->re_cmdstat); 1677 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1678 if (cmdstat & RE_TDESC_STAT_OWN) { 1679 panic("%s: tried to map busy TX descriptor", 1680 device_xname(sc->sc_dev)); 1681 } 1682 #endif 1683 1684 d->re_vlanctl = htole32(vlanctl); 1685 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1686 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1687 if (seg == 0) 1688 cmdstat |= RE_TDESC_CMD_SOF; 1689 else 1690 cmdstat |= RE_TDESC_CMD_OWN; 1691 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1692 cmdstat |= RE_TDESC_CMD_EOR; 1693 if (seg == nsegs - 1) { 1694 cmdstat |= RE_TDESC_CMD_EOF; 1695 lastdesc = curdesc; 1696 } 1697 d->re_cmdstat = htole32(cmdstat); 1698 RE_TXDESCSYNC(sc, curdesc, 1699 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1700 } 1701 if (__predict_false(pad)) { 1702 d = &sc->re_ldata.re_tx_list[curdesc]; 1703 d->re_vlanctl = htole32(vlanctl); 1704 re_set_bufaddr(d, RE_TXPADDADDR(sc)); 1705 cmdstat = re_flags | 1706 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1707 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1708 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1709 cmdstat |= RE_TDESC_CMD_EOR; 1710 d->re_cmdstat = htole32(cmdstat); 1711 RE_TXDESCSYNC(sc, curdesc, 1712 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1713 lastdesc = curdesc; 1714 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1715 } 1716 KASSERT(lastdesc != -1); 1717 1718 /* Transfer ownership of packet to the chip. */ 1719 1720 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1721 htole32(RE_TDESC_CMD_OWN); 1722 RE_TXDESCSYNC(sc, startdesc, 1723 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1724 1725 /* update info of TX queue and descriptors */ 1726 txq->txq_mbuf = m; 1727 txq->txq_descidx = lastdesc; 1728 txq->txq_nsegs = nsegs; 1729 1730 sc->re_ldata.re_txq_free--; 1731 sc->re_ldata.re_tx_free -= nsegs; 1732 sc->re_ldata.re_tx_nextfree = curdesc; 1733 1734 /* 1735 * If there's a BPF listener, bounce a copy of this frame 1736 * to him. 1737 */ 1738 bpf_mtap(ifp, m, BPF_D_OUT); 1739 } 1740 1741 if (sc->re_ldata.re_txq_free < ofree) { 1742 /* 1743 * TX packets are enqueued. 1744 */ 1745 sc->re_ldata.re_txq_prodidx = idx; 1746 1747 /* 1748 * Start the transmitter to poll. 1749 * 1750 * RealTek put the TX poll request register in a different 1751 * location on the 8169 gigE chip. I don't know why. 1752 */ 1753 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1754 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1755 else 1756 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1757 1758 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) { 1759 /* 1760 * Use the countdown timer for interrupt moderation. 1761 * 'TX done' interrupts are disabled. Instead, we reset 1762 * the countdown timer, which will begin counting until 1763 * it hits the value in the TIMERINT register, and then 1764 * trigger an interrupt. Each time we write to the 1765 * TIMERCNT register, the timer count is reset to 0. 1766 */ 1767 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1768 } 1769 1770 /* 1771 * Set a timeout in case the chip goes out to lunch. 1772 */ 1773 ifp->if_timer = 5; 1774 } 1775 } 1776 1777 static int 1778 re_init(struct ifnet *ifp) 1779 { 1780 struct rtk_softc *sc = ifp->if_softc; 1781 uint32_t rxcfg = 0; 1782 uint16_t cfg; 1783 int error; 1784 #ifdef RE_USE_EECMD 1785 const uint8_t *enaddr; 1786 uint32_t reg; 1787 #endif 1788 1789 if ((error = re_enable(sc)) != 0) 1790 goto out; 1791 1792 /* 1793 * Cancel pending I/O and free all RX/TX buffers. 1794 */ 1795 re_stop(ifp, 0); 1796 1797 re_reset(sc); 1798 1799 /* 1800 * Enable C+ RX and TX mode, as well as VLAN stripping and 1801 * RX checksum offload. We must configure the C+ register 1802 * before all others. 1803 */ 1804 cfg = RE_CPLUSCMD_PCI_MRW; 1805 1806 /* 1807 * XXX: For old 8169 set bit 14. 1808 * For 8169S/8110S and above, do not set bit 14. 1809 */ 1810 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1811 cfg |= (0x1 << 14); 1812 1813 if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0) 1814 cfg |= RE_CPLUSCMD_VLANSTRIP; 1815 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx | 1816 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0) 1817 cfg |= RE_CPLUSCMD_RXCSUM_ENB; 1818 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) { 1819 cfg |= RE_CPLUSCMD_MACSTAT_DIS; 1820 cfg |= RE_CPLUSCMD_TXENB; 1821 } else 1822 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB; 1823 1824 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg); 1825 1826 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1827 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 1828 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) { 1829 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1830 } else { 1831 CSR_WRITE_2(sc, RTK_IM, 0x5151); 1832 } 1833 } 1834 1835 DELAY(10000); 1836 1837 #ifdef RE_USE_EECMD 1838 /* 1839 * Init our MAC address. Even though the chipset 1840 * documentation doesn't mention it, we need to enter "Config 1841 * register write enable" mode to modify the ID registers. 1842 */ 1843 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1844 enaddr = CLLADDR(ifp->if_sadl); 1845 reg = enaddr[0] | (enaddr[1] << 8) | 1846 (enaddr[2] << 16) | (enaddr[3] << 24); 1847 CSR_WRITE_4(sc, RTK_IDR0, reg); 1848 reg = enaddr[4] | (enaddr[5] << 8); 1849 CSR_WRITE_4(sc, RTK_IDR4, reg); 1850 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1851 #endif 1852 1853 /* 1854 * For C+ mode, initialize the RX descriptors and mbufs. 1855 */ 1856 re_rx_list_init(sc); 1857 re_tx_list_init(sc); 1858 1859 /* 1860 * Load the addresses of the RX and TX lists into the chip. 1861 */ 1862 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1863 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1864 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1865 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1866 1867 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1868 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1869 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1870 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1871 1872 if (sc->sc_quirk & RTKQ_RXDV_GATED) { 1873 CSR_WRITE_4(sc, RTK_MISC, 1874 CSR_READ_4(sc, RTK_MISC) & ~RTK_MISC_RXDV_GATED_EN); 1875 } 1876 1877 /* 1878 * Enable transmit and receive. 1879 */ 1880 if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) == 0) 1881 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1882 1883 /* 1884 * Set the initial TX and RX configuration. 1885 */ 1886 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1887 /* test mode is needed only for old 8169 */ 1888 CSR_WRITE_4(sc, RTK_TXCFG, 1889 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1890 } else 1891 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1892 1893 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1894 1895 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1896 1897 /* Set the individual bit to receive frames for this host only. */ 1898 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1899 rxcfg |= RTK_RXCFG_RX_INDIV; 1900 1901 /* If we want promiscuous mode, set the allframes bit. */ 1902 if (ifp->if_flags & IFF_PROMISC) 1903 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1904 else 1905 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1906 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1907 1908 /* 1909 * Set capture broadcast bit to capture broadcast frames. 1910 */ 1911 if (ifp->if_flags & IFF_BROADCAST) 1912 rxcfg |= RTK_RXCFG_RX_BROAD; 1913 else 1914 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1915 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1916 1917 /* 1918 * Program the multicast filter, if necessary. 1919 */ 1920 rtk_setmulti(sc); 1921 1922 /* 1923 * some chips require to enable TX/RX *AFTER* TX/RX configuration 1924 */ 1925 if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) != 0) 1926 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1927 1928 /* 1929 * Enable interrupts. 1930 */ 1931 if (sc->re_testmode) 1932 CSR_WRITE_2(sc, RTK_IMR, 0); 1933 else if ((sc->sc_quirk & RTKQ_IM_HW) != 0) 1934 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_IM_HW); 1935 else 1936 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1937 1938 /* Start RX/TX process. */ 1939 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1940 #ifdef notdef 1941 /* Enable receiver and transmitter. */ 1942 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1943 #endif 1944 1945 /* 1946 * Initialize the timer interrupt register so that 1947 * a timer interrupt will be generated once the timer 1948 * reaches a certain number of ticks. The timer is 1949 * reloaded on each transmit. This gives us TX interrupt 1950 * moderation, which dramatically improves TX frame rate. 1951 */ 1952 1953 unsigned defer; /* timer interval / ns */ 1954 unsigned period; /* busclock period / ns */ 1955 1956 /* 1957 * Maximum frame rate 1958 * 1500 byte PDU -> 81274 Hz 1959 * 46 byte PDU -> 1488096 Hz 1960 * 1961 * Deferring interrupts by up to 128us needs descriptors for 1962 * 1500 byte PDU -> 10.4 frames 1963 * 46 byte PDU -> 190.4 frames 1964 * 1965 */ 1966 defer = 128000; 1967 1968 if ((sc->sc_quirk & RTKQ_IM_HW) != 0) { 1969 period = 1; 1970 defer = 0; 1971 } else if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1972 period = 8; 1973 } else { 1974 switch (CSR_READ_1(sc, RTK_CFG2_BUSFREQ) & 0x7) { 1975 case RTK_BUSFREQ_33MHZ: 1976 period = 30; 1977 break; 1978 case RTK_BUSFREQ_66MHZ: 1979 period = 15; 1980 break; 1981 default: 1982 /* lowest possible clock */ 1983 period = 60; 1984 break; 1985 } 1986 } 1987 1988 /* Timer Interrupt register address varies */ 1989 uint16_t re8139_reg; 1990 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1991 re8139_reg = RTK_TIMERINT; 1992 else 1993 re8139_reg = RTK_TIMERINT_8169; 1994 CSR_WRITE_4(sc, re8139_reg, defer / period); 1995 1996 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 1997 /* 1998 * For 8169 gigE NICs, set the max allowed RX packet 1999 * size so we can receive jumbo frames. 2000 */ 2001 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 2002 } 2003 2004 if (sc->re_testmode) 2005 return 0; 2006 2007 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 2008 2009 ifp->if_flags |= IFF_RUNNING; 2010 ifp->if_flags &= ~IFF_OACTIVE; 2011 2012 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 2013 2014 out: 2015 if (error) { 2016 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2017 ifp->if_timer = 0; 2018 printf("%s: interface not running\n", 2019 device_xname(sc->sc_dev)); 2020 } 2021 2022 return error; 2023 } 2024 2025 static int 2026 re_ioctl(struct ifnet *ifp, u_long command, void *data) 2027 { 2028 struct rtk_softc *sc = ifp->if_softc; 2029 struct ifreq *ifr = data; 2030 int s, error = 0; 2031 2032 s = splnet(); 2033 2034 switch (command) { 2035 case SIOCSIFMTU: 2036 /* 2037 * Disable jumbo frames if it's not supported. 2038 */ 2039 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 2040 ifr->ifr_mtu > ETHERMTU) { 2041 error = EINVAL; 2042 break; 2043 } 2044 2045 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2046 error = EINVAL; 2047 else if ((error = ifioctl_common(ifp, command, data)) == 2048 ENETRESET) 2049 error = 0; 2050 break; 2051 default: 2052 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2053 break; 2054 2055 error = 0; 2056 2057 if (command == SIOCSIFCAP) 2058 error = (*ifp->if_init)(ifp); 2059 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2060 ; 2061 else if (ifp->if_flags & IFF_RUNNING) 2062 rtk_setmulti(sc); 2063 break; 2064 } 2065 2066 splx(s); 2067 2068 return error; 2069 } 2070 2071 static void 2072 re_watchdog(struct ifnet *ifp) 2073 { 2074 struct rtk_softc *sc; 2075 int s; 2076 2077 sc = ifp->if_softc; 2078 s = splnet(); 2079 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2080 ifp->if_oerrors++; 2081 2082 re_txeof(sc); 2083 re_rxeof(sc); 2084 2085 re_init(ifp); 2086 2087 splx(s); 2088 } 2089 2090 /* 2091 * Stop the adapter and free any mbufs allocated to the 2092 * RX and TX lists. 2093 */ 2094 static void 2095 re_stop(struct ifnet *ifp, int disable) 2096 { 2097 int i; 2098 struct rtk_softc *sc = ifp->if_softc; 2099 2100 callout_stop(&sc->rtk_tick_ch); 2101 2102 mii_down(&sc->mii); 2103 2104 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0) 2105 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB | 2106 RTK_CMD_RX_ENB); 2107 else 2108 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2109 DELAY(1000); 2110 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2111 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 2112 2113 if (sc->re_head != NULL) { 2114 m_freem(sc->re_head); 2115 sc->re_head = sc->re_tail = NULL; 2116 } 2117 2118 /* Free the TX list buffers. */ 2119 for (i = 0; i < RE_TX_QLEN; i++) { 2120 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 2121 bus_dmamap_unload(sc->sc_dmat, 2122 sc->re_ldata.re_txq[i].txq_dmamap); 2123 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 2124 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 2125 } 2126 } 2127 2128 /* Free the RX list buffers. */ 2129 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2130 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 2131 bus_dmamap_unload(sc->sc_dmat, 2132 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2133 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2134 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2135 } 2136 } 2137 2138 if (disable) 2139 re_disable(sc); 2140 2141 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2142 ifp->if_timer = 0; 2143 } 2144
Indexes created Thu Sep 25 16:09:42 GMT 2025