rtl8169.c revision 1.17
1 /* $NetBSD: rtl8169.c,v 1.17 2005/03/30 11:38:06 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul (at) windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 50 * and the RTL8110S. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7.5K, so the max MTU possible with this 110 * driver is 7500 bytes. 111 */ 112 113 #include "bpfilter.h" 114 #include "vlan.h" 115 116 #include <sys/param.h> 117 #include <sys/endian.h> 118 #include <sys/systm.h> 119 #include <sys/sockio.h> 120 #include <sys/mbuf.h> 121 #include <sys/malloc.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/device.h> 125 126 #include <net/if.h> 127 #include <net/if_arp.h> 128 #include <net/if_dl.h> 129 #include <net/if_ether.h> 130 #include <net/if_media.h> 131 #include <net/if_vlanvar.h> 132 133 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 134 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 135 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 136 137 #if NBPFILTER > 0 138 #include <net/bpf.h> 139 #endif 140 141 #include <machine/bus.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 #include <dev/pci/pcidevs.h> 149 150 #include <dev/ic/rtl81x9reg.h> 151 #include <dev/ic/rtl81x9var.h> 152 153 #include <dev/ic/rtl8169var.h> 154 155 156 static int re_encap(struct rtk_softc *, struct mbuf *, int *); 157 158 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 159 static int re_rx_list_init(struct rtk_softc *); 160 static int re_tx_list_init(struct rtk_softc *); 161 static void re_rxeof(struct rtk_softc *); 162 static void re_txeof(struct rtk_softc *); 163 static void re_tick(void *); 164 static void re_start(struct ifnet *); 165 static int re_ioctl(struct ifnet *, u_long, caddr_t); 166 static int re_init(struct ifnet *); 167 static void re_stop(struct ifnet *, int); 168 static void re_watchdog(struct ifnet *); 169 170 static void re_shutdown(void *); 171 static int re_enable(struct rtk_softc *); 172 static void re_disable(struct rtk_softc *); 173 static void re_power(int, void *); 174 175 static int re_ifmedia_upd(struct ifnet *); 176 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177 178 static int re_gmii_readreg(struct device *, int, int); 179 static void re_gmii_writereg(struct device *, int, int, int); 180 181 static int re_miibus_readreg(struct device *, int, int); 182 static void re_miibus_writereg(struct device *, int, int, int); 183 static void re_miibus_statchg(struct device *); 184 185 static void re_reset(struct rtk_softc *); 186 187 static int 188 re_gmii_readreg(struct device *self, int phy, int reg) 189 { 190 struct rtk_softc *sc = (void *)self; 191 u_int32_t rval; 192 int i; 193 194 if (phy != 7) 195 return 0; 196 197 /* Let the rgephy driver read the GMEDIASTAT register */ 198 199 if (reg == RTK_GMEDIASTAT) { 200 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 201 return rval; 202 } 203 204 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 205 DELAY(1000); 206 207 for (i = 0; i < RTK_TIMEOUT; i++) { 208 rval = CSR_READ_4(sc, RTK_PHYAR); 209 if (rval & RTK_PHYAR_BUSY) 210 break; 211 DELAY(100); 212 } 213 214 if (i == RTK_TIMEOUT) { 215 aprint_error("%s: PHY read failed\n", sc->sc_dev.dv_xname); 216 return 0; 217 } 218 219 return rval & RTK_PHYAR_PHYDATA; 220 } 221 222 static void 223 re_gmii_writereg(struct device *dev, int phy, int reg, int data) 224 { 225 struct rtk_softc *sc = (void *)dev; 226 u_int32_t rval; 227 int i; 228 229 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 230 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 231 DELAY(1000); 232 233 for (i = 0; i < RTK_TIMEOUT; i++) { 234 rval = CSR_READ_4(sc, RTK_PHYAR); 235 if (!(rval & RTK_PHYAR_BUSY)) 236 break; 237 DELAY(100); 238 } 239 240 if (i == RTK_TIMEOUT) { 241 aprint_error("%s: PHY write reg %x <- %x failed\n", 242 sc->sc_dev.dv_xname, reg, data); 243 return; 244 } 245 246 return; 247 } 248 249 static int 250 re_miibus_readreg(struct device *dev, int phy, int reg) 251 { 252 struct rtk_softc *sc = (void *)dev; 253 u_int16_t rval = 0; 254 u_int16_t re8139_reg = 0; 255 int s; 256 257 s = splnet(); 258 259 if (sc->rtk_type == RTK_8169) { 260 rval = re_gmii_readreg(dev, phy, reg); 261 splx(s); 262 return rval; 263 } 264 265 /* Pretend the internal PHY is only at address 0 */ 266 if (phy) { 267 splx(s); 268 return 0; 269 } 270 switch (reg) { 271 case MII_BMCR: 272 re8139_reg = RTK_BMCR; 273 break; 274 case MII_BMSR: 275 re8139_reg = RTK_BMSR; 276 break; 277 case MII_ANAR: 278 re8139_reg = RTK_ANAR; 279 break; 280 case MII_ANER: 281 re8139_reg = RTK_ANER; 282 break; 283 case MII_ANLPAR: 284 re8139_reg = RTK_LPAR; 285 break; 286 case MII_PHYIDR1: 287 case MII_PHYIDR2: 288 splx(s); 289 return 0; 290 /* 291 * Allow the rlphy driver to read the media status 292 * register. If we have a link partner which does not 293 * support NWAY, this is the register which will tell 294 * us the results of parallel detection. 295 */ 296 case RTK_MEDIASTAT: 297 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 298 splx(s); 299 return rval; 300 default: 301 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 302 splx(s); 303 return 0; 304 } 305 rval = CSR_READ_2(sc, re8139_reg); 306 splx(s); 307 return rval; 308 } 309 310 static void 311 re_miibus_writereg(struct device *dev, int phy, int reg, int data) 312 { 313 struct rtk_softc *sc = (void *)dev; 314 u_int16_t re8139_reg = 0; 315 int s; 316 317 s = splnet(); 318 319 if (sc->rtk_type == RTK_8169) { 320 re_gmii_writereg(dev, phy, reg, data); 321 splx(s); 322 return; 323 } 324 325 /* Pretend the internal PHY is only at address 0 */ 326 if (phy) { 327 splx(s); 328 return; 329 } 330 switch (reg) { 331 case MII_BMCR: 332 re8139_reg = RTK_BMCR; 333 break; 334 case MII_BMSR: 335 re8139_reg = RTK_BMSR; 336 break; 337 case MII_ANAR: 338 re8139_reg = RTK_ANAR; 339 break; 340 case MII_ANER: 341 re8139_reg = RTK_ANER; 342 break; 343 case MII_ANLPAR: 344 re8139_reg = RTK_LPAR; 345 break; 346 case MII_PHYIDR1: 347 case MII_PHYIDR2: 348 splx(s); 349 return; 350 break; 351 default: 352 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 353 splx(s); 354 return; 355 } 356 CSR_WRITE_2(sc, re8139_reg, data); 357 splx(s); 358 return; 359 } 360 361 static void 362 re_miibus_statchg(struct device *dev) 363 { 364 365 return; 366 } 367 368 static void 369 re_reset(struct rtk_softc *sc) 370 { 371 register int i; 372 373 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 374 375 for (i = 0; i < RTK_TIMEOUT; i++) { 376 DELAY(10); 377 if (!(CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET)) 378 break; 379 } 380 if (i == RTK_TIMEOUT) 381 aprint_error("%s: reset never completed!\n", 382 sc->sc_dev.dv_xname); 383 384 /* 385 * NB: Realtek-supplied Linux driver does this only for 386 * MCFG_METHOD_2, which corresponds to sc->sc_rev == 2. 387 */ 388 if (1) /* XXX check softc flag for 8169s version */ 389 CSR_WRITE_1(sc, 0x82, 1); 390 391 return; 392 } 393 394 /* 395 * The following routine is designed to test for a defect on some 396 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 397 * lines connected to the bus, however for a 32-bit only card, they 398 * should be pulled high. The result of this defect is that the 399 * NIC will not work right if you plug it into a 64-bit slot: DMA 400 * operations will be done with 64-bit transfers, which will fail 401 * because the 64-bit data lines aren't connected. 402 * 403 * There's no way to work around this (short of talking a soldering 404 * iron to the board), however we can detect it. The method we use 405 * here is to put the NIC into digital loopback mode, set the receiver 406 * to promiscuous mode, and then try to send a frame. We then compare 407 * the frame data we sent to what was received. If the data matches, 408 * then the NIC is working correctly, otherwise we know the user has 409 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 410 * slot. In the latter case, there's no way the NIC can work correctly, 411 * so we print out a message on the console and abort the device attach. 412 */ 413 414 int 415 re_diag(struct rtk_softc *sc) 416 { 417 struct ifnet *ifp = &sc->ethercom.ec_if; 418 struct mbuf *m0; 419 struct ether_header *eh; 420 struct rtk_desc *cur_rx; 421 bus_dmamap_t dmamap; 422 u_int16_t status; 423 u_int32_t rxstat; 424 int total_len, i, s, error = 0; 425 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 426 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 427 428 /* Allocate a single mbuf */ 429 430 MGETHDR(m0, M_DONTWAIT, MT_DATA); 431 if (m0 == NULL) 432 return ENOBUFS; 433 434 /* 435 * Initialize the NIC in test mode. This sets the chip up 436 * so that it can send and receive frames, but performs the 437 * following special functions: 438 * - Puts receiver in promiscuous mode 439 * - Enables digital loopback mode 440 * - Leaves interrupts turned off 441 */ 442 443 ifp->if_flags |= IFF_PROMISC; 444 sc->rtk_testmode = 1; 445 re_init(ifp); 446 re_stop(ifp, 0); 447 DELAY(100000); 448 re_init(ifp); 449 450 /* Put some data in the mbuf */ 451 452 eh = mtod(m0, struct ether_header *); 453 bcopy((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 454 bcopy((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 455 eh->ether_type = htons(ETHERTYPE_IP); 456 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 457 458 /* 459 * Queue the packet, start transmission. 460 */ 461 462 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 463 s = splnet(); 464 IF_ENQUEUE(&ifp->if_snd, m0); 465 re_start(ifp); 466 splx(s); 467 m0 = NULL; 468 469 /* Wait for it to propagate through the chip */ 470 471 DELAY(100000); 472 for (i = 0; i < RTK_TIMEOUT; i++) { 473 status = CSR_READ_2(sc, RTK_ISR); 474 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 475 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 476 break; 477 DELAY(10); 478 } 479 if (i == RTK_TIMEOUT) { 480 aprint_error("%s: diagnostic failed, failed to receive packet " 481 "in loopback mode\n", sc->sc_dev.dv_xname); 482 error = EIO; 483 goto done; 484 } 485 486 /* 487 * The packet should have been dumped into the first 488 * entry in the RX DMA ring. Grab it from there. 489 */ 490 491 dmamap = sc->rtk_ldata.rtk_rx_list_map; 492 bus_dmamap_sync(sc->sc_dmat, 493 dmamap, 0, dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 494 dmamap = sc->rtk_ldata.rtk_rx_dmamap[0]; 495 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 496 BUS_DMASYNC_POSTWRITE); 497 bus_dmamap_unload(sc->sc_dmat, 498 sc->rtk_ldata.rtk_rx_dmamap[0]); 499 500 m0 = sc->rtk_ldata.rtk_rx_mbuf[0]; 501 sc->rtk_ldata.rtk_rx_mbuf[0] = NULL; 502 eh = mtod(m0, struct ether_header *); 503 504 cur_rx = &sc->rtk_ldata.rtk_rx_list[0]; 505 total_len = RTK_RXBYTES(cur_rx); 506 rxstat = le32toh(cur_rx->rtk_cmdstat); 507 508 if (total_len != ETHER_MIN_LEN) { 509 aprint_error("%s: diagnostic failed, received short packet\n", 510 sc->sc_dev.dv_xname); 511 error = EIO; 512 goto done; 513 } 514 515 /* Test that the received packet data matches what we sent. */ 516 517 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 518 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 519 ntohs(eh->ether_type) != ETHERTYPE_IP) { 520 aprint_error("%s: WARNING, DMA FAILURE!\n", 521 sc->sc_dev.dv_xname); 522 aprint_error("%s: expected TX data: %s", 523 sc->sc_dev.dv_xname, ether_sprintf(dst)); 524 aprint_error("/%s/0x%x\n", ether_sprintf(src), ETHERTYPE_IP); 525 aprint_error("%s: received RX data: %s", 526 sc->sc_dev.dv_xname, 527 ether_sprintf(eh->ether_dhost)); 528 aprint_error("/%s/0x%x\n", ether_sprintf(eh->ether_shost), 529 ntohs(eh->ether_type)); 530 aprint_error("%s: You may have a defective 32-bit NIC plugged " 531 "into a 64-bit PCI slot.\n", sc->sc_dev.dv_xname); 532 aprint_error("%s: Please re-install the NIC in a 32-bit slot " 533 "for proper operation.\n", sc->sc_dev.dv_xname); 534 aprint_error("%s: Read the re(4) man page for more details.\n", 535 sc->sc_dev.dv_xname); 536 error = EIO; 537 } 538 539 done: 540 /* Turn interface off, release resources */ 541 542 sc->rtk_testmode = 0; 543 ifp->if_flags &= ~IFF_PROMISC; 544 re_stop(ifp, 0); 545 if (m0 != NULL) 546 m_freem(m0); 547 548 return error; 549 } 550 551 552 /* 553 * Attach the interface. Allocate softc structures, do ifmedia 554 * setup and ethernet/BPF attach. 555 */ 556 void 557 re_attach(struct rtk_softc *sc) 558 { 559 u_char eaddr[ETHER_ADDR_LEN]; 560 u_int16_t val; 561 struct ifnet *ifp; 562 int error = 0, i, addr_len; 563 564 565 /* XXX JRS: bus-attach-independent code begins approximately here */ 566 567 /* Reset the adapter. */ 568 re_reset(sc); 569 570 if (sc->rtk_type == RTK_8169) { 571 uint32_t hwrev; 572 573 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 574 hwrev = CSR_READ_4(sc, RTK_TXCFG) & 0x7c800000; 575 if (hwrev == (0x1 << 28)) { 576 sc->sc_rev = 4; 577 } else if (hwrev == (0x1 << 26)) { 578 sc->sc_rev = 3; 579 } else if (hwrev == (0x1 << 23)) { 580 sc->sc_rev = 2; 581 } else 582 sc->sc_rev = 1; 583 584 /* Set RX length mask */ 585 586 sc->rtk_rxlenmask = RTK_RDESC_STAT_GFRAGLEN; 587 588 /* Force station address autoload from the EEPROM */ 589 590 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_AUTOLOAD); 591 for (i = 0; i < RTK_TIMEOUT; i++) { 592 if (!(CSR_READ_1(sc, RTK_EECMD) & RTK_EEMODE_AUTOLOAD)) 593 break; 594 DELAY(100); 595 } 596 if (i == RTK_TIMEOUT) 597 aprint_error("%s: eeprom autoload timed out\n", 598 sc->sc_dev.dv_xname); 599 600 for (i = 0; i < ETHER_ADDR_LEN; i++) 601 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 602 603 sc->rtk_ldata.rtk_tx_desc_cnt = RTK_TX_DESC_CNT_8169; 604 } else { 605 606 /* Set RX length mask */ 607 608 sc->rtk_rxlenmask = RTK_RDESC_STAT_FRAGLEN; 609 610 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 611 addr_len = RTK_EEADDR_LEN1; 612 else 613 addr_len = RTK_EEADDR_LEN0; 614 615 /* 616 * Get station address from the EEPROM. 617 */ 618 for (i = 0; i < 3; i++) { 619 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 620 eaddr[(i * 2) + 0] = val & 0xff; 621 eaddr[(i * 2) + 1] = val >> 8; 622 } 623 624 sc->rtk_ldata.rtk_tx_desc_cnt = RTK_TX_DESC_CNT_8139; 625 } 626 627 aprint_normal("%s: Ethernet address %s\n", 628 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 629 630 if (sc->rtk_ldata.rtk_tx_desc_cnt > 631 PAGE_SIZE / sizeof(struct rtk_desc)) { 632 sc->rtk_ldata.rtk_tx_desc_cnt = 633 PAGE_SIZE / sizeof(struct rtk_desc); 634 } 635 636 aprint_verbose("%s: using %d tx descriptors\n", 637 sc->sc_dev.dv_xname, sc->rtk_ldata.rtk_tx_desc_cnt); 638 639 /* Allocate DMA'able memory for the TX ring */ 640 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_TX_LIST_SZ(sc), 641 RTK_ETHER_ALIGN, 0, &sc->rtk_ldata.rtk_tx_listseg, 642 1, &sc->rtk_ldata.rtk_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 643 aprint_error("%s: can't allocate tx listseg, error = %d\n", 644 sc->sc_dev.dv_xname, error); 645 goto fail_0; 646 } 647 648 /* Load the map for the TX ring. */ 649 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_tx_listseg, 650 sc->rtk_ldata.rtk_tx_listnseg, RTK_TX_LIST_SZ(sc), 651 (caddr_t *)&sc->rtk_ldata.rtk_tx_list, 652 BUS_DMA_NOWAIT)) != 0) { 653 aprint_error("%s: can't map tx list, error = %d\n", 654 sc->sc_dev.dv_xname, error); 655 goto fail_1; 656 } 657 memset(sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ(sc)); 658 659 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_TX_LIST_SZ(sc), 1, 660 RTK_TX_LIST_SZ(sc), 0, BUS_DMA_ALLOCNOW, 661 &sc->rtk_ldata.rtk_tx_list_map)) != 0) { 662 aprint_error("%s: can't create tx list map, error = %d\n", 663 sc->sc_dev.dv_xname, error); 664 goto fail_2; 665 } 666 667 668 if ((error = bus_dmamap_load(sc->sc_dmat, 669 sc->rtk_ldata.rtk_tx_list_map, sc->rtk_ldata.rtk_tx_list, 670 RTK_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 671 aprint_error("%s: can't load tx list, error = %d\n", 672 sc->sc_dev.dv_xname, error); 673 goto fail_3; 674 } 675 676 /* Create DMA maps for TX buffers */ 677 for (i = 0; i < RTK_TX_QLEN; i++) { 678 error = bus_dmamap_create(sc->sc_dmat, 679 round_page(IP_MAXPACKET), 680 RTK_TX_DESC_CNT(sc) - 4, RTK_TDESC_CMD_FRAGLEN, 681 0, BUS_DMA_ALLOCNOW, 682 &sc->rtk_ldata.rtk_txq[i].txq_dmamap); 683 if (error) { 684 aprint_error("%s: can't create DMA map for TX\n", 685 sc->sc_dev.dv_xname); 686 goto fail_4; 687 } 688 } 689 690 /* Allocate DMA'able memory for the RX ring */ 691 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_RX_LIST_SZ, 692 RTK_RING_ALIGN, 0, &sc->rtk_ldata.rtk_rx_listseg, 1, 693 &sc->rtk_ldata.rtk_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 694 aprint_error("%s: can't allocate rx listseg, error = %d\n", 695 sc->sc_dev.dv_xname, error); 696 goto fail_4; 697 } 698 699 /* Load the map for the RX ring. */ 700 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_rx_listseg, 701 sc->rtk_ldata.rtk_rx_listnseg, RTK_RX_LIST_SZ, 702 (caddr_t *)&sc->rtk_ldata.rtk_rx_list, 703 BUS_DMA_NOWAIT)) != 0) { 704 aprint_error("%s: can't map rx list, error = %d\n", 705 sc->sc_dev.dv_xname, error); 706 goto fail_5; 707 } 708 memset(sc->rtk_ldata.rtk_rx_list, 0, RTK_RX_LIST_SZ); 709 710 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_RX_LIST_SZ, 1, 711 RTK_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 712 &sc->rtk_ldata.rtk_rx_list_map)) != 0) { 713 aprint_error("%s: can't create rx list map, error = %d\n", 714 sc->sc_dev.dv_xname, error); 715 goto fail_6; 716 } 717 718 if ((error = bus_dmamap_load(sc->sc_dmat, 719 sc->rtk_ldata.rtk_rx_list_map, sc->rtk_ldata.rtk_rx_list, 720 RTK_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 721 aprint_error("%s: can't load rx list, error = %d\n", 722 sc->sc_dev.dv_xname, error); 723 goto fail_7; 724 } 725 726 /* Create DMA maps for RX buffers */ 727 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 728 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 729 0, BUS_DMA_ALLOCNOW, &sc->rtk_ldata.rtk_rx_dmamap[i]); 730 if (error) { 731 aprint_error("%s: can't create DMA map for RX\n", 732 sc->sc_dev.dv_xname); 733 goto fail_8; 734 } 735 } 736 737 /* 738 * Record interface as attached. From here, we should not fail. 739 */ 740 sc->sc_flags |= RTK_ATTACHED; 741 742 ifp = &sc->ethercom.ec_if; 743 ifp->if_softc = sc; 744 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 745 ifp->if_mtu = ETHERMTU; 746 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 747 ifp->if_ioctl = re_ioctl; 748 sc->ethercom.ec_capabilities |= 749 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 750 ifp->if_start = re_start; 751 ifp->if_stop = re_stop; 752 ifp->if_capabilities |= 753 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4 | 754 IFCAP_TSOv4; 755 ifp->if_watchdog = re_watchdog; 756 ifp->if_init = re_init; 757 if (sc->rtk_type == RTK_8169) 758 ifp->if_baudrate = 1000000000; 759 else 760 ifp->if_baudrate = 100000000; 761 ifp->if_snd.ifq_maxlen = RTK_IFQ_MAXLEN; 762 ifp->if_capenable = ifp->if_capabilities; 763 IFQ_SET_READY(&ifp->if_snd); 764 765 callout_init(&sc->rtk_tick_ch); 766 767 /* Do MII setup */ 768 sc->mii.mii_ifp = ifp; 769 sc->mii.mii_readreg = re_miibus_readreg; 770 sc->mii.mii_writereg = re_miibus_writereg; 771 sc->mii.mii_statchg = re_miibus_statchg; 772 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, re_ifmedia_upd, 773 re_ifmedia_sts); 774 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 775 MII_OFFSET_ANY, 0); 776 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 777 778 /* 779 * Call MI attach routine. 780 */ 781 if_attach(ifp); 782 ether_ifattach(ifp, eaddr); 783 784 785 /* 786 * Make sure the interface is shutdown during reboot. 787 */ 788 sc->sc_sdhook = shutdownhook_establish(re_shutdown, sc); 789 if (sc->sc_sdhook == NULL) 790 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 791 sc->sc_dev.dv_xname); 792 /* 793 * Add a suspend hook to make sure we come back up after a 794 * resume. 795 */ 796 sc->sc_powerhook = powerhook_establish(re_power, sc); 797 if (sc->sc_powerhook == NULL) 798 aprint_error("%s: WARNING: unable to establish power hook\n", 799 sc->sc_dev.dv_xname); 800 801 802 return; 803 804 fail_8: 805 /* Destroy DMA maps for RX buffers. */ 806 for (i = 0; i < RTK_RX_DESC_CNT; i++) 807 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 808 bus_dmamap_destroy(sc->sc_dmat, 809 sc->rtk_ldata.rtk_rx_dmamap[i]); 810 811 /* Free DMA'able memory for the RX ring. */ 812 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 813 fail_7: 814 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 815 fail_6: 816 bus_dmamem_unmap(sc->sc_dmat, 817 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 818 fail_5: 819 bus_dmamem_free(sc->sc_dmat, 820 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 821 822 fail_4: 823 /* Destroy DMA maps for TX buffers. */ 824 for (i = 0; i < RTK_TX_QLEN; i++) 825 if (sc->rtk_ldata.rtk_txq[i].txq_dmamap != NULL) 826 bus_dmamap_destroy(sc->sc_dmat, 827 sc->rtk_ldata.rtk_txq[i].txq_dmamap); 828 829 /* Free DMA'able memory for the TX ring. */ 830 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 831 fail_3: 832 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 833 fail_2: 834 bus_dmamem_unmap(sc->sc_dmat, 835 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ(sc)); 836 fail_1: 837 bus_dmamem_free(sc->sc_dmat, 838 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 839 fail_0: 840 return; 841 } 842 843 844 /* 845 * re_activate: 846 * Handle device activation/deactivation requests. 847 */ 848 int 849 re_activate(struct device *self, enum devact act) 850 { 851 struct rtk_softc *sc = (void *) self; 852 int s, error = 0; 853 854 s = splnet(); 855 switch (act) { 856 case DVACT_ACTIVATE: 857 error = EOPNOTSUPP; 858 break; 859 case DVACT_DEACTIVATE: 860 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 861 if_deactivate(&sc->ethercom.ec_if); 862 break; 863 } 864 splx(s); 865 866 return error; 867 } 868 869 /* 870 * re_detach: 871 * Detach a rtk interface. 872 */ 873 int 874 re_detach(struct rtk_softc *sc) 875 { 876 struct ifnet *ifp = &sc->ethercom.ec_if; 877 int i; 878 879 /* 880 * Succeed now if there isn't any work to do. 881 */ 882 if ((sc->sc_flags & RTK_ATTACHED) == 0) 883 return 0; 884 885 /* Unhook our tick handler. */ 886 callout_stop(&sc->rtk_tick_ch); 887 888 /* Detach all PHYs. */ 889 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 890 891 /* Delete all remaining media. */ 892 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 893 894 ether_ifdetach(ifp); 895 if_detach(ifp); 896 897 /* XXX undo re_allocmem() */ 898 899 /* Destroy DMA maps for RX buffers. */ 900 for (i = 0; i < RTK_RX_DESC_CNT; i++) 901 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 902 bus_dmamap_destroy(sc->sc_dmat, 903 sc->rtk_ldata.rtk_rx_dmamap[i]); 904 905 /* Free DMA'able memory for the RX ring. */ 906 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 907 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 908 bus_dmamem_unmap(sc->sc_dmat, 909 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 910 bus_dmamem_free(sc->sc_dmat, 911 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 912 913 /* Destroy DMA maps for TX buffers. */ 914 for (i = 0; i < RTK_TX_QLEN; i++) 915 if (sc->rtk_ldata.rtk_txq[i].txq_dmamap != NULL) 916 bus_dmamap_destroy(sc->sc_dmat, 917 sc->rtk_ldata.rtk_txq[i].txq_dmamap); 918 919 /* Free DMA'able memory for the TX ring. */ 920 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 921 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 922 bus_dmamem_unmap(sc->sc_dmat, 923 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ(sc)); 924 bus_dmamem_free(sc->sc_dmat, 925 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 926 927 928 shutdownhook_disestablish(sc->sc_sdhook); 929 powerhook_disestablish(sc->sc_powerhook); 930 931 return 0; 932 } 933 934 /* 935 * re_enable: 936 * Enable the RTL81X9 chip. 937 */ 938 static int 939 re_enable(struct rtk_softc *sc) 940 { 941 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 942 if ((*sc->sc_enable)(sc) != 0) { 943 aprint_error("%s: device enable failed\n", 944 sc->sc_dev.dv_xname); 945 return EIO; 946 } 947 sc->sc_flags |= RTK_ENABLED; 948 } 949 return 0; 950 } 951 952 /* 953 * re_disable: 954 * Disable the RTL81X9 chip. 955 */ 956 static void 957 re_disable(struct rtk_softc *sc) 958 { 959 960 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 961 (*sc->sc_disable)(sc); 962 sc->sc_flags &= ~RTK_ENABLED; 963 } 964 } 965 966 /* 967 * re_power: 968 * Power management (suspend/resume) hook. 969 */ 970 void 971 re_power(int why, void *arg) 972 { 973 struct rtk_softc *sc = (void *) arg; 974 struct ifnet *ifp = &sc->ethercom.ec_if; 975 int s; 976 977 s = splnet(); 978 switch (why) { 979 case PWR_SUSPEND: 980 case PWR_STANDBY: 981 re_stop(ifp, 0); 982 if (sc->sc_power != NULL) 983 (*sc->sc_power)(sc, why); 984 break; 985 case PWR_RESUME: 986 if (ifp->if_flags & IFF_UP) { 987 if (sc->sc_power != NULL) 988 (*sc->sc_power)(sc, why); 989 re_init(ifp); 990 } 991 break; 992 case PWR_SOFTSUSPEND: 993 case PWR_SOFTSTANDBY: 994 case PWR_SOFTRESUME: 995 break; 996 } 997 splx(s); 998 } 999 1000 1001 static int 1002 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1003 { 1004 struct mbuf *n = NULL; 1005 bus_dmamap_t map; 1006 struct rtk_desc *d; 1007 u_int32_t cmdstat; 1008 int error; 1009 1010 if (m == NULL) { 1011 MGETHDR(n, M_DONTWAIT, MT_DATA); 1012 if (n == NULL) 1013 return ENOBUFS; 1014 m = n; 1015 1016 MCLGET(m, M_DONTWAIT); 1017 if (!(m->m_flags & M_EXT)) { 1018 m_freem(m); 1019 return ENOBUFS; 1020 } 1021 } else 1022 m->m_data = m->m_ext.ext_buf; 1023 1024 /* 1025 * Initialize mbuf length fields and fixup 1026 * alignment so that the frame payload is 1027 * longword aligned. 1028 */ 1029 m->m_len = m->m_pkthdr.len = MCLBYTES; 1030 m_adj(m, RTK_ETHER_ALIGN); 1031 1032 map = sc->rtk_ldata.rtk_rx_dmamap[idx]; 1033 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1034 1035 if (error) 1036 goto out; 1037 1038 d = &sc->rtk_ldata.rtk_rx_list[idx]; 1039 if (le32toh(d->rtk_cmdstat) & RTK_RDESC_STAT_OWN) 1040 goto out; 1041 1042 cmdstat = map->dm_segs[0].ds_len; 1043 d->rtk_bufaddr_lo = htole32(RTK_ADDR_LO(map->dm_segs[0].ds_addr)); 1044 d->rtk_bufaddr_hi = htole32(RTK_ADDR_HI(map->dm_segs[0].ds_addr)); 1045 if (idx == (RTK_RX_DESC_CNT - 1)) 1046 cmdstat |= RTK_RDESC_CMD_EOR; 1047 d->rtk_cmdstat = htole32(cmdstat); 1048 1049 sc->rtk_ldata.rtk_rx_list[idx].rtk_cmdstat |= 1050 htole32(RTK_RDESC_CMD_OWN); 1051 sc->rtk_ldata.rtk_rx_mbuf[idx] = m; 1052 1053 bus_dmamap_sync(sc->sc_dmat, sc->rtk_ldata.rtk_rx_dmamap[idx], 0, 1054 sc->rtk_ldata.rtk_rx_dmamap[idx]->dm_mapsize, 1055 BUS_DMASYNC_PREREAD); 1056 1057 return 0; 1058 out: 1059 if (n != NULL) 1060 m_freem(n); 1061 return ENOMEM; 1062 } 1063 1064 static int 1065 re_tx_list_init(struct rtk_softc *sc) 1066 { 1067 int i; 1068 1069 memset(sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ(sc)); 1070 for (i = 0; i < RTK_TX_QLEN; i++) { 1071 sc->rtk_ldata.rtk_txq[i].txq_mbuf = NULL; 1072 } 1073 1074 bus_dmamap_sync(sc->sc_dmat, 1075 sc->rtk_ldata.rtk_tx_list_map, 0, 1076 sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1077 sc->rtk_ldata.rtk_txq_prodidx = 0; 1078 sc->rtk_ldata.rtk_txq_considx = 0; 1079 sc->rtk_ldata.rtk_tx_free = RTK_TX_DESC_CNT(sc); 1080 sc->rtk_ldata.rtk_tx_nextfree = 0; 1081 1082 return 0; 1083 } 1084 1085 static int 1086 re_rx_list_init(struct rtk_softc *sc) 1087 { 1088 int i; 1089 1090 memset((char *)sc->rtk_ldata.rtk_rx_list, 0, RTK_RX_LIST_SZ); 1091 memset((char *)&sc->rtk_ldata.rtk_rx_mbuf, 0, 1092 (RTK_RX_DESC_CNT * sizeof(struct mbuf *))); 1093 1094 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 1095 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1096 return ENOBUFS; 1097 } 1098 1099 /* Flush the RX descriptors */ 1100 1101 bus_dmamap_sync(sc->sc_dmat, 1102 sc->rtk_ldata.rtk_rx_list_map, 1103 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1105 1106 sc->rtk_ldata.rtk_rx_prodidx = 0; 1107 sc->rtk_head = sc->rtk_tail = NULL; 1108 1109 return 0; 1110 } 1111 1112 /* 1113 * RX handler for C+ and 8169. For the gigE chips, we support 1114 * the reception of jumbo frames that have been fragmented 1115 * across multiple 2K mbuf cluster buffers. 1116 */ 1117 static void 1118 re_rxeof(struct rtk_softc *sc) 1119 { 1120 struct mbuf *m; 1121 struct ifnet *ifp; 1122 int i, total_len; 1123 struct rtk_desc *cur_rx; 1124 u_int32_t rxstat, rxvlan; 1125 1126 ifp = &sc->ethercom.ec_if; 1127 i = sc->rtk_ldata.rtk_rx_prodidx; 1128 1129 /* Invalidate the descriptor memory */ 1130 1131 bus_dmamap_sync(sc->sc_dmat, 1132 sc->rtk_ldata.rtk_rx_list_map, 1133 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1134 BUS_DMASYNC_POSTREAD); 1135 1136 while (!RTK_OWN(&sc->rtk_ldata.rtk_rx_list[i])) { 1137 1138 cur_rx = &sc->rtk_ldata.rtk_rx_list[i]; 1139 m = sc->rtk_ldata.rtk_rx_mbuf[i]; 1140 total_len = RTK_RXBYTES(cur_rx); 1141 rxstat = le32toh(cur_rx->rtk_cmdstat); 1142 rxvlan = le32toh(cur_rx->rtk_vlanctl); 1143 1144 /* Invalidate the RX mbuf and unload its map */ 1145 1146 bus_dmamap_sync(sc->sc_dmat, 1147 sc->rtk_ldata.rtk_rx_dmamap[i], 1148 0, sc->rtk_ldata.rtk_rx_dmamap[i]->dm_mapsize, 1149 BUS_DMASYNC_POSTWRITE); 1150 bus_dmamap_unload(sc->sc_dmat, 1151 sc->rtk_ldata.rtk_rx_dmamap[i]); 1152 1153 if (!(rxstat & RTK_RDESC_STAT_EOF)) { 1154 m->m_len = MCLBYTES - RTK_ETHER_ALIGN; 1155 if (sc->rtk_head == NULL) 1156 sc->rtk_head = sc->rtk_tail = m; 1157 else { 1158 m->m_flags &= ~M_PKTHDR; 1159 sc->rtk_tail->m_next = m; 1160 sc->rtk_tail = m; 1161 } 1162 re_newbuf(sc, i, NULL); 1163 RTK_RX_DESC_INC(sc, i); 1164 continue; 1165 } 1166 1167 /* 1168 * NOTE: for the 8139C+, the frame length field 1169 * is always 12 bits in size, but for the gigE chips, 1170 * it is 13 bits (since the max RX frame length is 16K). 1171 * Unfortunately, all 32 bits in the status word 1172 * were already used, so to make room for the extra 1173 * length bit, RealTek took out the 'frame alignment 1174 * error' bit and shifted the other status bits 1175 * over one slot. The OWN, EOR, FS and LS bits are 1176 * still in the same places. We have already extracted 1177 * the frame length and checked the OWN bit, so rather 1178 * than using an alternate bit mapping, we shift the 1179 * status bits one space to the right so we can evaluate 1180 * them using the 8169 status as though it was in the 1181 * same format as that of the 8139C+. 1182 */ 1183 if (sc->rtk_type == RTK_8169) 1184 rxstat >>= 1; 1185 1186 if (rxstat & RTK_RDESC_STAT_RXERRSUM) { 1187 ifp->if_ierrors++; 1188 /* 1189 * If this is part of a multi-fragment packet, 1190 * discard all the pieces. 1191 */ 1192 if (sc->rtk_head != NULL) { 1193 m_freem(sc->rtk_head); 1194 sc->rtk_head = sc->rtk_tail = NULL; 1195 } 1196 re_newbuf(sc, i, m); 1197 RTK_RX_DESC_INC(sc, i); 1198 continue; 1199 } 1200 1201 /* 1202 * If allocating a replacement mbuf fails, 1203 * reload the current one. 1204 */ 1205 1206 if (re_newbuf(sc, i, NULL)) { 1207 ifp->if_ierrors++; 1208 if (sc->rtk_head != NULL) { 1209 m_freem(sc->rtk_head); 1210 sc->rtk_head = sc->rtk_tail = NULL; 1211 } 1212 re_newbuf(sc, i, m); 1213 RTK_RX_DESC_INC(sc, i); 1214 continue; 1215 } 1216 1217 RTK_RX_DESC_INC(sc, i); 1218 1219 if (sc->rtk_head != NULL) { 1220 m->m_len = total_len % (MCLBYTES - RTK_ETHER_ALIGN); 1221 /* 1222 * Special case: if there's 4 bytes or less 1223 * in this buffer, the mbuf can be discarded: 1224 * the last 4 bytes is the CRC, which we don't 1225 * care about anyway. 1226 */ 1227 if (m->m_len <= ETHER_CRC_LEN) { 1228 sc->rtk_tail->m_len -= 1229 (ETHER_CRC_LEN - m->m_len); 1230 m_freem(m); 1231 } else { 1232 m->m_len -= ETHER_CRC_LEN; 1233 m->m_flags &= ~M_PKTHDR; 1234 sc->rtk_tail->m_next = m; 1235 } 1236 m = sc->rtk_head; 1237 sc->rtk_head = sc->rtk_tail = NULL; 1238 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1239 } else 1240 m->m_pkthdr.len = m->m_len = 1241 (total_len - ETHER_CRC_LEN); 1242 1243 ifp->if_ipackets++; 1244 m->m_pkthdr.rcvif = ifp; 1245 1246 /* Do RX checksumming if enabled */ 1247 1248 if (ifp->if_capenable & IFCAP_CSUM_IPv4) { 1249 1250 /* Check IP header checksum */ 1251 if (rxstat & RTK_RDESC_STAT_PROTOID) 1252 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;; 1253 if (rxstat & RTK_RDESC_STAT_IPSUMBAD) 1254 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1255 } 1256 1257 /* Check TCP/UDP checksum */ 1258 if (RTK_TCPPKT(rxstat) && 1259 (ifp->if_capenable & IFCAP_CSUM_TCPv4)) { 1260 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1261 if (rxstat & RTK_RDESC_STAT_TCPSUMBAD) 1262 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1263 } 1264 if (RTK_UDPPKT(rxstat) && 1265 (ifp->if_capenable & IFCAP_CSUM_UDPv4)) { 1266 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1267 if (rxstat & RTK_RDESC_STAT_UDPSUMBAD) 1268 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1269 } 1270 1271 if (rxvlan & RTK_RDESC_VLANCTL_TAG) { 1272 VLAN_INPUT_TAG(ifp, m, 1273 be16toh(rxvlan & RTK_RDESC_VLANCTL_DATA), 1274 continue); 1275 } 1276 #if NBPFILTER > 0 1277 if (ifp->if_bpf) 1278 bpf_mtap(ifp->if_bpf, m); 1279 #endif 1280 (*ifp->if_input)(ifp, m); 1281 } 1282 1283 /* Flush the RX DMA ring */ 1284 1285 bus_dmamap_sync(sc->sc_dmat, 1286 sc->rtk_ldata.rtk_rx_list_map, 1287 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1288 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1289 1290 sc->rtk_ldata.rtk_rx_prodidx = i; 1291 1292 return; 1293 } 1294 1295 static void 1296 re_txeof(struct rtk_softc *sc) 1297 { 1298 struct ifnet *ifp; 1299 int idx; 1300 1301 ifp = &sc->ethercom.ec_if; 1302 idx = sc->rtk_ldata.rtk_txq_considx; 1303 1304 /* Invalidate the TX descriptor list */ 1305 1306 bus_dmamap_sync(sc->sc_dmat, 1307 sc->rtk_ldata.rtk_tx_list_map, 1308 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1309 BUS_DMASYNC_POSTREAD); 1310 1311 while (/* CONSTCOND */ 1) { 1312 struct rtk_txq *txq = &sc->rtk_ldata.rtk_txq[idx]; 1313 int descidx; 1314 u_int32_t txstat; 1315 1316 if (txq->txq_mbuf == NULL) { 1317 KASSERT(idx == sc->rtk_ldata.rtk_txq_prodidx); 1318 break; 1319 } 1320 1321 descidx = txq->txq_descidx; 1322 txstat = 1323 le32toh(sc->rtk_ldata.rtk_tx_list[descidx].rtk_cmdstat); 1324 KASSERT((txstat & RTK_TDESC_CMD_EOF) != 0); 1325 if (txstat & RTK_TDESC_CMD_OWN) 1326 break; 1327 1328 sc->rtk_ldata.rtk_tx_free += txq->txq_dmamap->dm_nsegs; 1329 KASSERT(sc->rtk_ldata.rtk_tx_free <= RTK_TX_DESC_CNT(sc)); 1330 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1331 m_freem(txq->txq_mbuf); 1332 txq->txq_mbuf = NULL; 1333 1334 if (txstat & (RTK_TDESC_STAT_EXCESSCOL | RTK_TDESC_STAT_COLCNT)) 1335 ifp->if_collisions++; 1336 if (txstat & RTK_TDESC_STAT_TXERRSUM) 1337 ifp->if_oerrors++; 1338 else 1339 ifp->if_opackets++; 1340 1341 idx = (idx + 1) % RTK_TX_QLEN; 1342 } 1343 1344 /* No changes made to the TX ring, so no flush needed */ 1345 1346 if (idx != sc->rtk_ldata.rtk_txq_considx) { 1347 sc->rtk_ldata.rtk_txq_considx = idx; 1348 ifp->if_flags &= ~IFF_OACTIVE; 1349 ifp->if_timer = 0; 1350 } 1351 1352 /* 1353 * If not all descriptors have been released reaped yet, 1354 * reload the timer so that we will eventually get another 1355 * interrupt that will cause us to re-enter this routine. 1356 * This is done in case the transmitter has gone idle. 1357 */ 1358 if (sc->rtk_ldata.rtk_tx_free != RTK_TX_DESC_CNT(sc)) 1359 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1360 1361 return; 1362 } 1363 1364 /* 1365 * Stop all chip I/O so that the kernel's probe routines don't 1366 * get confused by errant DMAs when rebooting. 1367 */ 1368 static void 1369 re_shutdown(void *vsc) 1370 1371 { 1372 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1373 1374 re_stop(&sc->ethercom.ec_if, 0); 1375 } 1376 1377 1378 static void 1379 re_tick(void *xsc) 1380 { 1381 struct rtk_softc *sc = xsc; 1382 int s; 1383 1384 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1385 s = splnet(); 1386 1387 mii_tick(&sc->mii); 1388 splx(s); 1389 1390 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1391 } 1392 1393 #ifdef DEVICE_POLLING 1394 static void 1395 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1396 { 1397 struct rtk_softc *sc = ifp->if_softc; 1398 1399 RTK_LOCK(sc); 1400 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1401 ether_poll_deregister(ifp); 1402 cmd = POLL_DEREGISTER; 1403 } 1404 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1405 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1406 goto done; 1407 } 1408 1409 sc->rxcycles = count; 1410 re_rxeof(sc); 1411 re_txeof(sc); 1412 1413 if (ifp->if_snd.ifq_head != NULL) 1414 (*ifp->if_start)(ifp); 1415 1416 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1417 u_int16_t status; 1418 1419 status = CSR_READ_2(sc, RTK_ISR); 1420 if (status == 0xffff) 1421 goto done; 1422 if (status) 1423 CSR_WRITE_2(sc, RTK_ISR, status); 1424 1425 /* 1426 * XXX check behaviour on receiver stalls. 1427 */ 1428 1429 if (status & RTK_ISR_SYSTEM_ERR) { 1430 re_reset(sc); 1431 re_init(sc); 1432 } 1433 } 1434 done: 1435 RTK_UNLOCK(sc); 1436 } 1437 #endif /* DEVICE_POLLING */ 1438 1439 int 1440 re_intr(void *arg) 1441 { 1442 struct rtk_softc *sc = arg; 1443 struct ifnet *ifp; 1444 u_int16_t status; 1445 int handled = 0; 1446 1447 ifp = &sc->ethercom.ec_if; 1448 1449 if (!(ifp->if_flags & IFF_UP)) 1450 return 0; 1451 1452 #ifdef DEVICE_POLLING 1453 if (ifp->if_flags & IFF_POLLING) 1454 goto done; 1455 if ((ifp->if_capenable & IFCAP_POLLING) && 1456 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1457 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1458 re_poll(ifp, 0, 1); 1459 goto done; 1460 } 1461 #endif /* DEVICE_POLLING */ 1462 1463 for (;;) { 1464 1465 status = CSR_READ_2(sc, RTK_ISR); 1466 /* If the card has gone away the read returns 0xffff. */ 1467 if (status == 0xffff) 1468 break; 1469 if (status) { 1470 handled = 1; 1471 CSR_WRITE_2(sc, RTK_ISR, status); 1472 } 1473 1474 if ((status & RTK_INTRS_CPLUS) == 0) 1475 break; 1476 1477 if ((status & RTK_ISR_RX_OK) || 1478 (status & RTK_ISR_RX_ERR)) 1479 re_rxeof(sc); 1480 1481 if ((status & RTK_ISR_TIMEOUT_EXPIRED) || 1482 (status & RTK_ISR_TX_ERR) || 1483 (status & RTK_ISR_TX_DESC_UNAVAIL)) 1484 re_txeof(sc); 1485 1486 if (status & RTK_ISR_SYSTEM_ERR) { 1487 re_reset(sc); 1488 re_init(ifp); 1489 } 1490 1491 if (status & RTK_ISR_LINKCHG) { 1492 callout_stop(&sc->rtk_tick_ch); 1493 re_tick(sc); 1494 } 1495 } 1496 1497 if (ifp->if_flags & IFF_UP) /* kludge for interrupt during re_init() */ 1498 if (ifp->if_snd.ifq_head != NULL) 1499 (*ifp->if_start)(ifp); 1500 1501 #ifdef DEVICE_POLLING 1502 done: 1503 #endif 1504 1505 return handled; 1506 } 1507 1508 static int 1509 re_encap(struct rtk_softc *sc, struct mbuf *m, int *idx) 1510 { 1511 bus_dmamap_t map; 1512 int error, i, startidx, curidx; 1513 struct m_tag *mtag; 1514 struct rtk_desc *d; 1515 u_int32_t cmdstat, rtk_flags; 1516 struct rtk_txq *txq; 1517 1518 if (sc->rtk_ldata.rtk_tx_free <= 4) { 1519 return EFBIG; 1520 } 1521 1522 /* 1523 * Set up checksum offload. Note: checksum offload bits must 1524 * appear in all descriptors of a multi-descriptor transmit 1525 * attempt. (This is according to testing done with an 8169 1526 * chip. I'm not sure if this is a requirement or a bug.) 1527 */ 1528 1529 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1530 u_int32_t segsz = m->m_pkthdr.segsz; 1531 1532 rtk_flags = RTK_TDESC_CMD_LGSEND | 1533 (segsz << RTK_TDESC_CMD_MSSVAL_SHIFT); 1534 } else { 1535 1536 /* 1537 * set RTK_TDESC_CMD_IPCSUM if any checksum offloading 1538 * is requested. otherwise, RTK_TDESC_CMD_TCPCSUM/ 1539 * RTK_TDESC_CMD_UDPCSUM doesn't make effects. 1540 */ 1541 1542 rtk_flags = 0; 1543 if ((m->m_pkthdr.csum_flags & 1544 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) != 0) { 1545 rtk_flags |= RTK_TDESC_CMD_IPCSUM; 1546 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1547 rtk_flags |= RTK_TDESC_CMD_TCPCSUM; 1548 } else if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1549 rtk_flags |= RTK_TDESC_CMD_UDPCSUM; 1550 } 1551 } 1552 } 1553 1554 txq = &sc->rtk_ldata.rtk_txq[*idx]; 1555 map = txq->txq_dmamap; 1556 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1557 1558 if (error) { 1559 /* XXX try to defrag if EFBIG? */ 1560 1561 aprint_error("%s: can't map mbuf (error %d)\n", 1562 sc->sc_dev.dv_xname, error); 1563 1564 return error; 1565 } 1566 1567 if (map->dm_nsegs > sc->rtk_ldata.rtk_tx_free - 4) { 1568 error = EFBIG; 1569 goto fail_unload; 1570 } 1571 /* 1572 * Map the segment array into descriptors. Note that we set the 1573 * start-of-frame and end-of-frame markers for either TX or RX, but 1574 * they really only have meaning in the TX case. (In the RX case, 1575 * it's the chip that tells us where packets begin and end.) 1576 * We also keep track of the end of the ring and set the 1577 * end-of-ring bits as needed, and we set the ownership bits 1578 * in all except the very first descriptor. (The caller will 1579 * set this descriptor later when it start transmission or 1580 * reception.) 1581 */ 1582 i = 0; 1583 curidx = startidx = sc->rtk_ldata.rtk_tx_nextfree; 1584 while (1) { 1585 d = &sc->rtk_ldata.rtk_tx_list[curidx]; 1586 if (le32toh(d->rtk_cmdstat) & RTK_TDESC_STAT_OWN) { 1587 while (i > 0) { 1588 sc->rtk_ldata.rtk_tx_list[ 1589 (curidx + RTK_TX_DESC_CNT(sc) - i) % 1590 RTK_TX_DESC_CNT(sc)].rtk_cmdstat = 0; 1591 i--; 1592 } 1593 error = ENOBUFS; 1594 goto fail_unload; 1595 } 1596 1597 cmdstat = map->dm_segs[i].ds_len; 1598 d->rtk_bufaddr_lo = 1599 htole32(RTK_ADDR_LO(map->dm_segs[i].ds_addr)); 1600 d->rtk_bufaddr_hi = 1601 htole32(RTK_ADDR_HI(map->dm_segs[i].ds_addr)); 1602 if (i == 0) 1603 cmdstat |= RTK_TDESC_CMD_SOF; 1604 else 1605 cmdstat |= RTK_TDESC_CMD_OWN; 1606 if (curidx == (RTK_TX_DESC_CNT(sc) - 1)) 1607 cmdstat |= RTK_TDESC_CMD_EOR; 1608 d->rtk_cmdstat = htole32(cmdstat | rtk_flags); 1609 i++; 1610 if (i == map->dm_nsegs) 1611 break; 1612 RTK_TX_DESC_INC(sc, curidx); 1613 } 1614 1615 d->rtk_cmdstat |= htole32(RTK_TDESC_CMD_EOF); 1616 1617 txq->txq_mbuf = m; 1618 sc->rtk_ldata.rtk_tx_free -= map->dm_nsegs; 1619 1620 /* 1621 * Set up hardware VLAN tagging. Note: vlan tag info must 1622 * appear in the first descriptor of a multi-descriptor 1623 * transmission attempt. 1624 */ 1625 1626 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) { 1627 sc->rtk_ldata.rtk_tx_list[startidx].rtk_vlanctl = 1628 htole32(htons(VLAN_TAG_VALUE(mtag)) | 1629 RTK_TDESC_VLANCTL_TAG); 1630 } 1631 1632 /* Transfer ownership of packet to the chip. */ 1633 1634 sc->rtk_ldata.rtk_tx_list[curidx].rtk_cmdstat |= 1635 htole32(RTK_TDESC_CMD_OWN); 1636 if (startidx != curidx) 1637 sc->rtk_ldata.rtk_tx_list[startidx].rtk_cmdstat |= 1638 htole32(RTK_TDESC_CMD_OWN); 1639 1640 txq->txq_descidx = curidx; 1641 RTK_TX_DESC_INC(sc, curidx); 1642 sc->rtk_ldata.rtk_tx_nextfree = curidx; 1643 *idx = (*idx + 1) % RTK_TX_QLEN; 1644 1645 return 0; 1646 1647 fail_unload: 1648 bus_dmamap_unload(sc->sc_dmat, map); 1649 1650 return error; 1651 } 1652 1653 /* 1654 * Main transmit routine for C+ and gigE NICs. 1655 */ 1656 1657 static void 1658 re_start(struct ifnet *ifp) 1659 { 1660 struct rtk_softc *sc; 1661 int idx; 1662 1663 sc = ifp->if_softc; 1664 1665 idx = sc->rtk_ldata.rtk_txq_prodidx; 1666 while (/* CONSTCOND */ 1) { 1667 struct mbuf *m; 1668 int error; 1669 1670 IFQ_POLL(&ifp->if_snd, m); 1671 if (m == NULL) 1672 break; 1673 1674 if (sc->rtk_ldata.rtk_txq[idx].txq_mbuf != NULL) { 1675 KASSERT(idx == sc->rtk_ldata.rtk_txq_considx); 1676 ifp->if_flags |= IFF_OACTIVE; 1677 break; 1678 } 1679 1680 error = re_encap(sc, m, &idx); 1681 if (error == EFBIG && 1682 sc->rtk_ldata.rtk_tx_free == RTK_TX_DESC_CNT(sc)) { 1683 IFQ_DEQUEUE(&ifp->if_snd, m); 1684 m_freem(m); 1685 ifp->if_oerrors++; 1686 continue; 1687 } 1688 if (error) { 1689 ifp->if_flags |= IFF_OACTIVE; 1690 break; 1691 } 1692 1693 IFQ_DEQUEUE(&ifp->if_snd, m); 1694 1695 #if NBPFILTER > 0 1696 /* 1697 * If there's a BPF listener, bounce a copy of this frame 1698 * to him. 1699 */ 1700 if (ifp->if_bpf) 1701 bpf_mtap(ifp->if_bpf, m); 1702 #endif 1703 } 1704 1705 if (sc->rtk_ldata.rtk_txq_prodidx == idx) { 1706 return; 1707 } 1708 sc->rtk_ldata.rtk_txq_prodidx = idx; 1709 1710 /* Flush the TX descriptors */ 1711 1712 bus_dmamap_sync(sc->sc_dmat, 1713 sc->rtk_ldata.rtk_tx_list_map, 1714 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1715 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1716 1717 /* 1718 * RealTek put the TX poll request register in a different 1719 * location on the 8169 gigE chip. I don't know why. 1720 */ 1721 1722 if (sc->rtk_type == RTK_8169) 1723 CSR_WRITE_2(sc, RTK_GTXSTART, RTK_TXSTART_START); 1724 else 1725 CSR_WRITE_2(sc, RTK_TXSTART, RTK_TXSTART_START); 1726 1727 /* 1728 * Use the countdown timer for interrupt moderation. 1729 * 'TX done' interrupts are disabled. Instead, we reset the 1730 * countdown timer, which will begin counting until it hits 1731 * the value in the TIMERINT register, and then trigger an 1732 * interrupt. Each time we write to the TIMERCNT register, 1733 * the timer count is reset to 0. 1734 */ 1735 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1736 1737 /* 1738 * Set a timeout in case the chip goes out to lunch. 1739 */ 1740 ifp->if_timer = 5; 1741 1742 return; 1743 } 1744 1745 static int 1746 re_init(struct ifnet *ifp) 1747 { 1748 struct rtk_softc *sc = ifp->if_softc; 1749 u_int32_t rxcfg = 0; 1750 u_int32_t reg; 1751 int error; 1752 1753 if ((error = re_enable(sc)) != 0) 1754 goto out; 1755 1756 /* 1757 * Cancel pending I/O and free all RX/TX buffers. 1758 */ 1759 re_stop(ifp, 0); 1760 1761 /* 1762 * Enable C+ RX and TX mode, as well as VLAN stripping and 1763 * RX checksum offload. We must configure the C+ register 1764 * before all others. 1765 */ 1766 reg = 0; 1767 1768 /* 1769 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S. 1770 * FreeBSD drivers set these bits anyway (for 8139C+?). 1771 * So far, it works. 1772 */ 1773 1774 /* 1775 * XXX: For 8169 and 8196S revs below 2, set bit 14. 1776 * For 8169S/8110S rev 2 and above, do not set bit 14. 1777 */ 1778 if (sc->rtk_type == RTK_8169 && sc->sc_rev == 1) 1779 reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW;; 1780 1781 if (1) {/* not for 8169S ? */ 1782 reg |= RTK_CPLUSCMD_VLANSTRIP | 1783 (ifp->if_capenable & 1784 (IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4) ? 1785 RTK_CPLUSCMD_RXCSUM_ENB : 0); 1786 } 1787 1788 CSR_WRITE_2(sc, RTK_CPLUS_CMD, 1789 reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB); 1790 1791 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1792 if (sc->rtk_type == RTK_8169) 1793 CSR_WRITE_2(sc, RTK_CPLUS_CMD+0x2, 0x0000); 1794 1795 DELAY(10000); 1796 1797 /* 1798 * Init our MAC address. Even though the chipset 1799 * documentation doesn't mention it, we need to enter "Config 1800 * register write enable" mode to modify the ID registers. 1801 */ 1802 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1803 memcpy(®, LLADDR(ifp->if_sadl), 4); 1804 CSR_WRITE_STREAM_4(sc, RTK_IDR0, reg); 1805 reg = 0; 1806 memcpy(®, LLADDR(ifp->if_sadl) + 4, 4); 1807 CSR_WRITE_STREAM_4(sc, RTK_IDR4, reg); 1808 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1809 1810 /* 1811 * For C+ mode, initialize the RX descriptors and mbufs. 1812 */ 1813 re_rx_list_init(sc); 1814 re_tx_list_init(sc); 1815 1816 /* 1817 * Enable transmit and receive. 1818 */ 1819 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1820 1821 /* 1822 * Set the initial TX and RX configuration. 1823 */ 1824 if (sc->rtk_testmode) { 1825 if (sc->rtk_type == RTK_8169) 1826 CSR_WRITE_4(sc, RTK_TXCFG, 1827 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1828 else 1829 CSR_WRITE_4(sc, RTK_TXCFG, 1830 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON_CPLUS); 1831 } else 1832 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1833 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1834 1835 /* Set the individual bit to receive frames for this host only. */ 1836 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1837 rxcfg |= RTK_RXCFG_RX_INDIV; 1838 1839 /* If we want promiscuous mode, set the allframes bit. */ 1840 if (ifp->if_flags & IFF_PROMISC) 1841 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1842 else 1843 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1844 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1845 1846 /* 1847 * Set capture broadcast bit to capture broadcast frames. 1848 */ 1849 if (ifp->if_flags & IFF_BROADCAST) 1850 rxcfg |= RTK_RXCFG_RX_BROAD; 1851 else 1852 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1853 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1854 1855 /* 1856 * Program the multicast filter, if necessary. 1857 */ 1858 rtk_setmulti(sc); 1859 1860 #ifdef DEVICE_POLLING 1861 /* 1862 * Disable interrupts if we are polling. 1863 */ 1864 if (ifp->if_flags & IFF_POLLING) 1865 CSR_WRITE_2(sc, RTK_IMR, 0); 1866 else /* otherwise ... */ 1867 #endif /* DEVICE_POLLING */ 1868 /* 1869 * Enable interrupts. 1870 */ 1871 if (sc->rtk_testmode) 1872 CSR_WRITE_2(sc, RTK_IMR, 0); 1873 else 1874 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1875 1876 /* Start RX/TX process. */ 1877 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1878 #ifdef notdef 1879 /* Enable receiver and transmitter. */ 1880 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1881 #endif 1882 /* 1883 * Load the addresses of the RX and TX lists into the chip. 1884 */ 1885 1886 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1887 RTK_ADDR_HI(sc->rtk_ldata.rtk_rx_list_map->dm_segs[0].ds_addr)); 1888 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1889 RTK_ADDR_LO(sc->rtk_ldata.rtk_rx_list_map->dm_segs[0].ds_addr)); 1890 1891 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1892 RTK_ADDR_HI(sc->rtk_ldata.rtk_tx_list_map->dm_segs[0].ds_addr)); 1893 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1894 RTK_ADDR_LO(sc->rtk_ldata.rtk_tx_list_map->dm_segs[0].ds_addr)); 1895 1896 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1897 1898 /* 1899 * Initialize the timer interrupt register so that 1900 * a timer interrupt will be generated once the timer 1901 * reaches a certain number of ticks. The timer is 1902 * reloaded on each transmit. This gives us TX interrupt 1903 * moderation, which dramatically improves TX frame rate. 1904 */ 1905 1906 if (sc->rtk_type == RTK_8169) 1907 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1908 else 1909 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1910 1911 /* 1912 * For 8169 gigE NICs, set the max allowed RX packet 1913 * size so we can receive jumbo frames. 1914 */ 1915 if (sc->rtk_type == RTK_8169) 1916 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1917 1918 if (sc->rtk_testmode) 1919 return 0; 1920 1921 mii_mediachg(&sc->mii); 1922 1923 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD | RTK_CFG1_FULLDUPLEX); 1924 1925 ifp->if_flags |= IFF_RUNNING; 1926 ifp->if_flags &= ~IFF_OACTIVE; 1927 1928 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1929 1930 out: 1931 if (error) { 1932 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1933 ifp->if_timer = 0; 1934 aprint_error("%s: interface not running\n", 1935 sc->sc_dev.dv_xname); 1936 } 1937 1938 return error; 1939 1940 } 1941 1942 /* 1943 * Set media options. 1944 */ 1945 static int 1946 re_ifmedia_upd(struct ifnet *ifp) 1947 { 1948 struct rtk_softc *sc; 1949 1950 sc = ifp->if_softc; 1951 1952 return mii_mediachg(&sc->mii); 1953 } 1954 1955 /* 1956 * Report current media status. 1957 */ 1958 static void 1959 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1960 { 1961 struct rtk_softc *sc; 1962 1963 sc = ifp->if_softc; 1964 1965 mii_pollstat(&sc->mii); 1966 ifmr->ifm_active = sc->mii.mii_media_active; 1967 ifmr->ifm_status = sc->mii.mii_media_status; 1968 1969 return; 1970 } 1971 1972 static int 1973 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1974 { 1975 struct rtk_softc *sc = ifp->if_softc; 1976 struct ifreq *ifr = (struct ifreq *) data; 1977 int s, error = 0; 1978 1979 s = splnet(); 1980 1981 switch (command) { 1982 case SIOCSIFMTU: 1983 if (ifr->ifr_mtu > RTK_JUMBO_MTU) 1984 error = EINVAL; 1985 ifp->if_mtu = ifr->ifr_mtu; 1986 break; 1987 case SIOCGIFMEDIA: 1988 case SIOCSIFMEDIA: 1989 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1990 break; 1991 default: 1992 error = ether_ioctl(ifp, command, data); 1993 if (error == ENETRESET) { 1994 if (ifp->if_flags & IFF_RUNNING) 1995 rtk_setmulti(sc); 1996 error = 0; 1997 } 1998 break; 1999 } 2000 2001 splx(s); 2002 2003 return error; 2004 } 2005 2006 static void 2007 re_watchdog(struct ifnet *ifp) 2008 { 2009 struct rtk_softc *sc; 2010 int s; 2011 2012 sc = ifp->if_softc; 2013 s = splnet(); 2014 aprint_error("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2015 ifp->if_oerrors++; 2016 2017 re_txeof(sc); 2018 re_rxeof(sc); 2019 2020 re_init(ifp); 2021 2022 splx(s); 2023 } 2024 2025 /* 2026 * Stop the adapter and free any mbufs allocated to the 2027 * RX and TX lists. 2028 */ 2029 static void 2030 re_stop(struct ifnet *ifp, int disable) 2031 { 2032 register int i; 2033 struct rtk_softc *sc = ifp->if_softc; 2034 2035 callout_stop(&sc->rtk_tick_ch); 2036 2037 #ifdef DEVICE_POLLING 2038 ether_poll_deregister(ifp); 2039 #endif /* DEVICE_POLLING */ 2040 2041 mii_down(&sc->mii); 2042 2043 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2044 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2045 2046 if (sc->rtk_head != NULL) { 2047 m_freem(sc->rtk_head); 2048 sc->rtk_head = sc->rtk_tail = NULL; 2049 } 2050 2051 /* Free the TX list buffers. */ 2052 for (i = 0; i < RTK_TX_QLEN; i++) { 2053 if (sc->rtk_ldata.rtk_txq[i].txq_mbuf != NULL) { 2054 bus_dmamap_unload(sc->sc_dmat, 2055 sc->rtk_ldata.rtk_txq[i].txq_dmamap); 2056 m_freem(sc->rtk_ldata.rtk_txq[i].txq_mbuf); 2057 sc->rtk_ldata.rtk_txq[i].txq_mbuf = NULL; 2058 } 2059 } 2060 2061 /* Free the RX list buffers. */ 2062 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 2063 if (sc->rtk_ldata.rtk_rx_mbuf[i] != NULL) { 2064 bus_dmamap_unload(sc->sc_dmat, 2065 sc->rtk_ldata.rtk_rx_dmamap[i]); 2066 m_freem(sc->rtk_ldata.rtk_rx_mbuf[i]); 2067 sc->rtk_ldata.rtk_rx_mbuf[i] = NULL; 2068 } 2069 } 2070 2071 if (disable) 2072 re_disable(sc); 2073 2074 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2075 ifp->if_timer = 0; 2076 2077 return; 2078 } 2079
Indexes created Fri Sep 26 08:10:20 GMT 2025