rtl8169.c revision 1.5
1 /* $NetBSD: rtl8169.c,v 1.5 2005/01/09 12:25:25 kanaoka Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul (at) windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 50 * and the RTL8110S. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7.5K, so the max MTU possible with this 110 * driver is 7500 bytes. 111 */ 112 113 #include "bpfilter.h" 114 #include "vlan.h" 115 116 #include <sys/param.h> 117 #include <sys/endian.h> 118 #include <sys/systm.h> 119 #include <sys/sockio.h> 120 #include <sys/mbuf.h> 121 #include <sys/malloc.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/device.h> 125 126 #include <net/if.h> 127 #include <net/if_arp.h> 128 #include <net/if_dl.h> 129 #include <net/if_ether.h> 130 #include <net/if_media.h> 131 #include <net/if_vlanvar.h> 132 133 #if NBPFILTER > 0 134 #include <net/bpf.h> 135 #endif 136 137 #include <machine/bus.h> 138 139 #include <dev/mii/mii.h> 140 #include <dev/mii/miivar.h> 141 142 #include <dev/pci/pcireg.h> 143 #include <dev/pci/pcivar.h> 144 #include <dev/pci/pcidevs.h> 145 146 /* 147 * Default to using PIO access for this driver. 148 */ 149 #define RE_USEIOSPACE 150 151 #include <dev/ic/rtl81x9reg.h> 152 #include <dev/ic/rtl81x9var.h> 153 154 #include <dev/ic/rtl8169var.h> 155 156 157 static int re_encap(struct rtk_softc *, struct mbuf *, int *); 158 159 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 160 static int re_rx_list_init(struct rtk_softc *); 161 static int re_tx_list_init(struct rtk_softc *); 162 static void re_rxeof(struct rtk_softc *); 163 static void re_txeof(struct rtk_softc *); 164 static void re_tick(void *); 165 static void re_start(struct ifnet *); 166 static int re_ioctl(struct ifnet *, u_long, caddr_t); 167 static int re_init(struct ifnet *); 168 static void re_stop(struct ifnet *, int); 169 static void re_watchdog(struct ifnet *); 170 171 static void re_shutdown(void *); 172 static int re_enable(struct rtk_softc *); 173 static void re_disable(struct rtk_softc *); 174 static void re_power(int, void *); 175 176 static int re_ifmedia_upd(struct ifnet *); 177 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 178 179 static int re_gmii_readreg(struct device *, int, int); 180 static void re_gmii_writereg(struct device *, int, int, int); 181 182 static int re_miibus_readreg(struct device *, int, int); 183 static void re_miibus_writereg(struct device *, int, int, int); 184 static void re_miibus_statchg(struct device *); 185 186 static void re_reset(struct rtk_softc *); 187 188 static int re_diag(struct rtk_softc *); 189 190 #ifdef RE_USEIOSPACE 191 #define RTK_RES SYS_RES_IOPORT 192 #define RTK_RID RTK_PCI_LOIO 193 #else 194 #define RTK_RES SYS_RES_MEMORY 195 #define RTK_RID RTK_PCI_LOMEM 196 #endif 197 198 #define EE_SET(x) \ 199 CSR_WRITE_1(sc, RTK_EECMD, \ 200 CSR_READ_1(sc, RTK_EECMD) | x) 201 202 #define EE_CLR(x) \ 203 CSR_WRITE_1(sc, RTK_EECMD, \ 204 CSR_READ_1(sc, RTK_EECMD) & ~x) 205 206 static int 207 re_gmii_readreg(struct device *self, int phy, int reg) 208 { 209 struct rtk_softc *sc = (void *)self; 210 u_int32_t rval; 211 int i; 212 213 if (phy != 7) 214 return 0; 215 216 /* Let the rgephy driver read the GMEDIASTAT register */ 217 218 if (reg == RTK_GMEDIASTAT) { 219 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 220 return rval; 221 } 222 223 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 224 DELAY(1000); 225 226 for (i = 0; i < RTK_TIMEOUT; i++) { 227 rval = CSR_READ_4(sc, RTK_PHYAR); 228 if (rval & RTK_PHYAR_BUSY) 229 break; 230 DELAY(100); 231 } 232 233 if (i == RTK_TIMEOUT) { 234 aprint_error("%s: PHY read failed\n", sc->sc_dev.dv_xname); 235 return 0; 236 } 237 238 return rval & RTK_PHYAR_PHYDATA; 239 } 240 241 static void 242 re_gmii_writereg(struct device *dev, int phy, int reg, int data) 243 { 244 struct rtk_softc *sc = (void *)dev; 245 u_int32_t rval; 246 int i; 247 248 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 249 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 250 DELAY(1000); 251 252 for (i = 0; i < RTK_TIMEOUT; i++) { 253 rval = CSR_READ_4(sc, RTK_PHYAR); 254 if (!(rval & RTK_PHYAR_BUSY)) 255 break; 256 DELAY(100); 257 } 258 259 if (i == RTK_TIMEOUT) { 260 aprint_error("%s: PHY write reg %x <- %x failed\n", 261 sc->sc_dev.dv_xname, reg, data); 262 return; 263 } 264 265 return; 266 } 267 268 static int 269 re_miibus_readreg(struct device *dev, int phy, int reg) 270 { 271 struct rtk_softc *sc = (void *)dev; 272 u_int16_t rval = 0; 273 u_int16_t re8139_reg = 0; 274 int s; 275 276 s = splnet(); 277 278 if (sc->rtk_type == RTK_8169) { 279 rval = re_gmii_readreg(dev, phy, reg); 280 splx(s); 281 return rval; 282 } 283 284 /* Pretend the internal PHY is only at address 0 */ 285 if (phy) { 286 splx(s); 287 return 0; 288 } 289 switch (reg) { 290 case MII_BMCR: 291 re8139_reg = RTK_BMCR; 292 break; 293 case MII_BMSR: 294 re8139_reg = RTK_BMSR; 295 break; 296 case MII_ANAR: 297 re8139_reg = RTK_ANAR; 298 break; 299 case MII_ANER: 300 re8139_reg = RTK_ANER; 301 break; 302 case MII_ANLPAR: 303 re8139_reg = RTK_LPAR; 304 break; 305 case MII_PHYIDR1: 306 case MII_PHYIDR2: 307 splx(s); 308 return 0; 309 /* 310 * Allow the rlphy driver to read the media status 311 * register. If we have a link partner which does not 312 * support NWAY, this is the register which will tell 313 * us the results of parallel detection. 314 */ 315 case RTK_MEDIASTAT: 316 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 317 splx(s); 318 return rval; 319 default: 320 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 321 splx(s); 322 return 0; 323 } 324 rval = CSR_READ_2(sc, re8139_reg); 325 splx(s); 326 return rval; 327 } 328 329 static void 330 re_miibus_writereg(struct device *dev, int phy, int reg, int data) 331 { 332 struct rtk_softc *sc = (void *)dev; 333 u_int16_t re8139_reg = 0; 334 int s; 335 336 s = splnet(); 337 338 if (sc->rtk_type == RTK_8169) { 339 re_gmii_writereg(dev, phy, reg, data); 340 splx(s); 341 return; 342 } 343 344 /* Pretend the internal PHY is only at address 0 */ 345 if (phy) { 346 splx(s); 347 return; 348 } 349 switch (reg) { 350 case MII_BMCR: 351 re8139_reg = RTK_BMCR; 352 break; 353 case MII_BMSR: 354 re8139_reg = RTK_BMSR; 355 break; 356 case MII_ANAR: 357 re8139_reg = RTK_ANAR; 358 break; 359 case MII_ANER: 360 re8139_reg = RTK_ANER; 361 break; 362 case MII_ANLPAR: 363 re8139_reg = RTK_LPAR; 364 break; 365 case MII_PHYIDR1: 366 case MII_PHYIDR2: 367 splx(s); 368 return; 369 break; 370 default: 371 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 372 splx(s); 373 return; 374 } 375 CSR_WRITE_2(sc, re8139_reg, data); 376 splx(s); 377 return; 378 } 379 380 static void 381 re_miibus_statchg(struct device *dev) 382 { 383 384 return; 385 } 386 387 static void 388 re_reset(struct rtk_softc *sc) 389 { 390 register int i; 391 392 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 393 394 for (i = 0; i < RTK_TIMEOUT; i++) { 395 DELAY(10); 396 if (!(CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET)) 397 break; 398 } 399 if (i == RTK_TIMEOUT) 400 aprint_error("%s: reset never completed!\n", 401 sc->sc_dev.dv_xname); 402 403 /* 404 * NB: Realtek-supplied Linux driver does this only for 405 * MCFG_METHOD_2, which corresponds to sc->sc_rev == 2. 406 */ 407 if (1) /* XXX check softc flag for 8169s version */ 408 CSR_WRITE_1(sc, 0x82, 1); 409 410 return; 411 } 412 413 /* 414 * The following routine is designed to test for a defect on some 415 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 416 * lines connected to the bus, however for a 32-bit only card, they 417 * should be pulled high. The result of this defect is that the 418 * NIC will not work right if you plug it into a 64-bit slot: DMA 419 * operations will be done with 64-bit transfers, which will fail 420 * because the 64-bit data lines aren't connected. 421 * 422 * There's no way to work around this (short of talking a soldering 423 * iron to the board), however we can detect it. The method we use 424 * here is to put the NIC into digital loopback mode, set the receiver 425 * to promiscuous mode, and then try to send a frame. We then compare 426 * the frame data we sent to what was received. If the data matches, 427 * then the NIC is working correctly, otherwise we know the user has 428 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 429 * slot. In the latter case, there's no way the NIC can work correctly, 430 * so we print out a message on the console and abort the device attach. 431 */ 432 433 static int 434 re_diag(struct rtk_softc *sc) 435 { 436 struct ifnet *ifp = &sc->ethercom.ec_if; 437 struct mbuf *m0; 438 struct ether_header *eh; 439 struct rtk_desc *cur_rx; 440 bus_dmamap_t dmamap; 441 u_int16_t status; 442 u_int32_t rxstat; 443 int total_len, i, s, error = 0; 444 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 445 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 446 447 /* Allocate a single mbuf */ 448 449 MGETHDR(m0, M_DONTWAIT, MT_DATA); 450 if (m0 == NULL) 451 return ENOBUFS; 452 453 /* 454 * Initialize the NIC in test mode. This sets the chip up 455 * so that it can send and receive frames, but performs the 456 * following special functions: 457 * - Puts receiver in promiscuous mode 458 * - Enables digital loopback mode 459 * - Leaves interrupts turned off 460 */ 461 462 ifp->if_flags |= IFF_PROMISC; 463 sc->rtk_testmode = 1; 464 re_init(ifp); 465 re_stop(ifp, 1); 466 DELAY(100000); 467 re_init(ifp); 468 469 /* Put some data in the mbuf */ 470 471 eh = mtod(m0, struct ether_header *); 472 bcopy((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 473 bcopy((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 474 eh->ether_type = htons(ETHERTYPE_IP); 475 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 476 477 /* 478 * Queue the packet, start transmission. 479 */ 480 481 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 482 s = splnet(); 483 IF_ENQUEUE(&ifp->if_snd, m0); 484 re_start(ifp); 485 splx(s); 486 m0 = NULL; 487 488 /* Wait for it to propagate through the chip */ 489 490 DELAY(100000); 491 for (i = 0; i < RTK_TIMEOUT; i++) { 492 status = CSR_READ_2(sc, RTK_ISR); 493 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 494 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 495 break; 496 DELAY(10); 497 } 498 if (i == RTK_TIMEOUT) { 499 aprint_error("%s: diagnostic failed, failed to receive packet " 500 "in loopback mode\n", sc->sc_dev.dv_xname); 501 error = EIO; 502 goto done; 503 } 504 505 /* 506 * The packet should have been dumped into the first 507 * entry in the RX DMA ring. Grab it from there. 508 */ 509 510 dmamap = sc->rtk_ldata.rtk_rx_list_map; 511 bus_dmamap_sync(sc->sc_dmat, 512 dmamap, 0, dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 513 dmamap = sc->rtk_ldata.rtk_rx_dmamap[0]; 514 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 515 BUS_DMASYNC_POSTWRITE); 516 bus_dmamap_unload(sc->sc_dmat, 517 sc->rtk_ldata.rtk_rx_dmamap[0]); 518 519 m0 = sc->rtk_ldata.rtk_rx_mbuf[0]; 520 sc->rtk_ldata.rtk_rx_mbuf[0] = NULL; 521 eh = mtod(m0, struct ether_header *); 522 523 cur_rx = &sc->rtk_ldata.rtk_rx_list[0]; 524 total_len = RTK_RXBYTES(cur_rx); 525 rxstat = le32toh(cur_rx->rtk_cmdstat); 526 527 if (total_len != ETHER_MIN_LEN) { 528 aprint_error("%s: diagnostic failed, received short packet\n", 529 sc->sc_dev.dv_xname); 530 error = EIO; 531 goto done; 532 } 533 534 /* Test that the received packet data matches what we sent. */ 535 536 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 537 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 538 ntohs(eh->ether_type) != ETHERTYPE_IP) { 539 aprint_error("%s: WARNING, DMA FAILURE!\n", 540 sc->sc_dev.dv_xname); 541 aprint_error("%s: expected TX data: %s", 542 sc->sc_dev.dv_xname, ether_sprintf(dst)); 543 aprint_error("/%s/0x%x\n", ether_sprintf(src), ETHERTYPE_IP); 544 aprint_error("%s: received RX data: %s", 545 sc->sc_dev.dv_xname, 546 ether_sprintf(eh->ether_dhost)); 547 aprint_error("/%s/0x%x\n", ether_sprintf(eh->ether_shost), 548 ntohs(eh->ether_type)); 549 aprint_error("%s: You may have a defective 32-bit NIC plugged " 550 "into a 64-bit PCI slot.\n", sc->sc_dev.dv_xname); 551 aprint_error("%s: Please re-install the NIC in a 32-bit slot " 552 "for proper operation.\n", sc->sc_dev.dv_xname); 553 aprint_error("%s: Read the re(4) man page for more details.\n", 554 sc->sc_dev.dv_xname); 555 error = EIO; 556 } 557 558 done: 559 /* Turn interface off, release resources */ 560 561 sc->rtk_testmode = 0; 562 ifp->if_flags &= ~IFF_PROMISC; 563 re_stop(ifp, 1); 564 if (m0 != NULL) 565 m_freem(m0); 566 567 return error; 568 } 569 570 571 /* 572 * Attach the interface. Allocate softc structures, do ifmedia 573 * setup and ethernet/BPF attach. 574 */ 575 void 576 re_attach(struct rtk_softc *sc) 577 { 578 u_char eaddr[ETHER_ADDR_LEN]; 579 u_int16_t val; 580 struct ifnet *ifp; 581 int error = 0, i, addr_len; 582 583 584 /* XXX JRS: bus-attach-independent code begins approximately here */ 585 586 /* Reset the adapter. */ 587 re_reset(sc); 588 589 if (sc->rtk_type == RTK_8169) { 590 uint32_t hwrev; 591 592 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 593 hwrev = CSR_READ_4(sc, RTK_TXCFG) & 0x7c800000; 594 if (hwrev == (0x1 << 28)) { 595 sc->sc_rev = 4; 596 } else if (hwrev == (0x1 << 26)) { 597 sc->sc_rev = 3; 598 } else if (hwrev == (0x1 << 23)) { 599 sc->sc_rev = 2; 600 } else 601 sc->sc_rev = 1; 602 #if defined(DEBUG) || 1 603 aprint_normal("re_attach: MAC chip hwrev 0x%x softc %d\n", 604 hwrev, sc->sc_rev); 605 #endif 606 607 /* Set RX length mask */ 608 609 sc->rtk_rxlenmask = RTK_RDESC_STAT_GFRAGLEN; 610 611 /* Force station address autoload from the EEPROM */ 612 613 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_AUTOLOAD); 614 for (i = 0; i < RTK_TIMEOUT; i++) { 615 if (!(CSR_READ_1(sc, RTK_EECMD) & RTK_EEMODE_AUTOLOAD)) 616 break; 617 DELAY(100); 618 } 619 if (i == RTK_TIMEOUT) 620 aprint_error("%s: eeprom autoload timed out\n", 621 sc->sc_dev.dv_xname); 622 623 for (i = 0; i < ETHER_ADDR_LEN; i++) 624 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 625 } else { 626 627 /* Set RX length mask */ 628 629 sc->rtk_rxlenmask = RTK_RDESC_STAT_FRAGLEN; 630 631 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 632 addr_len = RTK_EEADDR_LEN1; 633 else 634 addr_len = RTK_EEADDR_LEN0; 635 636 /* 637 * Get station address from the EEPROM. 638 */ 639 for (i = 0; i < 3; i++) { 640 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 641 eaddr[(i * 2) + 0] = val & 0xff; 642 eaddr[(i * 2) + 1] = val >> 8; 643 } 644 } 645 646 aprint_normal("%s: Ethernet address %s\n", 647 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 648 649 650 /* Allocate DMA'able memory for the TX ring */ 651 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_TX_LIST_SZ, 652 RTK_ETHER_ALIGN, 0, &sc->rtk_ldata.rtk_tx_listseg, 653 1, &sc->rtk_ldata.rtk_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 654 aprint_error("%s: can't allocate tx listseg, error = %d\n", 655 sc->sc_dev.dv_xname, error); 656 goto fail_0; 657 } 658 659 /* Load the map for the TX ring. */ 660 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_tx_listseg, 661 sc->rtk_ldata.rtk_tx_listnseg, RTK_TX_LIST_SZ, 662 (caddr_t *)&sc->rtk_ldata.rtk_tx_list, 663 BUS_DMA_NOWAIT)) != 0) { 664 aprint_error("%s: can't map tx list, error = %d\n", 665 sc->sc_dev.dv_xname, error); 666 goto fail_1; 667 } 668 memset(sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ); 669 670 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_TX_LIST_SZ, 1, 671 RTK_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 672 &sc->rtk_ldata.rtk_tx_list_map)) != 0) { 673 aprint_error("%s: can't create tx list map, error = %d\n", 674 sc->sc_dev.dv_xname, error); 675 goto fail_2; 676 } 677 678 679 if ((error = bus_dmamap_load(sc->sc_dmat, 680 sc->rtk_ldata.rtk_tx_list_map, sc->rtk_ldata.rtk_tx_list, 681 RTK_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 682 aprint_error("%s: can't load tx list, error = %d\n", 683 sc->sc_dev.dv_xname, error); 684 goto fail_3; 685 } 686 687 /* Create DMA maps for TX buffers */ 688 for (i = 0; i < RTK_TX_DESC_CNT; i++) { 689 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * RTK_NTXSEGS, 690 RTK_NTXSEGS, MCLBYTES, 0, BUS_DMA_ALLOCNOW, 691 &sc->rtk_ldata.rtk_tx_dmamap[i]); 692 if (error) { 693 aprint_error("%s: can't create DMA map for TX\n", 694 sc->sc_dev.dv_xname); 695 goto fail_4; 696 } 697 } 698 699 /* Allocate DMA'able memory for the RX ring */ 700 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_RX_LIST_SZ, 701 RTK_RING_ALIGN, 0, &sc->rtk_ldata.rtk_rx_listseg, 1, 702 &sc->rtk_ldata.rtk_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 703 aprint_error("%s: can't allocate rx listseg, error = %d\n", 704 sc->sc_dev.dv_xname, error); 705 goto fail_4; 706 } 707 708 /* Load the map for the RX ring. */ 709 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_rx_listseg, 710 sc->rtk_ldata.rtk_rx_listnseg, RTK_RX_LIST_SZ, 711 (caddr_t *)&sc->rtk_ldata.rtk_rx_list, 712 BUS_DMA_NOWAIT)) != 0) { 713 aprint_error("%s: can't map rx list, error = %d\n", 714 sc->sc_dev.dv_xname, error); 715 goto fail_5; 716 } 717 memset(sc->rtk_ldata.rtk_rx_list, 0, RTK_TX_LIST_SZ); 718 719 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_RX_LIST_SZ, 1, 720 RTK_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 721 &sc->rtk_ldata.rtk_rx_list_map)) != 0) { 722 aprint_error("%s: can't create rx list map, error = %d\n", 723 sc->sc_dev.dv_xname, error); 724 goto fail_6; 725 } 726 727 if ((error = bus_dmamap_load(sc->sc_dmat, 728 sc->rtk_ldata.rtk_rx_list_map, sc->rtk_ldata.rtk_rx_list, 729 RTK_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 730 aprint_error("%s: can't load rx list, error = %d\n", 731 sc->sc_dev.dv_xname, error); 732 goto fail_7; 733 } 734 735 /* Create DMA maps for RX buffers */ 736 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 737 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 738 0, BUS_DMA_ALLOCNOW, &sc->rtk_ldata.rtk_rx_dmamap[i]); 739 if (error) { 740 aprint_error("%s: can't create DMA map for RX\n", 741 sc->sc_dev.dv_xname); 742 goto fail_8; 743 } 744 } 745 746 ifp = &sc->ethercom.ec_if; 747 ifp->if_softc = sc; 748 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 749 ifp->if_mtu = ETHERMTU; 750 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 751 ifp->if_ioctl = re_ioctl; 752 sc->ethercom.ec_capabilities |= 753 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 754 ifp->if_start = re_start; 755 ifp->if_stop = re_stop; 756 ifp->if_capabilities |= 757 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 758 ifp->if_watchdog = re_watchdog; 759 ifp->if_init = re_init; 760 if (sc->rtk_type == RTK_8169) 761 ifp->if_baudrate = 1000000000; 762 else 763 ifp->if_baudrate = 100000000; 764 ifp->if_snd.ifq_maxlen = RTK_IFQ_MAXLEN; 765 ifp->if_capenable = ifp->if_capabilities; 766 IFQ_SET_READY(&ifp->if_snd); 767 768 callout_init(&sc->rtk_tick_ch); 769 770 /* Do MII setup */ 771 sc->mii.mii_ifp = ifp; 772 sc->mii.mii_readreg = re_miibus_readreg; 773 sc->mii.mii_writereg = re_miibus_writereg; 774 sc->mii.mii_statchg = re_miibus_statchg; 775 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, re_ifmedia_upd, 776 re_ifmedia_sts); 777 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 778 MII_OFFSET_ANY, 0); 779 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 780 781 /* 782 * Call MI attach routine. 783 */ 784 if_attach(ifp); 785 ether_ifattach(ifp, eaddr); 786 787 /* 788 * Perform hardware diagnostic. 789 * XXX: this diagnostic only makes sense for attachemnts with 64-bit 790 * busses: PCI, but not CardBus. 791 */ 792 error = re_diag(sc); 793 794 if (error) { 795 aprint_error( 796 "%s: attach aborted due to hardware diag failure\n", 797 sc->sc_dev.dv_xname); 798 ether_ifdetach(ifp); 799 if_detach(ifp); 800 goto fail_8; 801 } 802 803 /* 804 * Record interface as attached. From here, we should not fail. 805 */ 806 807 /* 808 * Make sure the interface is shutdown during reboot. 809 */ 810 sc->sc_sdhook = shutdownhook_establish(re_shutdown, sc); 811 if (sc->sc_sdhook == NULL) 812 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 813 sc->sc_dev.dv_xname); 814 /* 815 * Add a suspend hook to make sure we come back up after a 816 * resume. 817 */ 818 sc->sc_powerhook = powerhook_establish(re_power, sc); 819 if (sc->sc_powerhook == NULL) 820 aprint_error("%s: WARNING: unable to establish power hook\n", 821 sc->sc_dev.dv_xname); 822 823 sc->sc_flags |= RTK_ATTACHED; 824 825 return; 826 827 fail_8: 828 /* Destroy DMA maps for RX buffers. */ 829 for (i = 0; i < RTK_RX_DESC_CNT; i++) 830 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 831 bus_dmamap_destroy(sc->sc_dmat, 832 sc->rtk_ldata.rtk_rx_dmamap[i]); 833 834 /* Free DMA'able memory for the RX ring. */ 835 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 836 fail_7: 837 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 838 fail_6: 839 bus_dmamem_unmap(sc->sc_dmat, 840 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 841 fail_5: 842 bus_dmamem_free(sc->sc_dmat, 843 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 844 845 fail_4: 846 /* Destroy DMA maps for TX buffers. */ 847 for (i = 0; i < RTK_TX_DESC_CNT; i++) 848 if (sc->rtk_ldata.rtk_tx_dmamap[i] != NULL) 849 bus_dmamap_destroy(sc->sc_dmat, 850 sc->rtk_ldata.rtk_tx_dmamap[i]); 851 852 /* Free DMA'able memory for the TX ring. */ 853 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 854 fail_3: 855 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 856 fail_2: 857 bus_dmamem_unmap(sc->sc_dmat, 858 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ); 859 fail_1: 860 bus_dmamem_free(sc->sc_dmat, 861 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 862 fail_0: 863 return; 864 } 865 866 867 /* 868 * re_activate: 869 * Handle device activation/deactivation requests. 870 */ 871 int 872 re_activate(struct device *self, enum devact act) 873 { 874 struct rtk_softc *sc = (void *) self; 875 int s, error = 0; 876 877 s = splnet(); 878 switch (act) { 879 case DVACT_ACTIVATE: 880 error = EOPNOTSUPP; 881 break; 882 case DVACT_DEACTIVATE: 883 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 884 if_deactivate(&sc->ethercom.ec_if); 885 break; 886 } 887 splx(s); 888 889 return error; 890 } 891 892 /* 893 * re_detach: 894 * Detach a rtk interface. 895 */ 896 int 897 re_detach(struct rtk_softc *sc) 898 { 899 struct ifnet *ifp = &sc->ethercom.ec_if; 900 int i; 901 902 /* 903 * Succeed now if there isn't any work to do. 904 */ 905 if ((sc->sc_flags & RTK_ATTACHED) == 0) 906 return 0; 907 908 /* Unhook our tick handler. */ 909 callout_stop(&sc->rtk_tick_ch); 910 911 /* Detach all PHYs. */ 912 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 913 914 /* Delete all remaining media. */ 915 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 916 917 ether_ifdetach(ifp); 918 if_detach(ifp); 919 920 /* XXX undo re_allocmem() */ 921 922 /* Destroy DMA maps for RX buffers. */ 923 for (i = 0; i < RTK_RX_DESC_CNT; i++) 924 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 925 bus_dmamap_destroy(sc->sc_dmat, 926 sc->rtk_ldata.rtk_rx_dmamap[i]); 927 928 /* Free DMA'able memory for the RX ring. */ 929 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 930 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 931 bus_dmamem_unmap(sc->sc_dmat, 932 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 933 bus_dmamem_free(sc->sc_dmat, 934 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 935 936 /* Destroy DMA maps for TX buffers. */ 937 for (i = 0; i < RTK_TX_DESC_CNT; i++) 938 if (sc->rtk_ldata.rtk_tx_dmamap[i] != NULL) 939 bus_dmamap_destroy(sc->sc_dmat, 940 sc->rtk_ldata.rtk_tx_dmamap[i]); 941 942 /* Free DMA'able memory for the TX ring. */ 943 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 944 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 945 bus_dmamem_unmap(sc->sc_dmat, 946 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ); 947 bus_dmamem_free(sc->sc_dmat, 948 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 949 950 951 shutdownhook_disestablish(sc->sc_sdhook); 952 powerhook_disestablish(sc->sc_powerhook); 953 954 return 0; 955 } 956 957 /* 958 * re_enable: 959 * Enable the RTL81X9 chip. 960 */ 961 static int 962 re_enable(struct rtk_softc *sc) 963 { 964 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 965 if ((*sc->sc_enable)(sc) != 0) { 966 aprint_error("%s: device enable failed\n", 967 sc->sc_dev.dv_xname); 968 return EIO; 969 } 970 sc->sc_flags |= RTK_ENABLED; 971 } 972 return 0; 973 } 974 975 /* 976 * re_disable: 977 * Disable the RTL81X9 chip. 978 */ 979 static void 980 re_disable(struct rtk_softc *sc) 981 { 982 983 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 984 (*sc->sc_disable)(sc); 985 sc->sc_flags &= ~RTK_ENABLED; 986 } 987 } 988 989 /* 990 * re_power: 991 * Power management (suspend/resume) hook. 992 */ 993 void 994 re_power(int why, void *arg) 995 { 996 struct rtk_softc *sc = (void *) arg; 997 struct ifnet *ifp = &sc->ethercom.ec_if; 998 int s; 999 1000 s = splnet(); 1001 switch (why) { 1002 case PWR_SUSPEND: 1003 case PWR_STANDBY: 1004 re_stop(ifp, 0); 1005 if (sc->sc_power != NULL) 1006 (*sc->sc_power)(sc, why); 1007 break; 1008 case PWR_RESUME: 1009 if (ifp->if_flags & IFF_UP) { 1010 if (sc->sc_power != NULL) 1011 (*sc->sc_power)(sc, why); 1012 re_init(ifp); 1013 } 1014 break; 1015 case PWR_SOFTSUSPEND: 1016 case PWR_SOFTSTANDBY: 1017 case PWR_SOFTRESUME: 1018 break; 1019 } 1020 splx(s); 1021 } 1022 1023 1024 static int 1025 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1026 { 1027 struct mbuf *n = NULL; 1028 bus_dmamap_t map; 1029 struct rtk_desc *d; 1030 u_int32_t cmdstat; 1031 int error; 1032 1033 if (m == NULL) { 1034 MGETHDR(n, M_DONTWAIT, MT_DATA); 1035 if (n == NULL) 1036 return ENOBUFS; 1037 m = n; 1038 1039 MCLGET(m, M_DONTWAIT); 1040 if (!(m->m_flags & M_EXT)) { 1041 m_freem(m); 1042 return ENOBUFS; 1043 } 1044 } else 1045 m->m_data = m->m_ext.ext_buf; 1046 1047 /* 1048 * Initialize mbuf length fields and fixup 1049 * alignment so that the frame payload is 1050 * longword aligned. 1051 */ 1052 m->m_len = m->m_pkthdr.len = MCLBYTES; 1053 m_adj(m, RTK_ETHER_ALIGN); 1054 1055 map = sc->rtk_ldata.rtk_rx_dmamap[idx]; 1056 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1057 1058 if (error) 1059 goto out; 1060 1061 d = &sc->rtk_ldata.rtk_rx_list[idx]; 1062 if (le32toh(d->rtk_cmdstat) & RTK_RDESC_STAT_OWN) 1063 goto out; 1064 1065 cmdstat = map->dm_segs[0].ds_len; 1066 d->rtk_bufaddr_lo = htole32(RTK_ADDR_LO(map->dm_segs[0].ds_addr)); 1067 d->rtk_bufaddr_hi = htole32(RTK_ADDR_HI(map->dm_segs[0].ds_addr)); 1068 cmdstat |= RTK_TDESC_CMD_SOF; 1069 if (idx == (RTK_RX_DESC_CNT - 1)) 1070 cmdstat |= RTK_TDESC_CMD_EOR; 1071 d->rtk_cmdstat = htole32(cmdstat); 1072 1073 d->rtk_cmdstat |= htole32(RTK_TDESC_CMD_EOF); 1074 1075 1076 sc->rtk_ldata.rtk_rx_list[idx].rtk_cmdstat |= 1077 htole32(RTK_RDESC_CMD_OWN); 1078 sc->rtk_ldata.rtk_rx_mbuf[idx] = m; 1079 1080 bus_dmamap_sync(sc->sc_dmat, sc->rtk_ldata.rtk_rx_dmamap[idx], 0, 1081 sc->rtk_ldata.rtk_rx_dmamap[idx]->dm_mapsize, 1082 BUS_DMASYNC_PREREAD); 1083 1084 return 0; 1085 out: 1086 if (n != NULL) 1087 m_freem(n); 1088 return ENOMEM; 1089 } 1090 1091 static int 1092 re_tx_list_init(struct rtk_softc *sc) 1093 { 1094 memset((char *)sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ); 1095 memset((char *)&sc->rtk_ldata.rtk_tx_mbuf, 0, 1096 (RTK_TX_DESC_CNT * sizeof(struct mbuf *))); 1097 1098 bus_dmamap_sync(sc->sc_dmat, 1099 sc->rtk_ldata.rtk_tx_list_map, 0, 1100 sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1101 sc->rtk_ldata.rtk_tx_prodidx = 0; 1102 sc->rtk_ldata.rtk_tx_considx = 0; 1103 sc->rtk_ldata.rtk_tx_free = RTK_TX_DESC_CNT; 1104 1105 return 0; 1106 } 1107 1108 static int 1109 re_rx_list_init(struct rtk_softc *sc) 1110 { 1111 int i; 1112 1113 memset((char *)sc->rtk_ldata.rtk_rx_list, 0, RTK_RX_LIST_SZ); 1114 memset((char *)&sc->rtk_ldata.rtk_rx_mbuf, 0, 1115 (RTK_RX_DESC_CNT * sizeof(struct mbuf *))); 1116 1117 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 1118 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1119 return ENOBUFS; 1120 } 1121 1122 /* Flush the RX descriptors */ 1123 1124 bus_dmamap_sync(sc->sc_dmat, 1125 sc->rtk_ldata.rtk_rx_list_map, 1126 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1127 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1128 1129 sc->rtk_ldata.rtk_rx_prodidx = 0; 1130 sc->rtk_head = sc->rtk_tail = NULL; 1131 1132 return 0; 1133 } 1134 1135 /* 1136 * RX handler for C+ and 8169. For the gigE chips, we support 1137 * the reception of jumbo frames that have been fragmented 1138 * across multiple 2K mbuf cluster buffers. 1139 */ 1140 static void 1141 re_rxeof(struct rtk_softc *sc) 1142 { 1143 struct mbuf *m; 1144 struct ifnet *ifp; 1145 int i, total_len; 1146 struct rtk_desc *cur_rx; 1147 struct m_tag *mtag; 1148 u_int32_t rxstat, rxvlan; 1149 1150 ifp = &sc->ethercom.ec_if; 1151 i = sc->rtk_ldata.rtk_rx_prodidx; 1152 1153 /* Invalidate the descriptor memory */ 1154 1155 bus_dmamap_sync(sc->sc_dmat, 1156 sc->rtk_ldata.rtk_rx_list_map, 1157 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1158 BUS_DMASYNC_POSTREAD); 1159 1160 while (!RTK_OWN(&sc->rtk_ldata.rtk_rx_list[i])) { 1161 1162 cur_rx = &sc->rtk_ldata.rtk_rx_list[i]; 1163 m = sc->rtk_ldata.rtk_rx_mbuf[i]; 1164 total_len = RTK_RXBYTES(cur_rx); 1165 rxstat = le32toh(cur_rx->rtk_cmdstat); 1166 rxvlan = le32toh(cur_rx->rtk_vlanctl); 1167 1168 /* Invalidate the RX mbuf and unload its map */ 1169 1170 bus_dmamap_sync(sc->sc_dmat, 1171 sc->rtk_ldata.rtk_rx_dmamap[i], 1172 0, sc->rtk_ldata.rtk_rx_dmamap[i]->dm_mapsize, 1173 BUS_DMASYNC_POSTWRITE); 1174 bus_dmamap_unload(sc->sc_dmat, 1175 sc->rtk_ldata.rtk_rx_dmamap[i]); 1176 1177 if (!(rxstat & RTK_RDESC_STAT_EOF)) { 1178 m->m_len = MCLBYTES - RTK_ETHER_ALIGN; 1179 if (sc->rtk_head == NULL) 1180 sc->rtk_head = sc->rtk_tail = m; 1181 else { 1182 m->m_flags &= ~M_PKTHDR; 1183 sc->rtk_tail->m_next = m; 1184 sc->rtk_tail = m; 1185 } 1186 re_newbuf(sc, i, NULL); 1187 RTK_DESC_INC(i); 1188 continue; 1189 } 1190 1191 /* 1192 * NOTE: for the 8139C+, the frame length field 1193 * is always 12 bits in size, but for the gigE chips, 1194 * it is 13 bits (since the max RX frame length is 16K). 1195 * Unfortunately, all 32 bits in the status word 1196 * were already used, so to make room for the extra 1197 * length bit, RealTek took out the 'frame alignment 1198 * error' bit and shifted the other status bits 1199 * over one slot. The OWN, EOR, FS and LS bits are 1200 * still in the same places. We have already extracted 1201 * the frame length and checked the OWN bit, so rather 1202 * than using an alternate bit mapping, we shift the 1203 * status bits one space to the right so we can evaluate 1204 * them using the 8169 status as though it was in the 1205 * same format as that of the 8139C+. 1206 */ 1207 if (sc->rtk_type == RTK_8169) 1208 rxstat >>= 1; 1209 1210 if (rxstat & RTK_RDESC_STAT_RXERRSUM) { 1211 ifp->if_ierrors++; 1212 /* 1213 * If this is part of a multi-fragment packet, 1214 * discard all the pieces. 1215 */ 1216 if (sc->rtk_head != NULL) { 1217 m_freem(sc->rtk_head); 1218 sc->rtk_head = sc->rtk_tail = NULL; 1219 } 1220 re_newbuf(sc, i, m); 1221 RTK_DESC_INC(i); 1222 continue; 1223 } 1224 1225 /* 1226 * If allocating a replacement mbuf fails, 1227 * reload the current one. 1228 */ 1229 1230 if (re_newbuf(sc, i, NULL)) { 1231 ifp->if_ierrors++; 1232 if (sc->rtk_head != NULL) { 1233 m_freem(sc->rtk_head); 1234 sc->rtk_head = sc->rtk_tail = NULL; 1235 } 1236 re_newbuf(sc, i, m); 1237 RTK_DESC_INC(i); 1238 continue; 1239 } 1240 1241 RTK_DESC_INC(i); 1242 1243 if (sc->rtk_head != NULL) { 1244 m->m_len = total_len % (MCLBYTES - RTK_ETHER_ALIGN); 1245 /* 1246 * Special case: if there's 4 bytes or less 1247 * in this buffer, the mbuf can be discarded: 1248 * the last 4 bytes is the CRC, which we don't 1249 * care about anyway. 1250 */ 1251 if (m->m_len <= ETHER_CRC_LEN) { 1252 sc->rtk_tail->m_len -= 1253 (ETHER_CRC_LEN - m->m_len); 1254 m_freem(m); 1255 } else { 1256 m->m_len -= ETHER_CRC_LEN; 1257 m->m_flags &= ~M_PKTHDR; 1258 sc->rtk_tail->m_next = m; 1259 } 1260 m = sc->rtk_head; 1261 sc->rtk_head = sc->rtk_tail = NULL; 1262 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1263 } else 1264 m->m_pkthdr.len = m->m_len = 1265 (total_len - ETHER_CRC_LEN); 1266 1267 ifp->if_ipackets++; 1268 m->m_pkthdr.rcvif = ifp; 1269 1270 /* Do RX checksumming if enabled */ 1271 1272 if (ifp->if_capenable & IFCAP_CSUM_IPv4) { 1273 1274 /* Check IP header checksum */ 1275 if (rxstat & RTK_RDESC_STAT_PROTOID) 1276 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;; 1277 if (rxstat & RTK_RDESC_STAT_IPSUMBAD) 1278 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1279 } 1280 1281 /* Check TCP/UDP checksum */ 1282 if (RTK_TCPPKT(rxstat) && 1283 (ifp->if_capenable & IFCAP_CSUM_TCPv4)) { 1284 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1285 if (rxstat & RTK_RDESC_STAT_TCPSUMBAD) 1286 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1287 } 1288 if (RTK_UDPPKT(rxstat) && 1289 (ifp->if_capenable & IFCAP_CSUM_UDPv4)) { 1290 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1291 if (rxstat & RTK_RDESC_STAT_UDPSUMBAD) 1292 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1293 } 1294 1295 if (rxvlan & RTK_RDESC_VLANCTL_TAG) { 1296 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1297 M_NOWAIT); 1298 if (mtag == NULL) { 1299 ifp->if_ierrors++; 1300 m_freem(m); 1301 continue; 1302 } 1303 *(u_int *)(mtag + 1) = 1304 be16toh(rxvlan & RTK_RDESC_VLANCTL_DATA); 1305 m_tag_prepend(m, mtag); 1306 } 1307 #if NBPFILTER > 0 1308 if (ifp->if_bpf) 1309 bpf_mtap(ifp->if_bpf, m); 1310 #endif 1311 (*ifp->if_input)(ifp, m); 1312 } 1313 1314 /* Flush the RX DMA ring */ 1315 1316 bus_dmamap_sync(sc->sc_dmat, 1317 sc->rtk_ldata.rtk_rx_list_map, 1318 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1319 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1320 1321 sc->rtk_ldata.rtk_rx_prodidx = i; 1322 1323 return; 1324 } 1325 1326 static void 1327 re_txeof(struct rtk_softc *sc) 1328 { 1329 struct ifnet *ifp; 1330 u_int32_t txstat; 1331 int idx; 1332 1333 ifp = &sc->ethercom.ec_if; 1334 idx = sc->rtk_ldata.rtk_tx_considx; 1335 1336 /* Invalidate the TX descriptor list */ 1337 1338 bus_dmamap_sync(sc->sc_dmat, 1339 sc->rtk_ldata.rtk_tx_list_map, 1340 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1341 BUS_DMASYNC_POSTREAD); 1342 1343 while (idx != sc->rtk_ldata.rtk_tx_prodidx) { 1344 1345 txstat = le32toh(sc->rtk_ldata.rtk_tx_list[idx].rtk_cmdstat); 1346 if (txstat & RTK_TDESC_CMD_OWN) 1347 break; 1348 1349 /* 1350 * We only stash mbufs in the last descriptor 1351 * in a fragment chain, which also happens to 1352 * be the only place where the TX status bits 1353 * are valid. 1354 */ 1355 1356 if (txstat & RTK_TDESC_CMD_EOF) { 1357 m_freem(sc->rtk_ldata.rtk_tx_mbuf[idx]); 1358 sc->rtk_ldata.rtk_tx_mbuf[idx] = NULL; 1359 bus_dmamap_unload(sc->sc_dmat, 1360 sc->rtk_ldata.rtk_tx_dmamap[idx]); 1361 if (txstat & (RTK_TDESC_STAT_EXCESSCOL | 1362 RTK_TDESC_STAT_COLCNT)) 1363 ifp->if_collisions++; 1364 if (txstat & RTK_TDESC_STAT_TXERRSUM) 1365 ifp->if_oerrors++; 1366 else 1367 ifp->if_opackets++; 1368 } 1369 sc->rtk_ldata.rtk_tx_free++; 1370 RTK_DESC_INC(idx); 1371 } 1372 1373 /* No changes made to the TX ring, so no flush needed */ 1374 1375 if (idx != sc->rtk_ldata.rtk_tx_considx) { 1376 sc->rtk_ldata.rtk_tx_considx = idx; 1377 ifp->if_flags &= ~IFF_OACTIVE; 1378 ifp->if_timer = 0; 1379 } 1380 1381 /* 1382 * If not all descriptors have been released reaped yet, 1383 * reload the timer so that we will eventually get another 1384 * interrupt that will cause us to re-enter this routine. 1385 * This is done in case the transmitter has gone idle. 1386 */ 1387 if (sc->rtk_ldata.rtk_tx_free != RTK_TX_DESC_CNT) 1388 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1389 1390 return; 1391 } 1392 1393 /* 1394 * Stop all chip I/O so that the kernel's probe routines don't 1395 * get confused by errant DMAs when rebooting. 1396 */ 1397 static void 1398 re_shutdown(void *vsc) 1399 1400 { 1401 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1402 1403 re_stop(&sc->ethercom.ec_if, 0); 1404 } 1405 1406 1407 static void 1408 re_tick(void *xsc) 1409 { 1410 struct rtk_softc *sc = xsc; 1411 int s; 1412 1413 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1414 s = splnet(); 1415 1416 mii_tick(&sc->mii); 1417 splx(s); 1418 1419 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1420 } 1421 1422 #ifdef DEVICE_POLLING 1423 static void 1424 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1425 { 1426 struct rtk_softc *sc = ifp->if_softc; 1427 1428 RTK_LOCK(sc); 1429 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1430 ether_poll_deregister(ifp); 1431 cmd = POLL_DEREGISTER; 1432 } 1433 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1434 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1435 goto done; 1436 } 1437 1438 sc->rxcycles = count; 1439 re_rxeof(sc); 1440 re_txeof(sc); 1441 1442 if (ifp->if_snd.ifq_head != NULL) 1443 (*ifp->if_start)(ifp); 1444 1445 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1446 u_int16_t status; 1447 1448 status = CSR_READ_2(sc, RTK_ISR); 1449 if (status == 0xffff) 1450 goto done; 1451 if (status) 1452 CSR_WRITE_2(sc, RTK_ISR, status); 1453 1454 /* 1455 * XXX check behaviour on receiver stalls. 1456 */ 1457 1458 if (status & RTK_ISR_SYSTEM_ERR) { 1459 re_reset(sc); 1460 re_init(sc); 1461 } 1462 } 1463 done: 1464 RTK_UNLOCK(sc); 1465 } 1466 #endif /* DEVICE_POLLING */ 1467 1468 int 1469 re_intr(void *arg) 1470 { 1471 struct rtk_softc *sc = arg; 1472 struct ifnet *ifp; 1473 u_int16_t status; 1474 int handled = 0; 1475 1476 ifp = &sc->ethercom.ec_if; 1477 1478 if (!(ifp->if_flags & IFF_UP)) 1479 return 0; 1480 1481 #ifdef DEVICE_POLLING 1482 if (ifp->if_flags & IFF_POLLING) 1483 goto done; 1484 if ((ifp->if_capenable & IFCAP_POLLING) && 1485 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1486 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1487 re_poll(ifp, 0, 1); 1488 goto done; 1489 } 1490 #endif /* DEVICE_POLLING */ 1491 1492 for (;;) { 1493 1494 status = CSR_READ_2(sc, RTK_ISR); 1495 /* If the card has gone away the read returns 0xffff. */ 1496 if (status == 0xffff) 1497 break; 1498 if (status) { 1499 handled = 1; 1500 CSR_WRITE_2(sc, RTK_ISR, status); 1501 } 1502 1503 if ((status & RTK_INTRS_CPLUS) == 0) 1504 break; 1505 1506 if (status & RTK_ISR_RX_OK) 1507 re_rxeof(sc); 1508 1509 if (status & RTK_ISR_RX_ERR) 1510 re_rxeof(sc); 1511 1512 if ((status & RTK_ISR_TIMEOUT_EXPIRED) || 1513 (status & RTK_ISR_TX_ERR) || 1514 (status & RTK_ISR_TX_DESC_UNAVAIL)) 1515 re_txeof(sc); 1516 1517 if (status & RTK_ISR_SYSTEM_ERR) { 1518 re_reset(sc); 1519 re_init(ifp); 1520 } 1521 1522 if (status & RTK_ISR_LINKCHG) { 1523 callout_stop(&sc->rtk_tick_ch); 1524 re_tick(sc); 1525 } 1526 } 1527 1528 if (ifp->if_flags & IFF_UP) /* kludge for interrupt during re_init() */ 1529 if (ifp->if_snd.ifq_head != NULL) 1530 (*ifp->if_start)(ifp); 1531 1532 #ifdef DEVICE_POLLING 1533 done: 1534 #endif 1535 1536 return handled; 1537 } 1538 1539 static int 1540 re_encap(struct rtk_softc *sc, struct mbuf *m_head, int *idx) 1541 { 1542 bus_dmamap_t map; 1543 int error, i, curidx; 1544 struct m_tag *mtag; 1545 struct rtk_desc *d; 1546 u_int32_t cmdstat, rtk_flags; 1547 1548 if (sc->rtk_ldata.rtk_tx_free <= 4) 1549 return EFBIG; 1550 1551 /* 1552 * Set up checksum offload. Note: checksum offload bits must 1553 * appear in all descriptors of a multi-descriptor transmit 1554 * attempt. (This is according to testing done with an 8169 1555 * chip. I'm not sure if this is a requirement or a bug.) 1556 */ 1557 1558 rtk_flags = 0; 1559 1560 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1561 rtk_flags |= RTK_TDESC_CMD_IPCSUM; 1562 if (m_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1563 rtk_flags |= RTK_TDESC_CMD_TCPCSUM; 1564 if (m_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1565 rtk_flags |= RTK_TDESC_CMD_UDPCSUM; 1566 1567 map = sc->rtk_ldata.rtk_tx_dmamap[*idx]; 1568 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, 1569 m_head, BUS_DMA_NOWAIT); 1570 1571 if (error) { 1572 aprint_error("%s: can't map mbuf (error %d)\n", 1573 sc->sc_dev.dv_xname, error); 1574 return ENOBUFS; 1575 } 1576 1577 if (map->dm_nsegs > sc->rtk_ldata.rtk_tx_free - 4) 1578 return ENOBUFS; 1579 /* 1580 * Map the segment array into descriptors. Note that we set the 1581 * start-of-frame and end-of-frame markers for either TX or RX, but 1582 * they really only have meaning in the TX case. (In the RX case, 1583 * it's the chip that tells us where packets begin and end.) 1584 * We also keep track of the end of the ring and set the 1585 * end-of-ring bits as needed, and we set the ownership bits 1586 * in all except the very first descriptor. (The caller will 1587 * set this descriptor later when it start transmission or 1588 * reception.) 1589 */ 1590 i = 0; 1591 curidx = *idx; 1592 while (1) { 1593 d = &sc->rtk_ldata.rtk_tx_list[curidx]; 1594 if (le32toh(d->rtk_cmdstat) & RTK_RDESC_STAT_OWN) 1595 return ENOBUFS; 1596 1597 cmdstat = map->dm_segs[i].ds_len; 1598 d->rtk_bufaddr_lo = 1599 htole32(RTK_ADDR_LO(map->dm_segs[i].ds_addr)); 1600 d->rtk_bufaddr_hi = 1601 htole32(RTK_ADDR_HI(map->dm_segs[i].ds_addr)); 1602 if (i == 0) 1603 cmdstat |= RTK_TDESC_CMD_SOF; 1604 else 1605 cmdstat |= RTK_TDESC_CMD_OWN; 1606 if (curidx == (RTK_RX_DESC_CNT - 1)) 1607 cmdstat |= RTK_TDESC_CMD_EOR; 1608 d->rtk_cmdstat = htole32(cmdstat | rtk_flags); 1609 i++; 1610 if (i == map->dm_nsegs) 1611 break; 1612 RTK_DESC_INC(curidx); 1613 } 1614 1615 d->rtk_cmdstat |= htole32(RTK_TDESC_CMD_EOF); 1616 1617 /* 1618 * Insure that the map for this transmission 1619 * is placed at the array index of the last descriptor 1620 * in this chain. 1621 */ 1622 sc->rtk_ldata.rtk_tx_dmamap[*idx] = 1623 sc->rtk_ldata.rtk_tx_dmamap[curidx]; 1624 sc->rtk_ldata.rtk_tx_dmamap[curidx] = map; 1625 sc->rtk_ldata.rtk_tx_mbuf[curidx] = m_head; 1626 sc->rtk_ldata.rtk_tx_free -= map->dm_nsegs; 1627 1628 /* 1629 * Set up hardware VLAN tagging. Note: vlan tag info must 1630 * appear in the first descriptor of a multi-descriptor 1631 * transmission attempt. 1632 */ 1633 1634 if (sc->ethercom.ec_nvlans && 1635 (mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL)) != NULL) 1636 sc->rtk_ldata.rtk_tx_list[*idx].rtk_vlanctl = 1637 htole32(htons(*(u_int *)(mtag + 1)) | 1638 RTK_TDESC_VLANCTL_TAG); 1639 1640 /* Transfer ownership of packet to the chip. */ 1641 1642 sc->rtk_ldata.rtk_tx_list[curidx].rtk_cmdstat |= 1643 htole32(RTK_TDESC_CMD_OWN); 1644 if (*idx != curidx) 1645 sc->rtk_ldata.rtk_tx_list[*idx].rtk_cmdstat |= 1646 htole32(RTK_TDESC_CMD_OWN); 1647 1648 RTK_DESC_INC(curidx); 1649 *idx = curidx; 1650 1651 return 0; 1652 } 1653 1654 /* 1655 * Main transmit routine for C+ and gigE NICs. 1656 */ 1657 1658 static void 1659 re_start(struct ifnet *ifp) 1660 { 1661 struct rtk_softc *sc; 1662 struct mbuf *m_head = NULL; 1663 int idx; 1664 1665 sc = ifp->if_softc; 1666 1667 idx = sc->rtk_ldata.rtk_tx_prodidx; 1668 while (sc->rtk_ldata.rtk_tx_mbuf[idx] == NULL) { 1669 IF_DEQUEUE(&ifp->if_snd, m_head); 1670 if (m_head == NULL) 1671 break; 1672 1673 if (re_encap(sc, m_head, &idx)) { 1674 IF_PREPEND(&ifp->if_snd, m_head); 1675 ifp->if_flags |= IFF_OACTIVE; 1676 break; 1677 } 1678 #if NBPFILTER > 0 1679 /* 1680 * If there's a BPF listener, bounce a copy of this frame 1681 * to him. 1682 */ 1683 if (ifp->if_bpf) 1684 bpf_mtap(ifp->if_bpf, m_head); 1685 #endif 1686 } 1687 1688 /* Flush the TX descriptors */ 1689 1690 bus_dmamap_sync(sc->sc_dmat, 1691 sc->rtk_ldata.rtk_tx_list_map, 1692 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1693 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1694 1695 sc->rtk_ldata.rtk_tx_prodidx = idx; 1696 1697 /* 1698 * RealTek put the TX poll request register in a different 1699 * location on the 8169 gigE chip. I don't know why. 1700 */ 1701 1702 if (sc->rtk_type == RTK_8169) 1703 CSR_WRITE_2(sc, RTK_GTXSTART, RTK_TXSTART_START); 1704 else 1705 CSR_WRITE_2(sc, RTK_TXSTART, RTK_TXSTART_START); 1706 1707 /* 1708 * Use the countdown timer for interrupt moderation. 1709 * 'TX done' interrupts are disabled. Instead, we reset the 1710 * countdown timer, which will begin counting until it hits 1711 * the value in the TIMERINT register, and then trigger an 1712 * interrupt. Each time we write to the TIMERCNT register, 1713 * the timer count is reset to 0. 1714 */ 1715 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1716 1717 /* 1718 * Set a timeout in case the chip goes out to lunch. 1719 */ 1720 ifp->if_timer = 5; 1721 1722 return; 1723 } 1724 1725 static int 1726 re_init(struct ifnet *ifp) 1727 { 1728 struct rtk_softc *sc = ifp->if_softc; 1729 u_int32_t rxcfg = 0; 1730 u_int32_t reg; 1731 int error; 1732 1733 if ((error = re_enable(sc)) != 0) 1734 goto out; 1735 1736 /* 1737 * Cancel pending I/O and free all RX/TX buffers. 1738 */ 1739 re_stop(ifp, 0); 1740 1741 /* 1742 * Enable C+ RX and TX mode, as well as VLAN stripping and 1743 * RX checksum offload. We must configure the C+ register 1744 * before all others. 1745 */ 1746 reg = 0; 1747 1748 /* 1749 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S. 1750 * FreeBSD drivers set these bits anyway (for 8139C+?). 1751 * So far, it works. 1752 */ 1753 1754 /* 1755 * XXX: For 8169 and 8196S revs below 2, set bit 14. 1756 * For 8169S/8110S rev 2 and above, do not set bit 14. 1757 */ 1758 if (sc->rtk_type == RTK_8169 && sc->sc_rev == 1) 1759 reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW;; 1760 1761 if (1) {/* not for 8169S ? */ 1762 reg |= RTK_CPLUSCMD_VLANSTRIP | 1763 (ifp->if_capenable & 1764 (IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4) ? 1765 RTK_CPLUSCMD_RXCSUM_ENB : 0); 1766 } 1767 1768 CSR_WRITE_2(sc, RTK_CPLUS_CMD, 1769 reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB); 1770 1771 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1772 if (sc->rtk_type == RTK_8169) 1773 CSR_WRITE_2(sc, RTK_CPLUS_CMD+0x2, 0x0000); 1774 1775 DELAY(10000); 1776 1777 /* 1778 * Init our MAC address. Even though the chipset 1779 * documentation doesn't mention it, we need to enter "Config 1780 * register write enable" mode to modify the ID registers. 1781 */ 1782 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1783 memcpy(®, LLADDR(ifp->if_sadl), 4); 1784 CSR_WRITE_STREAM_4(sc, RTK_IDR0, reg); 1785 reg = 0; 1786 memcpy(®, LLADDR(ifp->if_sadl) + 4, 4); 1787 CSR_WRITE_STREAM_4(sc, RTK_IDR4, reg); 1788 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1789 1790 /* 1791 * For C+ mode, initialize the RX descriptors and mbufs. 1792 */ 1793 re_rx_list_init(sc); 1794 re_tx_list_init(sc); 1795 1796 /* 1797 * Enable transmit and receive. 1798 */ 1799 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1800 1801 /* 1802 * Set the initial TX and RX configuration. 1803 */ 1804 if (sc->rtk_testmode) { 1805 if (sc->rtk_type == RTK_8169) 1806 CSR_WRITE_4(sc, RTK_TXCFG, 1807 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1808 else 1809 CSR_WRITE_4(sc, RTK_TXCFG, 1810 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON_CPLUS); 1811 } else 1812 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1813 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1814 1815 /* Set the individual bit to receive frames for this host only. */ 1816 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1817 rxcfg |= RTK_RXCFG_RX_INDIV; 1818 1819 /* If we want promiscuous mode, set the allframes bit. */ 1820 if (ifp->if_flags & IFF_PROMISC) { 1821 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1822 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1823 } else { 1824 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1825 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1826 } 1827 1828 /* 1829 * Set capture broadcast bit to capture broadcast frames. 1830 */ 1831 if (ifp->if_flags & IFF_BROADCAST) { 1832 rxcfg |= RTK_RXCFG_RX_BROAD; 1833 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1834 } else { 1835 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1836 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1837 } 1838 1839 /* 1840 * Program the multicast filter, if necessary. 1841 */ 1842 rtk_setmulti(sc); 1843 1844 #ifdef DEVICE_POLLING 1845 /* 1846 * Disable interrupts if we are polling. 1847 */ 1848 if (ifp->if_flags & IFF_POLLING) 1849 CSR_WRITE_2(sc, RTK_IMR, 0); 1850 else /* otherwise ... */ 1851 #endif /* DEVICE_POLLING */ 1852 /* 1853 * Enable interrupts. 1854 */ 1855 if (sc->rtk_testmode) 1856 CSR_WRITE_2(sc, RTK_IMR, 0); 1857 else 1858 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1859 1860 /* Start RX/TX process. */ 1861 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1862 #ifdef notdef 1863 /* Enable receiver and transmitter. */ 1864 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1865 #endif 1866 /* 1867 * Load the addresses of the RX and TX lists into the chip. 1868 */ 1869 1870 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1871 RTK_ADDR_HI(sc->rtk_ldata.rtk_rx_listseg.ds_addr)); 1872 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1873 RTK_ADDR_LO(sc->rtk_ldata.rtk_rx_listseg.ds_addr)); 1874 1875 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1876 RTK_ADDR_HI(sc->rtk_ldata.rtk_tx_listseg.ds_addr)); 1877 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1878 RTK_ADDR_LO(sc->rtk_ldata.rtk_tx_listseg.ds_addr)); 1879 1880 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1881 1882 /* 1883 * Initialize the timer interrupt register so that 1884 * a timer interrupt will be generated once the timer 1885 * reaches a certain number of ticks. The timer is 1886 * reloaded on each transmit. This gives us TX interrupt 1887 * moderation, which dramatically improves TX frame rate. 1888 */ 1889 1890 if (sc->rtk_type == RTK_8169) 1891 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1892 else 1893 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1894 1895 /* 1896 * For 8169 gigE NICs, set the max allowed RX packet 1897 * size so we can receive jumbo frames. 1898 */ 1899 if (sc->rtk_type == RTK_8169) 1900 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1901 1902 if (sc->rtk_testmode) 1903 return 0; 1904 1905 mii_mediachg(&sc->mii); 1906 1907 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD | RTK_CFG1_FULLDUPLEX); 1908 1909 ifp->if_flags |= IFF_RUNNING; 1910 ifp->if_flags &= ~IFF_OACTIVE; 1911 1912 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1913 1914 out: 1915 if (error) { 1916 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1917 ifp->if_timer = 0; 1918 aprint_error("%s: interface not running\n", 1919 sc->sc_dev.dv_xname); 1920 } 1921 1922 return error; 1923 1924 } 1925 1926 /* 1927 * Set media options. 1928 */ 1929 static int 1930 re_ifmedia_upd(struct ifnet *ifp) 1931 { 1932 struct rtk_softc *sc; 1933 1934 sc = ifp->if_softc; 1935 1936 return mii_mediachg(&sc->mii); 1937 } 1938 1939 /* 1940 * Report current media status. 1941 */ 1942 static void 1943 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1944 { 1945 struct rtk_softc *sc; 1946 1947 sc = ifp->if_softc; 1948 1949 mii_pollstat(&sc->mii); 1950 ifmr->ifm_active = sc->mii.mii_media_active; 1951 ifmr->ifm_status = sc->mii.mii_media_status; 1952 1953 return; 1954 } 1955 1956 static int 1957 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1958 { 1959 struct rtk_softc *sc = ifp->if_softc; 1960 struct ifreq *ifr = (struct ifreq *) data; 1961 int s, error = 0; 1962 1963 s = splnet(); 1964 1965 switch (command) { 1966 case SIOCSIFMTU: 1967 if (ifr->ifr_mtu > RTK_JUMBO_MTU) 1968 error = EINVAL; 1969 ifp->if_mtu = ifr->ifr_mtu; 1970 break; 1971 case SIOCGIFMEDIA: 1972 case SIOCSIFMEDIA: 1973 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1974 break; 1975 default: 1976 error = ether_ioctl(ifp, command, data); 1977 if (error == ENETRESET) { 1978 if (ifp->if_flags & IFF_RUNNING) 1979 rtk_setmulti(sc); 1980 error = 0; 1981 } 1982 break; 1983 } 1984 1985 splx(s); 1986 1987 return error; 1988 } 1989 1990 static void 1991 re_watchdog(struct ifnet *ifp) 1992 { 1993 struct rtk_softc *sc; 1994 int s; 1995 1996 sc = ifp->if_softc; 1997 s = splnet(); 1998 aprint_error("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1999 ifp->if_oerrors++; 2000 2001 re_txeof(sc); 2002 re_rxeof(sc); 2003 2004 re_init(ifp); 2005 2006 splx(s); 2007 } 2008 2009 /* 2010 * Stop the adapter and free any mbufs allocated to the 2011 * RX and TX lists. 2012 */ 2013 static void 2014 re_stop(struct ifnet *ifp, int disable) 2015 { 2016 register int i; 2017 struct rtk_softc *sc = ifp->if_softc; 2018 2019 callout_stop(&sc->rtk_tick_ch); 2020 2021 #ifdef DEVICE_POLLING 2022 ether_poll_deregister(ifp); 2023 #endif /* DEVICE_POLLING */ 2024 2025 mii_down(&sc->mii); 2026 2027 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2028 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2029 2030 if (sc->rtk_head != NULL) { 2031 m_freem(sc->rtk_head); 2032 sc->rtk_head = sc->rtk_tail = NULL; 2033 } 2034 2035 /* Free the TX list buffers. */ 2036 for (i = 0; i < RTK_TX_DESC_CNT; i++) { 2037 if (sc->rtk_ldata.rtk_tx_mbuf[i] != NULL) { 2038 bus_dmamap_unload(sc->sc_dmat, 2039 sc->rtk_ldata.rtk_tx_dmamap[i]); 2040 m_freem(sc->rtk_ldata.rtk_tx_mbuf[i]); 2041 sc->rtk_ldata.rtk_tx_mbuf[i] = NULL; 2042 } 2043 } 2044 2045 /* Free the RX list buffers. */ 2046 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 2047 if (sc->rtk_ldata.rtk_rx_mbuf[i] != NULL) { 2048 bus_dmamap_unload(sc->sc_dmat, 2049 sc->rtk_ldata.rtk_rx_dmamap[i]); 2050 m_freem(sc->rtk_ldata.rtk_rx_mbuf[i]); 2051 sc->rtk_ldata.rtk_rx_mbuf[i] = NULL; 2052 } 2053 } 2054 2055 if (disable) 2056 re_disable(sc); 2057 2058 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2059 ifp->if_timer = 0; 2060 2061 return; 2062 } 2063
Indexes created Mon Sep 22 13:09:51 GMT 2025