rtl81x9.c revision 1.103 1 1.103 msaitoh /* $NetBSD: rtl81x9.c,v 1.103 2018/06/26 06:48:00 msaitoh Exp $ */
2 1.1 haya
3 1.1 haya /*
4 1.1 haya * Copyright (c) 1997, 1998
5 1.1 haya * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved.
6 1.1 haya *
7 1.1 haya * Redistribution and use in source and binary forms, with or without
8 1.1 haya * modification, are permitted provided that the following conditions
9 1.1 haya * are met:
10 1.1 haya * 1. Redistributions of source code must retain the above copyright
11 1.1 haya * notice, this list of conditions and the following disclaimer.
12 1.1 haya * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 haya * notice, this list of conditions and the following disclaimer in the
14 1.1 haya * documentation and/or other materials provided with the distribution.
15 1.1 haya * 3. All advertising materials mentioning features or use of this software
16 1.1 haya * must display the following acknowledgement:
17 1.1 haya * This product includes software developed by Bill Paul.
18 1.1 haya * 4. Neither the name of the author nor the names of any co-contributors
19 1.1 haya * may be used to endorse or promote products derived from this software
20 1.1 haya * without specific prior written permission.
21 1.1 haya *
22 1.1 haya * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 1.1 haya * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 haya * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 haya * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 1.1 haya * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 1.1 haya * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 1.1 haya * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 1.1 haya * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 1.1 haya * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 1.1 haya * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 1.1 haya * THE POSSIBILITY OF SUCH DAMAGE.
33 1.1 haya *
34 1.1 haya * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp
35 1.1 haya */
36 1.1 haya
37 1.1 haya /*
38 1.1 haya * RealTek 8129/8139 PCI NIC driver
39 1.1 haya *
40 1.1 haya * Supports several extremely cheap PCI 10/100 adapters based on
41 1.1 haya * the RealTek chipset. Datasheets can be obtained from
42 1.1 haya * www.realtek.com.tw.
43 1.1 haya *
44 1.1 haya * Written by Bill Paul <wpaul (at) ctr.columbia.edu>
45 1.1 haya * Electrical Engineering Department
46 1.1 haya * Columbia University, New York City
47 1.1 haya */
48 1.1 haya
49 1.1 haya /*
50 1.1 haya * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
51 1.1 haya * probably the worst PCI ethernet controller ever made, with the possible
52 1.1 haya * exception of the FEAST chip made by SMC. The 8139 supports bus-master
53 1.1 haya * DMA, but it has a terrible interface that nullifies any performance
54 1.1 haya * gains that bus-master DMA usually offers.
55 1.1 haya *
56 1.1 haya * For transmission, the chip offers a series of four TX descriptor
57 1.1 haya * registers. Each transmit frame must be in a contiguous buffer, aligned
58 1.1 haya * on a longword (32-bit) boundary. This means we almost always have to
59 1.1 haya * do mbuf copies in order to transmit a frame, except in the unlikely
60 1.1 haya * case where a) the packet fits into a single mbuf, and b) the packet
61 1.1 haya * is 32-bit aligned within the mbuf's data area. The presence of only
62 1.1 haya * four descriptor registers means that we can never have more than four
63 1.1 haya * packets queued for transmission at any one time.
64 1.1 haya *
65 1.1 haya * Reception is not much better. The driver has to allocate a single large
66 1.1 haya * buffer area (up to 64K in size) into which the chip will DMA received
67 1.1 haya * frames. Because we don't know where within this region received packets
68 1.1 haya * will begin or end, we have no choice but to copy data from the buffer
69 1.1 haya * area into mbufs in order to pass the packets up to the higher protocol
70 1.1 haya * levels.
71 1.1 haya *
72 1.1 haya * It's impossible given this rotten design to really achieve decent
73 1.45 tsutsui * performance at 100Mbps, unless you happen to have a 400MHz PII or
74 1.1 haya * some equally overmuscled CPU to drive it.
75 1.1 haya *
76 1.1 haya * On the bright side, the 8139 does have a built-in PHY, although
77 1.1 haya * rather than using an MDIO serial interface like most other NICs, the
78 1.1 haya * PHY registers are directly accessible through the 8139's register
79 1.1 haya * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 1.1 haya * filter.
81 1.1 haya *
82 1.1 haya * The 8129 chip is an older version of the 8139 that uses an external PHY
83 1.1 haya * chip. The 8129 has a serial MDIO interface for accessing the MII where
84 1.1 haya * the 8139 lets you directly access the on-board PHY registers. We need
85 1.1 haya * to select which interface to use depending on the chip type.
86 1.1 haya */
87 1.40 lukem
88 1.40 lukem #include <sys/cdefs.h>
89 1.103 msaitoh __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.103 2018/06/26 06:48:00 msaitoh Exp $");
90 1.1 haya
91 1.1 haya
92 1.1 haya #include <sys/param.h>
93 1.1 haya #include <sys/systm.h>
94 1.1 haya #include <sys/callout.h>
95 1.1 haya #include <sys/device.h>
96 1.1 haya #include <sys/sockio.h>
97 1.1 haya #include <sys/mbuf.h>
98 1.1 haya #include <sys/malloc.h>
99 1.1 haya #include <sys/kernel.h>
100 1.1 haya #include <sys/socket.h>
101 1.1 haya
102 1.1 haya #include <net/if.h>
103 1.1 haya #include <net/if_arp.h>
104 1.1 haya #include <net/if_ether.h>
105 1.1 haya #include <net/if_dl.h>
106 1.1 haya #include <net/if_media.h>
107 1.1 haya
108 1.1 haya #include <net/bpf.h>
109 1.96 riastrad #include <sys/rndsource.h>
110 1.1 haya
111 1.77 ad #include <sys/bus.h>
112 1.3 tsutsui #include <machine/endian.h>
113 1.1 haya
114 1.1 haya #include <dev/mii/mii.h>
115 1.1 haya #include <dev/mii/miivar.h>
116 1.1 haya
117 1.1 haya #include <dev/ic/rtl81x9reg.h>
118 1.4 tsutsui #include <dev/ic/rtl81x9var.h>
119 1.1 haya
120 1.85 tsutsui static void rtk_reset(struct rtk_softc *);
121 1.85 tsutsui static void rtk_rxeof(struct rtk_softc *);
122 1.85 tsutsui static void rtk_txeof(struct rtk_softc *);
123 1.85 tsutsui static void rtk_start(struct ifnet *);
124 1.85 tsutsui static int rtk_ioctl(struct ifnet *, u_long, void *);
125 1.85 tsutsui static int rtk_init(struct ifnet *);
126 1.85 tsutsui static void rtk_stop(struct ifnet *, int);
127 1.85 tsutsui
128 1.85 tsutsui static void rtk_watchdog(struct ifnet *);
129 1.85 tsutsui
130 1.85 tsutsui static void rtk_eeprom_putbyte(struct rtk_softc *, int, int);
131 1.85 tsutsui static void rtk_mii_sync(struct rtk_softc *);
132 1.85 tsutsui static void rtk_mii_send(struct rtk_softc *, uint32_t, int);
133 1.85 tsutsui static int rtk_mii_readreg(struct rtk_softc *, struct rtk_mii_frame *);
134 1.85 tsutsui static int rtk_mii_writereg(struct rtk_softc *, struct rtk_mii_frame *);
135 1.85 tsutsui
136 1.85 tsutsui static int rtk_phy_readreg(device_t, int, int);
137 1.85 tsutsui static void rtk_phy_writereg(device_t, int, int, int);
138 1.94 matt static void rtk_phy_statchg(struct ifnet *);
139 1.85 tsutsui static void rtk_tick(void *);
140 1.49 perry
141 1.85 tsutsui static int rtk_enable(struct rtk_softc *);
142 1.85 tsutsui static void rtk_disable(struct rtk_softc *);
143 1.10 tsutsui
144 1.85 tsutsui static void rtk_list_tx_init(struct rtk_softc *);
145 1.1 haya
146 1.1 haya #define EE_SET(x) \
147 1.10 tsutsui CSR_WRITE_1(sc, RTK_EECMD, \
148 1.10 tsutsui CSR_READ_1(sc, RTK_EECMD) | (x))
149 1.1 haya
150 1.1 haya #define EE_CLR(x) \
151 1.10 tsutsui CSR_WRITE_1(sc, RTK_EECMD, \
152 1.10 tsutsui CSR_READ_1(sc, RTK_EECMD) & ~(x))
153 1.1 haya
154 1.67 tsutsui #define EE_DELAY() DELAY(100)
155 1.67 tsutsui
156 1.44 bouyer #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
157 1.44 bouyer
158 1.1 haya /*
159 1.1 haya * Send a read command and address to the EEPROM, check for ACK.
160 1.1 haya */
161 1.85 tsutsui static void
162 1.62 tsutsui rtk_eeprom_putbyte(struct rtk_softc *sc, int addr, int addr_len)
163 1.1 haya {
164 1.63 tsutsui int d, i;
165 1.1 haya
166 1.10 tsutsui d = (RTK_EECMD_READ << addr_len) | addr;
167 1.1 haya
168 1.1 haya /*
169 1.1 haya * Feed in each bit and stobe the clock.
170 1.1 haya */
171 1.23 tsutsui for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) {
172 1.23 tsutsui if (d & (1 << (i - 1))) {
173 1.10 tsutsui EE_SET(RTK_EE_DATAIN);
174 1.1 haya } else {
175 1.10 tsutsui EE_CLR(RTK_EE_DATAIN);
176 1.1 haya }
177 1.67 tsutsui EE_DELAY();
178 1.10 tsutsui EE_SET(RTK_EE_CLK);
179 1.67 tsutsui EE_DELAY();
180 1.10 tsutsui EE_CLR(RTK_EE_CLK);
181 1.67 tsutsui EE_DELAY();
182 1.1 haya }
183 1.1 haya }
184 1.1 haya
185 1.1 haya /*
186 1.1 haya * Read a word of data stored in the EEPROM at address 'addr.'
187 1.1 haya */
188 1.63 tsutsui uint16_t
189 1.62 tsutsui rtk_read_eeprom(struct rtk_softc *sc, int addr, int addr_len)
190 1.1 haya {
191 1.63 tsutsui uint16_t word;
192 1.63 tsutsui int i;
193 1.1 haya
194 1.1 haya /* Enter EEPROM access mode. */
195 1.67 tsutsui CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM);
196 1.67 tsutsui EE_DELAY();
197 1.67 tsutsui EE_SET(RTK_EE_SEL);
198 1.1 haya
199 1.1 haya /*
200 1.1 haya * Send address of word we want to read.
201 1.1 haya */
202 1.8 thorpej rtk_eeprom_putbyte(sc, addr, addr_len);
203 1.1 haya
204 1.1 haya /*
205 1.1 haya * Start reading bits from EEPROM.
206 1.1 haya */
207 1.63 tsutsui word = 0;
208 1.23 tsutsui for (i = 16; i > 0; i--) {
209 1.10 tsutsui EE_SET(RTK_EE_CLK);
210 1.67 tsutsui EE_DELAY();
211 1.10 tsutsui if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT)
212 1.23 tsutsui word |= 1 << (i - 1);
213 1.10 tsutsui EE_CLR(RTK_EE_CLK);
214 1.67 tsutsui EE_DELAY();
215 1.1 haya }
216 1.1 haya
217 1.1 haya /* Turn off EEPROM access mode. */
218 1.10 tsutsui CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
219 1.1 haya
220 1.63 tsutsui return word;
221 1.1 haya }
222 1.1 haya
223 1.1 haya /*
224 1.1 haya * MII access routines are provided for the 8129, which
225 1.1 haya * doesn't have a built-in PHY. For the 8139, we fake things
226 1.8 thorpej * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the
227 1.1 haya * direct access PHY registers.
228 1.1 haya */
229 1.1 haya #define MII_SET(x) \
230 1.23 tsutsui CSR_WRITE_1(sc, RTK_MII, \
231 1.10 tsutsui CSR_READ_1(sc, RTK_MII) | (x))
232 1.1 haya
233 1.1 haya #define MII_CLR(x) \
234 1.23 tsutsui CSR_WRITE_1(sc, RTK_MII, \
235 1.10 tsutsui CSR_READ_1(sc, RTK_MII) & ~(x))
236 1.1 haya
237 1.1 haya /*
238 1.1 haya * Sync the PHYs by setting data bit and strobing the clock 32 times.
239 1.1 haya */
240 1.85 tsutsui static void
241 1.62 tsutsui rtk_mii_sync(struct rtk_softc *sc)
242 1.1 haya {
243 1.63 tsutsui int i;
244 1.1 haya
245 1.10 tsutsui MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT);
246 1.1 haya
247 1.1 haya for (i = 0; i < 32; i++) {
248 1.10 tsutsui MII_SET(RTK_MII_CLK);
249 1.1 haya DELAY(1);
250 1.10 tsutsui MII_CLR(RTK_MII_CLK);
251 1.1 haya DELAY(1);
252 1.1 haya }
253 1.1 haya }
254 1.1 haya
255 1.1 haya /*
256 1.1 haya * Clock a series of bits through the MII.
257 1.1 haya */
258 1.85 tsutsui static void
259 1.63 tsutsui rtk_mii_send(struct rtk_softc *sc, uint32_t bits, int cnt)
260 1.1 haya {
261 1.63 tsutsui int i;
262 1.1 haya
263 1.10 tsutsui MII_CLR(RTK_MII_CLK);
264 1.1 haya
265 1.23 tsutsui for (i = cnt; i > 0; i--) {
266 1.61 tsutsui if (bits & (1 << (i - 1))) {
267 1.10 tsutsui MII_SET(RTK_MII_DATAOUT);
268 1.61 tsutsui } else {
269 1.10 tsutsui MII_CLR(RTK_MII_DATAOUT);
270 1.61 tsutsui }
271 1.1 haya DELAY(1);
272 1.10 tsutsui MII_CLR(RTK_MII_CLK);
273 1.1 haya DELAY(1);
274 1.10 tsutsui MII_SET(RTK_MII_CLK);
275 1.1 haya }
276 1.1 haya }
277 1.1 haya
278 1.1 haya /*
279 1.1 haya * Read an PHY register through the MII.
280 1.1 haya */
281 1.85 tsutsui static int
282 1.62 tsutsui rtk_mii_readreg(struct rtk_softc *sc, struct rtk_mii_frame *frame)
283 1.1 haya {
284 1.63 tsutsui int i, ack, s;
285 1.1 haya
286 1.9 thorpej s = splnet();
287 1.1 haya
288 1.1 haya /*
289 1.1 haya * Set up frame for RX.
290 1.1 haya */
291 1.10 tsutsui frame->mii_stdelim = RTK_MII_STARTDELIM;
292 1.10 tsutsui frame->mii_opcode = RTK_MII_READOP;
293 1.1 haya frame->mii_turnaround = 0;
294 1.1 haya frame->mii_data = 0;
295 1.23 tsutsui
296 1.10 tsutsui CSR_WRITE_2(sc, RTK_MII, 0);
297 1.1 haya
298 1.1 haya /*
299 1.61 tsutsui * Turn on data xmit.
300 1.1 haya */
301 1.10 tsutsui MII_SET(RTK_MII_DIR);
302 1.1 haya
303 1.8 thorpej rtk_mii_sync(sc);
304 1.1 haya
305 1.1 haya /*
306 1.1 haya * Send command/address info.
307 1.1 haya */
308 1.8 thorpej rtk_mii_send(sc, frame->mii_stdelim, 2);
309 1.8 thorpej rtk_mii_send(sc, frame->mii_opcode, 2);
310 1.8 thorpej rtk_mii_send(sc, frame->mii_phyaddr, 5);
311 1.8 thorpej rtk_mii_send(sc, frame->mii_regaddr, 5);
312 1.1 haya
313 1.1 haya /* Idle bit */
314 1.10 tsutsui MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT));
315 1.1 haya DELAY(1);
316 1.10 tsutsui MII_SET(RTK_MII_CLK);
317 1.1 haya DELAY(1);
318 1.1 haya
319 1.1 haya /* Turn off xmit. */
320 1.10 tsutsui MII_CLR(RTK_MII_DIR);
321 1.1 haya
322 1.1 haya /* Check for ack */
323 1.10 tsutsui MII_CLR(RTK_MII_CLK);
324 1.1 haya DELAY(1);
325 1.56 tsutsui ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN;
326 1.10 tsutsui MII_SET(RTK_MII_CLK);
327 1.1 haya DELAY(1);
328 1.1 haya
329 1.1 haya /*
330 1.1 haya * Now try reading data bits. If the ack failed, we still
331 1.1 haya * need to clock through 16 cycles to keep the PHY(s) in sync.
332 1.1 haya */
333 1.1 haya if (ack) {
334 1.23 tsutsui for (i = 0; i < 16; i++) {
335 1.10 tsutsui MII_CLR(RTK_MII_CLK);
336 1.1 haya DELAY(1);
337 1.10 tsutsui MII_SET(RTK_MII_CLK);
338 1.1 haya DELAY(1);
339 1.1 haya }
340 1.1 haya goto fail;
341 1.1 haya }
342 1.1 haya
343 1.23 tsutsui for (i = 16; i > 0; i--) {
344 1.10 tsutsui MII_CLR(RTK_MII_CLK);
345 1.1 haya DELAY(1);
346 1.1 haya if (!ack) {
347 1.10 tsutsui if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN)
348 1.23 tsutsui frame->mii_data |= 1 << (i - 1);
349 1.1 haya DELAY(1);
350 1.1 haya }
351 1.10 tsutsui MII_SET(RTK_MII_CLK);
352 1.1 haya DELAY(1);
353 1.1 haya }
354 1.1 haya
355 1.23 tsutsui fail:
356 1.10 tsutsui MII_CLR(RTK_MII_CLK);
357 1.1 haya DELAY(1);
358 1.10 tsutsui MII_SET(RTK_MII_CLK);
359 1.1 haya DELAY(1);
360 1.1 haya
361 1.1 haya splx(s);
362 1.1 haya
363 1.1 haya if (ack)
364 1.63 tsutsui return 1;
365 1.63 tsutsui return 0;
366 1.1 haya }
367 1.1 haya
368 1.1 haya /*
369 1.1 haya * Write to a PHY register through the MII.
370 1.1 haya */
371 1.85 tsutsui static int
372 1.62 tsutsui rtk_mii_writereg(struct rtk_softc *sc, struct rtk_mii_frame *frame)
373 1.1 haya {
374 1.63 tsutsui int s;
375 1.1 haya
376 1.9 thorpej s = splnet();
377 1.1 haya /*
378 1.1 haya * Set up frame for TX.
379 1.1 haya */
380 1.10 tsutsui frame->mii_stdelim = RTK_MII_STARTDELIM;
381 1.10 tsutsui frame->mii_opcode = RTK_MII_WRITEOP;
382 1.10 tsutsui frame->mii_turnaround = RTK_MII_TURNAROUND;
383 1.51 perry
384 1.1 haya /*
385 1.61 tsutsui * Turn on data output.
386 1.1 haya */
387 1.10 tsutsui MII_SET(RTK_MII_DIR);
388 1.1 haya
389 1.8 thorpej rtk_mii_sync(sc);
390 1.1 haya
391 1.8 thorpej rtk_mii_send(sc, frame->mii_stdelim, 2);
392 1.8 thorpej rtk_mii_send(sc, frame->mii_opcode, 2);
393 1.8 thorpej rtk_mii_send(sc, frame->mii_phyaddr, 5);
394 1.8 thorpej rtk_mii_send(sc, frame->mii_regaddr, 5);
395 1.8 thorpej rtk_mii_send(sc, frame->mii_turnaround, 2);
396 1.8 thorpej rtk_mii_send(sc, frame->mii_data, 16);
397 1.1 haya
398 1.1 haya /* Idle bit. */
399 1.10 tsutsui MII_SET(RTK_MII_CLK);
400 1.1 haya DELAY(1);
401 1.10 tsutsui MII_CLR(RTK_MII_CLK);
402 1.1 haya DELAY(1);
403 1.1 haya
404 1.1 haya /*
405 1.1 haya * Turn off xmit.
406 1.1 haya */
407 1.10 tsutsui MII_CLR(RTK_MII_DIR);
408 1.1 haya
409 1.1 haya splx(s);
410 1.1 haya
411 1.63 tsutsui return 0;
412 1.1 haya }
413 1.1 haya
414 1.85 tsutsui static int
415 1.78 uwe rtk_phy_readreg(device_t self, int phy, int reg)
416 1.1 haya {
417 1.78 uwe struct rtk_softc *sc = device_private(self);
418 1.63 tsutsui struct rtk_mii_frame frame;
419 1.63 tsutsui int rval;
420 1.63 tsutsui int rtk8139_reg;
421 1.1 haya
422 1.72 tsutsui if ((sc->sc_quirk & RTKQ_8129) == 0) {
423 1.1 haya if (phy != 7)
424 1.63 tsutsui return 0;
425 1.1 haya
426 1.63 tsutsui switch (reg) {
427 1.1 haya case MII_BMCR:
428 1.10 tsutsui rtk8139_reg = RTK_BMCR;
429 1.1 haya break;
430 1.1 haya case MII_BMSR:
431 1.10 tsutsui rtk8139_reg = RTK_BMSR;
432 1.1 haya break;
433 1.1 haya case MII_ANAR:
434 1.10 tsutsui rtk8139_reg = RTK_ANAR;
435 1.1 haya break;
436 1.12 drochner case MII_ANER:
437 1.12 drochner rtk8139_reg = RTK_ANER;
438 1.12 drochner break;
439 1.1 haya case MII_ANLPAR:
440 1.10 tsutsui rtk8139_reg = RTK_LPAR;
441 1.1 haya break;
442 1.1 haya default:
443 1.1 haya #if 0
444 1.78 uwe printf("%s: bad phy register\n", device_xname(self));
445 1.1 haya #endif
446 1.63 tsutsui return 0;
447 1.1 haya }
448 1.10 tsutsui rval = CSR_READ_2(sc, rtk8139_reg);
449 1.63 tsutsui return rval;
450 1.1 haya }
451 1.1 haya
452 1.84 tsutsui memset(&frame, 0, sizeof(frame));
453 1.1 haya
454 1.1 haya frame.mii_phyaddr = phy;
455 1.1 haya frame.mii_regaddr = reg;
456 1.8 thorpej rtk_mii_readreg(sc, &frame);
457 1.1 haya
458 1.63 tsutsui return frame.mii_data;
459 1.1 haya }
460 1.1 haya
461 1.85 tsutsui static void
462 1.78 uwe rtk_phy_writereg(device_t self, int phy, int reg, int data)
463 1.1 haya {
464 1.78 uwe struct rtk_softc *sc = device_private(self);
465 1.63 tsutsui struct rtk_mii_frame frame;
466 1.63 tsutsui int rtk8139_reg;
467 1.1 haya
468 1.72 tsutsui if ((sc->sc_quirk & RTKQ_8129) == 0) {
469 1.1 haya if (phy != 7)
470 1.1 haya return;
471 1.1 haya
472 1.63 tsutsui switch (reg) {
473 1.1 haya case MII_BMCR:
474 1.10 tsutsui rtk8139_reg = RTK_BMCR;
475 1.1 haya break;
476 1.1 haya case MII_BMSR:
477 1.10 tsutsui rtk8139_reg = RTK_BMSR;
478 1.1 haya break;
479 1.1 haya case MII_ANAR:
480 1.10 tsutsui rtk8139_reg = RTK_ANAR;
481 1.1 haya break;
482 1.12 drochner case MII_ANER:
483 1.12 drochner rtk8139_reg = RTK_ANER;
484 1.12 drochner break;
485 1.1 haya case MII_ANLPAR:
486 1.10 tsutsui rtk8139_reg = RTK_LPAR;
487 1.1 haya break;
488 1.1 haya default:
489 1.1 haya #if 0
490 1.78 uwe printf("%s: bad phy register\n", device_xname(self));
491 1.1 haya #endif
492 1.1 haya return;
493 1.1 haya }
494 1.10 tsutsui CSR_WRITE_2(sc, rtk8139_reg, data);
495 1.1 haya return;
496 1.1 haya }
497 1.1 haya
498 1.84 tsutsui memset(&frame, 0, sizeof(frame));
499 1.1 haya
500 1.1 haya frame.mii_phyaddr = phy;
501 1.1 haya frame.mii_regaddr = reg;
502 1.1 haya frame.mii_data = data;
503 1.1 haya
504 1.8 thorpej rtk_mii_writereg(sc, &frame);
505 1.1 haya }
506 1.1 haya
507 1.85 tsutsui static void
508 1.94 matt rtk_phy_statchg(struct ifnet *ifp)
509 1.1 haya {
510 1.1 haya
511 1.1 haya /* Nothing to do. */
512 1.1 haya }
513 1.1 haya
514 1.8 thorpej #define rtk_calchash(addr) \
515 1.7 thorpej (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
516 1.1 haya
517 1.1 haya /*
518 1.1 haya * Program the 64-bit multicast hash filter.
519 1.1 haya */
520 1.50 jdolecek void
521 1.62 tsutsui rtk_setmulti(struct rtk_softc *sc)
522 1.1 haya {
523 1.63 tsutsui struct ifnet *ifp;
524 1.63 tsutsui uint32_t hashes[2] = { 0, 0 };
525 1.72 tsutsui uint32_t rxfilt;
526 1.1 haya struct ether_multi *enm;
527 1.1 haya struct ether_multistep step;
528 1.63 tsutsui int h, mcnt;
529 1.1 haya
530 1.1 haya ifp = &sc->ethercom.ec_if;
531 1.1 haya
532 1.10 tsutsui rxfilt = CSR_READ_4(sc, RTK_RXCFG);
533 1.1 haya
534 1.28 enami if (ifp->if_flags & IFF_PROMISC) {
535 1.63 tsutsui allmulti:
536 1.28 enami ifp->if_flags |= IFF_ALLMULTI;
537 1.10 tsutsui rxfilt |= RTK_RXCFG_RX_MULTI;
538 1.10 tsutsui CSR_WRITE_4(sc, RTK_RXCFG, rxfilt);
539 1.10 tsutsui CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF);
540 1.10 tsutsui CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF);
541 1.1 haya return;
542 1.1 haya }
543 1.1 haya
544 1.1 haya /* first, zot all the existing hash bits */
545 1.10 tsutsui CSR_WRITE_4(sc, RTK_MAR0, 0);
546 1.10 tsutsui CSR_WRITE_4(sc, RTK_MAR4, 0);
547 1.1 haya
548 1.1 haya /* now program new ones */
549 1.1 haya ETHER_FIRST_MULTI(step, &sc->ethercom, enm);
550 1.63 tsutsui mcnt = 0;
551 1.1 haya while (enm != NULL) {
552 1.4 tsutsui if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
553 1.4 tsutsui ETHER_ADDR_LEN) != 0)
554 1.28 enami goto allmulti;
555 1.4 tsutsui
556 1.8 thorpej h = rtk_calchash(enm->enm_addrlo);
557 1.1 haya if (h < 32)
558 1.1 haya hashes[0] |= (1 << h);
559 1.1 haya else
560 1.1 haya hashes[1] |= (1 << (h - 32));
561 1.1 haya mcnt++;
562 1.1 haya ETHER_NEXT_MULTI(step, enm);
563 1.1 haya }
564 1.28 enami
565 1.28 enami ifp->if_flags &= ~IFF_ALLMULTI;
566 1.1 haya
567 1.1 haya if (mcnt)
568 1.10 tsutsui rxfilt |= RTK_RXCFG_RX_MULTI;
569 1.1 haya else
570 1.10 tsutsui rxfilt &= ~RTK_RXCFG_RX_MULTI;
571 1.1 haya
572 1.10 tsutsui CSR_WRITE_4(sc, RTK_RXCFG, rxfilt);
573 1.69 tsutsui
574 1.69 tsutsui /*
575 1.69 tsutsui * For some unfathomable reason, RealTek decided to reverse
576 1.69 tsutsui * the order of the multicast hash registers in the PCI Express
577 1.69 tsutsui * parts. This means we have to write the hash pattern in reverse
578 1.69 tsutsui * order for those devices.
579 1.69 tsutsui */
580 1.72 tsutsui if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
581 1.69 tsutsui CSR_WRITE_4(sc, RTK_MAR0, bswap32(hashes[1]));
582 1.69 tsutsui CSR_WRITE_4(sc, RTK_MAR4, bswap32(hashes[0]));
583 1.69 tsutsui } else {
584 1.69 tsutsui CSR_WRITE_4(sc, RTK_MAR0, hashes[0]);
585 1.69 tsutsui CSR_WRITE_4(sc, RTK_MAR4, hashes[1]);
586 1.69 tsutsui }
587 1.1 haya }
588 1.1 haya
589 1.50 jdolecek void
590 1.62 tsutsui rtk_reset(struct rtk_softc *sc)
591 1.1 haya {
592 1.63 tsutsui int i;
593 1.1 haya
594 1.10 tsutsui CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET);
595 1.1 haya
596 1.10 tsutsui for (i = 0; i < RTK_TIMEOUT; i++) {
597 1.1 haya DELAY(10);
598 1.23 tsutsui if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
599 1.1 haya break;
600 1.1 haya }
601 1.10 tsutsui if (i == RTK_TIMEOUT)
602 1.82 tsutsui printf("%s: reset never completed!\n",
603 1.82 tsutsui device_xname(sc->sc_dev));
604 1.1 haya }
605 1.1 haya
606 1.1 haya /*
607 1.1 haya * Attach the interface. Allocate softc structures, do ifmedia
608 1.1 haya * setup and ethernet/BPF attach.
609 1.1 haya */
610 1.1 haya void
611 1.62 tsutsui rtk_attach(struct rtk_softc *sc)
612 1.1 haya {
613 1.82 tsutsui device_t self = sc->sc_dev;
614 1.1 haya struct ifnet *ifp;
615 1.31 thorpej struct rtk_tx_desc *txd;
616 1.63 tsutsui uint16_t val;
617 1.63 tsutsui uint8_t eaddr[ETHER_ADDR_LEN];
618 1.10 tsutsui int error;
619 1.23 tsutsui int i, addr_len;
620 1.1 haya
621 1.75 ad callout_init(&sc->rtk_tick_ch, 0);
622 1.1 haya
623 1.6 tsutsui /*
624 1.6 tsutsui * Check EEPROM type 9346 or 9356.
625 1.6 tsutsui */
626 1.10 tsutsui if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129)
627 1.10 tsutsui addr_len = RTK_EEADDR_LEN1;
628 1.6 tsutsui else
629 1.10 tsutsui addr_len = RTK_EEADDR_LEN0;
630 1.6 tsutsui
631 1.6 tsutsui /*
632 1.6 tsutsui * Get station address.
633 1.6 tsutsui */
634 1.10 tsutsui val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len);
635 1.6 tsutsui eaddr[0] = val & 0xff;
636 1.6 tsutsui eaddr[1] = val >> 8;
637 1.10 tsutsui val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len);
638 1.6 tsutsui eaddr[2] = val & 0xff;
639 1.6 tsutsui eaddr[3] = val >> 8;
640 1.10 tsutsui val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len);
641 1.6 tsutsui eaddr[4] = val & 0xff;
642 1.6 tsutsui eaddr[5] = val >> 8;
643 1.6 tsutsui
644 1.1 haya if ((error = bus_dmamem_alloc(sc->sc_dmat,
645 1.23 tsutsui RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg,
646 1.1 haya BUS_DMA_NOWAIT)) != 0) {
647 1.78 uwe aprint_error_dev(self,
648 1.82 tsutsui "can't allocate recv buffer, error = %d\n", error);
649 1.10 tsutsui goto fail_0;
650 1.1 haya }
651 1.1 haya
652 1.10 tsutsui if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg,
653 1.71 christos RTK_RXBUFLEN + 16, (void **)&sc->rtk_rx_buf,
654 1.1 haya BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
655 1.78 uwe aprint_error_dev(self,
656 1.82 tsutsui "can't map recv buffer, error = %d\n", error);
657 1.10 tsutsui goto fail_1;
658 1.1 haya }
659 1.1 haya
660 1.1 haya if ((error = bus_dmamap_create(sc->sc_dmat,
661 1.23 tsutsui RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT,
662 1.1 haya &sc->recv_dmamap)) != 0) {
663 1.78 uwe aprint_error_dev(self,
664 1.82 tsutsui "can't create recv buffer DMA map, error = %d\n", error);
665 1.10 tsutsui goto fail_2;
666 1.1 haya }
667 1.1 haya
668 1.1 haya if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap,
669 1.30 thorpej sc->rtk_rx_buf, RTK_RXBUFLEN + 16,
670 1.35 thorpej NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) {
671 1.78 uwe aprint_error_dev(self,
672 1.82 tsutsui "can't load recv buffer DMA map, error = %d\n", error);
673 1.10 tsutsui goto fail_3;
674 1.1 haya }
675 1.1 haya
676 1.31 thorpej for (i = 0; i < RTK_TX_LIST_CNT; i++) {
677 1.31 thorpej txd = &sc->rtk_tx_descs[i];
678 1.4 tsutsui if ((error = bus_dmamap_create(sc->sc_dmat,
679 1.6 tsutsui MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT,
680 1.31 thorpej &txd->txd_dmamap)) != 0) {
681 1.78 uwe aprint_error_dev(self,
682 1.82 tsutsui "can't create snd buffer DMA map, error = %d\n",
683 1.82 tsutsui error);
684 1.10 tsutsui goto fail_4;
685 1.5 tsutsui }
686 1.31 thorpej txd->txd_txaddr = RTK_TXADDR0 + (i * 4);
687 1.31 thorpej txd->txd_txstat = RTK_TXSTAT0 + (i * 4);
688 1.31 thorpej }
689 1.31 thorpej SIMPLEQ_INIT(&sc->rtk_tx_free);
690 1.31 thorpej SIMPLEQ_INIT(&sc->rtk_tx_dirty);
691 1.31 thorpej
692 1.10 tsutsui /*
693 1.10 tsutsui * From this point forward, the attachment cannot fail. A failure
694 1.10 tsutsui * before this releases all resources thar may have been
695 1.10 tsutsui * allocated.
696 1.10 tsutsui */
697 1.10 tsutsui sc->sc_flags |= RTK_ATTACHED;
698 1.1 haya
699 1.6 tsutsui /* Reset the adapter. */
700 1.8 thorpej rtk_reset(sc);
701 1.6 tsutsui
702 1.78 uwe aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr));
703 1.6 tsutsui
704 1.1 haya ifp = &sc->ethercom.ec_if;
705 1.1 haya ifp->if_softc = sc;
706 1.78 uwe strcpy(ifp->if_xname, device_xname(self));
707 1.1 haya ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
708 1.8 thorpej ifp->if_ioctl = rtk_ioctl;
709 1.8 thorpej ifp->if_start = rtk_start;
710 1.8 thorpej ifp->if_watchdog = rtk_watchdog;
711 1.15 thorpej ifp->if_init = rtk_init;
712 1.15 thorpej ifp->if_stop = rtk_stop;
713 1.25 thorpej IFQ_SET_READY(&ifp->if_snd);
714 1.1 haya
715 1.1 haya /*
716 1.1 haya * Do ifmedia setup.
717 1.1 haya */
718 1.1 haya sc->mii.mii_ifp = ifp;
719 1.8 thorpej sc->mii.mii_readreg = rtk_phy_readreg;
720 1.8 thorpej sc->mii.mii_writereg = rtk_phy_writereg;
721 1.8 thorpej sc->mii.mii_statchg = rtk_phy_statchg;
722 1.81 dyoung sc->ethercom.ec_mii = &sc->mii;
723 1.81 dyoung ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange,
724 1.81 dyoung ether_mediastatus);
725 1.78 uwe mii_attach(self, &sc->mii, 0xffffffff,
726 1.23 tsutsui MII_PHY_ANY, MII_OFFSET_ANY, 0);
727 1.1 haya
728 1.1 haya /* Choose a default media. */
729 1.1 haya if (LIST_FIRST(&sc->mii.mii_phys) == NULL) {
730 1.10 tsutsui ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
731 1.1 haya ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE);
732 1.1 haya } else {
733 1.1 haya ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO);
734 1.1 haya }
735 1.1 haya
736 1.1 haya /*
737 1.1 haya * Call MI attach routines.
738 1.1 haya */
739 1.1 haya if_attach(ifp);
740 1.102 ozaki if_deferred_start_init(ifp, NULL);
741 1.1 haya ether_ifattach(ifp, eaddr);
742 1.1 haya
743 1.78 uwe rnd_attach_source(&sc->rnd_source, device_xname(self),
744 1.95 tls RND_TYPE_NET, RND_FLAG_DEFAULT);
745 1.48 dan
746 1.10 tsutsui return;
747 1.23 tsutsui fail_4:
748 1.31 thorpej for (i = 0; i < RTK_TX_LIST_CNT; i++) {
749 1.31 thorpej txd = &sc->rtk_tx_descs[i];
750 1.31 thorpej if (txd->txd_dmamap != NULL)
751 1.31 thorpej bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap);
752 1.31 thorpej }
753 1.23 tsutsui fail_3:
754 1.10 tsutsui bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap);
755 1.23 tsutsui fail_2:
756 1.84 tsutsui bus_dmamem_unmap(sc->sc_dmat, sc->rtk_rx_buf,
757 1.23 tsutsui RTK_RXBUFLEN + 16);
758 1.23 tsutsui fail_1:
759 1.10 tsutsui bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg);
760 1.23 tsutsui fail_0:
761 1.1 haya return;
762 1.1 haya }
763 1.1 haya
764 1.1 haya /*
765 1.1 haya * Initialize the transmit descriptors.
766 1.1 haya */
767 1.85 tsutsui static void
768 1.62 tsutsui rtk_list_tx_init(struct rtk_softc *sc)
769 1.1 haya {
770 1.31 thorpej struct rtk_tx_desc *txd;
771 1.31 thorpej int i;
772 1.31 thorpej
773 1.31 thorpej while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL)
774 1.41 lukem SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q);
775 1.31 thorpej while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL)
776 1.41 lukem SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q);
777 1.1 haya
778 1.10 tsutsui for (i = 0; i < RTK_TX_LIST_CNT; i++) {
779 1.31 thorpej txd = &sc->rtk_tx_descs[i];
780 1.31 thorpej CSR_WRITE_4(sc, txd->txd_txaddr, 0);
781 1.31 thorpej SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q);
782 1.1 haya }
783 1.1 haya }
784 1.1 haya
785 1.1 haya /*
786 1.10 tsutsui * rtk_activate:
787 1.10 tsutsui * Handle device activation/deactivation requests.
788 1.10 tsutsui */
789 1.10 tsutsui int
790 1.78 uwe rtk_activate(device_t self, enum devact act)
791 1.10 tsutsui {
792 1.78 uwe struct rtk_softc *sc = device_private(self);
793 1.23 tsutsui
794 1.10 tsutsui switch (act) {
795 1.10 tsutsui case DVACT_DEACTIVATE:
796 1.10 tsutsui if_deactivate(&sc->ethercom.ec_if);
797 1.87 dyoung return 0;
798 1.87 dyoung default:
799 1.87 dyoung return EOPNOTSUPP;
800 1.10 tsutsui }
801 1.10 tsutsui }
802 1.10 tsutsui
803 1.10 tsutsui /*
804 1.10 tsutsui * rtk_detach:
805 1.10 tsutsui * Detach a rtk interface.
806 1.10 tsutsui */
807 1.51 perry int
808 1.62 tsutsui rtk_detach(struct rtk_softc *sc)
809 1.10 tsutsui {
810 1.10 tsutsui struct ifnet *ifp = &sc->ethercom.ec_if;
811 1.31 thorpej struct rtk_tx_desc *txd;
812 1.10 tsutsui int i;
813 1.10 tsutsui
814 1.10 tsutsui /*
815 1.39 wiz * Succeed now if there isn't any work to do.
816 1.10 tsutsui */
817 1.10 tsutsui if ((sc->sc_flags & RTK_ATTACHED) == 0)
818 1.63 tsutsui return 0;
819 1.23 tsutsui
820 1.10 tsutsui /* Unhook our tick handler. */
821 1.10 tsutsui callout_stop(&sc->rtk_tick_ch);
822 1.10 tsutsui
823 1.10 tsutsui /* Detach all PHYs. */
824 1.10 tsutsui mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY);
825 1.10 tsutsui
826 1.10 tsutsui /* Delete all remaining media. */
827 1.10 tsutsui ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY);
828 1.10 tsutsui
829 1.48 dan rnd_detach_source(&sc->rnd_source);
830 1.48 dan
831 1.10 tsutsui ether_ifdetach(ifp);
832 1.10 tsutsui if_detach(ifp);
833 1.10 tsutsui
834 1.31 thorpej for (i = 0; i < RTK_TX_LIST_CNT; i++) {
835 1.31 thorpej txd = &sc->rtk_tx_descs[i];
836 1.31 thorpej if (txd->txd_dmamap != NULL)
837 1.31 thorpej bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap);
838 1.31 thorpej }
839 1.10 tsutsui bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap);
840 1.84 tsutsui bus_dmamem_unmap(sc->sc_dmat, sc->rtk_rx_buf,
841 1.23 tsutsui RTK_RXBUFLEN + 16);
842 1.24 tsutsui bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg);
843 1.10 tsutsui
844 1.91 jakllsch /* we don't want to run again */
845 1.91 jakllsch sc->sc_flags &= ~RTK_ATTACHED;
846 1.91 jakllsch
847 1.63 tsutsui return 0;
848 1.10 tsutsui }
849 1.10 tsutsui
850 1.10 tsutsui /*
851 1.10 tsutsui * rtk_enable:
852 1.10 tsutsui * Enable the RTL81X9 chip.
853 1.10 tsutsui */
854 1.51 perry int
855 1.62 tsutsui rtk_enable(struct rtk_softc *sc)
856 1.10 tsutsui {
857 1.23 tsutsui
858 1.10 tsutsui if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) {
859 1.10 tsutsui if ((*sc->sc_enable)(sc) != 0) {
860 1.10 tsutsui printf("%s: device enable failed\n",
861 1.82 tsutsui device_xname(sc->sc_dev));
862 1.63 tsutsui return EIO;
863 1.10 tsutsui }
864 1.10 tsutsui sc->sc_flags |= RTK_ENABLED;
865 1.10 tsutsui }
866 1.63 tsutsui return 0;
867 1.10 tsutsui }
868 1.10 tsutsui
869 1.10 tsutsui /*
870 1.10 tsutsui * rtk_disable:
871 1.10 tsutsui * Disable the RTL81X9 chip.
872 1.10 tsutsui */
873 1.51 perry void
874 1.62 tsutsui rtk_disable(struct rtk_softc *sc)
875 1.10 tsutsui {
876 1.23 tsutsui
877 1.10 tsutsui if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) {
878 1.10 tsutsui (*sc->sc_disable)(sc);
879 1.10 tsutsui sc->sc_flags &= ~RTK_ENABLED;
880 1.10 tsutsui }
881 1.10 tsutsui }
882 1.10 tsutsui
883 1.10 tsutsui /*
884 1.1 haya * A frame has been uploaded: pass the resulting mbuf chain up to
885 1.1 haya * the higher level protocols.
886 1.1 haya *
887 1.22 tsutsui * You know there's something wrong with a PCI bus-master chip design.
888 1.1 haya *
889 1.1 haya * The receive operation is badly documented in the datasheet, so I'll
890 1.1 haya * attempt to document it here. The driver provides a buffer area and
891 1.1 haya * places its base address in the RX buffer start address register.
892 1.1 haya * The chip then begins copying frames into the RX buffer. Each frame
893 1.39 wiz * is preceded by a 32-bit RX status word which specifies the length
894 1.1 haya * of the frame and certain other status bits. Each frame (starting with
895 1.1 haya * the status word) is also 32-bit aligned. The frame length is in the
896 1.1 haya * first 16 bits of the status word; the lower 15 bits correspond with
897 1.1 haya * the 'rx status register' mentioned in the datasheet.
898 1.1 haya *
899 1.1 haya * Note: to make the Alpha happy, the frame payload needs to be aligned
900 1.22 tsutsui * on a 32-bit boundary. To achieve this, we copy the data to mbuf
901 1.22 tsutsui * shifted forward 2 bytes.
902 1.1 haya */
903 1.85 tsutsui static void
904 1.62 tsutsui rtk_rxeof(struct rtk_softc *sc)
905 1.1 haya {
906 1.63 tsutsui struct mbuf *m;
907 1.63 tsutsui struct ifnet *ifp;
908 1.84 tsutsui uint8_t *rxbufpos, *dst;
909 1.63 tsutsui u_int total_len, wrap;
910 1.63 tsutsui uint32_t rxstat;
911 1.63 tsutsui uint16_t cur_rx, new_rx;
912 1.63 tsutsui uint16_t limit;
913 1.63 tsutsui uint16_t rx_bytes, max_bytes;
914 1.1 haya
915 1.1 haya ifp = &sc->ethercom.ec_if;
916 1.1 haya
917 1.10 tsutsui cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN;
918 1.1 haya
919 1.1 haya /* Do not try to read past this point. */
920 1.10 tsutsui limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN;
921 1.1 haya
922 1.1 haya if (limit < cur_rx)
923 1.10 tsutsui max_bytes = (RTK_RXBUFLEN - cur_rx) + limit;
924 1.1 haya else
925 1.1 haya max_bytes = limit - cur_rx;
926 1.63 tsutsui rx_bytes = 0;
927 1.1 haya
928 1.63 tsutsui while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) {
929 1.84 tsutsui rxbufpos = sc->rtk_rx_buf + cur_rx;
930 1.4 tsutsui bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx,
931 1.21 tsutsui RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD);
932 1.63 tsutsui rxstat = le32toh(*(uint32_t *)rxbufpos);
933 1.4 tsutsui bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx,
934 1.21 tsutsui RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD);
935 1.1 haya
936 1.1 haya /*
937 1.1 haya * Here's a totally undocumented fact for you. When the
938 1.1 haya * RealTek chip is in the process of copying a packet into
939 1.1 haya * RAM for you, the length will be 0xfff0. If you spot a
940 1.1 haya * packet header with this value, you need to stop. The
941 1.1 haya * datasheet makes absolutely no mention of this and
942 1.1 haya * RealTek should be shot for this.
943 1.1 haya */
944 1.22 tsutsui total_len = rxstat >> 16;
945 1.22 tsutsui if (total_len == RTK_RXSTAT_UNFINISHED)
946 1.1 haya break;
947 1.22 tsutsui
948 1.27 tsutsui if ((rxstat & RTK_RXSTAT_RXOK) == 0 ||
949 1.54 tsutsui total_len < ETHER_MIN_LEN ||
950 1.68 tsutsui total_len > (MCLBYTES - RTK_ETHER_ALIGN)) {
951 1.1 haya ifp->if_ierrors++;
952 1.1 haya
953 1.1 haya /*
954 1.51 perry * submitted by:[netbsd-pcmcia:00484]
955 1.1 haya * Takahiro Kambe <taca (at) sky.yamashina.kyoto.jp>
956 1.1 haya * obtain from:
957 1.1 haya * FreeBSD if_rl.c rev 1.24->1.25
958 1.1 haya *
959 1.1 haya */
960 1.1 haya #if 0
961 1.10 tsutsui if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT|
962 1.21 tsutsui RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR|
963 1.21 tsutsui RTK_RXSTAT_ALIGNERR)) {
964 1.10 tsutsui CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB);
965 1.21 tsutsui CSR_WRITE_2(sc, RTK_COMMAND,
966 1.21 tsutsui RTK_CMD_TX_ENB|RTK_CMD_RX_ENB);
967 1.10 tsutsui CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG);
968 1.10 tsutsui CSR_WRITE_4(sc, RTK_RXADDR,
969 1.21 tsutsui sc->recv_dmamap->dm_segs[0].ds_addr);
970 1.1 haya cur_rx = 0;
971 1.1 haya }
972 1.1 haya break;
973 1.1 haya #else
974 1.15 thorpej rtk_init(ifp);
975 1.1 haya return;
976 1.1 haya #endif
977 1.1 haya }
978 1.1 haya
979 1.51 perry /* No errors; receive the packet. */
980 1.21 tsutsui rx_bytes += total_len + RTK_RXSTAT_LEN;
981 1.1 haya
982 1.1 haya /*
983 1.1 haya * Avoid trying to read more bytes than we know
984 1.1 haya * the chip has prepared for us.
985 1.1 haya */
986 1.1 haya if (rx_bytes > max_bytes)
987 1.1 haya break;
988 1.1 haya
989 1.22 tsutsui /*
990 1.22 tsutsui * Skip the status word, wrapping around to the beginning
991 1.22 tsutsui * of the Rx area, if necessary.
992 1.22 tsutsui */
993 1.29 thorpej cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN;
994 1.84 tsutsui rxbufpos = sc->rtk_rx_buf + cur_rx;
995 1.4 tsutsui
996 1.22 tsutsui /*
997 1.22 tsutsui * Compute the number of bytes at which the packet
998 1.22 tsutsui * will wrap to the beginning of the ring buffer.
999 1.22 tsutsui */
1000 1.29 thorpej wrap = RTK_RXBUFLEN - cur_rx;
1001 1.1 haya
1002 1.22 tsutsui /*
1003 1.22 tsutsui * Compute where the next pending packet is.
1004 1.22 tsutsui */
1005 1.22 tsutsui if (total_len > wrap)
1006 1.22 tsutsui new_rx = total_len - wrap;
1007 1.22 tsutsui else
1008 1.22 tsutsui new_rx = cur_rx + total_len;
1009 1.22 tsutsui /* Round up to 32-bit boundary. */
1010 1.83 tsutsui new_rx = roundup2(new_rx, sizeof(uint32_t)) % RTK_RXBUFLEN;
1011 1.1 haya
1012 1.22 tsutsui /*
1013 1.54 tsutsui * The RealTek chip includes the CRC with every
1014 1.54 tsutsui * incoming packet; trim it off here.
1015 1.54 tsutsui */
1016 1.54 tsutsui total_len -= ETHER_CRC_LEN;
1017 1.54 tsutsui
1018 1.54 tsutsui /*
1019 1.22 tsutsui * Now allocate an mbuf (and possibly a cluster) to hold
1020 1.22 tsutsui * the packet. Note we offset the packet 2 bytes so that
1021 1.22 tsutsui * data after the Ethernet header will be 4-byte aligned.
1022 1.22 tsutsui */
1023 1.22 tsutsui MGETHDR(m, M_DONTWAIT, MT_DATA);
1024 1.22 tsutsui if (m == NULL) {
1025 1.22 tsutsui printf("%s: unable to allocate Rx mbuf\n",
1026 1.82 tsutsui device_xname(sc->sc_dev));
1027 1.22 tsutsui ifp->if_ierrors++;
1028 1.22 tsutsui goto next_packet;
1029 1.22 tsutsui }
1030 1.22 tsutsui if (total_len > (MHLEN - RTK_ETHER_ALIGN)) {
1031 1.22 tsutsui MCLGET(m, M_DONTWAIT);
1032 1.22 tsutsui if ((m->m_flags & M_EXT) == 0) {
1033 1.22 tsutsui printf("%s: unable to allocate Rx cluster\n",
1034 1.82 tsutsui device_xname(sc->sc_dev));
1035 1.22 tsutsui ifp->if_ierrors++;
1036 1.22 tsutsui m_freem(m);
1037 1.22 tsutsui m = NULL;
1038 1.22 tsutsui goto next_packet;
1039 1.22 tsutsui }
1040 1.22 tsutsui }
1041 1.22 tsutsui m->m_data += RTK_ETHER_ALIGN; /* for alignment */
1042 1.100 ozaki m_set_rcvif(m, ifp);
1043 1.22 tsutsui m->m_pkthdr.len = m->m_len = total_len;
1044 1.71 christos dst = mtod(m, void *);
1045 1.1 haya
1046 1.22 tsutsui /*
1047 1.22 tsutsui * If the packet wraps, copy up to the wrapping point.
1048 1.22 tsutsui */
1049 1.1 haya if (total_len > wrap) {
1050 1.22 tsutsui bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
1051 1.22 tsutsui cur_rx, wrap, BUS_DMASYNC_POSTREAD);
1052 1.22 tsutsui memcpy(dst, rxbufpos, wrap);
1053 1.22 tsutsui bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
1054 1.22 tsutsui cur_rx, wrap, BUS_DMASYNC_PREREAD);
1055 1.22 tsutsui cur_rx = 0;
1056 1.30 thorpej rxbufpos = sc->rtk_rx_buf;
1057 1.22 tsutsui total_len -= wrap;
1058 1.22 tsutsui dst += wrap;
1059 1.1 haya }
1060 1.1 haya
1061 1.1 haya /*
1062 1.22 tsutsui * ...and now the rest.
1063 1.1 haya */
1064 1.22 tsutsui bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
1065 1.22 tsutsui cur_rx, total_len, BUS_DMASYNC_POSTREAD);
1066 1.22 tsutsui memcpy(dst, rxbufpos, total_len);
1067 1.22 tsutsui bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
1068 1.22 tsutsui cur_rx, total_len, BUS_DMASYNC_PREREAD);
1069 1.22 tsutsui
1070 1.23 tsutsui next_packet:
1071 1.57 tsutsui CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN);
1072 1.22 tsutsui cur_rx = new_rx;
1073 1.1 haya
1074 1.1 haya if (m == NULL)
1075 1.1 haya continue;
1076 1.16 thorpej
1077 1.1 haya /* pass it on. */
1078 1.97 ozaki if_percpuq_enqueue(ifp->if_percpuq, m);
1079 1.1 haya }
1080 1.1 haya }
1081 1.1 haya
1082 1.1 haya /*
1083 1.1 haya * A frame was downloaded to the chip. It's safe for us to clean up
1084 1.1 haya * the list buffers.
1085 1.1 haya */
1086 1.85 tsutsui static void
1087 1.62 tsutsui rtk_txeof(struct rtk_softc *sc)
1088 1.1 haya {
1089 1.31 thorpej struct ifnet *ifp;
1090 1.31 thorpej struct rtk_tx_desc *txd;
1091 1.63 tsutsui uint32_t txstat;
1092 1.1 haya
1093 1.1 haya ifp = &sc->ethercom.ec_if;
1094 1.1 haya
1095 1.1 haya /*
1096 1.1 haya * Go through our tx list and free mbufs for those
1097 1.1 haya * frames that have been uploaded.
1098 1.1 haya */
1099 1.31 thorpej while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) {
1100 1.31 thorpej txstat = CSR_READ_4(sc, txd->txd_txstat);
1101 1.23 tsutsui if ((txstat & (RTK_TXSTAT_TX_OK|
1102 1.23 tsutsui RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0)
1103 1.1 haya break;
1104 1.1 haya
1105 1.41 lukem SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q);
1106 1.31 thorpej
1107 1.31 thorpej bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0,
1108 1.31 thorpej txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1109 1.31 thorpej bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap);
1110 1.31 thorpej m_freem(txd->txd_mbuf);
1111 1.31 thorpej txd->txd_mbuf = NULL;
1112 1.4 tsutsui
1113 1.10 tsutsui ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24;
1114 1.1 haya
1115 1.10 tsutsui if (txstat & RTK_TXSTAT_TX_OK)
1116 1.1 haya ifp->if_opackets++;
1117 1.1 haya else {
1118 1.1 haya ifp->if_oerrors++;
1119 1.36 kanaoka
1120 1.36 kanaoka /*
1121 1.36 kanaoka * Increase Early TX threshold if underrun occurred.
1122 1.36 kanaoka * Increase step 64 bytes.
1123 1.36 kanaoka */
1124 1.36 kanaoka if (txstat & RTK_TXSTAT_TX_UNDERRUN) {
1125 1.52 xtraeme #ifdef DEBUG
1126 1.36 kanaoka printf("%s: transmit underrun;",
1127 1.82 tsutsui device_xname(sc->sc_dev));
1128 1.52 xtraeme #endif
1129 1.65 tsutsui if (sc->sc_txthresh < RTK_TXTH_MAX) {
1130 1.36 kanaoka sc->sc_txthresh += 2;
1131 1.52 xtraeme #ifdef DEBUG
1132 1.36 kanaoka printf(" new threshold: %d bytes",
1133 1.36 kanaoka sc->sc_txthresh * 32);
1134 1.52 xtraeme #endif
1135 1.36 kanaoka }
1136 1.86 tsutsui #ifdef DEBUG
1137 1.36 kanaoka printf("\n");
1138 1.86 tsutsui #endif
1139 1.36 kanaoka }
1140 1.23 tsutsui if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN))
1141 1.10 tsutsui CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG);
1142 1.1 haya }
1143 1.31 thorpej SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q);
1144 1.1 haya ifp->if_flags &= ~IFF_OACTIVE;
1145 1.31 thorpej }
1146 1.55 tsutsui
1147 1.55 tsutsui /* Clear the timeout timer if there is no pending packet. */
1148 1.58 tsutsui if (SIMPLEQ_EMPTY(&sc->rtk_tx_dirty))
1149 1.55 tsutsui ifp->if_timer = 0;
1150 1.55 tsutsui
1151 1.1 haya }
1152 1.1 haya
1153 1.50 jdolecek int
1154 1.62 tsutsui rtk_intr(void *arg)
1155 1.1 haya {
1156 1.63 tsutsui struct rtk_softc *sc;
1157 1.63 tsutsui struct ifnet *ifp;
1158 1.63 tsutsui uint16_t status;
1159 1.63 tsutsui int handled;
1160 1.1 haya
1161 1.1 haya sc = arg;
1162 1.1 haya ifp = &sc->ethercom.ec_if;
1163 1.1 haya
1164 1.82 tsutsui if (!device_has_power(sc->sc_dev))
1165 1.80 joerg return 0;
1166 1.80 joerg
1167 1.1 haya /* Disable interrupts. */
1168 1.10 tsutsui CSR_WRITE_2(sc, RTK_IMR, 0x0000);
1169 1.1 haya
1170 1.63 tsutsui handled = 0;
1171 1.1 haya for (;;) {
1172 1.1 haya
1173 1.10 tsutsui status = CSR_READ_2(sc, RTK_ISR);
1174 1.74 joerg
1175 1.74 joerg if (status == 0xffff)
1176 1.74 joerg break; /* Card is gone... */
1177 1.74 joerg
1178 1.1 haya if (status)
1179 1.10 tsutsui CSR_WRITE_2(sc, RTK_ISR, status);
1180 1.1 haya
1181 1.10 tsutsui if ((status & RTK_INTRS) == 0)
1182 1.1 haya break;
1183 1.1 haya
1184 1.59 tsutsui handled = 1;
1185 1.59 tsutsui
1186 1.10 tsutsui if (status & RTK_ISR_RX_OK)
1187 1.8 thorpej rtk_rxeof(sc);
1188 1.1 haya
1189 1.10 tsutsui if (status & RTK_ISR_RX_ERR)
1190 1.8 thorpej rtk_rxeof(sc);
1191 1.1 haya
1192 1.23 tsutsui if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR))
1193 1.8 thorpej rtk_txeof(sc);
1194 1.1 haya
1195 1.10 tsutsui if (status & RTK_ISR_SYSTEM_ERR) {
1196 1.8 thorpej rtk_reset(sc);
1197 1.15 thorpej rtk_init(ifp);
1198 1.1 haya }
1199 1.1 haya }
1200 1.1 haya
1201 1.1 haya /* Re-enable interrupts. */
1202 1.10 tsutsui CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
1203 1.1 haya
1204 1.102 ozaki if_schedule_deferred_start(ifp);
1205 1.1 haya
1206 1.93 tls rnd_add_uint32(&sc->rnd_source, status);
1207 1.48 dan
1208 1.63 tsutsui return handled;
1209 1.1 haya }
1210 1.1 haya
1211 1.1 haya /*
1212 1.1 haya * Main transmit routine.
1213 1.1 haya */
1214 1.1 haya
1215 1.85 tsutsui static void
1216 1.62 tsutsui rtk_start(struct ifnet *ifp)
1217 1.1 haya {
1218 1.31 thorpej struct rtk_softc *sc;
1219 1.31 thorpej struct rtk_tx_desc *txd;
1220 1.63 tsutsui struct mbuf *m_head, *m_new;
1221 1.31 thorpej int error, len;
1222 1.1 haya
1223 1.1 haya sc = ifp->if_softc;
1224 1.1 haya
1225 1.31 thorpej while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) {
1226 1.25 thorpej IFQ_POLL(&ifp->if_snd, m_head);
1227 1.1 haya if (m_head == NULL)
1228 1.1 haya break;
1229 1.26 thorpej m_new = NULL;
1230 1.1 haya
1231 1.4 tsutsui /*
1232 1.4 tsutsui * Load the DMA map. If this fails, the packet didn't
1233 1.4 tsutsui * fit in one DMA segment, and we need to copy. Note,
1234 1.4 tsutsui * the packet must also be aligned.
1235 1.44 bouyer * if the packet is too small, copy it too, so we're sure
1236 1.89 snj * so have enough room for the pad buffer.
1237 1.4 tsutsui */
1238 1.38 mrg if ((mtod(m_head, uintptr_t) & 3) != 0 ||
1239 1.44 bouyer m_head->m_pkthdr.len < ETHER_PAD_LEN ||
1240 1.31 thorpej bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap,
1241 1.35 thorpej m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) {
1242 1.4 tsutsui MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1243 1.4 tsutsui if (m_new == NULL) {
1244 1.4 tsutsui printf("%s: unable to allocate Tx mbuf\n",
1245 1.82 tsutsui device_xname(sc->sc_dev));
1246 1.4 tsutsui break;
1247 1.4 tsutsui }
1248 1.4 tsutsui if (m_head->m_pkthdr.len > MHLEN) {
1249 1.4 tsutsui MCLGET(m_new, M_DONTWAIT);
1250 1.4 tsutsui if ((m_new->m_flags & M_EXT) == 0) {
1251 1.4 tsutsui printf("%s: unable to allocate Tx "
1252 1.82 tsutsui "cluster\n",
1253 1.82 tsutsui device_xname(sc->sc_dev));
1254 1.4 tsutsui m_freem(m_new);
1255 1.4 tsutsui break;
1256 1.4 tsutsui }
1257 1.4 tsutsui }
1258 1.4 tsutsui m_copydata(m_head, 0, m_head->m_pkthdr.len,
1259 1.71 christos mtod(m_new, void *));
1260 1.4 tsutsui m_new->m_pkthdr.len = m_new->m_len =
1261 1.4 tsutsui m_head->m_pkthdr.len;
1262 1.44 bouyer if (m_head->m_pkthdr.len < ETHER_PAD_LEN) {
1263 1.44 bouyer memset(
1264 1.71 christos mtod(m_new, char *) + m_head->m_pkthdr.len,
1265 1.44 bouyer 0, ETHER_PAD_LEN - m_head->m_pkthdr.len);
1266 1.44 bouyer m_new->m_pkthdr.len = m_new->m_len =
1267 1.44 bouyer ETHER_PAD_LEN;
1268 1.44 bouyer }
1269 1.4 tsutsui error = bus_dmamap_load_mbuf(sc->sc_dmat,
1270 1.35 thorpej txd->txd_dmamap, m_new,
1271 1.35 thorpej BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1272 1.4 tsutsui if (error) {
1273 1.4 tsutsui printf("%s: unable to load Tx buffer, "
1274 1.82 tsutsui "error = %d\n",
1275 1.82 tsutsui device_xname(sc->sc_dev), error);
1276 1.4 tsutsui break;
1277 1.4 tsutsui }
1278 1.4 tsutsui }
1279 1.25 thorpej IFQ_DEQUEUE(&ifp->if_snd, m_head);
1280 1.44 bouyer /*
1281 1.44 bouyer * If there's a BPF listener, bounce a copy of this frame
1282 1.44 bouyer * to him.
1283 1.44 bouyer */
1284 1.103 msaitoh bpf_mtap(ifp, m_head, BPF_D_OUT);
1285 1.26 thorpej if (m_new != NULL) {
1286 1.26 thorpej m_freem(m_head);
1287 1.26 thorpej m_head = m_new;
1288 1.26 thorpej }
1289 1.31 thorpej txd->txd_mbuf = m_head;
1290 1.4 tsutsui
1291 1.41 lukem SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q);
1292 1.31 thorpej SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q);
1293 1.1 haya
1294 1.1 haya /*
1295 1.1 haya * Transmit the frame.
1296 1.61 tsutsui */
1297 1.4 tsutsui bus_dmamap_sync(sc->sc_dmat,
1298 1.31 thorpej txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize,
1299 1.4 tsutsui BUS_DMASYNC_PREWRITE);
1300 1.4 tsutsui
1301 1.31 thorpej len = txd->txd_dmamap->dm_segs[0].ds_len;
1302 1.4 tsutsui
1303 1.31 thorpej CSR_WRITE_4(sc, txd->txd_txaddr,
1304 1.31 thorpej txd->txd_dmamap->dm_segs[0].ds_addr);
1305 1.65 tsutsui CSR_WRITE_4(sc, txd->txd_txstat,
1306 1.65 tsutsui RTK_TXSTAT_THRESH(sc->sc_txthresh) | len);
1307 1.60 tsutsui
1308 1.60 tsutsui /*
1309 1.60 tsutsui * Set a timeout in case the chip goes out to lunch.
1310 1.60 tsutsui */
1311 1.60 tsutsui ifp->if_timer = 5;
1312 1.1 haya }
1313 1.1 haya
1314 1.1 haya /*
1315 1.1 haya * We broke out of the loop because all our TX slots are
1316 1.1 haya * full. Mark the NIC as busy until it drains some of the
1317 1.1 haya * packets from the queue.
1318 1.1 haya */
1319 1.41 lukem if (SIMPLEQ_EMPTY(&sc->rtk_tx_free))
1320 1.1 haya ifp->if_flags |= IFF_OACTIVE;
1321 1.1 haya }
1322 1.1 haya
1323 1.85 tsutsui static int
1324 1.62 tsutsui rtk_init(struct ifnet *ifp)
1325 1.1 haya {
1326 1.63 tsutsui struct rtk_softc *sc = ifp->if_softc;
1327 1.63 tsutsui int error, i;
1328 1.63 tsutsui uint32_t rxcfg;
1329 1.1 haya
1330 1.15 thorpej if ((error = rtk_enable(sc)) != 0)
1331 1.15 thorpej goto out;
1332 1.1 haya
1333 1.1 haya /*
1334 1.15 thorpej * Cancel pending I/O.
1335 1.1 haya */
1336 1.15 thorpej rtk_stop(ifp, 0);
1337 1.1 haya
1338 1.1 haya /* Init our MAC address */
1339 1.1 haya for (i = 0; i < ETHER_ADDR_LEN; i++) {
1340 1.76 dyoung CSR_WRITE_1(sc, RTK_IDR0 + i, CLLADDR(ifp->if_sadl)[i]);
1341 1.1 haya }
1342 1.1 haya
1343 1.1 haya /* Init the RX buffer pointer register. */
1344 1.4 tsutsui bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0,
1345 1.4 tsutsui sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1346 1.10 tsutsui CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr);
1347 1.1 haya
1348 1.1 haya /* Init TX descriptors. */
1349 1.8 thorpej rtk_list_tx_init(sc);
1350 1.1 haya
1351 1.36 kanaoka /* Init Early TX threshold. */
1352 1.65 tsutsui sc->sc_txthresh = RTK_TXTH_256;
1353 1.1 haya /*
1354 1.1 haya * Enable transmit and receive.
1355 1.1 haya */
1356 1.10 tsutsui CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB);
1357 1.1 haya
1358 1.1 haya /*
1359 1.1 haya * Set the initial TX and RX configuration.
1360 1.1 haya */
1361 1.10 tsutsui CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG);
1362 1.10 tsutsui CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG);
1363 1.1 haya
1364 1.1 haya /* Set the individual bit to receive frames for this host only. */
1365 1.10 tsutsui rxcfg = CSR_READ_4(sc, RTK_RXCFG);
1366 1.10 tsutsui rxcfg |= RTK_RXCFG_RX_INDIV;
1367 1.1 haya
1368 1.1 haya /* If we want promiscuous mode, set the allframes bit. */
1369 1.1 haya if (ifp->if_flags & IFF_PROMISC) {
1370 1.10 tsutsui rxcfg |= RTK_RXCFG_RX_ALLPHYS;
1371 1.10 tsutsui CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1372 1.1 haya } else {
1373 1.10 tsutsui rxcfg &= ~RTK_RXCFG_RX_ALLPHYS;
1374 1.10 tsutsui CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1375 1.1 haya }
1376 1.1 haya
1377 1.1 haya /*
1378 1.1 haya * Set capture broadcast bit to capture broadcast frames.
1379 1.1 haya */
1380 1.1 haya if (ifp->if_flags & IFF_BROADCAST) {
1381 1.10 tsutsui rxcfg |= RTK_RXCFG_RX_BROAD;
1382 1.10 tsutsui CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1383 1.1 haya } else {
1384 1.10 tsutsui rxcfg &= ~RTK_RXCFG_RX_BROAD;
1385 1.10 tsutsui CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1386 1.1 haya }
1387 1.1 haya
1388 1.1 haya /*
1389 1.1 haya * Program the multicast filter, if necessary.
1390 1.1 haya */
1391 1.8 thorpej rtk_setmulti(sc);
1392 1.1 haya
1393 1.1 haya /*
1394 1.1 haya * Enable interrupts.
1395 1.1 haya */
1396 1.10 tsutsui CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
1397 1.1 haya
1398 1.1 haya /* Start RX/TX process. */
1399 1.10 tsutsui CSR_WRITE_4(sc, RTK_MISSEDPKT, 0);
1400 1.1 haya
1401 1.1 haya /* Enable receiver and transmitter. */
1402 1.10 tsutsui CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB);
1403 1.1 haya
1404 1.10 tsutsui CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX);
1405 1.1 haya
1406 1.1 haya /*
1407 1.1 haya * Set current media.
1408 1.1 haya */
1409 1.81 dyoung if ((error = ether_mediachange(ifp)) != 0)
1410 1.81 dyoung goto out;
1411 1.1 haya
1412 1.1 haya ifp->if_flags |= IFF_RUNNING;
1413 1.1 haya ifp->if_flags &= ~IFF_OACTIVE;
1414 1.1 haya
1415 1.15 thorpej callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc);
1416 1.1 haya
1417 1.15 thorpej out:
1418 1.15 thorpej if (error) {
1419 1.15 thorpej ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1420 1.15 thorpej ifp->if_timer = 0;
1421 1.82 tsutsui printf("%s: interface not running\n", device_xname(sc->sc_dev));
1422 1.15 thorpej }
1423 1.63 tsutsui return error;
1424 1.1 haya }
1425 1.1 haya
1426 1.85 tsutsui static int
1427 1.71 christos rtk_ioctl(struct ifnet *ifp, u_long command, void *data)
1428 1.1 haya {
1429 1.63 tsutsui struct rtk_softc *sc = ifp->if_softc;
1430 1.63 tsutsui int s, error;
1431 1.1 haya
1432 1.9 thorpej s = splnet();
1433 1.81 dyoung error = ether_ioctl(ifp, command, data);
1434 1.81 dyoung if (error == ENETRESET) {
1435 1.81 dyoung if (ifp->if_flags & IFF_RUNNING) {
1436 1.81 dyoung /*
1437 1.81 dyoung * Multicast list has changed. Set the
1438 1.81 dyoung * hardware filter accordingly.
1439 1.81 dyoung */
1440 1.81 dyoung rtk_setmulti(sc);
1441 1.15 thorpej }
1442 1.81 dyoung error = 0;
1443 1.1 haya }
1444 1.12 drochner splx(s);
1445 1.1 haya
1446 1.63 tsutsui return error;
1447 1.1 haya }
1448 1.1 haya
1449 1.85 tsutsui static void
1450 1.62 tsutsui rtk_watchdog(struct ifnet *ifp)
1451 1.1 haya {
1452 1.63 tsutsui struct rtk_softc *sc;
1453 1.1 haya
1454 1.1 haya sc = ifp->if_softc;
1455 1.1 haya
1456 1.82 tsutsui printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
1457 1.1 haya ifp->if_oerrors++;
1458 1.8 thorpej rtk_txeof(sc);
1459 1.8 thorpej rtk_rxeof(sc);
1460 1.15 thorpej rtk_init(ifp);
1461 1.1 haya }
1462 1.1 haya
1463 1.1 haya /*
1464 1.1 haya * Stop the adapter and free any mbufs allocated to the
1465 1.1 haya * RX and TX lists.
1466 1.1 haya */
1467 1.85 tsutsui static void
1468 1.62 tsutsui rtk_stop(struct ifnet *ifp, int disable)
1469 1.1 haya {
1470 1.15 thorpej struct rtk_softc *sc = ifp->if_softc;
1471 1.31 thorpej struct rtk_tx_desc *txd;
1472 1.1 haya
1473 1.8 thorpej callout_stop(&sc->rtk_tick_ch);
1474 1.1 haya
1475 1.1 haya mii_down(&sc->mii);
1476 1.1 haya
1477 1.10 tsutsui CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
1478 1.10 tsutsui CSR_WRITE_2(sc, RTK_IMR, 0x0000);
1479 1.1 haya
1480 1.1 haya /*
1481 1.1 haya * Free the TX list buffers.
1482 1.1 haya */
1483 1.31 thorpej while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) {
1484 1.41 lukem SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q);
1485 1.31 thorpej bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap);
1486 1.31 thorpej m_freem(txd->txd_mbuf);
1487 1.31 thorpej txd->txd_mbuf = NULL;
1488 1.31 thorpej CSR_WRITE_4(sc, txd->txd_txaddr, 0);
1489 1.1 haya }
1490 1.1 haya
1491 1.15 thorpej if (disable)
1492 1.15 thorpej rtk_disable(sc);
1493 1.15 thorpej
1494 1.1 haya ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1495 1.15 thorpej ifp->if_timer = 0;
1496 1.1 haya }
1497 1.1 haya
1498 1.85 tsutsui static void
1499 1.62 tsutsui rtk_tick(void *arg)
1500 1.1 haya {
1501 1.8 thorpej struct rtk_softc *sc = arg;
1502 1.63 tsutsui int s;
1503 1.1 haya
1504 1.63 tsutsui s = splnet();
1505 1.1 haya mii_tick(&sc->mii);
1506 1.1 haya splx(s);
1507 1.1 haya
1508 1.8 thorpej callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc);
1509 1.1 haya }
1510