rtl81x9.c revision 1.12
1 /* $NetBSD: rtl81x9.c,v 1.12 2000/09/01 15:07:23 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include "opt_inet.h" 89 #include "opt_ns.h" 90 #include "bpfilter.h" 91 #include "rnd.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/callout.h> 96 #include <sys/device.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/if_inarp.h> 111 #endif 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #if NBPFILTER > 0 118 #include <net/bpf.h> 119 #endif 120 #if NRND > 0 121 #include <sys/rnd.h> 122 #endif 123 124 #include <machine/bus.h> 125 #include <machine/endian.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 130 #include <dev/ic/rtl81x9reg.h> 131 #include <dev/ic/rtl81x9var.h> 132 133 #if defined DEBUG 134 #define STATIC 135 #else 136 #define STATIC static 137 #endif 138 139 STATIC void rtk_reset __P((struct rtk_softc *)); 140 STATIC void rtk_rxeof __P((struct rtk_softc *)); 141 STATIC void rtk_txeof __P((struct rtk_softc *)); 142 STATIC void rtk_start __P((struct ifnet *)); 143 STATIC int rtk_ioctl __P((struct ifnet *, u_long, caddr_t)); 144 STATIC void rtk_init __P((void *)); 145 STATIC void rtk_stop __P((struct rtk_softc *)); 146 STATIC void rtk_watchdog __P((struct ifnet *)); 147 STATIC void rtk_shutdown __P((void *)); 148 STATIC int rtk_ifmedia_upd __P((struct ifnet *)); 149 STATIC void rtk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 150 151 STATIC u_int16_t rtk_read_eeprom __P((struct rtk_softc *, int, int)); 152 STATIC void rtk_eeprom_putbyte __P((struct rtk_softc *, int, int)); 153 STATIC void rtk_mii_sync __P((struct rtk_softc *)); 154 STATIC void rtk_mii_send __P((struct rtk_softc *, u_int32_t, int)); 155 STATIC int rtk_mii_readreg __P((struct rtk_softc *, struct rtk_mii_frame *)); 156 STATIC int rtk_mii_writereg __P((struct rtk_softc *, struct rtk_mii_frame *)); 157 158 STATIC int rtk_phy_readreg __P((struct device *, int, int)); 159 STATIC void rtk_phy_writereg __P((struct device *, int, int, int)); 160 STATIC void rtk_phy_statchg __P((struct device *)); 161 STATIC void rtk_tick __P((void *)); 162 163 STATIC int rtk_enable __P((struct rtk_softc *)); 164 STATIC void rtk_disable __P((struct rtk_softc *)); 165 STATIC void rtk_power __P((int, void *)); 166 167 STATIC void rtk_setmulti __P((struct rtk_softc *)); 168 STATIC int rtk_list_tx_init __P((struct rtk_softc *)); 169 170 STATIC int rtk_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 171 172 173 #define EE_SET(x) \ 174 CSR_WRITE_1(sc, RTK_EECMD, \ 175 CSR_READ_1(sc, RTK_EECMD) | (x)) 176 177 #define EE_CLR(x) \ 178 CSR_WRITE_1(sc, RTK_EECMD, \ 179 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 180 181 /* 182 * Send a read command and address to the EEPROM, check for ACK. 183 */ 184 STATIC void rtk_eeprom_putbyte(sc, addr, addr_len) 185 struct rtk_softc *sc; 186 int addr, addr_len; 187 { 188 int d, i; 189 190 d = (RTK_EECMD_READ << addr_len) | addr; 191 192 /* 193 * Feed in each bit and stobe the clock. 194 */ 195 for (i = RTK_EECMD_LEN + addr_len - 1; i >= 0; i--) { 196 if (d & (1 << i)) { 197 EE_SET(RTK_EE_DATAIN); 198 } else { 199 EE_CLR(RTK_EE_DATAIN); 200 } 201 DELAY(100); 202 EE_SET(RTK_EE_CLK); 203 DELAY(150); 204 EE_CLR(RTK_EE_CLK); 205 DELAY(100); 206 } 207 } 208 209 /* 210 * Read a word of data stored in the EEPROM at address 'addr.' 211 */ 212 u_int16_t rtk_read_eeprom(sc, addr, addr_len) 213 struct rtk_softc *sc; 214 int addr, addr_len; 215 { 216 u_int16_t word = 0; 217 int i; 218 219 /* Enter EEPROM access mode. */ 220 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 221 222 /* 223 * Send address of word we want to read. 224 */ 225 rtk_eeprom_putbyte(sc, addr, addr_len); 226 227 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 228 229 /* 230 * Start reading bits from EEPROM. 231 */ 232 for (i = 15; i >= 0; i--) { 233 EE_SET(RTK_EE_CLK); 234 DELAY(100); 235 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 236 word |= (1 << i); 237 EE_CLR(RTK_EE_CLK); 238 DELAY(100); 239 } 240 241 /* Turn off EEPROM access mode. */ 242 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 243 244 return (word); 245 } 246 247 /* 248 * MII access routines are provided for the 8129, which 249 * doesn't have a built-in PHY. For the 8139, we fake things 250 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 251 * direct access PHY registers. 252 */ 253 #define MII_SET(x) \ 254 CSR_WRITE_1(sc, RTK_MII, \ 255 CSR_READ_1(sc, RTK_MII) | (x)) 256 257 #define MII_CLR(x) \ 258 CSR_WRITE_1(sc, RTK_MII, \ 259 CSR_READ_1(sc, RTK_MII) & ~(x)) 260 261 /* 262 * Sync the PHYs by setting data bit and strobing the clock 32 times. 263 */ 264 STATIC void rtk_mii_sync(sc) 265 struct rtk_softc *sc; 266 { 267 int i; 268 269 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 270 271 for (i = 0; i < 32; i++) { 272 MII_SET(RTK_MII_CLK); 273 DELAY(1); 274 MII_CLR(RTK_MII_CLK); 275 DELAY(1); 276 } 277 278 return; 279 } 280 281 /* 282 * Clock a series of bits through the MII. 283 */ 284 STATIC void rtk_mii_send(sc, bits, cnt) 285 struct rtk_softc *sc; 286 u_int32_t bits; 287 int cnt; 288 { 289 int i; 290 291 MII_CLR(RTK_MII_CLK); 292 293 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 294 if (bits & i) { 295 MII_SET(RTK_MII_DATAOUT); 296 } else { 297 MII_CLR(RTK_MII_DATAOUT); 298 } 299 DELAY(1); 300 MII_CLR(RTK_MII_CLK); 301 DELAY(1); 302 MII_SET(RTK_MII_CLK); 303 } 304 } 305 306 /* 307 * Read an PHY register through the MII. 308 */ 309 STATIC int rtk_mii_readreg(sc, frame) 310 struct rtk_softc *sc; 311 struct rtk_mii_frame *frame; 312 313 { 314 int i, ack, s; 315 316 s = splnet(); 317 318 /* 319 * Set up frame for RX. 320 */ 321 frame->mii_stdelim = RTK_MII_STARTDELIM; 322 frame->mii_opcode = RTK_MII_READOP; 323 frame->mii_turnaround = 0; 324 frame->mii_data = 0; 325 326 CSR_WRITE_2(sc, RTK_MII, 0); 327 328 /* 329 * Turn on data xmit. 330 */ 331 MII_SET(RTK_MII_DIR); 332 333 rtk_mii_sync(sc); 334 335 /* 336 * Send command/address info. 337 */ 338 rtk_mii_send(sc, frame->mii_stdelim, 2); 339 rtk_mii_send(sc, frame->mii_opcode, 2); 340 rtk_mii_send(sc, frame->mii_phyaddr, 5); 341 rtk_mii_send(sc, frame->mii_regaddr, 5); 342 343 /* Idle bit */ 344 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 345 DELAY(1); 346 MII_SET(RTK_MII_CLK); 347 DELAY(1); 348 349 /* Turn off xmit. */ 350 MII_CLR(RTK_MII_DIR); 351 352 /* Check for ack */ 353 MII_CLR(RTK_MII_CLK); 354 DELAY(1); 355 MII_SET(RTK_MII_CLK); 356 DELAY(1); 357 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 358 359 /* 360 * Now try reading data bits. If the ack failed, we still 361 * need to clock through 16 cycles to keep the PHY(s) in sync. 362 */ 363 if (ack) { 364 for(i = 0; i < 16; i++) { 365 MII_CLR(RTK_MII_CLK); 366 DELAY(1); 367 MII_SET(RTK_MII_CLK); 368 DELAY(1); 369 } 370 goto fail; 371 } 372 373 for (i = 0x8000; i; i >>= 1) { 374 MII_CLR(RTK_MII_CLK); 375 DELAY(1); 376 if (!ack) { 377 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 378 frame->mii_data |= i; 379 DELAY(1); 380 } 381 MII_SET(RTK_MII_CLK); 382 DELAY(1); 383 } 384 385 fail: 386 387 MII_CLR(RTK_MII_CLK); 388 DELAY(1); 389 MII_SET(RTK_MII_CLK); 390 DELAY(1); 391 392 splx(s); 393 394 if (ack) 395 return(1); 396 return(0); 397 } 398 399 /* 400 * Write to a PHY register through the MII. 401 */ 402 STATIC int rtk_mii_writereg(sc, frame) 403 struct rtk_softc *sc; 404 struct rtk_mii_frame *frame; 405 406 { 407 int s; 408 409 s = splnet(); 410 /* 411 * Set up frame for TX. 412 */ 413 414 frame->mii_stdelim = RTK_MII_STARTDELIM; 415 frame->mii_opcode = RTK_MII_WRITEOP; 416 frame->mii_turnaround = RTK_MII_TURNAROUND; 417 418 /* 419 * Turn on data output. 420 */ 421 MII_SET(RTK_MII_DIR); 422 423 rtk_mii_sync(sc); 424 425 rtk_mii_send(sc, frame->mii_stdelim, 2); 426 rtk_mii_send(sc, frame->mii_opcode, 2); 427 rtk_mii_send(sc, frame->mii_phyaddr, 5); 428 rtk_mii_send(sc, frame->mii_regaddr, 5); 429 rtk_mii_send(sc, frame->mii_turnaround, 2); 430 rtk_mii_send(sc, frame->mii_data, 16); 431 432 /* Idle bit. */ 433 MII_SET(RTK_MII_CLK); 434 DELAY(1); 435 MII_CLR(RTK_MII_CLK); 436 DELAY(1); 437 438 /* 439 * Turn off xmit. 440 */ 441 MII_CLR(RTK_MII_DIR); 442 443 splx(s); 444 445 return(0); 446 } 447 448 STATIC int rtk_phy_readreg(self, phy, reg) 449 struct device *self; 450 int phy, reg; 451 { 452 struct rtk_softc *sc = (void *)self; 453 struct rtk_mii_frame frame; 454 u_int16_t rval = 0; 455 u_int16_t rtk8139_reg = 0; 456 457 if (sc->rtk_type == RTK_8139) { 458 if (phy != 7) 459 return (0); 460 461 switch(reg) { 462 case MII_BMCR: 463 rtk8139_reg = RTK_BMCR; 464 break; 465 case MII_BMSR: 466 rtk8139_reg = RTK_BMSR; 467 break; 468 case MII_ANAR: 469 rtk8139_reg = RTK_ANAR; 470 break; 471 case MII_ANER: 472 rtk8139_reg = RTK_ANER; 473 break; 474 case MII_ANLPAR: 475 rtk8139_reg = RTK_LPAR; 476 break; 477 default: 478 #if 0 479 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 480 #endif 481 return(0); 482 } 483 rval = CSR_READ_2(sc, rtk8139_reg); 484 return(rval); 485 } 486 487 bzero((char *)&frame, sizeof(frame)); 488 489 frame.mii_phyaddr = phy; 490 frame.mii_regaddr = reg; 491 rtk_mii_readreg(sc, &frame); 492 493 return(frame.mii_data); 494 } 495 496 STATIC void rtk_phy_writereg(self, phy, reg, data) 497 struct device *self; 498 int phy, reg; 499 int data; 500 { 501 struct rtk_softc *sc = (void *)self; 502 struct rtk_mii_frame frame; 503 u_int16_t rtk8139_reg = 0; 504 505 if (sc->rtk_type == RTK_8139) { 506 if (phy != 7) 507 return; 508 509 switch(reg) { 510 case MII_BMCR: 511 rtk8139_reg = RTK_BMCR; 512 break; 513 case MII_BMSR: 514 rtk8139_reg = RTK_BMSR; 515 break; 516 case MII_ANAR: 517 rtk8139_reg = RTK_ANAR; 518 break; 519 case MII_ANER: 520 rtk8139_reg = RTK_ANER; 521 break; 522 case MII_ANLPAR: 523 rtk8139_reg = RTK_LPAR; 524 break; 525 default: 526 #if 0 527 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 528 #endif 529 return; 530 } 531 CSR_WRITE_2(sc, rtk8139_reg, data); 532 return; 533 } 534 535 bzero((char *)&frame, sizeof(frame)); 536 537 frame.mii_phyaddr = phy; 538 frame.mii_regaddr = reg; 539 frame.mii_data = data; 540 541 rtk_mii_writereg(sc, &frame); 542 543 return; 544 } 545 546 STATIC void 547 rtk_phy_statchg(v) 548 struct device *v; 549 { 550 551 /* Nothing to do. */ 552 } 553 554 #define rtk_calchash(addr) \ 555 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 556 557 /* 558 * Program the 64-bit multicast hash filter. 559 */ 560 STATIC void rtk_setmulti(sc) 561 struct rtk_softc *sc; 562 { 563 struct ifnet *ifp; 564 int h = 0; 565 u_int32_t hashes[2] = { 0, 0 }; 566 u_int32_t rxfilt; 567 int mcnt = 0; 568 struct ether_multi *enm; 569 struct ether_multistep step; 570 571 ifp = &sc->ethercom.ec_if; 572 573 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 574 575 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 576 rxfilt |= RTK_RXCFG_RX_MULTI; 577 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 578 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 579 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 580 return; 581 } 582 583 /* first, zot all the existing hash bits */ 584 CSR_WRITE_4(sc, RTK_MAR0, 0); 585 CSR_WRITE_4(sc, RTK_MAR4, 0); 586 587 /* now program new ones */ 588 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 589 while (enm != NULL) { 590 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 591 ETHER_ADDR_LEN) != 0) 592 continue; 593 594 h = rtk_calchash(enm->enm_addrlo); 595 if (h < 32) 596 hashes[0] |= (1 << h); 597 else 598 hashes[1] |= (1 << (h - 32)); 599 mcnt++; 600 ETHER_NEXT_MULTI(step, enm); 601 } 602 603 if (mcnt) 604 rxfilt |= RTK_RXCFG_RX_MULTI; 605 else 606 rxfilt &= ~RTK_RXCFG_RX_MULTI; 607 608 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 609 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 610 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 611 612 return; 613 } 614 615 void rtk_reset(sc) 616 struct rtk_softc *sc; 617 { 618 int i; 619 620 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 621 622 for (i = 0; i < RTK_TIMEOUT; i++) { 623 DELAY(10); 624 if (!(CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET)) 625 break; 626 } 627 if (i == RTK_TIMEOUT) 628 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 629 630 return; 631 } 632 633 /* 634 * Attach the interface. Allocate softc structures, do ifmedia 635 * setup and ethernet/BPF attach. 636 */ 637 void 638 rtk_attach(sc) 639 struct rtk_softc *sc; 640 { 641 642 struct ifnet *ifp; 643 u_int16_t val; 644 u_int8_t eaddr[ETHER_ADDR_LEN]; 645 int error; 646 int i,addr_len; 647 648 callout_init(&sc->rtk_tick_ch); 649 650 /* 651 * Check EEPROM type 9346 or 9356. 652 */ 653 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 654 addr_len = RTK_EEADDR_LEN1; 655 else 656 addr_len = RTK_EEADDR_LEN0; 657 658 /* 659 * Get station address. 660 */ 661 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 662 eaddr[0] = val & 0xff; 663 eaddr[1] = val >> 8; 664 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 665 eaddr[2] = val & 0xff; 666 eaddr[3] = val >> 8; 667 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 668 eaddr[4] = val & 0xff; 669 eaddr[5] = val >> 8; 670 671 if ((error = bus_dmamem_alloc(sc->sc_dmat, 672 RTK_RXBUFLEN + 32, NBPG, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 673 BUS_DMA_NOWAIT)) != 0) { 674 printf("%s: can't allocate recv buffer, error = %d\n", 675 sc->sc_dev.dv_xname, error); 676 goto fail_0; 677 } 678 679 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 680 RTK_RXBUFLEN + 32, (caddr_t *)&sc->rtk_cdata.rtk_rx_buf, 681 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 682 printf("%s: can't map recv buffer, error = %d\n", 683 sc->sc_dev.dv_xname, error); 684 goto fail_1; 685 } 686 687 /* Leave a few bytes before the start of the RX ring buffer. */ 688 sc->rtk_cdata.rtk_rx_buf_ptr = sc->rtk_cdata.rtk_rx_buf; 689 sc->rtk_cdata.rtk_rx_buf += sizeof(u_int64_t); 690 691 if ((error = bus_dmamap_create(sc->sc_dmat, 692 RTK_RXBUFLEN + 32 - sizeof(u_int64_t), 1, 693 RTK_RXBUFLEN + 32 - sizeof(u_int64_t), 0, BUS_DMA_NOWAIT, 694 &sc->recv_dmamap)) != 0) { 695 printf("%s: can't create recv buffer DMA map, error = %d\n", 696 sc->sc_dev.dv_xname, error); 697 goto fail_2; 698 } 699 700 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 701 sc->rtk_cdata.rtk_rx_buf, RTK_RXBUFLEN + 32 - sizeof(u_int64_t), 702 NULL, BUS_DMA_NOWAIT)) != 0) { 703 printf("%s: can't load recv buffer DMA map, error = %d\n", 704 sc->sc_dev.dv_xname, error); 705 goto fail_3; 706 } 707 708 for (i = 0; i < RTK_TX_LIST_CNT; i++) 709 if ((error = bus_dmamap_create(sc->sc_dmat, 710 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 711 &sc->snd_dmamap[i])) != 0) { 712 printf("%s: can't create snd buffer DMA map," 713 " error = %d\n", sc->sc_dev.dv_xname, error); 714 goto fail_4; 715 } 716 /* 717 * From this point forward, the attachment cannot fail. A failure 718 * before this releases all resources thar may have been 719 * allocated. 720 */ 721 sc->sc_flags |= RTK_ATTACHED; 722 723 /* Reset the adapter. */ 724 rtk_reset(sc); 725 726 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 727 ether_sprintf(eaddr)); 728 729 ifp = &sc->ethercom.ec_if; 730 ifp->if_softc = sc; 731 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 732 ifp->if_mtu = ETHERMTU; 733 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 734 ifp->if_ioctl = rtk_ioctl; 735 #if 0 736 ifp->if_output = ether_output; 737 #endif 738 ifp->if_start = rtk_start; 739 ifp->if_watchdog = rtk_watchdog; 740 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 741 742 /* 743 * Do ifmedia setup. 744 */ 745 sc->mii.mii_ifp = ifp; 746 sc->mii.mii_readreg = rtk_phy_readreg; 747 sc->mii.mii_writereg = rtk_phy_writereg; 748 sc->mii.mii_statchg = rtk_phy_statchg; 749 ifmedia_init(&sc->mii.mii_media, 0, rtk_ifmedia_upd, rtk_ifmedia_sts); 750 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 751 MII_PHY_ANY, MII_OFFSET_ANY, 0); 752 753 /* Choose a default media. */ 754 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 755 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 756 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 757 } else { 758 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 759 } 760 761 /* 762 * Call MI attach routines. 763 */ 764 if_attach(ifp); 765 ether_ifattach(ifp, eaddr); 766 767 #if NBPFILTER > 0 768 bpfattach(&sc->ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 769 sizeof(struct ether_header)); 770 #endif 771 /* 772 * Make sure the interface is shutdown during reboot. 773 */ 774 sc->sc_sdhook = shutdownhook_establish(rtk_shutdown, sc); 775 if (sc->sc_sdhook == NULL) 776 printf("%s: WARNING: unbale to establish shutdown hook\n", 777 sc->sc_dev.dv_xname); 778 /* 779 * Add a suspend hook to make sure we come back up after a 780 * resume. 781 */ 782 sc->sc_powerhook = powerhook_establish(rtk_power, sc); 783 if (sc->sc_powerhook == NULL) 784 printf("%s: WARNING: unable to establish power hook\n", 785 sc->sc_dev.dv_xname); 786 787 return; 788 fail_4: 789 for (i = 0; i < RTK_TX_LIST_CNT; i++) 790 if (sc->snd_dmamap[i] != NULL) 791 bus_dmamap_destroy(sc->sc_dmat, sc->snd_dmamap[i]); 792 fail_3: 793 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 794 fail_2: 795 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_cdata.rtk_rx_buf_ptr, 796 RTK_RXBUFLEN + 32 - sizeof(u_int64_t)); 797 fail_1: 798 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 799 fail_0: 800 return; 801 } 802 803 /* 804 * Initialize the transmit descriptors. 805 */ 806 STATIC int rtk_list_tx_init(sc) 807 struct rtk_softc *sc; 808 { 809 struct rtk_chain_data *cd; 810 int i; 811 812 cd = &sc->rtk_cdata; 813 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 814 cd->rtk_tx_chain[i] = NULL; 815 CSR_WRITE_4(sc, 816 RTK_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 817 } 818 819 sc->rtk_cdata.cur_tx = 0; 820 sc->rtk_cdata.last_tx = 0; 821 822 return(0); 823 } 824 825 /* 826 * rtk_activate: 827 * Handle device activation/deactivation requests. 828 */ 829 int 830 rtk_activate(self, act) 831 struct device *self; 832 enum devact act; 833 { 834 struct rtk_softc *sc = (void *) self; 835 int s, error = 0; 836 837 s = splnet(); 838 switch (act) { 839 case DVACT_ACTIVATE: 840 error = EOPNOTSUPP; 841 break; 842 case DVACT_DEACTIVATE: 843 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 844 if_deactivate(&sc->ethercom.ec_if); 845 break; 846 } 847 splx(s); 848 849 return (error); 850 } 851 852 /* 853 * rtk_detach: 854 * Detach a rtk interface. 855 */ 856 int 857 rtk_detach(sc) 858 struct rtk_softc *sc; 859 { 860 struct ifnet *ifp = &sc->ethercom.ec_if; 861 int i; 862 863 /* 864 * Succeed now if thereisn't any work to do. 865 */ 866 if ((sc->sc_flags & RTK_ATTACHED) == 0) 867 return (0); 868 869 /* Unhook our tick handler. */ 870 callout_stop(&sc->rtk_tick_ch); 871 872 /* Detach all PHYs. */ 873 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 874 875 /* Delete all remaining media. */ 876 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 877 878 #if NBPFILTER > 0 879 bpfdetach(ifp); 880 #endif 881 ether_ifdetach(ifp); 882 if_detach(ifp); 883 884 for (i = 0; i < RTK_TX_LIST_CNT; i++) 885 if (sc->snd_dmamap[i] != NULL) 886 bus_dmamap_destroy(sc->sc_dmat, sc->snd_dmamap[i]); 887 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 888 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_cdata.rtk_rx_buf_ptr, 889 RTK_RXBUFLEN + 32 - sizeof(u_int64_t)); 890 891 shutdownhook_disestablish(sc->sc_sdhook); 892 powerhook_disestablish(sc->sc_powerhook); 893 894 return (0); 895 } 896 897 /* 898 * rtk_enable: 899 * Enable the RTL81X9 chip. 900 */ 901 int 902 rtk_enable(sc) 903 struct rtk_softc *sc; 904 { 905 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 906 if ((*sc->sc_enable)(sc) != 0) { 907 printf("%s: device enable failed\n", 908 sc->sc_dev.dv_xname); 909 return(EIO); 910 } 911 sc->sc_flags |= RTK_ENABLED; 912 } 913 return (0); 914 } 915 916 /* 917 * rtk_disable: 918 * Disable the RTL81X9 chip. 919 */ 920 void 921 rtk_disable(sc) 922 struct rtk_softc *sc; 923 { 924 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 925 (*sc->sc_disable)(sc); 926 sc->sc_flags &= ~RTK_ENABLED; 927 } 928 } 929 930 /* 931 * rtk_power: 932 * Power management (suspend/resume) hook. 933 */ 934 void 935 rtk_power(why, arg) 936 int why; 937 void *arg; 938 { 939 struct rtk_softc *sc = (void *) arg; 940 struct ifnet *ifp = &sc->ethercom.ec_if; 941 int s; 942 943 s = splnet(); 944 if (why != PWR_RESUME) { 945 rtk_stop(sc); 946 if (sc->sc_power != NULL) 947 (*sc->sc_power)(sc, why); 948 } else if (ifp->if_flags & IFF_UP) { 949 if (sc->sc_power != NULL) 950 (*sc->sc_power)(sc, why); 951 rtk_init(sc); 952 } 953 splx(s); 954 955 } 956 957 /* 958 * A frame has been uploaded: pass the resulting mbuf chain up to 959 * the higher level protocols. 960 * 961 * You know there's something wrong with a PCI bus-master chip design 962 * when you have to use m_devget(). 963 * 964 * The receive operation is badly documented in the datasheet, so I'll 965 * attempt to document it here. The driver provides a buffer area and 966 * places its base address in the RX buffer start address register. 967 * The chip then begins copying frames into the RX buffer. Each frame 968 * is preceeded by a 32-bit RX status word which specifies the length 969 * of the frame and certain other status bits. Each frame (starting with 970 * the status word) is also 32-bit aligned. The frame length is in the 971 * first 16 bits of the status word; the lower 15 bits correspond with 972 * the 'rx status register' mentioned in the datasheet. 973 * 974 * Note: to make the Alpha happy, the frame payload needs to be aligned 975 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 976 * the ring buffer starting at an address two bytes before the actual 977 * data location. We can then shave off the first two bytes using m_adj(). 978 * The reason we do this is because m_devget() doesn't let us specify an 979 * offset into the mbuf storage space, so we have to artificially create 980 * one. The ring is allocated in such a way that there are a few unused 981 * bytes of space preceecing it so that it will be safe for us to do the 982 * 2-byte backstep even if reading from the ring at offset 0. 983 */ 984 STATIC void rtk_rxeof(sc) 985 struct rtk_softc *sc; 986 { 987 struct ether_header *eh; 988 struct mbuf *m; 989 struct ifnet *ifp; 990 int total_len = 0; 991 u_int32_t rxstat; 992 caddr_t rxbufpos; 993 int wrap = 0; 994 u_int16_t cur_rx; 995 u_int16_t limit; 996 u_int16_t rx_bytes = 0, max_bytes; 997 998 ifp = &sc->ethercom.ec_if; 999 1000 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 1001 1002 /* Do not try to read past this point. */ 1003 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 1004 1005 if (limit < cur_rx) 1006 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 1007 else 1008 max_bytes = limit - cur_rx; 1009 1010 while((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 1011 rxbufpos = sc->rtk_cdata.rtk_rx_buf + cur_rx; 1012 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1013 sizeof(u_int32_t *), BUS_DMASYNC_POSTREAD); 1014 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1015 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1016 sizeof(u_int32_t *), BUS_DMASYNC_PREREAD); 1017 1018 /* 1019 * Here's a totally undocumented fact for you. When the 1020 * RealTek chip is in the process of copying a packet into 1021 * RAM for you, the length will be 0xfff0. If you spot a 1022 * packet header with this value, you need to stop. The 1023 * datasheet makes absolutely no mention of this and 1024 * RealTek should be shot for this. 1025 */ 1026 if ((u_int16_t)(rxstat >> 16) == RTK_RXSTAT_UNFINISHED) 1027 break; 1028 1029 if (!(rxstat & RTK_RXSTAT_RXOK)) { 1030 ifp->if_ierrors++; 1031 1032 /* 1033 * submitted by:[netbsd-pcmcia:00484] 1034 * Takahiro Kambe <taca (at) sky.yamashina.kyoto.jp> 1035 * obtain from: 1036 * FreeBSD if_rl.c rev 1.24->1.25 1037 * 1038 */ 1039 #if 0 1040 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1041 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1042 RTK_RXSTAT_ALIGNERR)) { 1043 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1044 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1045 RTK_RXSTAT_ALIGNERR)) { 1046 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 1047 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB| 1048 RTK_CMD_RX_ENB); 1049 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1050 CSR_WRITE_4(sc, RTK_RXADDR, 1051 sc->recv_dmamap->dm_segs[0].ds_addr); 1052 CSR_WRITE_2(sc, RTK_CURRXADDR, cur_rx - 16); 1053 cur_rx = 0; 1054 } 1055 break; 1056 #else 1057 rtk_init(sc); 1058 return; 1059 #endif 1060 } 1061 1062 /* No errors; receive the packet. */ 1063 total_len = rxstat >> 16; 1064 rx_bytes += total_len + 4; 1065 1066 /* 1067 * XXX The RealTek chip includes the CRC with every 1068 * received frame, and there's no way to turn this 1069 * behavior off (at least, I can't find anything in 1070 * the manual that explains how to do it) so we have 1071 * to trim off the CRC manually. 1072 */ 1073 total_len -= ETHER_CRC_LEN; 1074 1075 /* 1076 * Avoid trying to read more bytes than we know 1077 * the chip has prepared for us. 1078 */ 1079 if (rx_bytes > max_bytes) 1080 break; 1081 1082 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1083 cur_rx + sizeof(u_int32_t), total_len, 1084 BUS_DMASYNC_POSTREAD); 1085 1086 rxbufpos = sc->rtk_cdata.rtk_rx_buf + 1087 ((cur_rx + sizeof(u_int32_t)) % RTK_RXBUFLEN); 1088 1089 if (rxbufpos == (sc->rtk_cdata.rtk_rx_buf + RTK_RXBUFLEN)) 1090 rxbufpos = sc->rtk_cdata.rtk_rx_buf; 1091 1092 wrap = (sc->rtk_cdata.rtk_rx_buf + RTK_RXBUFLEN) - rxbufpos; 1093 1094 if (total_len > wrap) { 1095 m = m_devget(rxbufpos - RTK_ETHER_ALIGN, 1096 wrap + RTK_ETHER_ALIGN, 0, ifp, NULL); 1097 if (m == NULL) { 1098 ifp->if_ierrors++; 1099 printf("%s: out of mbufs, tried to " 1100 "copy %d bytes\n", sc->sc_dev.dv_xname, 1101 wrap); 1102 } else { 1103 m_adj(m, RTK_ETHER_ALIGN); 1104 m_copyback(m, wrap, total_len - wrap, 1105 sc->rtk_cdata.rtk_rx_buf); 1106 } 1107 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1108 } else { 1109 m = m_devget(rxbufpos - RTK_ETHER_ALIGN, 1110 total_len + RTK_ETHER_ALIGN, 0, ifp, NULL); 1111 if (m == NULL) { 1112 ifp->if_ierrors++; 1113 printf("%s: out of mbufs, tried to " 1114 "copy %d bytes\n", sc->sc_dev.dv_xname, 1115 total_len); 1116 } else 1117 m_adj(m, RTK_ETHER_ALIGN); 1118 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1119 } 1120 1121 /* 1122 * Round up to 32-bit boundary. 1123 */ 1124 cur_rx = (cur_rx + 3) & ~3; 1125 CSR_WRITE_2(sc, RTK_CURRXADDR, cur_rx - 16); 1126 1127 if (m == NULL) 1128 continue; 1129 1130 eh = mtod(m, struct ether_header *); 1131 ifp->if_ipackets++; 1132 1133 #if NBPFILTER > 0 1134 /* 1135 * Handle BPF listeners. Let the BPF user see the packet, but 1136 * don't pass it up to the ether_input() layer unless it's 1137 * a broadcast packet, multicast packet, matches our ethernet 1138 * address or the interface is in promiscuous mode. 1139 */ 1140 if (ifp->if_bpf) { 1141 bpf_mtap(ifp->if_bpf, m); 1142 if ((ifp->if_flags & IFF_PROMISC) != 0 && 1143 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 1144 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 1145 ETHER_ADDR_LEN) != 0) { 1146 m_freem(m); 1147 continue; 1148 } 1149 } 1150 #endif 1151 /* pass it on. */ 1152 (*ifp->if_input)(ifp, m); 1153 1154 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1155 cur_rx + sizeof(u_int32_t), 1156 total_len, BUS_DMASYNC_PREREAD); 1157 } 1158 1159 return; 1160 } 1161 1162 /* 1163 * A frame was downloaded to the chip. It's safe for us to clean up 1164 * the list buffers. 1165 */ 1166 STATIC void rtk_txeof(sc) 1167 struct rtk_softc *sc; 1168 { 1169 struct ifnet *ifp; 1170 u_int32_t txstat; 1171 1172 ifp = &sc->ethercom.ec_if; 1173 1174 /* Clear the timeout timer. */ 1175 ifp->if_timer = 0; 1176 1177 /* 1178 * Go through our tx list and free mbufs for those 1179 * frames that have been uploaded. 1180 */ 1181 do { 1182 txstat = CSR_READ_4(sc, RTK_LAST_TXSTAT(sc)); 1183 if (!(txstat & (RTK_TXSTAT_TX_OK| 1184 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT))) 1185 break; 1186 1187 bus_dmamap_sync(sc->sc_dmat, 1188 sc->snd_dmamap[sc->rtk_cdata.last_tx], 0, 1189 sc->snd_dmamap[sc->rtk_cdata.last_tx]->dm_mapsize, 1190 BUS_DMASYNC_POSTWRITE); 1191 bus_dmamap_unload(sc->sc_dmat, 1192 sc->snd_dmamap[sc->rtk_cdata.last_tx]); 1193 m_freem(RTK_LAST_TXMBUF(sc)); 1194 RTK_LAST_TXMBUF(sc) = NULL; 1195 1196 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1197 1198 if (txstat & RTK_TXSTAT_TX_OK) 1199 ifp->if_opackets++; 1200 else { 1201 ifp->if_oerrors++; 1202 if ((txstat & RTK_TXSTAT_TXABRT) || 1203 (txstat & RTK_TXSTAT_OUTOFWIN)) 1204 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1205 } 1206 RTK_INC(sc->rtk_cdata.last_tx); 1207 ifp->if_flags &= ~IFF_OACTIVE; 1208 } while (sc->rtk_cdata.last_tx != sc->rtk_cdata.cur_tx); 1209 1210 return; 1211 } 1212 1213 int rtk_intr(arg) 1214 void *arg; 1215 { 1216 struct rtk_softc *sc; 1217 struct ifnet *ifp; 1218 u_int16_t status; 1219 int handled = 0; 1220 1221 sc = arg; 1222 ifp = &sc->ethercom.ec_if; 1223 1224 /* Disable interrupts. */ 1225 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1226 1227 for (;;) { 1228 1229 status = CSR_READ_2(sc, RTK_ISR); 1230 if (status) 1231 CSR_WRITE_2(sc, RTK_ISR, status); 1232 1233 handled = 1; 1234 1235 if ((status & RTK_INTRS) == 0) 1236 break; 1237 1238 if (status & RTK_ISR_RX_OK) 1239 rtk_rxeof(sc); 1240 1241 if (status & RTK_ISR_RX_ERR) 1242 rtk_rxeof(sc); 1243 1244 if ((status & RTK_ISR_TX_OK) || (status & RTK_ISR_TX_ERR)) 1245 rtk_txeof(sc); 1246 1247 if (status & RTK_ISR_SYSTEM_ERR) { 1248 rtk_reset(sc); 1249 rtk_init(sc); 1250 } 1251 1252 } 1253 1254 /* Re-enable interrupts. */ 1255 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1256 1257 if (ifp->if_snd.ifq_head != NULL) { 1258 rtk_start(ifp); 1259 } 1260 1261 return (handled); 1262 } 1263 1264 /* 1265 * Main transmit routine. 1266 */ 1267 1268 STATIC void rtk_start(ifp) 1269 struct ifnet *ifp; 1270 { 1271 struct rtk_softc *sc; 1272 struct mbuf *m_head = NULL, *m_new; 1273 int error, idx, len; 1274 1275 sc = ifp->if_softc; 1276 1277 while(RTK_CUR_TXMBUF(sc) == NULL) { 1278 IF_DEQUEUE(&ifp->if_snd, m_head); 1279 if (m_head == NULL) 1280 break; 1281 1282 idx = sc->rtk_cdata.cur_tx; 1283 1284 /* 1285 * Load the DMA map. If this fails, the packet didn't 1286 * fit in one DMA segment, and we need to copy. Note, 1287 * the packet must also be aligned. 1288 */ 1289 if ((mtod(m_head, bus_addr_t) & 3) != 0 || 1290 bus_dmamap_load_mbuf(sc->sc_dmat, sc->snd_dmamap[idx], 1291 m_head, BUS_DMA_NOWAIT) != 0) { 1292 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1293 if (m_new == NULL) { 1294 printf("%s: unable to allocate Tx mbuf\n", 1295 sc->sc_dev.dv_xname); 1296 IF_PREPEND(&ifp->if_snd, m_new); 1297 break; 1298 } 1299 if (m_head->m_pkthdr.len > MHLEN) { 1300 MCLGET(m_new, M_DONTWAIT); 1301 if ((m_new->m_flags & M_EXT) == 0) { 1302 printf("%s: unable to allocate Tx " 1303 "cluster\n", sc->sc_dev.dv_xname); 1304 m_freem(m_new); 1305 IF_PREPEND(&ifp->if_snd, m_head); 1306 break; 1307 } 1308 } 1309 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1310 mtod(m_new, caddr_t)); 1311 m_new->m_pkthdr.len = m_new->m_len = 1312 m_head->m_pkthdr.len; 1313 m_freem(m_head); 1314 m_head = m_new; 1315 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1316 sc->snd_dmamap[idx], m_head, BUS_DMA_NOWAIT); 1317 if (error) { 1318 printf("%s: unable to load Tx buffer, " 1319 "error = %d\n", sc->sc_dev.dv_xname, error); 1320 IF_PREPEND(&ifp->if_snd, m_head); 1321 break; 1322 } 1323 } 1324 1325 RTK_CUR_TXMBUF(sc) = m_head; 1326 1327 #if NBPFILTER > 0 1328 /* 1329 * If there's a BPF listener, bounce a copy of this frame 1330 * to him. 1331 */ 1332 if (ifp->if_bpf) 1333 bpf_mtap(ifp->if_bpf, RTK_CUR_TXMBUF(sc)); 1334 #endif 1335 /* 1336 * Transmit the frame. 1337 */ 1338 bus_dmamap_sync(sc->sc_dmat, 1339 sc->snd_dmamap[idx], 0, sc->snd_dmamap[idx]->dm_mapsize, 1340 BUS_DMASYNC_PREWRITE); 1341 1342 len = sc->snd_dmamap[idx]->dm_segs[0].ds_len; 1343 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 1344 len = (ETHER_MIN_LEN - ETHER_CRC_LEN); 1345 1346 CSR_WRITE_4(sc, RTK_CUR_TXADDR(sc), 1347 sc->snd_dmamap[idx]->dm_segs[0].ds_addr); 1348 CSR_WRITE_4(sc, RTK_CUR_TXSTAT(sc), RTK_TX_EARLYTHRESH | len); 1349 1350 RTK_INC(sc->rtk_cdata.cur_tx); 1351 } 1352 1353 /* 1354 * We broke out of the loop because all our TX slots are 1355 * full. Mark the NIC as busy until it drains some of the 1356 * packets from the queue. 1357 */ 1358 if (RTK_CUR_TXMBUF(sc) != NULL) 1359 ifp->if_flags |= IFF_OACTIVE; 1360 1361 /* 1362 * Set a timeout in case the chip goes out to lunch. 1363 */ 1364 ifp->if_timer = 5; 1365 1366 return; 1367 } 1368 1369 STATIC void rtk_init(xsc) 1370 void *xsc; 1371 { 1372 struct rtk_softc *sc = xsc; 1373 struct ifnet *ifp = &sc->ethercom.ec_if; 1374 int s, i; 1375 u_int32_t rxcfg; 1376 1377 s = splnet(); 1378 1379 /* 1380 * Cancel pending I/O and free all RX/TX buffers. 1381 */ 1382 rtk_stop(sc); 1383 1384 /* Init our MAC address */ 1385 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1386 CSR_WRITE_1(sc, RTK_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1387 } 1388 1389 /* Init the RX buffer pointer register. */ 1390 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1391 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1392 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1393 1394 /* Init TX descriptors. */ 1395 rtk_list_tx_init(sc); 1396 1397 /* 1398 * Enable transmit and receive. 1399 */ 1400 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1401 1402 /* 1403 * Set the initial TX and RX configuration. 1404 */ 1405 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1406 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1407 1408 /* Set the individual bit to receive frames for this host only. */ 1409 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1410 rxcfg |= RTK_RXCFG_RX_INDIV; 1411 1412 /* If we want promiscuous mode, set the allframes bit. */ 1413 if (ifp->if_flags & IFF_PROMISC) { 1414 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1415 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1416 } else { 1417 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1418 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1419 } 1420 1421 /* 1422 * Set capture broadcast bit to capture broadcast frames. 1423 */ 1424 if (ifp->if_flags & IFF_BROADCAST) { 1425 rxcfg |= RTK_RXCFG_RX_BROAD; 1426 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1427 } else { 1428 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1429 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1430 } 1431 1432 /* 1433 * Program the multicast filter, if necessary. 1434 */ 1435 rtk_setmulti(sc); 1436 1437 /* 1438 * Enable interrupts. 1439 */ 1440 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1441 1442 /* Start RX/TX process. */ 1443 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1444 1445 /* Enable receiver and transmitter. */ 1446 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1447 1448 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1449 1450 /* 1451 * Set current media. 1452 */ 1453 mii_mediachg(&sc->mii); 1454 1455 ifp->if_flags |= IFF_RUNNING; 1456 ifp->if_flags &= ~IFF_OACTIVE; 1457 1458 (void)splx(s); 1459 1460 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1461 } 1462 1463 /* 1464 * Set media options. 1465 */ 1466 STATIC int rtk_ifmedia_upd(ifp) 1467 struct ifnet *ifp; 1468 { 1469 struct rtk_softc *sc; 1470 1471 sc = ifp->if_softc; 1472 1473 return (mii_mediachg(&sc->mii)); 1474 } 1475 1476 /* 1477 * Report current media status. 1478 */ 1479 STATIC void rtk_ifmedia_sts(ifp, ifmr) 1480 struct ifnet *ifp; 1481 struct ifmediareq *ifmr; 1482 { 1483 struct rtk_softc *sc; 1484 1485 sc = ifp->if_softc; 1486 1487 mii_pollstat(&sc->mii); 1488 ifmr->ifm_status = sc->mii.mii_media_status; 1489 ifmr->ifm_active = sc->mii.mii_media_active; 1490 } 1491 1492 STATIC int 1493 rtk_ether_ioctl(ifp, cmd, data) 1494 struct ifnet *ifp; 1495 u_long cmd; 1496 caddr_t data; 1497 { 1498 struct ifaddr *ifa = (struct ifaddr *) data; 1499 struct rtk_softc *sc = ifp->if_softc; 1500 int error = 0; 1501 1502 switch (cmd) { 1503 case SIOCSIFADDR: 1504 if ((error = rtk_enable(sc)) != 0) 1505 break; 1506 ifp->if_flags |= IFF_UP; 1507 1508 switch (ifa->ifa_addr->sa_family) { 1509 #ifdef INET 1510 case AF_INET: 1511 rtk_init(sc); 1512 arp_ifinit(ifp, ifa); 1513 break; 1514 #endif 1515 #ifdef NS 1516 case AF_NS: 1517 { 1518 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1519 1520 if (ns_nullhost(*ina)) 1521 ina->x_host = *(union ns_host *) 1522 LLADDR(ifp->if_sadl); 1523 else 1524 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1525 ifp->if_addrlen); 1526 /* Set new address. */ 1527 rtk_init(sc); 1528 break; 1529 } 1530 #endif 1531 default: 1532 rtk_init(sc); 1533 break; 1534 } 1535 break; 1536 1537 default: 1538 return (EINVAL); 1539 } 1540 1541 return (error); 1542 } 1543 1544 STATIC int rtk_ioctl(ifp, command, data) 1545 struct ifnet *ifp; 1546 u_long command; 1547 caddr_t data; 1548 { 1549 struct rtk_softc *sc = ifp->if_softc; 1550 struct ifreq *ifr = (struct ifreq *) data; 1551 int s, error = 0; 1552 1553 s = splnet(); 1554 1555 switch (command) { 1556 case SIOCSIFADDR: 1557 case SIOCGIFADDR: 1558 case SIOCSIFMTU: 1559 error = rtk_ether_ioctl(ifp, command, data); 1560 break; 1561 case SIOCSIFFLAGS: 1562 if (ifp->if_flags & IFF_UP) { 1563 if ((error = rtk_enable(sc)) != 0) 1564 break; 1565 rtk_init(sc); 1566 } else { 1567 if (ifp->if_flags & IFF_RUNNING) { 1568 rtk_stop(sc); 1569 rtk_disable(sc); 1570 } 1571 } 1572 error = 0; 1573 break; 1574 case SIOCADDMULTI: 1575 case SIOCDELMULTI: 1576 error = (command == SIOCADDMULTI) ? 1577 ether_addmulti(ifr, &sc->ethercom) : 1578 ether_delmulti(ifr, &sc->ethercom); 1579 1580 if (error == ENETRESET) { 1581 /* 1582 * Multicast list has changed; set the hardware filter 1583 * accordingly. 1584 */ 1585 rtk_setmulti(sc); 1586 error = 0; 1587 } 1588 break; 1589 case SIOCGIFMEDIA: 1590 case SIOCSIFMEDIA: 1591 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1592 break; 1593 default: 1594 error = EINVAL; 1595 break; 1596 } 1597 1598 splx(s); 1599 1600 return(error); 1601 } 1602 1603 STATIC void rtk_watchdog(ifp) 1604 struct ifnet *ifp; 1605 { 1606 struct rtk_softc *sc; 1607 1608 sc = ifp->if_softc; 1609 1610 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1611 ifp->if_oerrors++; 1612 rtk_txeof(sc); 1613 rtk_rxeof(sc); 1614 rtk_init(sc); 1615 1616 return; 1617 } 1618 1619 /* 1620 * Stop the adapter and free any mbufs allocated to the 1621 * RX and TX lists. 1622 */ 1623 STATIC void rtk_stop(sc) 1624 struct rtk_softc *sc; 1625 { 1626 int i; 1627 struct ifnet *ifp; 1628 1629 ifp = &sc->ethercom.ec_if; 1630 ifp->if_timer = 0; 1631 1632 callout_stop(&sc->rtk_tick_ch); 1633 1634 mii_down(&sc->mii); 1635 1636 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1637 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1638 1639 /* 1640 * Free the TX list buffers. 1641 */ 1642 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 1643 if (sc->rtk_cdata.rtk_tx_chain[i] != NULL) { 1644 bus_dmamap_unload(sc->sc_dmat, sc->snd_dmamap[i]); 1645 m_freem(sc->rtk_cdata.rtk_tx_chain[i]); 1646 sc->rtk_cdata.rtk_tx_chain[i] = NULL; 1647 CSR_WRITE_4(sc, RTK_TXADDR0 + i, 0x0000000); 1648 } 1649 } 1650 1651 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1652 1653 return; 1654 } 1655 1656 /* 1657 * Stop all chip I/O so that the kernel's probe routines don't 1658 * get confused by errant DMAs when rebooting. 1659 */ 1660 STATIC void rtk_shutdown(vsc) 1661 void *vsc; 1662 { 1663 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1664 1665 rtk_stop(sc); 1666 1667 return; 1668 } 1669 1670 STATIC void 1671 rtk_tick(arg) 1672 void *arg; 1673 { 1674 struct rtk_softc *sc = arg; 1675 int s = splnet(); 1676 1677 mii_tick(&sc->mii); 1678 splx(s); 1679 1680 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1681 } 1682
Indexes created Wed Sep 24 05:09:52 GMT 2025