rtl81x9.c revision 1.5
1 /* $NetBSD: rtl81x9.c,v 1.5 2000/04/30 12:00:40 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include "opt_inet.h" 89 #include "opt_ns.h" 90 #include "bpfilter.h" 91 #include "rnd.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/callout.h> 96 #include <sys/device.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/if_inarp.h> 111 #endif 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #if NBPFILTER > 0 118 #include <net/bpf.h> 119 #endif 120 #if NRND > 0 121 #include <sys/rnd.h> 122 #endif 123 124 #include <machine/bus.h> 125 #include <machine/endian.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 130 /* 131 * Default to using PIO access for this driver. On SMP systems, 132 * there appear to be problems with memory mapped mode: it looks like 133 * doing too many memory mapped access back to back in rapid succession 134 * can hang the bus. I'm inclined to blame this on crummy design/construction 135 * on the part of RealTek. Memory mapped mode does appear to work on 136 * uniprocessor systems though. 137 */ 138 139 #include <dev/ic/rtl81x9reg.h> 140 #include <dev/ic/rtl81x9var.h> 141 142 #if defined DEBUG 143 #define STATIC 144 #else 145 #define STATIC static 146 #endif 147 148 STATIC void rl_rxeof __P((struct rl_softc *)); 149 STATIC void rl_txeof __P((struct rl_softc *)); 150 STATIC void rl_start __P((struct ifnet *)); 151 STATIC int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 152 STATIC void rl_init __P((void *)); 153 STATIC void rl_stop __P((struct rl_softc *)); 154 STATIC void rl_watchdog __P((struct ifnet *)); 155 STATIC void rl_shutdown __P((void *)); 156 STATIC int rl_ifmedia_upd __P((struct ifnet *)); 157 STATIC void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 158 159 STATIC void rl_eeprom_putbyte __P((struct rl_softc *, int, int)); 160 STATIC void rl_mii_sync __P((struct rl_softc *)); 161 STATIC void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 162 STATIC int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 163 STATIC int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 164 165 STATIC int rl_phy_readreg __P((struct device *, int, int)); 166 STATIC void rl_phy_writereg __P((struct device *, int, int, int)); 167 STATIC void rl_phy_statchg __P((struct device *)); 168 STATIC void rl_tick __P((void *)); 169 170 STATIC u_int8_t rl_calchash __P((caddr_t)); 171 STATIC void rl_setmulti __P((struct rl_softc *)); 172 STATIC int rl_list_tx_init __P((struct rl_softc *)); 173 174 STATIC int rl_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 175 176 177 #define EE_SET(x) \ 178 CSR_WRITE_1(sc, RL_EECMD, \ 179 CSR_READ_1(sc, RL_EECMD) | (x)) 180 181 #define EE_CLR(x) \ 182 CSR_WRITE_1(sc, RL_EECMD, \ 183 CSR_READ_1(sc, RL_EECMD) & ~(x)) 184 185 /* 186 * Send a read command and address to the EEPROM, check for ACK. 187 */ 188 STATIC void rl_eeprom_putbyte(sc, addr, addr_len) 189 struct rl_softc *sc; 190 int addr, addr_len; 191 { 192 int d, i; 193 194 d = (RL_EECMD_READ << addr_len) | addr; 195 196 /* 197 * Feed in each bit and stobe the clock. 198 */ 199 for (i = RL_EECMD_LEN + addr_len - 1; i >= 0; i--) { 200 if (d & (1 << i)) { 201 EE_SET(RL_EE_DATAIN); 202 } else { 203 EE_CLR(RL_EE_DATAIN); 204 } 205 DELAY(100); 206 EE_SET(RL_EE_CLK); 207 DELAY(150); 208 EE_CLR(RL_EE_CLK); 209 DELAY(100); 210 } 211 } 212 213 /* 214 * Read a word of data stored in the EEPROM at address 'addr.' 215 */ 216 u_int16_t rl_read_eeprom(sc, addr, addr_len) 217 struct rl_softc *sc; 218 int addr, addr_len; 219 { 220 u_int16_t word = 0; 221 int i; 222 223 /* Enter EEPROM access mode. */ 224 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 225 226 /* 227 * Send address of word we want to read. 228 */ 229 rl_eeprom_putbyte(sc, addr, addr_len); 230 231 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 232 233 /* 234 * Start reading bits from EEPROM. 235 */ 236 for (i = 15; i >= 0; i--) { 237 EE_SET(RL_EE_CLK); 238 DELAY(100); 239 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 240 word |= (1 << i); 241 EE_CLR(RL_EE_CLK); 242 DELAY(100); 243 } 244 245 /* Turn off EEPROM access mode. */ 246 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 247 248 return (word); 249 } 250 251 /* 252 * MII access routines are provided for the 8129, which 253 * doesn't have a built-in PHY. For the 8139, we fake things 254 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 255 * direct access PHY registers. 256 */ 257 #define MII_SET(x) \ 258 CSR_WRITE_1(sc, RL_MII, \ 259 CSR_READ_1(sc, RL_MII) | x) 260 261 #define MII_CLR(x) \ 262 CSR_WRITE_1(sc, RL_MII, \ 263 CSR_READ_1(sc, RL_MII) & ~x) 264 265 /* 266 * Sync the PHYs by setting data bit and strobing the clock 32 times. 267 */ 268 STATIC void rl_mii_sync(sc) 269 struct rl_softc *sc; 270 { 271 int i; 272 273 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 274 275 for (i = 0; i < 32; i++) { 276 MII_SET(RL_MII_CLK); 277 DELAY(1); 278 MII_CLR(RL_MII_CLK); 279 DELAY(1); 280 } 281 282 return; 283 } 284 285 /* 286 * Clock a series of bits through the MII. 287 */ 288 STATIC void rl_mii_send(sc, bits, cnt) 289 struct rl_softc *sc; 290 u_int32_t bits; 291 int cnt; 292 { 293 int i; 294 295 MII_CLR(RL_MII_CLK); 296 297 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 298 if (bits & i) { 299 MII_SET(RL_MII_DATAOUT); 300 } else { 301 MII_CLR(RL_MII_DATAOUT); 302 } 303 DELAY(1); 304 MII_CLR(RL_MII_CLK); 305 DELAY(1); 306 MII_SET(RL_MII_CLK); 307 } 308 } 309 310 /* 311 * Read an PHY register through the MII. 312 */ 313 STATIC int rl_mii_readreg(sc, frame) 314 struct rl_softc *sc; 315 struct rl_mii_frame *frame; 316 317 { 318 int i, ack, s; 319 320 s = splimp(); 321 322 /* 323 * Set up frame for RX. 324 */ 325 frame->mii_stdelim = RL_MII_STARTDELIM; 326 frame->mii_opcode = RL_MII_READOP; 327 frame->mii_turnaround = 0; 328 frame->mii_data = 0; 329 330 CSR_WRITE_2(sc, RL_MII, 0); 331 332 /* 333 * Turn on data xmit. 334 */ 335 MII_SET(RL_MII_DIR); 336 337 rl_mii_sync(sc); 338 339 /* 340 * Send command/address info. 341 */ 342 rl_mii_send(sc, frame->mii_stdelim, 2); 343 rl_mii_send(sc, frame->mii_opcode, 2); 344 rl_mii_send(sc, frame->mii_phyaddr, 5); 345 rl_mii_send(sc, frame->mii_regaddr, 5); 346 347 /* Idle bit */ 348 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 349 DELAY(1); 350 MII_SET(RL_MII_CLK); 351 DELAY(1); 352 353 /* Turn off xmit. */ 354 MII_CLR(RL_MII_DIR); 355 356 /* Check for ack */ 357 MII_CLR(RL_MII_CLK); 358 DELAY(1); 359 MII_SET(RL_MII_CLK); 360 DELAY(1); 361 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 362 363 /* 364 * Now try reading data bits. If the ack failed, we still 365 * need to clock through 16 cycles to keep the PHY(s) in sync. 366 */ 367 if (ack) { 368 for(i = 0; i < 16; i++) { 369 MII_CLR(RL_MII_CLK); 370 DELAY(1); 371 MII_SET(RL_MII_CLK); 372 DELAY(1); 373 } 374 goto fail; 375 } 376 377 for (i = 0x8000; i; i >>= 1) { 378 MII_CLR(RL_MII_CLK); 379 DELAY(1); 380 if (!ack) { 381 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 382 frame->mii_data |= i; 383 DELAY(1); 384 } 385 MII_SET(RL_MII_CLK); 386 DELAY(1); 387 } 388 389 fail: 390 391 MII_CLR(RL_MII_CLK); 392 DELAY(1); 393 MII_SET(RL_MII_CLK); 394 DELAY(1); 395 396 splx(s); 397 398 if (ack) 399 return(1); 400 return(0); 401 } 402 403 /* 404 * Write to a PHY register through the MII. 405 */ 406 STATIC int rl_mii_writereg(sc, frame) 407 struct rl_softc *sc; 408 struct rl_mii_frame *frame; 409 410 { 411 int s; 412 413 s = splimp(); 414 /* 415 * Set up frame for TX. 416 */ 417 418 frame->mii_stdelim = RL_MII_STARTDELIM; 419 frame->mii_opcode = RL_MII_WRITEOP; 420 frame->mii_turnaround = RL_MII_TURNAROUND; 421 422 /* 423 * Turn on data output. 424 */ 425 MII_SET(RL_MII_DIR); 426 427 rl_mii_sync(sc); 428 429 rl_mii_send(sc, frame->mii_stdelim, 2); 430 rl_mii_send(sc, frame->mii_opcode, 2); 431 rl_mii_send(sc, frame->mii_phyaddr, 5); 432 rl_mii_send(sc, frame->mii_regaddr, 5); 433 rl_mii_send(sc, frame->mii_turnaround, 2); 434 rl_mii_send(sc, frame->mii_data, 16); 435 436 /* Idle bit. */ 437 MII_SET(RL_MII_CLK); 438 DELAY(1); 439 MII_CLR(RL_MII_CLK); 440 DELAY(1); 441 442 /* 443 * Turn off xmit. 444 */ 445 MII_CLR(RL_MII_DIR); 446 447 splx(s); 448 449 return(0); 450 } 451 452 STATIC int rl_phy_readreg(self, phy, reg) 453 struct device *self; 454 int phy, reg; 455 { 456 struct rl_softc *sc = (void *)self; 457 struct rl_mii_frame frame; 458 u_int16_t rval = 0; 459 u_int16_t rl8139_reg = 0; 460 461 if (sc->rl_type == RL_8139) { 462 if (phy != 7) 463 return (0); 464 465 switch(reg) { 466 case MII_BMCR: 467 rl8139_reg = RL_BMCR; 468 break; 469 case MII_BMSR: 470 rl8139_reg = RL_BMSR; 471 break; 472 case MII_ANAR: 473 rl8139_reg = RL_ANAR; 474 break; 475 case MII_ANLPAR: 476 rl8139_reg = RL_LPAR; 477 break; 478 default: 479 #if 0 480 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 481 #endif 482 return(0); 483 } 484 rval = CSR_READ_2(sc, rl8139_reg); 485 return(rval); 486 } 487 488 bzero((char *)&frame, sizeof(frame)); 489 490 frame.mii_phyaddr = phy; 491 frame.mii_regaddr = reg; 492 rl_mii_readreg(sc, &frame); 493 494 return(frame.mii_data); 495 } 496 497 STATIC void rl_phy_writereg(self, phy, reg, data) 498 struct device *self; 499 int phy, reg; 500 int data; 501 { 502 struct rl_softc *sc = (void *)self; 503 struct rl_mii_frame frame; 504 u_int16_t rl8139_reg = 0; 505 506 if (sc->rl_type == RL_8139) { 507 if (phy != 7) 508 return; 509 510 switch(reg) { 511 case MII_BMCR: 512 rl8139_reg = RL_BMCR; 513 break; 514 case MII_BMSR: 515 rl8139_reg = RL_BMSR; 516 break; 517 case MII_ANAR: 518 rl8139_reg = RL_ANAR; 519 break; 520 case MII_ANLPAR: 521 rl8139_reg = RL_LPAR; 522 break; 523 default: 524 #if 0 525 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 526 #endif 527 return; 528 } 529 CSR_WRITE_2(sc, rl8139_reg, data); 530 return; 531 } 532 533 bzero((char *)&frame, sizeof(frame)); 534 535 frame.mii_phyaddr = phy; 536 frame.mii_regaddr = reg; 537 frame.mii_data = data; 538 539 rl_mii_writereg(sc, &frame); 540 541 return; 542 } 543 544 STATIC void 545 rl_phy_statchg(v) 546 struct device *v; 547 { 548 549 /* Nothing to do. */ 550 } 551 552 /* 553 * Calculate CRC of a multicast group address, return the upper 6 bits. 554 */ 555 STATIC u_int8_t rl_calchash(addr) 556 caddr_t addr; 557 { 558 u_int32_t crc, carry; 559 int i, j; 560 u_int8_t c; 561 562 /* Compute CRC for the address value. */ 563 crc = 0xFFFFFFFF; /* initial value */ 564 565 for (i = 0; i < 6; i++) { 566 c = *(addr + i); 567 for (j = 0; j < 8; j++) { 568 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 569 crc <<= 1; 570 c >>= 1; 571 if (carry) 572 crc = (crc ^ 0x04c11db6) | carry; 573 } 574 } 575 576 /* return the filter bit position */ 577 return(crc >> 26); 578 } 579 580 /* 581 * Program the 64-bit multicast hash filter. 582 */ 583 STATIC void rl_setmulti(sc) 584 struct rl_softc *sc; 585 { 586 struct ifnet *ifp; 587 int h = 0; 588 u_int32_t hashes[2] = { 0, 0 }; 589 u_int32_t rxfilt; 590 int mcnt = 0; 591 struct ether_multi *enm; 592 struct ether_multistep step; 593 594 ifp = &sc->ethercom.ec_if; 595 596 rxfilt = CSR_READ_4(sc, RL_RXCFG); 597 598 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 599 rxfilt |= RL_RXCFG_RX_MULTI; 600 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 601 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 602 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 603 return; 604 } 605 606 /* first, zot all the existing hash bits */ 607 CSR_WRITE_4(sc, RL_MAR0, 0); 608 CSR_WRITE_4(sc, RL_MAR4, 0); 609 610 /* now program new ones */ 611 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 612 while (enm != NULL) { 613 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 614 ETHER_ADDR_LEN) != 0) 615 continue; 616 617 h = rl_calchash(enm->enm_addrlo); 618 if (h < 32) 619 hashes[0] |= (1 << h); 620 else 621 hashes[1] |= (1 << (h - 32)); 622 mcnt++; 623 ETHER_NEXT_MULTI(step, enm); 624 } 625 626 if (mcnt) 627 rxfilt |= RL_RXCFG_RX_MULTI; 628 else 629 rxfilt &= ~RL_RXCFG_RX_MULTI; 630 631 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 632 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 633 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 634 635 return; 636 } 637 638 void rl_reset(sc) 639 struct rl_softc *sc; 640 { 641 int i; 642 643 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 644 645 for (i = 0; i < RL_TIMEOUT; i++) { 646 DELAY(10); 647 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 648 break; 649 } 650 if (i == RL_TIMEOUT) 651 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 652 653 return; 654 } 655 656 /* 657 * Attach the interface. Allocate softc structures, do ifmedia 658 * setup and ethernet/BPF attach. 659 */ 660 void 661 rl_attach(sc, eaddr) 662 struct rl_softc *sc; 663 const u_int8_t *eaddr; 664 { 665 666 struct ifnet *ifp; 667 bus_dma_segment_t dmaseg; 668 int error,dmanseg; 669 int i; 670 671 callout_init(&sc->rl_tick_ch); 672 673 if ((error = bus_dmamem_alloc(sc->sc_dmat, 674 RL_RXBUFLEN + 32, NBPG, 0, &dmaseg, 1, &dmanseg, 675 BUS_DMA_NOWAIT)) != 0) { 676 printf("%s: can't allocate recv buffer, error = %d\n", 677 sc->sc_dev.dv_xname, error); 678 goto fail; 679 } 680 681 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 682 RL_RXBUFLEN + 32, (caddr_t *)&sc->rl_cdata.rl_rx_buf, 683 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 684 printf("%s: can't map recv buffer, error = %d\n", 685 sc->sc_dev.dv_xname, error); 686 goto fail; 687 } 688 689 /* Leave a few bytes before the start of the RX ring buffer. */ 690 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 691 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 692 693 if ((error = bus_dmamap_create(sc->sc_dmat, 694 RL_RXBUFLEN + 32 - sizeof(u_int64_t), 1, 695 RL_RXBUFLEN + 32 - sizeof(u_int64_t), 0, BUS_DMA_NOWAIT, 696 &sc->recv_dmamap)) != 0) { 697 printf("%s: can't create recv buffer DMA map, error = %d\n", 698 sc->sc_dev.dv_xname, error); 699 goto fail; 700 } 701 702 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 703 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32 - sizeof(u_int64_t), NULL, 704 BUS_DMA_NOWAIT)) != 0) { 705 printf("%s: can't load recv buffer DMA map, error = %d\n", 706 sc->sc_dev.dv_xname, error); 707 goto fail; 708 } 709 710 for (i = 0; i < RL_TX_LIST_CNT; i++) 711 if ((error = bus_dmamap_create(sc->sc_dmat, 712 MCLBYTES, 1, 713 MCLBYTES, 0, BUS_DMA_NOWAIT, 714 &sc->snd_dmamap[i])) != 0) { 715 printf("%s: can't create snd buffer DMA map," 716 " error = %d\n", sc->sc_dev.dv_xname, error); 717 goto fail; 718 } 719 720 ifp = &sc->ethercom.ec_if; 721 ifp->if_softc = sc; 722 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 723 ifp->if_mtu = ETHERMTU; 724 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 725 ifp->if_ioctl = rl_ioctl; 726 #if 0 727 ifp->if_output = ether_output; 728 #endif 729 ifp->if_start = rl_start; 730 ifp->if_watchdog = rl_watchdog; 731 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 732 733 /* 734 * Do ifmedia setup. 735 */ 736 sc->mii.mii_ifp = ifp; 737 sc->mii.mii_readreg = rl_phy_readreg; 738 sc->mii.mii_writereg = rl_phy_writereg; 739 sc->mii.mii_statchg = rl_phy_statchg; 740 ifmedia_init(&sc->mii.mii_media, 0, rl_ifmedia_upd, rl_ifmedia_sts); 741 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 742 MII_PHY_ANY, MII_OFFSET_ANY, 0); 743 744 /* Choose a default media. */ 745 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 746 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 747 0, NULL); 748 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 749 } else { 750 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 751 } 752 753 /* 754 * Call MI attach routines. 755 */ 756 if_attach(ifp); 757 ether_ifattach(ifp, eaddr); 758 759 #if NBPFILTER > 0 760 bpfattach(&sc->ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 761 sizeof(struct ether_header)); 762 #endif 763 shutdownhook_establish(rl_shutdown, sc); 764 765 fail: 766 return; 767 } 768 769 /* 770 * Initialize the transmit descriptors. 771 */ 772 STATIC int rl_list_tx_init(sc) 773 struct rl_softc *sc; 774 { 775 struct rl_chain_data *cd; 776 int i; 777 778 cd = &sc->rl_cdata; 779 for (i = 0; i < RL_TX_LIST_CNT; i++) { 780 cd->rl_tx_chain[i] = NULL; 781 CSR_WRITE_4(sc, 782 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 783 } 784 785 sc->rl_cdata.cur_tx = 0; 786 sc->rl_cdata.last_tx = 0; 787 788 return(0); 789 } 790 791 /* 792 * A frame has been uploaded: pass the resulting mbuf chain up to 793 * the higher level protocols. 794 * 795 * You know there's something wrong with a PCI bus-master chip design 796 * when you have to use m_devget(). 797 * 798 * The receive operation is badly documented in the datasheet, so I'll 799 * attempt to document it here. The driver provides a buffer area and 800 * places its base address in the RX buffer start address register. 801 * The chip then begins copying frames into the RX buffer. Each frame 802 * is preceeded by a 32-bit RX status word which specifies the length 803 * of the frame and certain other status bits. Each frame (starting with 804 * the status word) is also 32-bit aligned. The frame length is in the 805 * first 16 bits of the status word; the lower 15 bits correspond with 806 * the 'rx status register' mentioned in the datasheet. 807 * 808 * Note: to make the Alpha happy, the frame payload needs to be aligned 809 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 810 * the ring buffer starting at an address two bytes before the actual 811 * data location. We can then shave off the first two bytes using m_adj(). 812 * The reason we do this is because m_devget() doesn't let us specify an 813 * offset into the mbuf storage space, so we have to artificially create 814 * one. The ring is allocated in such a way that there are a few unused 815 * bytes of space preceecing it so that it will be safe for us to do the 816 * 2-byte backstep even if reading from the ring at offset 0. 817 */ 818 STATIC void rl_rxeof(sc) 819 struct rl_softc *sc; 820 { 821 struct ether_header *eh; 822 struct mbuf *m; 823 struct ifnet *ifp; 824 int total_len = 0; 825 u_int32_t rxstat; 826 caddr_t rxbufpos; 827 int wrap = 0; 828 u_int16_t cur_rx; 829 u_int16_t limit; 830 u_int16_t rx_bytes = 0, max_bytes; 831 832 ifp = &sc->ethercom.ec_if; 833 834 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 835 836 /* Do not try to read past this point. */ 837 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 838 839 if (limit < cur_rx) 840 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 841 else 842 max_bytes = limit - cur_rx; 843 844 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 845 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 846 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 847 sizeof(u_int32_t *), BUS_DMASYNC_POSTREAD); 848 rxstat = le32toh(*(u_int32_t *)rxbufpos); 849 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 850 sizeof(u_int32_t *), BUS_DMASYNC_PREREAD); 851 852 /* 853 * Here's a totally undocumented fact for you. When the 854 * RealTek chip is in the process of copying a packet into 855 * RAM for you, the length will be 0xfff0. If you spot a 856 * packet header with this value, you need to stop. The 857 * datasheet makes absolutely no mention of this and 858 * RealTek should be shot for this. 859 */ 860 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 861 break; 862 863 if (!(rxstat & RL_RXSTAT_RXOK)) { 864 ifp->if_ierrors++; 865 866 /* 867 * submitted by:[netbsd-pcmcia:00484] 868 * Takahiro Kambe <taca (at) sky.yamashina.kyoto.jp> 869 * obtain from: 870 * FreeBSD if_rl.c rev 1.24->1.25 871 * 872 */ 873 #if 0 874 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 875 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 876 RL_RXSTAT_ALIGNERR)) { 877 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 878 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 879 RL_RXSTAT_ALIGNERR)) { 880 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB); 881 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB| 882 RL_CMD_RX_ENB); 883 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 884 CSR_WRITE_4(sc, RL_RXADDR, 885 sc->recv_dmamap->dm_segs[0].ds_addr); 886 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 887 cur_rx = 0; 888 } 889 break; 890 #else 891 rl_init(sc); 892 return; 893 #endif 894 } 895 896 /* No errors; receive the packet. */ 897 total_len = rxstat >> 16; 898 rx_bytes += total_len + 4; 899 900 /* 901 * XXX The RealTek chip includes the CRC with every 902 * received frame, and there's no way to turn this 903 * behavior off (at least, I can't find anything in 904 * the manual that explains how to do it) so we have 905 * to trim off the CRC manually. 906 */ 907 total_len -= ETHER_CRC_LEN; 908 909 /* 910 * Avoid trying to read more bytes than we know 911 * the chip has prepared for us. 912 */ 913 if (rx_bytes > max_bytes) 914 break; 915 916 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 917 cur_rx + sizeof(u_int32_t), total_len, BUS_DMASYNC_POSTREAD); 918 919 rxbufpos = sc->rl_cdata.rl_rx_buf + 920 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 921 922 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 923 rxbufpos = sc->rl_cdata.rl_rx_buf; 924 925 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 926 927 if (total_len > wrap) { 928 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 929 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 930 if (m == NULL) { 931 ifp->if_ierrors++; 932 printf("%s: out of mbufs, tried to " 933 "copy %d bytes\n", sc->sc_dev.dv_xname, wrap); 934 } 935 else { 936 m_adj(m, RL_ETHER_ALIGN); 937 m_copyback(m, wrap, total_len - wrap, 938 sc->rl_cdata.rl_rx_buf); 939 } 940 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 941 } else { 942 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 943 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 944 if (m == NULL) { 945 ifp->if_ierrors++; 946 printf("%s: out of mbufs, tried to " 947 "copy %d bytes\n", sc->sc_dev.dv_xname, total_len); 948 } else 949 m_adj(m, RL_ETHER_ALIGN); 950 cur_rx += total_len + 4 + ETHER_CRC_LEN; 951 } 952 953 /* 954 * Round up to 32-bit boundary. 955 */ 956 cur_rx = (cur_rx + 3) & ~3; 957 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 958 959 if (m == NULL) 960 continue; 961 962 eh = mtod(m, struct ether_header *); 963 ifp->if_ipackets++; 964 965 #if NBPFILTER > 0 966 /* 967 * Handle BPF listeners. Let the BPF user see the packet, but 968 * don't pass it up to the ether_input() layer unless it's 969 * a broadcast packet, multicast packet, matches our ethernet 970 * address or the interface is in promiscuous mode. 971 */ 972 if (ifp->if_bpf) { 973 bpf_mtap(ifp->if_bpf, m); 974 if ((ifp->if_flags & IFF_PROMISC) != 0 && 975 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 976 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 977 ETHER_ADDR_LEN) != 0) { 978 m_freem(m); 979 continue; 980 } 981 } 982 #endif 983 /* pass it on. */ 984 (*ifp->if_input)(ifp, m); 985 986 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 987 cur_rx + sizeof(u_int32_t), 988 total_len, BUS_DMASYNC_PREREAD); 989 } 990 991 return; 992 } 993 994 /* 995 * A frame was downloaded to the chip. It's safe for us to clean up 996 * the list buffers. 997 */ 998 STATIC void rl_txeof(sc) 999 struct rl_softc *sc; 1000 { 1001 struct ifnet *ifp; 1002 u_int32_t txstat; 1003 1004 ifp = &sc->ethercom.ec_if; 1005 1006 /* Clear the timeout timer. */ 1007 ifp->if_timer = 0; 1008 1009 /* 1010 * Go through our tx list and free mbufs for those 1011 * frames that have been uploaded. 1012 */ 1013 do { 1014 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1015 if (!(txstat & (RL_TXSTAT_TX_OK| 1016 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1017 break; 1018 1019 bus_dmamap_sync(sc->sc_dmat, 1020 sc->snd_dmamap[sc->rl_cdata.last_tx], 0, 1021 sc->snd_dmamap[sc->rl_cdata.last_tx]->dm_mapsize, 1022 BUS_DMASYNC_POSTWRITE); 1023 bus_dmamap_unload(sc->sc_dmat, 1024 sc->snd_dmamap[sc->rl_cdata.last_tx]); 1025 m_freem(RL_LAST_TXMBUF(sc)); 1026 RL_LAST_TXMBUF(sc) = NULL; 1027 1028 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1029 1030 if (txstat & RL_TXSTAT_TX_OK) 1031 ifp->if_opackets++; 1032 else { 1033 ifp->if_oerrors++; 1034 if ((txstat & RL_TXSTAT_TXABRT) || 1035 (txstat & RL_TXSTAT_OUTOFWIN)) 1036 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1037 } 1038 RL_INC(sc->rl_cdata.last_tx); 1039 ifp->if_flags &= ~IFF_OACTIVE; 1040 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1041 1042 return; 1043 } 1044 1045 int rl_intr(arg) 1046 void *arg; 1047 { 1048 struct rl_softc *sc; 1049 struct ifnet *ifp; 1050 u_int16_t status; 1051 int handled = 0; 1052 1053 sc = arg; 1054 ifp = &sc->ethercom.ec_if; 1055 1056 /* Disable interrupts. */ 1057 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1058 1059 for (;;) { 1060 1061 status = CSR_READ_2(sc, RL_ISR); 1062 if (status) 1063 CSR_WRITE_2(sc, RL_ISR, status); 1064 1065 handled = 1; 1066 1067 if ((status & RL_INTRS) == 0) 1068 break; 1069 1070 if (status & RL_ISR_RX_OK) 1071 rl_rxeof(sc); 1072 1073 if (status & RL_ISR_RX_ERR) 1074 rl_rxeof(sc); 1075 1076 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1077 rl_txeof(sc); 1078 1079 if (status & RL_ISR_SYSTEM_ERR) { 1080 rl_reset(sc); 1081 rl_init(sc); 1082 } 1083 1084 } 1085 1086 /* Re-enable interrupts. */ 1087 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1088 1089 if (ifp->if_snd.ifq_head != NULL) { 1090 rl_start(ifp); 1091 } 1092 1093 return (handled); 1094 } 1095 1096 /* 1097 * Main transmit routine. 1098 */ 1099 1100 STATIC void rl_start(ifp) 1101 struct ifnet *ifp; 1102 { 1103 struct rl_softc *sc; 1104 struct mbuf *m_head = NULL, *m_new; 1105 int error, idx, len; 1106 1107 sc = ifp->if_softc; 1108 1109 while(RL_CUR_TXMBUF(sc) == NULL) { 1110 IF_DEQUEUE(&ifp->if_snd, m_head); 1111 if (m_head == NULL) 1112 break; 1113 1114 idx = sc->rl_cdata.cur_tx; 1115 1116 /* 1117 * Load the DMA map. If this fails, the packet didn't 1118 * fit in one DMA segment, and we need to copy. Note, 1119 * the packet must also be aligned. 1120 */ 1121 if ((mtod(m_head, bus_addr_t) & 3) != 0 || 1122 bus_dmamap_load_mbuf(sc->sc_dmat, sc->snd_dmamap[idx], 1123 m_head, BUS_DMA_NOWAIT) != 0) { 1124 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1125 if (m_new == NULL) { 1126 printf("%s: unable to allocate Tx mbuf\n", 1127 sc->sc_dev.dv_xname); 1128 IF_PREPEND(&ifp->if_snd, m_new); 1129 break; 1130 } 1131 if (m_head->m_pkthdr.len > MHLEN) { 1132 MCLGET(m_new, M_DONTWAIT); 1133 if ((m_new->m_flags & M_EXT) == 0) { 1134 printf("%s: unable to allocate Tx " 1135 "cluster\n", sc->sc_dev.dv_xname); 1136 m_freem(m_new); 1137 IF_PREPEND(&ifp->if_snd, m_head); 1138 break; 1139 } 1140 } 1141 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1142 mtod(m_new, caddr_t)); 1143 m_new->m_pkthdr.len = m_new->m_len = 1144 m_head->m_pkthdr.len; 1145 m_freem(m_head); 1146 m_head = m_new; 1147 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1148 sc->snd_dmamap[idx], m_head, BUS_DMA_NOWAIT); 1149 if (error) { 1150 printf("%s: unable to load Tx buffer, " 1151 "error = %d\n", sc->sc_dev.dv_xname, error); 1152 IF_PREPEND(&ifp->if_snd, m_head); 1153 break; 1154 } 1155 } 1156 1157 RL_CUR_TXMBUF(sc) = m_head; 1158 1159 #if NBPFILTER > 0 1160 /* 1161 * If there's a BPF listener, bounce a copy of this frame 1162 * to him. 1163 */ 1164 if (ifp->if_bpf) 1165 bpf_mtap(ifp->if_bpf, RL_CUR_TXMBUF(sc)); 1166 #endif 1167 /* 1168 * Transmit the frame. 1169 */ 1170 bus_dmamap_sync(sc->sc_dmat, 1171 sc->snd_dmamap[idx], 0, sc->snd_dmamap[idx]->dm_mapsize, 1172 BUS_DMASYNC_PREWRITE); 1173 1174 len = sc->snd_dmamap[idx]->dm_segs[0].ds_len; 1175 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 1176 len = (ETHER_MIN_LEN - ETHER_CRC_LEN); 1177 1178 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1179 sc->snd_dmamap[idx]->dm_segs[0].ds_addr); 1180 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), RL_TX_EARLYTHRESH | len); 1181 1182 RL_INC(sc->rl_cdata.cur_tx); 1183 } 1184 1185 /* 1186 * We broke out of the loop because all our TX slots are 1187 * full. Mark the NIC as busy until it drains some of the 1188 * packets from the queue. 1189 */ 1190 if (RL_CUR_TXMBUF(sc) != NULL) 1191 ifp->if_flags |= IFF_OACTIVE; 1192 1193 /* 1194 * Set a timeout in case the chip goes out to lunch. 1195 */ 1196 ifp->if_timer = 5; 1197 1198 return; 1199 } 1200 1201 STATIC void rl_init(xsc) 1202 void *xsc; 1203 { 1204 struct rl_softc *sc = xsc; 1205 struct ifnet *ifp = &sc->ethercom.ec_if; 1206 int s, i; 1207 u_int32_t rxcfg; 1208 u_int16_t phy_bmcr = 0; 1209 1210 s = splimp(); 1211 1212 /* 1213 * XXX Hack for the 8139: the built-in autoneg logic's state 1214 * gets reset by rl_init() when we don't want it to. Try 1215 * to preserve it. 1216 */ 1217 if (sc->rl_type == RL_8139) 1218 phy_bmcr = rl_phy_readreg((struct device *)sc, 7, MII_BMCR); 1219 1220 /* 1221 * Cancel pending I/O and free all RX/TX buffers. 1222 */ 1223 rl_stop(sc); 1224 1225 /* Init our MAC address */ 1226 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1227 CSR_WRITE_1(sc, RL_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1228 } 1229 1230 /* Init the RX buffer pointer register. */ 1231 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1232 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1233 CSR_WRITE_4(sc, RL_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1234 1235 /* Init TX descriptors. */ 1236 rl_list_tx_init(sc); 1237 1238 /* 1239 * Enable transmit and receive. 1240 */ 1241 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1242 1243 /* 1244 * Set the initial TX and RX configuration. 1245 */ 1246 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1247 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1248 1249 /* Set the individual bit to receive frames for this host only. */ 1250 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1251 rxcfg |= RL_RXCFG_RX_INDIV; 1252 1253 /* If we want promiscuous mode, set the allframes bit. */ 1254 if (ifp->if_flags & IFF_PROMISC) { 1255 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1256 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1257 } else { 1258 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1259 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1260 } 1261 1262 /* 1263 * Set capture broadcast bit to capture broadcast frames. 1264 */ 1265 if (ifp->if_flags & IFF_BROADCAST) { 1266 rxcfg |= RL_RXCFG_RX_BROAD; 1267 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1268 } else { 1269 rxcfg &= ~RL_RXCFG_RX_BROAD; 1270 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1271 } 1272 1273 /* 1274 * Program the multicast filter, if necessary. 1275 */ 1276 rl_setmulti(sc); 1277 1278 /* 1279 * Enable interrupts. 1280 */ 1281 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1282 1283 /* Start RX/TX process. */ 1284 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1285 1286 /* Enable receiver and transmitter. */ 1287 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1288 1289 /* Restore state of BMCR */ 1290 if (sc->rl_type == RL_8139) 1291 rl_phy_writereg((struct device *)sc, 7, MII_BMCR, phy_bmcr); 1292 1293 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1294 1295 /* 1296 * Set current media. 1297 */ 1298 mii_mediachg(&sc->mii); 1299 1300 ifp->if_flags |= IFF_RUNNING; 1301 ifp->if_flags &= ~IFF_OACTIVE; 1302 1303 (void)splx(s); 1304 1305 callout_reset(&sc->rl_tick_ch, hz, rl_tick, sc); 1306 } 1307 1308 /* 1309 * Set media options. 1310 */ 1311 STATIC int rl_ifmedia_upd(ifp) 1312 struct ifnet *ifp; 1313 { 1314 struct rl_softc *sc; 1315 struct ifmedia *ifm; 1316 1317 sc = ifp->if_softc; 1318 ifm = &sc->mii.mii_media; 1319 1320 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1321 return(EINVAL); 1322 1323 return (mii_mediachg(&sc->mii)); 1324 } 1325 1326 /* 1327 * Report current media status. 1328 */ 1329 STATIC void rl_ifmedia_sts(ifp, ifmr) 1330 struct ifnet *ifp; 1331 struct ifmediareq *ifmr; 1332 { 1333 struct rl_softc *sc; 1334 1335 sc = ifp->if_softc; 1336 1337 mii_pollstat(&sc->mii); 1338 ifmr->ifm_status = sc->mii.mii_media_status; 1339 ifmr->ifm_active = sc->mii.mii_media_active; 1340 } 1341 1342 STATIC int 1343 rl_ether_ioctl(ifp, cmd, data) 1344 struct ifnet *ifp; 1345 u_long cmd; 1346 caddr_t data; 1347 { 1348 struct ifaddr *ifa = (struct ifaddr *) data; 1349 struct rl_softc *sc = ifp->if_softc; 1350 1351 switch (cmd) { 1352 case SIOCSIFADDR: 1353 ifp->if_flags |= IFF_UP; 1354 1355 switch (ifa->ifa_addr->sa_family) { 1356 #ifdef INET 1357 case AF_INET: 1358 rl_init(sc); 1359 arp_ifinit(ifp, ifa); 1360 break; 1361 #endif 1362 #ifdef NS 1363 case AF_NS: 1364 { 1365 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1366 1367 if (ns_nullhost(*ina)) 1368 ina->x_host = *(union ns_host *) 1369 LLADDR(ifp->if_sadl); 1370 else 1371 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1372 ifp->if_addrlen); 1373 /* Set new address. */ 1374 rl_init(sc); 1375 break; 1376 } 1377 #endif 1378 default: 1379 rl_init(sc); 1380 break; 1381 } 1382 break; 1383 1384 default: 1385 return (EINVAL); 1386 } 1387 1388 return (0); 1389 } 1390 1391 STATIC int rl_ioctl(ifp, command, data) 1392 struct ifnet *ifp; 1393 u_long command; 1394 caddr_t data; 1395 { 1396 struct rl_softc *sc = ifp->if_softc; 1397 struct ifreq *ifr = (struct ifreq *) data; 1398 int s, error = 0; 1399 1400 s = splimp(); 1401 1402 switch(command) { 1403 case SIOCSIFADDR: 1404 case SIOCGIFADDR: 1405 case SIOCSIFMTU: 1406 error = rl_ether_ioctl(ifp, command, data); 1407 break; 1408 case SIOCSIFFLAGS: 1409 if (ifp->if_flags & IFF_UP) { 1410 rl_init(sc); 1411 } else { 1412 if (ifp->if_flags & IFF_RUNNING) 1413 rl_stop(sc); 1414 } 1415 error = 0; 1416 break; 1417 case SIOCADDMULTI: 1418 case SIOCDELMULTI: 1419 rl_setmulti(sc); 1420 error = 0; 1421 break; 1422 case SIOCGIFMEDIA: 1423 case SIOCSIFMEDIA: 1424 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1425 break; 1426 default: 1427 error = EINVAL; 1428 break; 1429 } 1430 1431 (void)splx(s); 1432 1433 return(error); 1434 } 1435 1436 STATIC void rl_watchdog(ifp) 1437 struct ifnet *ifp; 1438 { 1439 struct rl_softc *sc; 1440 1441 sc = ifp->if_softc; 1442 1443 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1444 ifp->if_oerrors++; 1445 rl_txeof(sc); 1446 rl_rxeof(sc); 1447 rl_init(sc); 1448 1449 return; 1450 } 1451 1452 /* 1453 * Stop the adapter and free any mbufs allocated to the 1454 * RX and TX lists. 1455 */ 1456 STATIC void rl_stop(sc) 1457 struct rl_softc *sc; 1458 { 1459 int i; 1460 struct ifnet *ifp; 1461 1462 ifp = &sc->ethercom.ec_if; 1463 ifp->if_timer = 0; 1464 1465 callout_stop(&sc->rl_tick_ch); 1466 1467 mii_down(&sc->mii); 1468 1469 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1470 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1471 1472 /* 1473 * Free the TX list buffers. 1474 */ 1475 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1476 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1477 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1478 sc->rl_cdata.rl_tx_chain[i] = NULL; 1479 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1480 } 1481 } 1482 1483 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1484 1485 return; 1486 } 1487 1488 /* 1489 * Stop all chip I/O so that the kernel's probe routines don't 1490 * get confused by errant DMAs when rebooting. 1491 */ 1492 STATIC void rl_shutdown(vsc) 1493 void *vsc; 1494 { 1495 struct rl_softc *sc = (struct rl_softc *)vsc; 1496 1497 rl_stop(sc); 1498 1499 return; 1500 } 1501 1502 STATIC void 1503 rl_tick(arg) 1504 void *arg; 1505 { 1506 struct rl_softc *sc = arg; 1507 int s = splnet(); 1508 1509 mii_tick(&sc->mii); 1510 splx(s); 1511 1512 callout_reset(&sc->rl_tick_ch, hz, rl_tick, sc); 1513 } 1514
Indexes created Thu Sep 25 16:09:42 GMT 2025