rtl81x9.c revision 1.6
1 /* $NetBSD: rtl81x9.c,v 1.6 2000/05/01 15:08:55 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include "opt_inet.h" 89 #include "opt_ns.h" 90 #include "bpfilter.h" 91 #include "rnd.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/callout.h> 96 #include <sys/device.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/if_inarp.h> 111 #endif 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #if NBPFILTER > 0 118 #include <net/bpf.h> 119 #endif 120 #if NRND > 0 121 #include <sys/rnd.h> 122 #endif 123 124 #include <machine/bus.h> 125 #include <machine/endian.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 130 /* 131 * Default to using PIO access for this driver. On SMP systems, 132 * there appear to be problems with memory mapped mode: it looks like 133 * doing too many memory mapped access back to back in rapid succession 134 * can hang the bus. I'm inclined to blame this on crummy design/construction 135 * on the part of RealTek. Memory mapped mode does appear to work on 136 * uniprocessor systems though. 137 */ 138 139 #include <dev/ic/rtl81x9reg.h> 140 #include <dev/ic/rtl81x9var.h> 141 142 #if defined DEBUG 143 #define STATIC 144 #else 145 #define STATIC static 146 #endif 147 148 STATIC void rl_reset __P((struct rl_softc *)); 149 STATIC void rl_rxeof __P((struct rl_softc *)); 150 STATIC void rl_txeof __P((struct rl_softc *)); 151 STATIC void rl_start __P((struct ifnet *)); 152 STATIC int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 153 STATIC void rl_init __P((void *)); 154 STATIC void rl_stop __P((struct rl_softc *)); 155 STATIC void rl_watchdog __P((struct ifnet *)); 156 STATIC void rl_shutdown __P((void *)); 157 STATIC int rl_ifmedia_upd __P((struct ifnet *)); 158 STATIC void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 159 160 STATIC u_int16_t rl_read_eeprom __P((struct rl_softc *, int, int)); 161 STATIC void rl_eeprom_putbyte __P((struct rl_softc *, int, int)); 162 STATIC void rl_mii_sync __P((struct rl_softc *)); 163 STATIC void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 164 STATIC int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 165 STATIC int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 166 167 STATIC int rl_phy_readreg __P((struct device *, int, int)); 168 STATIC void rl_phy_writereg __P((struct device *, int, int, int)); 169 STATIC void rl_phy_statchg __P((struct device *)); 170 STATIC void rl_tick __P((void *)); 171 172 STATIC u_int8_t rl_calchash __P((caddr_t)); 173 STATIC void rl_setmulti __P((struct rl_softc *)); 174 STATIC int rl_list_tx_init __P((struct rl_softc *)); 175 176 STATIC int rl_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 177 178 179 #define EE_SET(x) \ 180 CSR_WRITE_1(sc, RL_EECMD, \ 181 CSR_READ_1(sc, RL_EECMD) | (x)) 182 183 #define EE_CLR(x) \ 184 CSR_WRITE_1(sc, RL_EECMD, \ 185 CSR_READ_1(sc, RL_EECMD) & ~(x)) 186 187 /* 188 * Send a read command and address to the EEPROM, check for ACK. 189 */ 190 STATIC void rl_eeprom_putbyte(sc, addr, addr_len) 191 struct rl_softc *sc; 192 int addr, addr_len; 193 { 194 int d, i; 195 196 d = (RL_EECMD_READ << addr_len) | addr; 197 198 /* 199 * Feed in each bit and stobe the clock. 200 */ 201 for (i = RL_EECMD_LEN + addr_len - 1; i >= 0; i--) { 202 if (d & (1 << i)) { 203 EE_SET(RL_EE_DATAIN); 204 } else { 205 EE_CLR(RL_EE_DATAIN); 206 } 207 DELAY(100); 208 EE_SET(RL_EE_CLK); 209 DELAY(150); 210 EE_CLR(RL_EE_CLK); 211 DELAY(100); 212 } 213 } 214 215 /* 216 * Read a word of data stored in the EEPROM at address 'addr.' 217 */ 218 u_int16_t rl_read_eeprom(sc, addr, addr_len) 219 struct rl_softc *sc; 220 int addr, addr_len; 221 { 222 u_int16_t word = 0; 223 int i; 224 225 /* Enter EEPROM access mode. */ 226 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 227 228 /* 229 * Send address of word we want to read. 230 */ 231 rl_eeprom_putbyte(sc, addr, addr_len); 232 233 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 234 235 /* 236 * Start reading bits from EEPROM. 237 */ 238 for (i = 15; i >= 0; i--) { 239 EE_SET(RL_EE_CLK); 240 DELAY(100); 241 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 242 word |= (1 << i); 243 EE_CLR(RL_EE_CLK); 244 DELAY(100); 245 } 246 247 /* Turn off EEPROM access mode. */ 248 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 249 250 return (word); 251 } 252 253 /* 254 * MII access routines are provided for the 8129, which 255 * doesn't have a built-in PHY. For the 8139, we fake things 256 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 257 * direct access PHY registers. 258 */ 259 #define MII_SET(x) \ 260 CSR_WRITE_1(sc, RL_MII, \ 261 CSR_READ_1(sc, RL_MII) | (x)) 262 263 #define MII_CLR(x) \ 264 CSR_WRITE_1(sc, RL_MII, \ 265 CSR_READ_1(sc, RL_MII) & ~(x)) 266 267 /* 268 * Sync the PHYs by setting data bit and strobing the clock 32 times. 269 */ 270 STATIC void rl_mii_sync(sc) 271 struct rl_softc *sc; 272 { 273 int i; 274 275 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 276 277 for (i = 0; i < 32; i++) { 278 MII_SET(RL_MII_CLK); 279 DELAY(1); 280 MII_CLR(RL_MII_CLK); 281 DELAY(1); 282 } 283 284 return; 285 } 286 287 /* 288 * Clock a series of bits through the MII. 289 */ 290 STATIC void rl_mii_send(sc, bits, cnt) 291 struct rl_softc *sc; 292 u_int32_t bits; 293 int cnt; 294 { 295 int i; 296 297 MII_CLR(RL_MII_CLK); 298 299 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 300 if (bits & i) { 301 MII_SET(RL_MII_DATAOUT); 302 } else { 303 MII_CLR(RL_MII_DATAOUT); 304 } 305 DELAY(1); 306 MII_CLR(RL_MII_CLK); 307 DELAY(1); 308 MII_SET(RL_MII_CLK); 309 } 310 } 311 312 /* 313 * Read an PHY register through the MII. 314 */ 315 STATIC int rl_mii_readreg(sc, frame) 316 struct rl_softc *sc; 317 struct rl_mii_frame *frame; 318 319 { 320 int i, ack, s; 321 322 s = splimp(); 323 324 /* 325 * Set up frame for RX. 326 */ 327 frame->mii_stdelim = RL_MII_STARTDELIM; 328 frame->mii_opcode = RL_MII_READOP; 329 frame->mii_turnaround = 0; 330 frame->mii_data = 0; 331 332 CSR_WRITE_2(sc, RL_MII, 0); 333 334 /* 335 * Turn on data xmit. 336 */ 337 MII_SET(RL_MII_DIR); 338 339 rl_mii_sync(sc); 340 341 /* 342 * Send command/address info. 343 */ 344 rl_mii_send(sc, frame->mii_stdelim, 2); 345 rl_mii_send(sc, frame->mii_opcode, 2); 346 rl_mii_send(sc, frame->mii_phyaddr, 5); 347 rl_mii_send(sc, frame->mii_regaddr, 5); 348 349 /* Idle bit */ 350 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 351 DELAY(1); 352 MII_SET(RL_MII_CLK); 353 DELAY(1); 354 355 /* Turn off xmit. */ 356 MII_CLR(RL_MII_DIR); 357 358 /* Check for ack */ 359 MII_CLR(RL_MII_CLK); 360 DELAY(1); 361 MII_SET(RL_MII_CLK); 362 DELAY(1); 363 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 364 365 /* 366 * Now try reading data bits. If the ack failed, we still 367 * need to clock through 16 cycles to keep the PHY(s) in sync. 368 */ 369 if (ack) { 370 for(i = 0; i < 16; i++) { 371 MII_CLR(RL_MII_CLK); 372 DELAY(1); 373 MII_SET(RL_MII_CLK); 374 DELAY(1); 375 } 376 goto fail; 377 } 378 379 for (i = 0x8000; i; i >>= 1) { 380 MII_CLR(RL_MII_CLK); 381 DELAY(1); 382 if (!ack) { 383 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 384 frame->mii_data |= i; 385 DELAY(1); 386 } 387 MII_SET(RL_MII_CLK); 388 DELAY(1); 389 } 390 391 fail: 392 393 MII_CLR(RL_MII_CLK); 394 DELAY(1); 395 MII_SET(RL_MII_CLK); 396 DELAY(1); 397 398 splx(s); 399 400 if (ack) 401 return(1); 402 return(0); 403 } 404 405 /* 406 * Write to a PHY register through the MII. 407 */ 408 STATIC int rl_mii_writereg(sc, frame) 409 struct rl_softc *sc; 410 struct rl_mii_frame *frame; 411 412 { 413 int s; 414 415 s = splimp(); 416 /* 417 * Set up frame for TX. 418 */ 419 420 frame->mii_stdelim = RL_MII_STARTDELIM; 421 frame->mii_opcode = RL_MII_WRITEOP; 422 frame->mii_turnaround = RL_MII_TURNAROUND; 423 424 /* 425 * Turn on data output. 426 */ 427 MII_SET(RL_MII_DIR); 428 429 rl_mii_sync(sc); 430 431 rl_mii_send(sc, frame->mii_stdelim, 2); 432 rl_mii_send(sc, frame->mii_opcode, 2); 433 rl_mii_send(sc, frame->mii_phyaddr, 5); 434 rl_mii_send(sc, frame->mii_regaddr, 5); 435 rl_mii_send(sc, frame->mii_turnaround, 2); 436 rl_mii_send(sc, frame->mii_data, 16); 437 438 /* Idle bit. */ 439 MII_SET(RL_MII_CLK); 440 DELAY(1); 441 MII_CLR(RL_MII_CLK); 442 DELAY(1); 443 444 /* 445 * Turn off xmit. 446 */ 447 MII_CLR(RL_MII_DIR); 448 449 splx(s); 450 451 return(0); 452 } 453 454 STATIC int rl_phy_readreg(self, phy, reg) 455 struct device *self; 456 int phy, reg; 457 { 458 struct rl_softc *sc = (void *)self; 459 struct rl_mii_frame frame; 460 u_int16_t rval = 0; 461 u_int16_t rl8139_reg = 0; 462 463 if (sc->rl_type == RL_8139) { 464 if (phy != 7) 465 return (0); 466 467 switch(reg) { 468 case MII_BMCR: 469 rl8139_reg = RL_BMCR; 470 break; 471 case MII_BMSR: 472 rl8139_reg = RL_BMSR; 473 break; 474 case MII_ANAR: 475 rl8139_reg = RL_ANAR; 476 break; 477 case MII_ANLPAR: 478 rl8139_reg = RL_LPAR; 479 break; 480 default: 481 #if 0 482 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 483 #endif 484 return(0); 485 } 486 rval = CSR_READ_2(sc, rl8139_reg); 487 return(rval); 488 } 489 490 bzero((char *)&frame, sizeof(frame)); 491 492 frame.mii_phyaddr = phy; 493 frame.mii_regaddr = reg; 494 rl_mii_readreg(sc, &frame); 495 496 return(frame.mii_data); 497 } 498 499 STATIC void rl_phy_writereg(self, phy, reg, data) 500 struct device *self; 501 int phy, reg; 502 int data; 503 { 504 struct rl_softc *sc = (void *)self; 505 struct rl_mii_frame frame; 506 u_int16_t rl8139_reg = 0; 507 508 if (sc->rl_type == RL_8139) { 509 if (phy != 7) 510 return; 511 512 switch(reg) { 513 case MII_BMCR: 514 rl8139_reg = RL_BMCR; 515 break; 516 case MII_BMSR: 517 rl8139_reg = RL_BMSR; 518 break; 519 case MII_ANAR: 520 rl8139_reg = RL_ANAR; 521 break; 522 case MII_ANLPAR: 523 rl8139_reg = RL_LPAR; 524 break; 525 default: 526 #if 0 527 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 528 #endif 529 return; 530 } 531 CSR_WRITE_2(sc, rl8139_reg, data); 532 return; 533 } 534 535 bzero((char *)&frame, sizeof(frame)); 536 537 frame.mii_phyaddr = phy; 538 frame.mii_regaddr = reg; 539 frame.mii_data = data; 540 541 rl_mii_writereg(sc, &frame); 542 543 return; 544 } 545 546 STATIC void 547 rl_phy_statchg(v) 548 struct device *v; 549 { 550 551 /* Nothing to do. */ 552 } 553 554 /* 555 * Calculate CRC of a multicast group address, return the upper 6 bits. 556 */ 557 STATIC u_int8_t rl_calchash(addr) 558 caddr_t addr; 559 { 560 u_int32_t crc, carry; 561 int i, j; 562 u_int8_t c; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xFFFFFFFF; /* initial value */ 566 567 for (i = 0; i < 6; i++) { 568 c = *(addr + i); 569 for (j = 0; j < 8; j++) { 570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 571 crc <<= 1; 572 c >>= 1; 573 if (carry) 574 crc = (crc ^ 0x04c11db6) | carry; 575 } 576 } 577 578 /* return the filter bit position */ 579 return(crc >> 26); 580 } 581 582 /* 583 * Program the 64-bit multicast hash filter. 584 */ 585 STATIC void rl_setmulti(sc) 586 struct rl_softc *sc; 587 { 588 struct ifnet *ifp; 589 int h = 0; 590 u_int32_t hashes[2] = { 0, 0 }; 591 u_int32_t rxfilt; 592 int mcnt = 0; 593 struct ether_multi *enm; 594 struct ether_multistep step; 595 596 ifp = &sc->ethercom.ec_if; 597 598 rxfilt = CSR_READ_4(sc, RL_RXCFG); 599 600 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 601 rxfilt |= RL_RXCFG_RX_MULTI; 602 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 603 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 604 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 605 return; 606 } 607 608 /* first, zot all the existing hash bits */ 609 CSR_WRITE_4(sc, RL_MAR0, 0); 610 CSR_WRITE_4(sc, RL_MAR4, 0); 611 612 /* now program new ones */ 613 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 614 while (enm != NULL) { 615 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 616 ETHER_ADDR_LEN) != 0) 617 continue; 618 619 h = rl_calchash(enm->enm_addrlo); 620 if (h < 32) 621 hashes[0] |= (1 << h); 622 else 623 hashes[1] |= (1 << (h - 32)); 624 mcnt++; 625 ETHER_NEXT_MULTI(step, enm); 626 } 627 628 if (mcnt) 629 rxfilt |= RL_RXCFG_RX_MULTI; 630 else 631 rxfilt &= ~RL_RXCFG_RX_MULTI; 632 633 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 634 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 635 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 636 637 return; 638 } 639 640 void rl_reset(sc) 641 struct rl_softc *sc; 642 { 643 int i; 644 645 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 646 647 for (i = 0; i < RL_TIMEOUT; i++) { 648 DELAY(10); 649 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 650 break; 651 } 652 if (i == RL_TIMEOUT) 653 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 654 655 return; 656 } 657 658 /* 659 * Attach the interface. Allocate softc structures, do ifmedia 660 * setup and ethernet/BPF attach. 661 */ 662 void 663 rl_attach(sc) 664 struct rl_softc *sc; 665 { 666 667 struct ifnet *ifp; 668 u_int16_t val; 669 u_int8_t eaddr[ETHER_ADDR_LEN]; 670 bus_dma_segment_t dmaseg; 671 int error,dmanseg; 672 int i,addr_len; 673 674 callout_init(&sc->rl_tick_ch); 675 676 /* 677 * Check EEPROM type 9346 or 9356. 678 */ 679 if (rl_read_eeprom(sc, RL_EE_ID, RL_EEADDR_LEN1) == 0x8129) 680 addr_len = RL_EEADDR_LEN1; 681 else 682 addr_len = RL_EEADDR_LEN0; 683 684 /* 685 * Get station address. 686 */ 687 val = rl_read_eeprom(sc, RL_EE_EADDR0, addr_len); 688 eaddr[0] = val & 0xff; 689 eaddr[1] = val >> 8; 690 val = rl_read_eeprom(sc, RL_EE_EADDR1, addr_len); 691 eaddr[2] = val & 0xff; 692 eaddr[3] = val >> 8; 693 val = rl_read_eeprom(sc, RL_EE_EADDR2, addr_len); 694 eaddr[4] = val & 0xff; 695 eaddr[5] = val >> 8; 696 697 if ((error = bus_dmamem_alloc(sc->sc_dmat, 698 RL_RXBUFLEN + 32, NBPG, 0, &dmaseg, 1, &dmanseg, 699 BUS_DMA_NOWAIT)) != 0) { 700 printf("%s: can't allocate recv buffer, error = %d\n", 701 sc->sc_dev.dv_xname, error); 702 goto fail; 703 } 704 705 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 706 RL_RXBUFLEN + 32, (caddr_t *)&sc->rl_cdata.rl_rx_buf, 707 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 708 printf("%s: can't map recv buffer, error = %d\n", 709 sc->sc_dev.dv_xname, error); 710 goto fail; 711 } 712 713 /* Leave a few bytes before the start of the RX ring buffer. */ 714 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 715 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 716 717 if ((error = bus_dmamap_create(sc->sc_dmat, 718 RL_RXBUFLEN + 32 - sizeof(u_int64_t), 1, 719 RL_RXBUFLEN + 32 - sizeof(u_int64_t), 0, BUS_DMA_NOWAIT, 720 &sc->recv_dmamap)) != 0) { 721 printf("%s: can't create recv buffer DMA map, error = %d\n", 722 sc->sc_dev.dv_xname, error); 723 goto fail; 724 } 725 726 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 727 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32 - sizeof(u_int64_t), NULL, 728 BUS_DMA_NOWAIT)) != 0) { 729 printf("%s: can't load recv buffer DMA map, error = %d\n", 730 sc->sc_dev.dv_xname, error); 731 goto fail; 732 } 733 734 for (i = 0; i < RL_TX_LIST_CNT; i++) 735 if ((error = bus_dmamap_create(sc->sc_dmat, 736 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 737 &sc->snd_dmamap[i])) != 0) { 738 printf("%s: can't create snd buffer DMA map," 739 " error = %d\n", sc->sc_dev.dv_xname, error); 740 goto fail; 741 } 742 743 /* Reset the adapter. */ 744 rl_reset(sc); 745 746 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 747 ether_sprintf(eaddr)); 748 749 ifp = &sc->ethercom.ec_if; 750 ifp->if_softc = sc; 751 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 752 ifp->if_mtu = ETHERMTU; 753 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 754 ifp->if_ioctl = rl_ioctl; 755 #if 0 756 ifp->if_output = ether_output; 757 #endif 758 ifp->if_start = rl_start; 759 ifp->if_watchdog = rl_watchdog; 760 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 761 762 /* 763 * Do ifmedia setup. 764 */ 765 sc->mii.mii_ifp = ifp; 766 sc->mii.mii_readreg = rl_phy_readreg; 767 sc->mii.mii_writereg = rl_phy_writereg; 768 sc->mii.mii_statchg = rl_phy_statchg; 769 ifmedia_init(&sc->mii.mii_media, 0, rl_ifmedia_upd, rl_ifmedia_sts); 770 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 771 MII_PHY_ANY, MII_OFFSET_ANY, 0); 772 773 /* Choose a default media. */ 774 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 775 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 776 0, NULL); 777 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 778 } else { 779 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 780 } 781 782 /* 783 * Call MI attach routines. 784 */ 785 if_attach(ifp); 786 ether_ifattach(ifp, eaddr); 787 788 #if NBPFILTER > 0 789 bpfattach(&sc->ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 790 sizeof(struct ether_header)); 791 #endif 792 shutdownhook_establish(rl_shutdown, sc); 793 794 fail: 795 return; 796 } 797 798 /* 799 * Initialize the transmit descriptors. 800 */ 801 STATIC int rl_list_tx_init(sc) 802 struct rl_softc *sc; 803 { 804 struct rl_chain_data *cd; 805 int i; 806 807 cd = &sc->rl_cdata; 808 for (i = 0; i < RL_TX_LIST_CNT; i++) { 809 cd->rl_tx_chain[i] = NULL; 810 CSR_WRITE_4(sc, 811 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 812 } 813 814 sc->rl_cdata.cur_tx = 0; 815 sc->rl_cdata.last_tx = 0; 816 817 return(0); 818 } 819 820 /* 821 * A frame has been uploaded: pass the resulting mbuf chain up to 822 * the higher level protocols. 823 * 824 * You know there's something wrong with a PCI bus-master chip design 825 * when you have to use m_devget(). 826 * 827 * The receive operation is badly documented in the datasheet, so I'll 828 * attempt to document it here. The driver provides a buffer area and 829 * places its base address in the RX buffer start address register. 830 * The chip then begins copying frames into the RX buffer. Each frame 831 * is preceeded by a 32-bit RX status word which specifies the length 832 * of the frame and certain other status bits. Each frame (starting with 833 * the status word) is also 32-bit aligned. The frame length is in the 834 * first 16 bits of the status word; the lower 15 bits correspond with 835 * the 'rx status register' mentioned in the datasheet. 836 * 837 * Note: to make the Alpha happy, the frame payload needs to be aligned 838 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 839 * the ring buffer starting at an address two bytes before the actual 840 * data location. We can then shave off the first two bytes using m_adj(). 841 * The reason we do this is because m_devget() doesn't let us specify an 842 * offset into the mbuf storage space, so we have to artificially create 843 * one. The ring is allocated in such a way that there are a few unused 844 * bytes of space preceecing it so that it will be safe for us to do the 845 * 2-byte backstep even if reading from the ring at offset 0. 846 */ 847 STATIC void rl_rxeof(sc) 848 struct rl_softc *sc; 849 { 850 struct ether_header *eh; 851 struct mbuf *m; 852 struct ifnet *ifp; 853 int total_len = 0; 854 u_int32_t rxstat; 855 caddr_t rxbufpos; 856 int wrap = 0; 857 u_int16_t cur_rx; 858 u_int16_t limit; 859 u_int16_t rx_bytes = 0, max_bytes; 860 861 ifp = &sc->ethercom.ec_if; 862 863 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 864 865 /* Do not try to read past this point. */ 866 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 867 868 if (limit < cur_rx) 869 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 870 else 871 max_bytes = limit - cur_rx; 872 873 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 874 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 875 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 876 sizeof(u_int32_t *), BUS_DMASYNC_POSTREAD); 877 rxstat = le32toh(*(u_int32_t *)rxbufpos); 878 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 879 sizeof(u_int32_t *), BUS_DMASYNC_PREREAD); 880 881 /* 882 * Here's a totally undocumented fact for you. When the 883 * RealTek chip is in the process of copying a packet into 884 * RAM for you, the length will be 0xfff0. If you spot a 885 * packet header with this value, you need to stop. The 886 * datasheet makes absolutely no mention of this and 887 * RealTek should be shot for this. 888 */ 889 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 890 break; 891 892 if (!(rxstat & RL_RXSTAT_RXOK)) { 893 ifp->if_ierrors++; 894 895 /* 896 * submitted by:[netbsd-pcmcia:00484] 897 * Takahiro Kambe <taca (at) sky.yamashina.kyoto.jp> 898 * obtain from: 899 * FreeBSD if_rl.c rev 1.24->1.25 900 * 901 */ 902 #if 0 903 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 904 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 905 RL_RXSTAT_ALIGNERR)) { 906 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 907 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 908 RL_RXSTAT_ALIGNERR)) { 909 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB); 910 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB| 911 RL_CMD_RX_ENB); 912 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 913 CSR_WRITE_4(sc, RL_RXADDR, 914 sc->recv_dmamap->dm_segs[0].ds_addr); 915 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 916 cur_rx = 0; 917 } 918 break; 919 #else 920 rl_init(sc); 921 return; 922 #endif 923 } 924 925 /* No errors; receive the packet. */ 926 total_len = rxstat >> 16; 927 rx_bytes += total_len + 4; 928 929 /* 930 * XXX The RealTek chip includes the CRC with every 931 * received frame, and there's no way to turn this 932 * behavior off (at least, I can't find anything in 933 * the manual that explains how to do it) so we have 934 * to trim off the CRC manually. 935 */ 936 total_len -= ETHER_CRC_LEN; 937 938 /* 939 * Avoid trying to read more bytes than we know 940 * the chip has prepared for us. 941 */ 942 if (rx_bytes > max_bytes) 943 break; 944 945 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 946 cur_rx + sizeof(u_int32_t), total_len, 947 BUS_DMASYNC_POSTREAD); 948 949 rxbufpos = sc->rl_cdata.rl_rx_buf + 950 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 951 952 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 953 rxbufpos = sc->rl_cdata.rl_rx_buf; 954 955 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 956 957 if (total_len > wrap) { 958 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 959 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 960 if (m == NULL) { 961 ifp->if_ierrors++; 962 printf("%s: out of mbufs, tried to " 963 "copy %d bytes\n", sc->sc_dev.dv_xname, 964 wrap); 965 } 966 else { 967 m_adj(m, RL_ETHER_ALIGN); 968 m_copyback(m, wrap, total_len - wrap, 969 sc->rl_cdata.rl_rx_buf); 970 } 971 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 972 } else { 973 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 974 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 975 if (m == NULL) { 976 ifp->if_ierrors++; 977 printf("%s: out of mbufs, tried to " 978 "copy %d bytes\n", sc->sc_dev.dv_xname, 979 total_len); 980 } else 981 m_adj(m, RL_ETHER_ALIGN); 982 cur_rx += total_len + 4 + ETHER_CRC_LEN; 983 } 984 985 /* 986 * Round up to 32-bit boundary. 987 */ 988 cur_rx = (cur_rx + 3) & ~3; 989 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 990 991 if (m == NULL) 992 continue; 993 994 eh = mtod(m, struct ether_header *); 995 ifp->if_ipackets++; 996 997 #if NBPFILTER > 0 998 /* 999 * Handle BPF listeners. Let the BPF user see the packet, but 1000 * don't pass it up to the ether_input() layer unless it's 1001 * a broadcast packet, multicast packet, matches our ethernet 1002 * address or the interface is in promiscuous mode. 1003 */ 1004 if (ifp->if_bpf) { 1005 bpf_mtap(ifp->if_bpf, m); 1006 if ((ifp->if_flags & IFF_PROMISC) != 0 && 1007 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 1008 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 1009 ETHER_ADDR_LEN) != 0) { 1010 m_freem(m); 1011 continue; 1012 } 1013 } 1014 #endif 1015 /* pass it on. */ 1016 (*ifp->if_input)(ifp, m); 1017 1018 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1019 cur_rx + sizeof(u_int32_t), 1020 total_len, BUS_DMASYNC_PREREAD); 1021 } 1022 1023 return; 1024 } 1025 1026 /* 1027 * A frame was downloaded to the chip. It's safe for us to clean up 1028 * the list buffers. 1029 */ 1030 STATIC void rl_txeof(sc) 1031 struct rl_softc *sc; 1032 { 1033 struct ifnet *ifp; 1034 u_int32_t txstat; 1035 1036 ifp = &sc->ethercom.ec_if; 1037 1038 /* Clear the timeout timer. */ 1039 ifp->if_timer = 0; 1040 1041 /* 1042 * Go through our tx list and free mbufs for those 1043 * frames that have been uploaded. 1044 */ 1045 do { 1046 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1047 if (!(txstat & (RL_TXSTAT_TX_OK| 1048 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1049 break; 1050 1051 bus_dmamap_sync(sc->sc_dmat, 1052 sc->snd_dmamap[sc->rl_cdata.last_tx], 0, 1053 sc->snd_dmamap[sc->rl_cdata.last_tx]->dm_mapsize, 1054 BUS_DMASYNC_POSTWRITE); 1055 bus_dmamap_unload(sc->sc_dmat, 1056 sc->snd_dmamap[sc->rl_cdata.last_tx]); 1057 m_freem(RL_LAST_TXMBUF(sc)); 1058 RL_LAST_TXMBUF(sc) = NULL; 1059 1060 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1061 1062 if (txstat & RL_TXSTAT_TX_OK) 1063 ifp->if_opackets++; 1064 else { 1065 ifp->if_oerrors++; 1066 if ((txstat & RL_TXSTAT_TXABRT) || 1067 (txstat & RL_TXSTAT_OUTOFWIN)) 1068 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1069 } 1070 RL_INC(sc->rl_cdata.last_tx); 1071 ifp->if_flags &= ~IFF_OACTIVE; 1072 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1073 1074 return; 1075 } 1076 1077 int rl_intr(arg) 1078 void *arg; 1079 { 1080 struct rl_softc *sc; 1081 struct ifnet *ifp; 1082 u_int16_t status; 1083 int handled = 0; 1084 1085 sc = arg; 1086 ifp = &sc->ethercom.ec_if; 1087 1088 /* Disable interrupts. */ 1089 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1090 1091 for (;;) { 1092 1093 status = CSR_READ_2(sc, RL_ISR); 1094 if (status) 1095 CSR_WRITE_2(sc, RL_ISR, status); 1096 1097 handled = 1; 1098 1099 if ((status & RL_INTRS) == 0) 1100 break; 1101 1102 if (status & RL_ISR_RX_OK) 1103 rl_rxeof(sc); 1104 1105 if (status & RL_ISR_RX_ERR) 1106 rl_rxeof(sc); 1107 1108 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1109 rl_txeof(sc); 1110 1111 if (status & RL_ISR_SYSTEM_ERR) { 1112 rl_reset(sc); 1113 rl_init(sc); 1114 } 1115 1116 } 1117 1118 /* Re-enable interrupts. */ 1119 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1120 1121 if (ifp->if_snd.ifq_head != NULL) { 1122 rl_start(ifp); 1123 } 1124 1125 return (handled); 1126 } 1127 1128 /* 1129 * Main transmit routine. 1130 */ 1131 1132 STATIC void rl_start(ifp) 1133 struct ifnet *ifp; 1134 { 1135 struct rl_softc *sc; 1136 struct mbuf *m_head = NULL, *m_new; 1137 int error, idx, len; 1138 1139 sc = ifp->if_softc; 1140 1141 while(RL_CUR_TXMBUF(sc) == NULL) { 1142 IF_DEQUEUE(&ifp->if_snd, m_head); 1143 if (m_head == NULL) 1144 break; 1145 1146 idx = sc->rl_cdata.cur_tx; 1147 1148 /* 1149 * Load the DMA map. If this fails, the packet didn't 1150 * fit in one DMA segment, and we need to copy. Note, 1151 * the packet must also be aligned. 1152 */ 1153 if ((mtod(m_head, bus_addr_t) & 3) != 0 || 1154 bus_dmamap_load_mbuf(sc->sc_dmat, sc->snd_dmamap[idx], 1155 m_head, BUS_DMA_NOWAIT) != 0) { 1156 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1157 if (m_new == NULL) { 1158 printf("%s: unable to allocate Tx mbuf\n", 1159 sc->sc_dev.dv_xname); 1160 IF_PREPEND(&ifp->if_snd, m_new); 1161 break; 1162 } 1163 if (m_head->m_pkthdr.len > MHLEN) { 1164 MCLGET(m_new, M_DONTWAIT); 1165 if ((m_new->m_flags & M_EXT) == 0) { 1166 printf("%s: unable to allocate Tx " 1167 "cluster\n", sc->sc_dev.dv_xname); 1168 m_freem(m_new); 1169 IF_PREPEND(&ifp->if_snd, m_head); 1170 break; 1171 } 1172 } 1173 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1174 mtod(m_new, caddr_t)); 1175 m_new->m_pkthdr.len = m_new->m_len = 1176 m_head->m_pkthdr.len; 1177 m_freem(m_head); 1178 m_head = m_new; 1179 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1180 sc->snd_dmamap[idx], m_head, BUS_DMA_NOWAIT); 1181 if (error) { 1182 printf("%s: unable to load Tx buffer, " 1183 "error = %d\n", sc->sc_dev.dv_xname, error); 1184 IF_PREPEND(&ifp->if_snd, m_head); 1185 break; 1186 } 1187 } 1188 1189 RL_CUR_TXMBUF(sc) = m_head; 1190 1191 #if NBPFILTER > 0 1192 /* 1193 * If there's a BPF listener, bounce a copy of this frame 1194 * to him. 1195 */ 1196 if (ifp->if_bpf) 1197 bpf_mtap(ifp->if_bpf, RL_CUR_TXMBUF(sc)); 1198 #endif 1199 /* 1200 * Transmit the frame. 1201 */ 1202 bus_dmamap_sync(sc->sc_dmat, 1203 sc->snd_dmamap[idx], 0, sc->snd_dmamap[idx]->dm_mapsize, 1204 BUS_DMASYNC_PREWRITE); 1205 1206 len = sc->snd_dmamap[idx]->dm_segs[0].ds_len; 1207 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 1208 len = (ETHER_MIN_LEN - ETHER_CRC_LEN); 1209 1210 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1211 sc->snd_dmamap[idx]->dm_segs[0].ds_addr); 1212 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), RL_TX_EARLYTHRESH | len); 1213 1214 RL_INC(sc->rl_cdata.cur_tx); 1215 } 1216 1217 /* 1218 * We broke out of the loop because all our TX slots are 1219 * full. Mark the NIC as busy until it drains some of the 1220 * packets from the queue. 1221 */ 1222 if (RL_CUR_TXMBUF(sc) != NULL) 1223 ifp->if_flags |= IFF_OACTIVE; 1224 1225 /* 1226 * Set a timeout in case the chip goes out to lunch. 1227 */ 1228 ifp->if_timer = 5; 1229 1230 return; 1231 } 1232 1233 STATIC void rl_init(xsc) 1234 void *xsc; 1235 { 1236 struct rl_softc *sc = xsc; 1237 struct ifnet *ifp = &sc->ethercom.ec_if; 1238 int s, i; 1239 u_int32_t rxcfg; 1240 u_int16_t phy_bmcr = 0; 1241 1242 s = splimp(); 1243 1244 /* 1245 * XXX Hack for the 8139: the built-in autoneg logic's state 1246 * gets reset by rl_init() when we don't want it to. Try 1247 * to preserve it. 1248 */ 1249 if (sc->rl_type == RL_8139) 1250 phy_bmcr = rl_phy_readreg((struct device *)sc, 7, MII_BMCR); 1251 1252 /* 1253 * Cancel pending I/O and free all RX/TX buffers. 1254 */ 1255 rl_stop(sc); 1256 1257 /* Init our MAC address */ 1258 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1259 CSR_WRITE_1(sc, RL_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1260 } 1261 1262 /* Init the RX buffer pointer register. */ 1263 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1264 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1265 CSR_WRITE_4(sc, RL_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1266 1267 /* Init TX descriptors. */ 1268 rl_list_tx_init(sc); 1269 1270 /* 1271 * Enable transmit and receive. 1272 */ 1273 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1274 1275 /* 1276 * Set the initial TX and RX configuration. 1277 */ 1278 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1279 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1280 1281 /* Set the individual bit to receive frames for this host only. */ 1282 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1283 rxcfg |= RL_RXCFG_RX_INDIV; 1284 1285 /* If we want promiscuous mode, set the allframes bit. */ 1286 if (ifp->if_flags & IFF_PROMISC) { 1287 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1288 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1289 } else { 1290 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1291 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1292 } 1293 1294 /* 1295 * Set capture broadcast bit to capture broadcast frames. 1296 */ 1297 if (ifp->if_flags & IFF_BROADCAST) { 1298 rxcfg |= RL_RXCFG_RX_BROAD; 1299 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1300 } else { 1301 rxcfg &= ~RL_RXCFG_RX_BROAD; 1302 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1303 } 1304 1305 /* 1306 * Program the multicast filter, if necessary. 1307 */ 1308 rl_setmulti(sc); 1309 1310 /* 1311 * Enable interrupts. 1312 */ 1313 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1314 1315 /* Start RX/TX process. */ 1316 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1317 1318 /* Enable receiver and transmitter. */ 1319 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1320 1321 /* Restore state of BMCR */ 1322 if (sc->rl_type == RL_8139) 1323 rl_phy_writereg((struct device *)sc, 7, MII_BMCR, phy_bmcr); 1324 1325 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1326 1327 /* 1328 * Set current media. 1329 */ 1330 mii_mediachg(&sc->mii); 1331 1332 ifp->if_flags |= IFF_RUNNING; 1333 ifp->if_flags &= ~IFF_OACTIVE; 1334 1335 (void)splx(s); 1336 1337 callout_reset(&sc->rl_tick_ch, hz, rl_tick, sc); 1338 } 1339 1340 /* 1341 * Set media options. 1342 */ 1343 STATIC int rl_ifmedia_upd(ifp) 1344 struct ifnet *ifp; 1345 { 1346 struct rl_softc *sc; 1347 struct ifmedia *ifm; 1348 1349 sc = ifp->if_softc; 1350 ifm = &sc->mii.mii_media; 1351 1352 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1353 return(EINVAL); 1354 1355 return (mii_mediachg(&sc->mii)); 1356 } 1357 1358 /* 1359 * Report current media status. 1360 */ 1361 STATIC void rl_ifmedia_sts(ifp, ifmr) 1362 struct ifnet *ifp; 1363 struct ifmediareq *ifmr; 1364 { 1365 struct rl_softc *sc; 1366 1367 sc = ifp->if_softc; 1368 1369 mii_pollstat(&sc->mii); 1370 ifmr->ifm_status = sc->mii.mii_media_status; 1371 ifmr->ifm_active = sc->mii.mii_media_active; 1372 } 1373 1374 STATIC int 1375 rl_ether_ioctl(ifp, cmd, data) 1376 struct ifnet *ifp; 1377 u_long cmd; 1378 caddr_t data; 1379 { 1380 struct ifaddr *ifa = (struct ifaddr *) data; 1381 struct rl_softc *sc = ifp->if_softc; 1382 1383 switch (cmd) { 1384 case SIOCSIFADDR: 1385 ifp->if_flags |= IFF_UP; 1386 1387 switch (ifa->ifa_addr->sa_family) { 1388 #ifdef INET 1389 case AF_INET: 1390 rl_init(sc); 1391 arp_ifinit(ifp, ifa); 1392 break; 1393 #endif 1394 #ifdef NS 1395 case AF_NS: 1396 { 1397 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1398 1399 if (ns_nullhost(*ina)) 1400 ina->x_host = *(union ns_host *) 1401 LLADDR(ifp->if_sadl); 1402 else 1403 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1404 ifp->if_addrlen); 1405 /* Set new address. */ 1406 rl_init(sc); 1407 break; 1408 } 1409 #endif 1410 default: 1411 rl_init(sc); 1412 break; 1413 } 1414 break; 1415 1416 default: 1417 return (EINVAL); 1418 } 1419 1420 return (0); 1421 } 1422 1423 STATIC int rl_ioctl(ifp, command, data) 1424 struct ifnet *ifp; 1425 u_long command; 1426 caddr_t data; 1427 { 1428 struct rl_softc *sc = ifp->if_softc; 1429 struct ifreq *ifr = (struct ifreq *) data; 1430 int s, error = 0; 1431 1432 s = splimp(); 1433 1434 switch(command) { 1435 case SIOCSIFADDR: 1436 case SIOCGIFADDR: 1437 case SIOCSIFMTU: 1438 error = rl_ether_ioctl(ifp, command, data); 1439 break; 1440 case SIOCSIFFLAGS: 1441 if (ifp->if_flags & IFF_UP) { 1442 rl_init(sc); 1443 } else { 1444 if (ifp->if_flags & IFF_RUNNING) 1445 rl_stop(sc); 1446 } 1447 error = 0; 1448 break; 1449 case SIOCADDMULTI: 1450 case SIOCDELMULTI: 1451 rl_setmulti(sc); 1452 error = 0; 1453 break; 1454 case SIOCGIFMEDIA: 1455 case SIOCSIFMEDIA: 1456 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1457 break; 1458 default: 1459 error = EINVAL; 1460 break; 1461 } 1462 1463 (void)splx(s); 1464 1465 return(error); 1466 } 1467 1468 STATIC void rl_watchdog(ifp) 1469 struct ifnet *ifp; 1470 { 1471 struct rl_softc *sc; 1472 1473 sc = ifp->if_softc; 1474 1475 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1476 ifp->if_oerrors++; 1477 rl_txeof(sc); 1478 rl_rxeof(sc); 1479 rl_init(sc); 1480 1481 return; 1482 } 1483 1484 /* 1485 * Stop the adapter and free any mbufs allocated to the 1486 * RX and TX lists. 1487 */ 1488 STATIC void rl_stop(sc) 1489 struct rl_softc *sc; 1490 { 1491 int i; 1492 struct ifnet *ifp; 1493 1494 ifp = &sc->ethercom.ec_if; 1495 ifp->if_timer = 0; 1496 1497 callout_stop(&sc->rl_tick_ch); 1498 1499 mii_down(&sc->mii); 1500 1501 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1502 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1503 1504 /* 1505 * Free the TX list buffers. 1506 */ 1507 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1508 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1509 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1510 sc->rl_cdata.rl_tx_chain[i] = NULL; 1511 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1512 } 1513 } 1514 1515 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1516 1517 return; 1518 } 1519 1520 /* 1521 * Stop all chip I/O so that the kernel's probe routines don't 1522 * get confused by errant DMAs when rebooting. 1523 */ 1524 STATIC void rl_shutdown(vsc) 1525 void *vsc; 1526 { 1527 struct rl_softc *sc = (struct rl_softc *)vsc; 1528 1529 rl_stop(sc); 1530 1531 return; 1532 } 1533 1534 STATIC void 1535 rl_tick(arg) 1536 void *arg; 1537 { 1538 struct rl_softc *sc = arg; 1539 int s = splnet(); 1540 1541 mii_tick(&sc->mii); 1542 splx(s); 1543 1544 callout_reset(&sc->rl_tick_ch, hz, rl_tick, sc); 1545 } 1546
Indexes created Tue Sep 23 02:09:52 GMT 2025