rtl81x9.c revision 1.7
1 /* $NetBSD: rtl81x9.c,v 1.7 2000/05/12 16:44:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include "opt_inet.h" 89 #include "opt_ns.h" 90 #include "bpfilter.h" 91 #include "rnd.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/callout.h> 96 #include <sys/device.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/if_inarp.h> 111 #endif 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #if NBPFILTER > 0 118 #include <net/bpf.h> 119 #endif 120 #if NRND > 0 121 #include <sys/rnd.h> 122 #endif 123 124 #include <machine/bus.h> 125 #include <machine/endian.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 130 /* 131 * Default to using PIO access for this driver. On SMP systems, 132 * there appear to be problems with memory mapped mode: it looks like 133 * doing too many memory mapped access back to back in rapid succession 134 * can hang the bus. I'm inclined to blame this on crummy design/construction 135 * on the part of RealTek. Memory mapped mode does appear to work on 136 * uniprocessor systems though. 137 */ 138 139 #include <dev/ic/rtl81x9reg.h> 140 #include <dev/ic/rtl81x9var.h> 141 142 #if defined DEBUG 143 #define STATIC 144 #else 145 #define STATIC static 146 #endif 147 148 STATIC void rl_reset __P((struct rl_softc *)); 149 STATIC void rl_rxeof __P((struct rl_softc *)); 150 STATIC void rl_txeof __P((struct rl_softc *)); 151 STATIC void rl_start __P((struct ifnet *)); 152 STATIC int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 153 STATIC void rl_init __P((void *)); 154 STATIC void rl_stop __P((struct rl_softc *)); 155 STATIC void rl_watchdog __P((struct ifnet *)); 156 STATIC void rl_shutdown __P((void *)); 157 STATIC int rl_ifmedia_upd __P((struct ifnet *)); 158 STATIC void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 159 160 STATIC u_int16_t rl_read_eeprom __P((struct rl_softc *, int, int)); 161 STATIC void rl_eeprom_putbyte __P((struct rl_softc *, int, int)); 162 STATIC void rl_mii_sync __P((struct rl_softc *)); 163 STATIC void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 164 STATIC int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 165 STATIC int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 166 167 STATIC int rl_phy_readreg __P((struct device *, int, int)); 168 STATIC void rl_phy_writereg __P((struct device *, int, int, int)); 169 STATIC void rl_phy_statchg __P((struct device *)); 170 STATIC void rl_tick __P((void *)); 171 172 STATIC void rl_setmulti __P((struct rl_softc *)); 173 STATIC int rl_list_tx_init __P((struct rl_softc *)); 174 175 STATIC int rl_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 176 177 178 #define EE_SET(x) \ 179 CSR_WRITE_1(sc, RL_EECMD, \ 180 CSR_READ_1(sc, RL_EECMD) | (x)) 181 182 #define EE_CLR(x) \ 183 CSR_WRITE_1(sc, RL_EECMD, \ 184 CSR_READ_1(sc, RL_EECMD) & ~(x)) 185 186 /* 187 * Send a read command and address to the EEPROM, check for ACK. 188 */ 189 STATIC void rl_eeprom_putbyte(sc, addr, addr_len) 190 struct rl_softc *sc; 191 int addr, addr_len; 192 { 193 int d, i; 194 195 d = (RL_EECMD_READ << addr_len) | addr; 196 197 /* 198 * Feed in each bit and stobe the clock. 199 */ 200 for (i = RL_EECMD_LEN + addr_len - 1; i >= 0; i--) { 201 if (d & (1 << i)) { 202 EE_SET(RL_EE_DATAIN); 203 } else { 204 EE_CLR(RL_EE_DATAIN); 205 } 206 DELAY(100); 207 EE_SET(RL_EE_CLK); 208 DELAY(150); 209 EE_CLR(RL_EE_CLK); 210 DELAY(100); 211 } 212 } 213 214 /* 215 * Read a word of data stored in the EEPROM at address 'addr.' 216 */ 217 u_int16_t rl_read_eeprom(sc, addr, addr_len) 218 struct rl_softc *sc; 219 int addr, addr_len; 220 { 221 u_int16_t word = 0; 222 int i; 223 224 /* Enter EEPROM access mode. */ 225 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 226 227 /* 228 * Send address of word we want to read. 229 */ 230 rl_eeprom_putbyte(sc, addr, addr_len); 231 232 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 233 234 /* 235 * Start reading bits from EEPROM. 236 */ 237 for (i = 15; i >= 0; i--) { 238 EE_SET(RL_EE_CLK); 239 DELAY(100); 240 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 241 word |= (1 << i); 242 EE_CLR(RL_EE_CLK); 243 DELAY(100); 244 } 245 246 /* Turn off EEPROM access mode. */ 247 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 248 249 return (word); 250 } 251 252 /* 253 * MII access routines are provided for the 8129, which 254 * doesn't have a built-in PHY. For the 8139, we fake things 255 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 256 * direct access PHY registers. 257 */ 258 #define MII_SET(x) \ 259 CSR_WRITE_1(sc, RL_MII, \ 260 CSR_READ_1(sc, RL_MII) | (x)) 261 262 #define MII_CLR(x) \ 263 CSR_WRITE_1(sc, RL_MII, \ 264 CSR_READ_1(sc, RL_MII) & ~(x)) 265 266 /* 267 * Sync the PHYs by setting data bit and strobing the clock 32 times. 268 */ 269 STATIC void rl_mii_sync(sc) 270 struct rl_softc *sc; 271 { 272 int i; 273 274 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 275 276 for (i = 0; i < 32; i++) { 277 MII_SET(RL_MII_CLK); 278 DELAY(1); 279 MII_CLR(RL_MII_CLK); 280 DELAY(1); 281 } 282 283 return; 284 } 285 286 /* 287 * Clock a series of bits through the MII. 288 */ 289 STATIC void rl_mii_send(sc, bits, cnt) 290 struct rl_softc *sc; 291 u_int32_t bits; 292 int cnt; 293 { 294 int i; 295 296 MII_CLR(RL_MII_CLK); 297 298 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 299 if (bits & i) { 300 MII_SET(RL_MII_DATAOUT); 301 } else { 302 MII_CLR(RL_MII_DATAOUT); 303 } 304 DELAY(1); 305 MII_CLR(RL_MII_CLK); 306 DELAY(1); 307 MII_SET(RL_MII_CLK); 308 } 309 } 310 311 /* 312 * Read an PHY register through the MII. 313 */ 314 STATIC int rl_mii_readreg(sc, frame) 315 struct rl_softc *sc; 316 struct rl_mii_frame *frame; 317 318 { 319 int i, ack, s; 320 321 s = splimp(); 322 323 /* 324 * Set up frame for RX. 325 */ 326 frame->mii_stdelim = RL_MII_STARTDELIM; 327 frame->mii_opcode = RL_MII_READOP; 328 frame->mii_turnaround = 0; 329 frame->mii_data = 0; 330 331 CSR_WRITE_2(sc, RL_MII, 0); 332 333 /* 334 * Turn on data xmit. 335 */ 336 MII_SET(RL_MII_DIR); 337 338 rl_mii_sync(sc); 339 340 /* 341 * Send command/address info. 342 */ 343 rl_mii_send(sc, frame->mii_stdelim, 2); 344 rl_mii_send(sc, frame->mii_opcode, 2); 345 rl_mii_send(sc, frame->mii_phyaddr, 5); 346 rl_mii_send(sc, frame->mii_regaddr, 5); 347 348 /* Idle bit */ 349 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 350 DELAY(1); 351 MII_SET(RL_MII_CLK); 352 DELAY(1); 353 354 /* Turn off xmit. */ 355 MII_CLR(RL_MII_DIR); 356 357 /* Check for ack */ 358 MII_CLR(RL_MII_CLK); 359 DELAY(1); 360 MII_SET(RL_MII_CLK); 361 DELAY(1); 362 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 363 364 /* 365 * Now try reading data bits. If the ack failed, we still 366 * need to clock through 16 cycles to keep the PHY(s) in sync. 367 */ 368 if (ack) { 369 for(i = 0; i < 16; i++) { 370 MII_CLR(RL_MII_CLK); 371 DELAY(1); 372 MII_SET(RL_MII_CLK); 373 DELAY(1); 374 } 375 goto fail; 376 } 377 378 for (i = 0x8000; i; i >>= 1) { 379 MII_CLR(RL_MII_CLK); 380 DELAY(1); 381 if (!ack) { 382 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 383 frame->mii_data |= i; 384 DELAY(1); 385 } 386 MII_SET(RL_MII_CLK); 387 DELAY(1); 388 } 389 390 fail: 391 392 MII_CLR(RL_MII_CLK); 393 DELAY(1); 394 MII_SET(RL_MII_CLK); 395 DELAY(1); 396 397 splx(s); 398 399 if (ack) 400 return(1); 401 return(0); 402 } 403 404 /* 405 * Write to a PHY register through the MII. 406 */ 407 STATIC int rl_mii_writereg(sc, frame) 408 struct rl_softc *sc; 409 struct rl_mii_frame *frame; 410 411 { 412 int s; 413 414 s = splimp(); 415 /* 416 * Set up frame for TX. 417 */ 418 419 frame->mii_stdelim = RL_MII_STARTDELIM; 420 frame->mii_opcode = RL_MII_WRITEOP; 421 frame->mii_turnaround = RL_MII_TURNAROUND; 422 423 /* 424 * Turn on data output. 425 */ 426 MII_SET(RL_MII_DIR); 427 428 rl_mii_sync(sc); 429 430 rl_mii_send(sc, frame->mii_stdelim, 2); 431 rl_mii_send(sc, frame->mii_opcode, 2); 432 rl_mii_send(sc, frame->mii_phyaddr, 5); 433 rl_mii_send(sc, frame->mii_regaddr, 5); 434 rl_mii_send(sc, frame->mii_turnaround, 2); 435 rl_mii_send(sc, frame->mii_data, 16); 436 437 /* Idle bit. */ 438 MII_SET(RL_MII_CLK); 439 DELAY(1); 440 MII_CLR(RL_MII_CLK); 441 DELAY(1); 442 443 /* 444 * Turn off xmit. 445 */ 446 MII_CLR(RL_MII_DIR); 447 448 splx(s); 449 450 return(0); 451 } 452 453 STATIC int rl_phy_readreg(self, phy, reg) 454 struct device *self; 455 int phy, reg; 456 { 457 struct rl_softc *sc = (void *)self; 458 struct rl_mii_frame frame; 459 u_int16_t rval = 0; 460 u_int16_t rl8139_reg = 0; 461 462 if (sc->rl_type == RL_8139) { 463 if (phy != 7) 464 return (0); 465 466 switch(reg) { 467 case MII_BMCR: 468 rl8139_reg = RL_BMCR; 469 break; 470 case MII_BMSR: 471 rl8139_reg = RL_BMSR; 472 break; 473 case MII_ANAR: 474 rl8139_reg = RL_ANAR; 475 break; 476 case MII_ANLPAR: 477 rl8139_reg = RL_LPAR; 478 break; 479 default: 480 #if 0 481 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 482 #endif 483 return(0); 484 } 485 rval = CSR_READ_2(sc, rl8139_reg); 486 return(rval); 487 } 488 489 bzero((char *)&frame, sizeof(frame)); 490 491 frame.mii_phyaddr = phy; 492 frame.mii_regaddr = reg; 493 rl_mii_readreg(sc, &frame); 494 495 return(frame.mii_data); 496 } 497 498 STATIC void rl_phy_writereg(self, phy, reg, data) 499 struct device *self; 500 int phy, reg; 501 int data; 502 { 503 struct rl_softc *sc = (void *)self; 504 struct rl_mii_frame frame; 505 u_int16_t rl8139_reg = 0; 506 507 if (sc->rl_type == RL_8139) { 508 if (phy != 7) 509 return; 510 511 switch(reg) { 512 case MII_BMCR: 513 rl8139_reg = RL_BMCR; 514 break; 515 case MII_BMSR: 516 rl8139_reg = RL_BMSR; 517 break; 518 case MII_ANAR: 519 rl8139_reg = RL_ANAR; 520 break; 521 case MII_ANLPAR: 522 rl8139_reg = RL_LPAR; 523 break; 524 default: 525 #if 0 526 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 527 #endif 528 return; 529 } 530 CSR_WRITE_2(sc, rl8139_reg, data); 531 return; 532 } 533 534 bzero((char *)&frame, sizeof(frame)); 535 536 frame.mii_phyaddr = phy; 537 frame.mii_regaddr = reg; 538 frame.mii_data = data; 539 540 rl_mii_writereg(sc, &frame); 541 542 return; 543 } 544 545 STATIC void 546 rl_phy_statchg(v) 547 struct device *v; 548 { 549 550 /* Nothing to do. */ 551 } 552 553 #define rl_calchash(addr) \ 554 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 555 556 /* 557 * Program the 64-bit multicast hash filter. 558 */ 559 STATIC void rl_setmulti(sc) 560 struct rl_softc *sc; 561 { 562 struct ifnet *ifp; 563 int h = 0; 564 u_int32_t hashes[2] = { 0, 0 }; 565 u_int32_t rxfilt; 566 int mcnt = 0; 567 struct ether_multi *enm; 568 struct ether_multistep step; 569 570 ifp = &sc->ethercom.ec_if; 571 572 rxfilt = CSR_READ_4(sc, RL_RXCFG); 573 574 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 575 rxfilt |= RL_RXCFG_RX_MULTI; 576 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 577 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 578 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 579 return; 580 } 581 582 /* first, zot all the existing hash bits */ 583 CSR_WRITE_4(sc, RL_MAR0, 0); 584 CSR_WRITE_4(sc, RL_MAR4, 0); 585 586 /* now program new ones */ 587 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 588 while (enm != NULL) { 589 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 590 ETHER_ADDR_LEN) != 0) 591 continue; 592 593 h = rl_calchash(enm->enm_addrlo); 594 if (h < 32) 595 hashes[0] |= (1 << h); 596 else 597 hashes[1] |= (1 << (h - 32)); 598 mcnt++; 599 ETHER_NEXT_MULTI(step, enm); 600 } 601 602 if (mcnt) 603 rxfilt |= RL_RXCFG_RX_MULTI; 604 else 605 rxfilt &= ~RL_RXCFG_RX_MULTI; 606 607 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 608 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 609 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 610 611 return; 612 } 613 614 void rl_reset(sc) 615 struct rl_softc *sc; 616 { 617 int i; 618 619 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 620 621 for (i = 0; i < RL_TIMEOUT; i++) { 622 DELAY(10); 623 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 624 break; 625 } 626 if (i == RL_TIMEOUT) 627 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 628 629 return; 630 } 631 632 /* 633 * Attach the interface. Allocate softc structures, do ifmedia 634 * setup and ethernet/BPF attach. 635 */ 636 void 637 rl_attach(sc) 638 struct rl_softc *sc; 639 { 640 641 struct ifnet *ifp; 642 u_int16_t val; 643 u_int8_t eaddr[ETHER_ADDR_LEN]; 644 bus_dma_segment_t dmaseg; 645 int error,dmanseg; 646 int i,addr_len; 647 648 callout_init(&sc->rl_tick_ch); 649 650 /* 651 * Check EEPROM type 9346 or 9356. 652 */ 653 if (rl_read_eeprom(sc, RL_EE_ID, RL_EEADDR_LEN1) == 0x8129) 654 addr_len = RL_EEADDR_LEN1; 655 else 656 addr_len = RL_EEADDR_LEN0; 657 658 /* 659 * Get station address. 660 */ 661 val = rl_read_eeprom(sc, RL_EE_EADDR0, addr_len); 662 eaddr[0] = val & 0xff; 663 eaddr[1] = val >> 8; 664 val = rl_read_eeprom(sc, RL_EE_EADDR1, addr_len); 665 eaddr[2] = val & 0xff; 666 eaddr[3] = val >> 8; 667 val = rl_read_eeprom(sc, RL_EE_EADDR2, addr_len); 668 eaddr[4] = val & 0xff; 669 eaddr[5] = val >> 8; 670 671 if ((error = bus_dmamem_alloc(sc->sc_dmat, 672 RL_RXBUFLEN + 32, NBPG, 0, &dmaseg, 1, &dmanseg, 673 BUS_DMA_NOWAIT)) != 0) { 674 printf("%s: can't allocate recv buffer, error = %d\n", 675 sc->sc_dev.dv_xname, error); 676 goto fail; 677 } 678 679 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 680 RL_RXBUFLEN + 32, (caddr_t *)&sc->rl_cdata.rl_rx_buf, 681 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 682 printf("%s: can't map recv buffer, error = %d\n", 683 sc->sc_dev.dv_xname, error); 684 goto fail; 685 } 686 687 /* Leave a few bytes before the start of the RX ring buffer. */ 688 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 689 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 690 691 if ((error = bus_dmamap_create(sc->sc_dmat, 692 RL_RXBUFLEN + 32 - sizeof(u_int64_t), 1, 693 RL_RXBUFLEN + 32 - sizeof(u_int64_t), 0, BUS_DMA_NOWAIT, 694 &sc->recv_dmamap)) != 0) { 695 printf("%s: can't create recv buffer DMA map, error = %d\n", 696 sc->sc_dev.dv_xname, error); 697 goto fail; 698 } 699 700 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 701 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32 - sizeof(u_int64_t), NULL, 702 BUS_DMA_NOWAIT)) != 0) { 703 printf("%s: can't load recv buffer DMA map, error = %d\n", 704 sc->sc_dev.dv_xname, error); 705 goto fail; 706 } 707 708 for (i = 0; i < RL_TX_LIST_CNT; i++) 709 if ((error = bus_dmamap_create(sc->sc_dmat, 710 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 711 &sc->snd_dmamap[i])) != 0) { 712 printf("%s: can't create snd buffer DMA map," 713 " error = %d\n", sc->sc_dev.dv_xname, error); 714 goto fail; 715 } 716 717 /* Reset the adapter. */ 718 rl_reset(sc); 719 720 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 721 ether_sprintf(eaddr)); 722 723 ifp = &sc->ethercom.ec_if; 724 ifp->if_softc = sc; 725 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 726 ifp->if_mtu = ETHERMTU; 727 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 728 ifp->if_ioctl = rl_ioctl; 729 #if 0 730 ifp->if_output = ether_output; 731 #endif 732 ifp->if_start = rl_start; 733 ifp->if_watchdog = rl_watchdog; 734 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 735 736 /* 737 * Do ifmedia setup. 738 */ 739 sc->mii.mii_ifp = ifp; 740 sc->mii.mii_readreg = rl_phy_readreg; 741 sc->mii.mii_writereg = rl_phy_writereg; 742 sc->mii.mii_statchg = rl_phy_statchg; 743 ifmedia_init(&sc->mii.mii_media, 0, rl_ifmedia_upd, rl_ifmedia_sts); 744 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 745 MII_PHY_ANY, MII_OFFSET_ANY, 0); 746 747 /* Choose a default media. */ 748 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 749 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 750 0, NULL); 751 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 752 } else { 753 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 754 } 755 756 /* 757 * Call MI attach routines. 758 */ 759 if_attach(ifp); 760 ether_ifattach(ifp, eaddr); 761 762 #if NBPFILTER > 0 763 bpfattach(&sc->ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 764 sizeof(struct ether_header)); 765 #endif 766 shutdownhook_establish(rl_shutdown, sc); 767 768 fail: 769 return; 770 } 771 772 /* 773 * Initialize the transmit descriptors. 774 */ 775 STATIC int rl_list_tx_init(sc) 776 struct rl_softc *sc; 777 { 778 struct rl_chain_data *cd; 779 int i; 780 781 cd = &sc->rl_cdata; 782 for (i = 0; i < RL_TX_LIST_CNT; i++) { 783 cd->rl_tx_chain[i] = NULL; 784 CSR_WRITE_4(sc, 785 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 786 } 787 788 sc->rl_cdata.cur_tx = 0; 789 sc->rl_cdata.last_tx = 0; 790 791 return(0); 792 } 793 794 /* 795 * A frame has been uploaded: pass the resulting mbuf chain up to 796 * the higher level protocols. 797 * 798 * You know there's something wrong with a PCI bus-master chip design 799 * when you have to use m_devget(). 800 * 801 * The receive operation is badly documented in the datasheet, so I'll 802 * attempt to document it here. The driver provides a buffer area and 803 * places its base address in the RX buffer start address register. 804 * The chip then begins copying frames into the RX buffer. Each frame 805 * is preceeded by a 32-bit RX status word which specifies the length 806 * of the frame and certain other status bits. Each frame (starting with 807 * the status word) is also 32-bit aligned. The frame length is in the 808 * first 16 bits of the status word; the lower 15 bits correspond with 809 * the 'rx status register' mentioned in the datasheet. 810 * 811 * Note: to make the Alpha happy, the frame payload needs to be aligned 812 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 813 * the ring buffer starting at an address two bytes before the actual 814 * data location. We can then shave off the first two bytes using m_adj(). 815 * The reason we do this is because m_devget() doesn't let us specify an 816 * offset into the mbuf storage space, so we have to artificially create 817 * one. The ring is allocated in such a way that there are a few unused 818 * bytes of space preceecing it so that it will be safe for us to do the 819 * 2-byte backstep even if reading from the ring at offset 0. 820 */ 821 STATIC void rl_rxeof(sc) 822 struct rl_softc *sc; 823 { 824 struct ether_header *eh; 825 struct mbuf *m; 826 struct ifnet *ifp; 827 int total_len = 0; 828 u_int32_t rxstat; 829 caddr_t rxbufpos; 830 int wrap = 0; 831 u_int16_t cur_rx; 832 u_int16_t limit; 833 u_int16_t rx_bytes = 0, max_bytes; 834 835 ifp = &sc->ethercom.ec_if; 836 837 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 838 839 /* Do not try to read past this point. */ 840 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 841 842 if (limit < cur_rx) 843 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 844 else 845 max_bytes = limit - cur_rx; 846 847 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 848 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 849 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 850 sizeof(u_int32_t *), BUS_DMASYNC_POSTREAD); 851 rxstat = le32toh(*(u_int32_t *)rxbufpos); 852 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 853 sizeof(u_int32_t *), BUS_DMASYNC_PREREAD); 854 855 /* 856 * Here's a totally undocumented fact for you. When the 857 * RealTek chip is in the process of copying a packet into 858 * RAM for you, the length will be 0xfff0. If you spot a 859 * packet header with this value, you need to stop. The 860 * datasheet makes absolutely no mention of this and 861 * RealTek should be shot for this. 862 */ 863 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 864 break; 865 866 if (!(rxstat & RL_RXSTAT_RXOK)) { 867 ifp->if_ierrors++; 868 869 /* 870 * submitted by:[netbsd-pcmcia:00484] 871 * Takahiro Kambe <taca (at) sky.yamashina.kyoto.jp> 872 * obtain from: 873 * FreeBSD if_rl.c rev 1.24->1.25 874 * 875 */ 876 #if 0 877 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 878 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 879 RL_RXSTAT_ALIGNERR)) { 880 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 881 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 882 RL_RXSTAT_ALIGNERR)) { 883 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB); 884 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB| 885 RL_CMD_RX_ENB); 886 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 887 CSR_WRITE_4(sc, RL_RXADDR, 888 sc->recv_dmamap->dm_segs[0].ds_addr); 889 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 890 cur_rx = 0; 891 } 892 break; 893 #else 894 rl_init(sc); 895 return; 896 #endif 897 } 898 899 /* No errors; receive the packet. */ 900 total_len = rxstat >> 16; 901 rx_bytes += total_len + 4; 902 903 /* 904 * XXX The RealTek chip includes the CRC with every 905 * received frame, and there's no way to turn this 906 * behavior off (at least, I can't find anything in 907 * the manual that explains how to do it) so we have 908 * to trim off the CRC manually. 909 */ 910 total_len -= ETHER_CRC_LEN; 911 912 /* 913 * Avoid trying to read more bytes than we know 914 * the chip has prepared for us. 915 */ 916 if (rx_bytes > max_bytes) 917 break; 918 919 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 920 cur_rx + sizeof(u_int32_t), total_len, 921 BUS_DMASYNC_POSTREAD); 922 923 rxbufpos = sc->rl_cdata.rl_rx_buf + 924 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 925 926 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 927 rxbufpos = sc->rl_cdata.rl_rx_buf; 928 929 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 930 931 if (total_len > wrap) { 932 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 933 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 934 if (m == NULL) { 935 ifp->if_ierrors++; 936 printf("%s: out of mbufs, tried to " 937 "copy %d bytes\n", sc->sc_dev.dv_xname, 938 wrap); 939 } 940 else { 941 m_adj(m, RL_ETHER_ALIGN); 942 m_copyback(m, wrap, total_len - wrap, 943 sc->rl_cdata.rl_rx_buf); 944 } 945 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 946 } else { 947 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 948 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 949 if (m == NULL) { 950 ifp->if_ierrors++; 951 printf("%s: out of mbufs, tried to " 952 "copy %d bytes\n", sc->sc_dev.dv_xname, 953 total_len); 954 } else 955 m_adj(m, RL_ETHER_ALIGN); 956 cur_rx += total_len + 4 + ETHER_CRC_LEN; 957 } 958 959 /* 960 * Round up to 32-bit boundary. 961 */ 962 cur_rx = (cur_rx + 3) & ~3; 963 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 964 965 if (m == NULL) 966 continue; 967 968 eh = mtod(m, struct ether_header *); 969 ifp->if_ipackets++; 970 971 #if NBPFILTER > 0 972 /* 973 * Handle BPF listeners. Let the BPF user see the packet, but 974 * don't pass it up to the ether_input() layer unless it's 975 * a broadcast packet, multicast packet, matches our ethernet 976 * address or the interface is in promiscuous mode. 977 */ 978 if (ifp->if_bpf) { 979 bpf_mtap(ifp->if_bpf, m); 980 if ((ifp->if_flags & IFF_PROMISC) != 0 && 981 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 982 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 983 ETHER_ADDR_LEN) != 0) { 984 m_freem(m); 985 continue; 986 } 987 } 988 #endif 989 /* pass it on. */ 990 (*ifp->if_input)(ifp, m); 991 992 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 993 cur_rx + sizeof(u_int32_t), 994 total_len, BUS_DMASYNC_PREREAD); 995 } 996 997 return; 998 } 999 1000 /* 1001 * A frame was downloaded to the chip. It's safe for us to clean up 1002 * the list buffers. 1003 */ 1004 STATIC void rl_txeof(sc) 1005 struct rl_softc *sc; 1006 { 1007 struct ifnet *ifp; 1008 u_int32_t txstat; 1009 1010 ifp = &sc->ethercom.ec_if; 1011 1012 /* Clear the timeout timer. */ 1013 ifp->if_timer = 0; 1014 1015 /* 1016 * Go through our tx list and free mbufs for those 1017 * frames that have been uploaded. 1018 */ 1019 do { 1020 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1021 if (!(txstat & (RL_TXSTAT_TX_OK| 1022 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1023 break; 1024 1025 bus_dmamap_sync(sc->sc_dmat, 1026 sc->snd_dmamap[sc->rl_cdata.last_tx], 0, 1027 sc->snd_dmamap[sc->rl_cdata.last_tx]->dm_mapsize, 1028 BUS_DMASYNC_POSTWRITE); 1029 bus_dmamap_unload(sc->sc_dmat, 1030 sc->snd_dmamap[sc->rl_cdata.last_tx]); 1031 m_freem(RL_LAST_TXMBUF(sc)); 1032 RL_LAST_TXMBUF(sc) = NULL; 1033 1034 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1035 1036 if (txstat & RL_TXSTAT_TX_OK) 1037 ifp->if_opackets++; 1038 else { 1039 ifp->if_oerrors++; 1040 if ((txstat & RL_TXSTAT_TXABRT) || 1041 (txstat & RL_TXSTAT_OUTOFWIN)) 1042 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1043 } 1044 RL_INC(sc->rl_cdata.last_tx); 1045 ifp->if_flags &= ~IFF_OACTIVE; 1046 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1047 1048 return; 1049 } 1050 1051 int rl_intr(arg) 1052 void *arg; 1053 { 1054 struct rl_softc *sc; 1055 struct ifnet *ifp; 1056 u_int16_t status; 1057 int handled = 0; 1058 1059 sc = arg; 1060 ifp = &sc->ethercom.ec_if; 1061 1062 /* Disable interrupts. */ 1063 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1064 1065 for (;;) { 1066 1067 status = CSR_READ_2(sc, RL_ISR); 1068 if (status) 1069 CSR_WRITE_2(sc, RL_ISR, status); 1070 1071 handled = 1; 1072 1073 if ((status & RL_INTRS) == 0) 1074 break; 1075 1076 if (status & RL_ISR_RX_OK) 1077 rl_rxeof(sc); 1078 1079 if (status & RL_ISR_RX_ERR) 1080 rl_rxeof(sc); 1081 1082 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1083 rl_txeof(sc); 1084 1085 if (status & RL_ISR_SYSTEM_ERR) { 1086 rl_reset(sc); 1087 rl_init(sc); 1088 } 1089 1090 } 1091 1092 /* Re-enable interrupts. */ 1093 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1094 1095 if (ifp->if_snd.ifq_head != NULL) { 1096 rl_start(ifp); 1097 } 1098 1099 return (handled); 1100 } 1101 1102 /* 1103 * Main transmit routine. 1104 */ 1105 1106 STATIC void rl_start(ifp) 1107 struct ifnet *ifp; 1108 { 1109 struct rl_softc *sc; 1110 struct mbuf *m_head = NULL, *m_new; 1111 int error, idx, len; 1112 1113 sc = ifp->if_softc; 1114 1115 while(RL_CUR_TXMBUF(sc) == NULL) { 1116 IF_DEQUEUE(&ifp->if_snd, m_head); 1117 if (m_head == NULL) 1118 break; 1119 1120 idx = sc->rl_cdata.cur_tx; 1121 1122 /* 1123 * Load the DMA map. If this fails, the packet didn't 1124 * fit in one DMA segment, and we need to copy. Note, 1125 * the packet must also be aligned. 1126 */ 1127 if ((mtod(m_head, bus_addr_t) & 3) != 0 || 1128 bus_dmamap_load_mbuf(sc->sc_dmat, sc->snd_dmamap[idx], 1129 m_head, BUS_DMA_NOWAIT) != 0) { 1130 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1131 if (m_new == NULL) { 1132 printf("%s: unable to allocate Tx mbuf\n", 1133 sc->sc_dev.dv_xname); 1134 IF_PREPEND(&ifp->if_snd, m_new); 1135 break; 1136 } 1137 if (m_head->m_pkthdr.len > MHLEN) { 1138 MCLGET(m_new, M_DONTWAIT); 1139 if ((m_new->m_flags & M_EXT) == 0) { 1140 printf("%s: unable to allocate Tx " 1141 "cluster\n", sc->sc_dev.dv_xname); 1142 m_freem(m_new); 1143 IF_PREPEND(&ifp->if_snd, m_head); 1144 break; 1145 } 1146 } 1147 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1148 mtod(m_new, caddr_t)); 1149 m_new->m_pkthdr.len = m_new->m_len = 1150 m_head->m_pkthdr.len; 1151 m_freem(m_head); 1152 m_head = m_new; 1153 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1154 sc->snd_dmamap[idx], m_head, BUS_DMA_NOWAIT); 1155 if (error) { 1156 printf("%s: unable to load Tx buffer, " 1157 "error = %d\n", sc->sc_dev.dv_xname, error); 1158 IF_PREPEND(&ifp->if_snd, m_head); 1159 break; 1160 } 1161 } 1162 1163 RL_CUR_TXMBUF(sc) = m_head; 1164 1165 #if NBPFILTER > 0 1166 /* 1167 * If there's a BPF listener, bounce a copy of this frame 1168 * to him. 1169 */ 1170 if (ifp->if_bpf) 1171 bpf_mtap(ifp->if_bpf, RL_CUR_TXMBUF(sc)); 1172 #endif 1173 /* 1174 * Transmit the frame. 1175 */ 1176 bus_dmamap_sync(sc->sc_dmat, 1177 sc->snd_dmamap[idx], 0, sc->snd_dmamap[idx]->dm_mapsize, 1178 BUS_DMASYNC_PREWRITE); 1179 1180 len = sc->snd_dmamap[idx]->dm_segs[0].ds_len; 1181 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 1182 len = (ETHER_MIN_LEN - ETHER_CRC_LEN); 1183 1184 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1185 sc->snd_dmamap[idx]->dm_segs[0].ds_addr); 1186 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), RL_TX_EARLYTHRESH | len); 1187 1188 RL_INC(sc->rl_cdata.cur_tx); 1189 } 1190 1191 /* 1192 * We broke out of the loop because all our TX slots are 1193 * full. Mark the NIC as busy until it drains some of the 1194 * packets from the queue. 1195 */ 1196 if (RL_CUR_TXMBUF(sc) != NULL) 1197 ifp->if_flags |= IFF_OACTIVE; 1198 1199 /* 1200 * Set a timeout in case the chip goes out to lunch. 1201 */ 1202 ifp->if_timer = 5; 1203 1204 return; 1205 } 1206 1207 STATIC void rl_init(xsc) 1208 void *xsc; 1209 { 1210 struct rl_softc *sc = xsc; 1211 struct ifnet *ifp = &sc->ethercom.ec_if; 1212 int s, i; 1213 u_int32_t rxcfg; 1214 u_int16_t phy_bmcr = 0; 1215 1216 s = splimp(); 1217 1218 /* 1219 * XXX Hack for the 8139: the built-in autoneg logic's state 1220 * gets reset by rl_init() when we don't want it to. Try 1221 * to preserve it. 1222 */ 1223 if (sc->rl_type == RL_8139) 1224 phy_bmcr = rl_phy_readreg((struct device *)sc, 7, MII_BMCR); 1225 1226 /* 1227 * Cancel pending I/O and free all RX/TX buffers. 1228 */ 1229 rl_stop(sc); 1230 1231 /* Init our MAC address */ 1232 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1233 CSR_WRITE_1(sc, RL_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1234 } 1235 1236 /* Init the RX buffer pointer register. */ 1237 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1238 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1239 CSR_WRITE_4(sc, RL_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1240 1241 /* Init TX descriptors. */ 1242 rl_list_tx_init(sc); 1243 1244 /* 1245 * Enable transmit and receive. 1246 */ 1247 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1248 1249 /* 1250 * Set the initial TX and RX configuration. 1251 */ 1252 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1253 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1254 1255 /* Set the individual bit to receive frames for this host only. */ 1256 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1257 rxcfg |= RL_RXCFG_RX_INDIV; 1258 1259 /* If we want promiscuous mode, set the allframes bit. */ 1260 if (ifp->if_flags & IFF_PROMISC) { 1261 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1262 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1263 } else { 1264 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1265 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1266 } 1267 1268 /* 1269 * Set capture broadcast bit to capture broadcast frames. 1270 */ 1271 if (ifp->if_flags & IFF_BROADCAST) { 1272 rxcfg |= RL_RXCFG_RX_BROAD; 1273 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1274 } else { 1275 rxcfg &= ~RL_RXCFG_RX_BROAD; 1276 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1277 } 1278 1279 /* 1280 * Program the multicast filter, if necessary. 1281 */ 1282 rl_setmulti(sc); 1283 1284 /* 1285 * Enable interrupts. 1286 */ 1287 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1288 1289 /* Start RX/TX process. */ 1290 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1291 1292 /* Enable receiver and transmitter. */ 1293 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1294 1295 /* Restore state of BMCR */ 1296 if (sc->rl_type == RL_8139) 1297 rl_phy_writereg((struct device *)sc, 7, MII_BMCR, phy_bmcr); 1298 1299 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1300 1301 /* 1302 * Set current media. 1303 */ 1304 mii_mediachg(&sc->mii); 1305 1306 ifp->if_flags |= IFF_RUNNING; 1307 ifp->if_flags &= ~IFF_OACTIVE; 1308 1309 (void)splx(s); 1310 1311 callout_reset(&sc->rl_tick_ch, hz, rl_tick, sc); 1312 } 1313 1314 /* 1315 * Set media options. 1316 */ 1317 STATIC int rl_ifmedia_upd(ifp) 1318 struct ifnet *ifp; 1319 { 1320 struct rl_softc *sc; 1321 struct ifmedia *ifm; 1322 1323 sc = ifp->if_softc; 1324 ifm = &sc->mii.mii_media; 1325 1326 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1327 return(EINVAL); 1328 1329 return (mii_mediachg(&sc->mii)); 1330 } 1331 1332 /* 1333 * Report current media status. 1334 */ 1335 STATIC void rl_ifmedia_sts(ifp, ifmr) 1336 struct ifnet *ifp; 1337 struct ifmediareq *ifmr; 1338 { 1339 struct rl_softc *sc; 1340 1341 sc = ifp->if_softc; 1342 1343 mii_pollstat(&sc->mii); 1344 ifmr->ifm_status = sc->mii.mii_media_status; 1345 ifmr->ifm_active = sc->mii.mii_media_active; 1346 } 1347 1348 STATIC int 1349 rl_ether_ioctl(ifp, cmd, data) 1350 struct ifnet *ifp; 1351 u_long cmd; 1352 caddr_t data; 1353 { 1354 struct ifaddr *ifa = (struct ifaddr *) data; 1355 struct rl_softc *sc = ifp->if_softc; 1356 1357 switch (cmd) { 1358 case SIOCSIFADDR: 1359 ifp->if_flags |= IFF_UP; 1360 1361 switch (ifa->ifa_addr->sa_family) { 1362 #ifdef INET 1363 case AF_INET: 1364 rl_init(sc); 1365 arp_ifinit(ifp, ifa); 1366 break; 1367 #endif 1368 #ifdef NS 1369 case AF_NS: 1370 { 1371 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1372 1373 if (ns_nullhost(*ina)) 1374 ina->x_host = *(union ns_host *) 1375 LLADDR(ifp->if_sadl); 1376 else 1377 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1378 ifp->if_addrlen); 1379 /* Set new address. */ 1380 rl_init(sc); 1381 break; 1382 } 1383 #endif 1384 default: 1385 rl_init(sc); 1386 break; 1387 } 1388 break; 1389 1390 default: 1391 return (EINVAL); 1392 } 1393 1394 return (0); 1395 } 1396 1397 STATIC int rl_ioctl(ifp, command, data) 1398 struct ifnet *ifp; 1399 u_long command; 1400 caddr_t data; 1401 { 1402 struct rl_softc *sc = ifp->if_softc; 1403 struct ifreq *ifr = (struct ifreq *) data; 1404 int s, error = 0; 1405 1406 s = splimp(); 1407 1408 switch(command) { 1409 case SIOCSIFADDR: 1410 case SIOCGIFADDR: 1411 case SIOCSIFMTU: 1412 error = rl_ether_ioctl(ifp, command, data); 1413 break; 1414 case SIOCSIFFLAGS: 1415 if (ifp->if_flags & IFF_UP) { 1416 rl_init(sc); 1417 } else { 1418 if (ifp->if_flags & IFF_RUNNING) 1419 rl_stop(sc); 1420 } 1421 error = 0; 1422 break; 1423 case SIOCADDMULTI: 1424 case SIOCDELMULTI: 1425 rl_setmulti(sc); 1426 error = 0; 1427 break; 1428 case SIOCGIFMEDIA: 1429 case SIOCSIFMEDIA: 1430 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1431 break; 1432 default: 1433 error = EINVAL; 1434 break; 1435 } 1436 1437 (void)splx(s); 1438 1439 return(error); 1440 } 1441 1442 STATIC void rl_watchdog(ifp) 1443 struct ifnet *ifp; 1444 { 1445 struct rl_softc *sc; 1446 1447 sc = ifp->if_softc; 1448 1449 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1450 ifp->if_oerrors++; 1451 rl_txeof(sc); 1452 rl_rxeof(sc); 1453 rl_init(sc); 1454 1455 return; 1456 } 1457 1458 /* 1459 * Stop the adapter and free any mbufs allocated to the 1460 * RX and TX lists. 1461 */ 1462 STATIC void rl_stop(sc) 1463 struct rl_softc *sc; 1464 { 1465 int i; 1466 struct ifnet *ifp; 1467 1468 ifp = &sc->ethercom.ec_if; 1469 ifp->if_timer = 0; 1470 1471 callout_stop(&sc->rl_tick_ch); 1472 1473 mii_down(&sc->mii); 1474 1475 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1476 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1477 1478 /* 1479 * Free the TX list buffers. 1480 */ 1481 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1482 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1483 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1484 sc->rl_cdata.rl_tx_chain[i] = NULL; 1485 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1486 } 1487 } 1488 1489 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1490 1491 return; 1492 } 1493 1494 /* 1495 * Stop all chip I/O so that the kernel's probe routines don't 1496 * get confused by errant DMAs when rebooting. 1497 */ 1498 STATIC void rl_shutdown(vsc) 1499 void *vsc; 1500 { 1501 struct rl_softc *sc = (struct rl_softc *)vsc; 1502 1503 rl_stop(sc); 1504 1505 return; 1506 } 1507 1508 STATIC void 1509 rl_tick(arg) 1510 void *arg; 1511 { 1512 struct rl_softc *sc = arg; 1513 int s = splnet(); 1514 1515 mii_tick(&sc->mii); 1516 splx(s); 1517 1518 callout_reset(&sc->rl_tick_ch, hz, rl_tick, sc); 1519 } 1520
Indexes created Thu Sep 25 08:09:54 GMT 2025