rtl81x9.c revision 1.8
1 /* $NetBSD: rtl81x9.c,v 1.8 2000/05/15 01:55:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include "opt_inet.h" 89 #include "opt_ns.h" 90 #include "bpfilter.h" 91 #include "rnd.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/callout.h> 96 #include <sys/device.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/if_inarp.h> 111 #endif 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #if NBPFILTER > 0 118 #include <net/bpf.h> 119 #endif 120 #if NRND > 0 121 #include <sys/rnd.h> 122 #endif 123 124 #include <machine/bus.h> 125 #include <machine/endian.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 130 #include <dev/ic/rtl81x9reg.h> 131 #include <dev/ic/rtl81x9var.h> 132 133 #if defined DEBUG 134 #define STATIC 135 #else 136 #define STATIC static 137 #endif 138 139 STATIC void rtk_reset __P((struct rtk_softc *)); 140 STATIC void rtk_rxeof __P((struct rtk_softc *)); 141 STATIC void rtk_txeof __P((struct rtk_softc *)); 142 STATIC void rtk_start __P((struct ifnet *)); 143 STATIC int rtk_ioctl __P((struct ifnet *, u_long, caddr_t)); 144 STATIC void rtk_init __P((void *)); 145 STATIC void rtk_stop __P((struct rtk_softc *)); 146 STATIC void rtk_watchdog __P((struct ifnet *)); 147 STATIC void rtk_shutdown __P((void *)); 148 STATIC int rtk_ifmedia_upd __P((struct ifnet *)); 149 STATIC void rtk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 150 151 STATIC u_int16_t rtk_read_eeprom __P((struct rtk_softc *, int, int)); 152 STATIC void rtk_eeprom_putbyte __P((struct rtk_softc *, int, int)); 153 STATIC void rtk_mii_sync __P((struct rtk_softc *)); 154 STATIC void rtk_mii_send __P((struct rtk_softc *, u_int32_t, int)); 155 STATIC int rtk_mii_readreg __P((struct rtk_softc *, struct rtk_mii_frame *)); 156 STATIC int rtk_mii_writereg __P((struct rtk_softc *, struct rtk_mii_frame *)); 157 158 STATIC int rtk_phy_readreg __P((struct device *, int, int)); 159 STATIC void rtk_phy_writereg __P((struct device *, int, int, int)); 160 STATIC void rtk_phy_statchg __P((struct device *)); 161 STATIC void rtk_tick __P((void *)); 162 163 STATIC void rtk_setmulti __P((struct rtk_softc *)); 164 STATIC int rtk_list_tx_init __P((struct rtk_softc *)); 165 166 STATIC int rtk_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 167 168 169 #define EE_SET(x) \ 170 CSR_WRITE_1(sc, RL_EECMD, \ 171 CSR_READ_1(sc, RL_EECMD) | (x)) 172 173 #define EE_CLR(x) \ 174 CSR_WRITE_1(sc, RL_EECMD, \ 175 CSR_READ_1(sc, RL_EECMD) & ~(x)) 176 177 /* 178 * Send a read command and address to the EEPROM, check for ACK. 179 */ 180 STATIC void rtk_eeprom_putbyte(sc, addr, addr_len) 181 struct rtk_softc *sc; 182 int addr, addr_len; 183 { 184 int d, i; 185 186 d = (RL_EECMD_READ << addr_len) | addr; 187 188 /* 189 * Feed in each bit and stobe the clock. 190 */ 191 for (i = RL_EECMD_LEN + addr_len - 1; i >= 0; i--) { 192 if (d & (1 << i)) { 193 EE_SET(RL_EE_DATAIN); 194 } else { 195 EE_CLR(RL_EE_DATAIN); 196 } 197 DELAY(100); 198 EE_SET(RL_EE_CLK); 199 DELAY(150); 200 EE_CLR(RL_EE_CLK); 201 DELAY(100); 202 } 203 } 204 205 /* 206 * Read a word of data stored in the EEPROM at address 'addr.' 207 */ 208 u_int16_t rtk_read_eeprom(sc, addr, addr_len) 209 struct rtk_softc *sc; 210 int addr, addr_len; 211 { 212 u_int16_t word = 0; 213 int i; 214 215 /* Enter EEPROM access mode. */ 216 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 217 218 /* 219 * Send address of word we want to read. 220 */ 221 rtk_eeprom_putbyte(sc, addr, addr_len); 222 223 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 224 225 /* 226 * Start reading bits from EEPROM. 227 */ 228 for (i = 15; i >= 0; i--) { 229 EE_SET(RL_EE_CLK); 230 DELAY(100); 231 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 232 word |= (1 << i); 233 EE_CLR(RL_EE_CLK); 234 DELAY(100); 235 } 236 237 /* Turn off EEPROM access mode. */ 238 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 239 240 return (word); 241 } 242 243 /* 244 * MII access routines are provided for the 8129, which 245 * doesn't have a built-in PHY. For the 8139, we fake things 246 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 247 * direct access PHY registers. 248 */ 249 #define MII_SET(x) \ 250 CSR_WRITE_1(sc, RL_MII, \ 251 CSR_READ_1(sc, RL_MII) | (x)) 252 253 #define MII_CLR(x) \ 254 CSR_WRITE_1(sc, RL_MII, \ 255 CSR_READ_1(sc, RL_MII) & ~(x)) 256 257 /* 258 * Sync the PHYs by setting data bit and strobing the clock 32 times. 259 */ 260 STATIC void rtk_mii_sync(sc) 261 struct rtk_softc *sc; 262 { 263 int i; 264 265 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 266 267 for (i = 0; i < 32; i++) { 268 MII_SET(RL_MII_CLK); 269 DELAY(1); 270 MII_CLR(RL_MII_CLK); 271 DELAY(1); 272 } 273 274 return; 275 } 276 277 /* 278 * Clock a series of bits through the MII. 279 */ 280 STATIC void rtk_mii_send(sc, bits, cnt) 281 struct rtk_softc *sc; 282 u_int32_t bits; 283 int cnt; 284 { 285 int i; 286 287 MII_CLR(RL_MII_CLK); 288 289 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 290 if (bits & i) { 291 MII_SET(RL_MII_DATAOUT); 292 } else { 293 MII_CLR(RL_MII_DATAOUT); 294 } 295 DELAY(1); 296 MII_CLR(RL_MII_CLK); 297 DELAY(1); 298 MII_SET(RL_MII_CLK); 299 } 300 } 301 302 /* 303 * Read an PHY register through the MII. 304 */ 305 STATIC int rtk_mii_readreg(sc, frame) 306 struct rtk_softc *sc; 307 struct rtk_mii_frame *frame; 308 309 { 310 int i, ack, s; 311 312 s = splimp(); 313 314 /* 315 * Set up frame for RX. 316 */ 317 frame->mii_stdelim = RL_MII_STARTDELIM; 318 frame->mii_opcode = RL_MII_READOP; 319 frame->mii_turnaround = 0; 320 frame->mii_data = 0; 321 322 CSR_WRITE_2(sc, RL_MII, 0); 323 324 /* 325 * Turn on data xmit. 326 */ 327 MII_SET(RL_MII_DIR); 328 329 rtk_mii_sync(sc); 330 331 /* 332 * Send command/address info. 333 */ 334 rtk_mii_send(sc, frame->mii_stdelim, 2); 335 rtk_mii_send(sc, frame->mii_opcode, 2); 336 rtk_mii_send(sc, frame->mii_phyaddr, 5); 337 rtk_mii_send(sc, frame->mii_regaddr, 5); 338 339 /* Idle bit */ 340 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 341 DELAY(1); 342 MII_SET(RL_MII_CLK); 343 DELAY(1); 344 345 /* Turn off xmit. */ 346 MII_CLR(RL_MII_DIR); 347 348 /* Check for ack */ 349 MII_CLR(RL_MII_CLK); 350 DELAY(1); 351 MII_SET(RL_MII_CLK); 352 DELAY(1); 353 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 354 355 /* 356 * Now try reading data bits. If the ack failed, we still 357 * need to clock through 16 cycles to keep the PHY(s) in sync. 358 */ 359 if (ack) { 360 for(i = 0; i < 16; i++) { 361 MII_CLR(RL_MII_CLK); 362 DELAY(1); 363 MII_SET(RL_MII_CLK); 364 DELAY(1); 365 } 366 goto fail; 367 } 368 369 for (i = 0x8000; i; i >>= 1) { 370 MII_CLR(RL_MII_CLK); 371 DELAY(1); 372 if (!ack) { 373 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 374 frame->mii_data |= i; 375 DELAY(1); 376 } 377 MII_SET(RL_MII_CLK); 378 DELAY(1); 379 } 380 381 fail: 382 383 MII_CLR(RL_MII_CLK); 384 DELAY(1); 385 MII_SET(RL_MII_CLK); 386 DELAY(1); 387 388 splx(s); 389 390 if (ack) 391 return(1); 392 return(0); 393 } 394 395 /* 396 * Write to a PHY register through the MII. 397 */ 398 STATIC int rtk_mii_writereg(sc, frame) 399 struct rtk_softc *sc; 400 struct rtk_mii_frame *frame; 401 402 { 403 int s; 404 405 s = splimp(); 406 /* 407 * Set up frame for TX. 408 */ 409 410 frame->mii_stdelim = RL_MII_STARTDELIM; 411 frame->mii_opcode = RL_MII_WRITEOP; 412 frame->mii_turnaround = RL_MII_TURNAROUND; 413 414 /* 415 * Turn on data output. 416 */ 417 MII_SET(RL_MII_DIR); 418 419 rtk_mii_sync(sc); 420 421 rtk_mii_send(sc, frame->mii_stdelim, 2); 422 rtk_mii_send(sc, frame->mii_opcode, 2); 423 rtk_mii_send(sc, frame->mii_phyaddr, 5); 424 rtk_mii_send(sc, frame->mii_regaddr, 5); 425 rtk_mii_send(sc, frame->mii_turnaround, 2); 426 rtk_mii_send(sc, frame->mii_data, 16); 427 428 /* Idle bit. */ 429 MII_SET(RL_MII_CLK); 430 DELAY(1); 431 MII_CLR(RL_MII_CLK); 432 DELAY(1); 433 434 /* 435 * Turn off xmit. 436 */ 437 MII_CLR(RL_MII_DIR); 438 439 splx(s); 440 441 return(0); 442 } 443 444 STATIC int rtk_phy_readreg(self, phy, reg) 445 struct device *self; 446 int phy, reg; 447 { 448 struct rtk_softc *sc = (void *)self; 449 struct rtk_mii_frame frame; 450 u_int16_t rval = 0; 451 u_int16_t rl8139_reg = 0; 452 453 if (sc->rtk_type == RL_8139) { 454 if (phy != 7) 455 return (0); 456 457 switch(reg) { 458 case MII_BMCR: 459 rl8139_reg = RL_BMCR; 460 break; 461 case MII_BMSR: 462 rl8139_reg = RL_BMSR; 463 break; 464 case MII_ANAR: 465 rl8139_reg = RL_ANAR; 466 break; 467 case MII_ANLPAR: 468 rl8139_reg = RL_LPAR; 469 break; 470 default: 471 #if 0 472 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 473 #endif 474 return(0); 475 } 476 rval = CSR_READ_2(sc, rl8139_reg); 477 return(rval); 478 } 479 480 bzero((char *)&frame, sizeof(frame)); 481 482 frame.mii_phyaddr = phy; 483 frame.mii_regaddr = reg; 484 rtk_mii_readreg(sc, &frame); 485 486 return(frame.mii_data); 487 } 488 489 STATIC void rtk_phy_writereg(self, phy, reg, data) 490 struct device *self; 491 int phy, reg; 492 int data; 493 { 494 struct rtk_softc *sc = (void *)self; 495 struct rtk_mii_frame frame; 496 u_int16_t rl8139_reg = 0; 497 498 if (sc->rtk_type == RL_8139) { 499 if (phy != 7) 500 return; 501 502 switch(reg) { 503 case MII_BMCR: 504 rl8139_reg = RL_BMCR; 505 break; 506 case MII_BMSR: 507 rl8139_reg = RL_BMSR; 508 break; 509 case MII_ANAR: 510 rl8139_reg = RL_ANAR; 511 break; 512 case MII_ANLPAR: 513 rl8139_reg = RL_LPAR; 514 break; 515 default: 516 #if 0 517 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 518 #endif 519 return; 520 } 521 CSR_WRITE_2(sc, rl8139_reg, data); 522 return; 523 } 524 525 bzero((char *)&frame, sizeof(frame)); 526 527 frame.mii_phyaddr = phy; 528 frame.mii_regaddr = reg; 529 frame.mii_data = data; 530 531 rtk_mii_writereg(sc, &frame); 532 533 return; 534 } 535 536 STATIC void 537 rtk_phy_statchg(v) 538 struct device *v; 539 { 540 541 /* Nothing to do. */ 542 } 543 544 #define rtk_calchash(addr) \ 545 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 546 547 /* 548 * Program the 64-bit multicast hash filter. 549 */ 550 STATIC void rtk_setmulti(sc) 551 struct rtk_softc *sc; 552 { 553 struct ifnet *ifp; 554 int h = 0; 555 u_int32_t hashes[2] = { 0, 0 }; 556 u_int32_t rxfilt; 557 int mcnt = 0; 558 struct ether_multi *enm; 559 struct ether_multistep step; 560 561 ifp = &sc->ethercom.ec_if; 562 563 rxfilt = CSR_READ_4(sc, RL_RXCFG); 564 565 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 566 rxfilt |= RL_RXCFG_RX_MULTI; 567 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 568 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 569 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 570 return; 571 } 572 573 /* first, zot all the existing hash bits */ 574 CSR_WRITE_4(sc, RL_MAR0, 0); 575 CSR_WRITE_4(sc, RL_MAR4, 0); 576 577 /* now program new ones */ 578 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 579 while (enm != NULL) { 580 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 581 ETHER_ADDR_LEN) != 0) 582 continue; 583 584 h = rtk_calchash(enm->enm_addrlo); 585 if (h < 32) 586 hashes[0] |= (1 << h); 587 else 588 hashes[1] |= (1 << (h - 32)); 589 mcnt++; 590 ETHER_NEXT_MULTI(step, enm); 591 } 592 593 if (mcnt) 594 rxfilt |= RL_RXCFG_RX_MULTI; 595 else 596 rxfilt &= ~RL_RXCFG_RX_MULTI; 597 598 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 599 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 600 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 601 602 return; 603 } 604 605 void rtk_reset(sc) 606 struct rtk_softc *sc; 607 { 608 int i; 609 610 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 611 612 for (i = 0; i < RL_TIMEOUT; i++) { 613 DELAY(10); 614 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 615 break; 616 } 617 if (i == RL_TIMEOUT) 618 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 619 620 return; 621 } 622 623 /* 624 * Attach the interface. Allocate softc structures, do ifmedia 625 * setup and ethernet/BPF attach. 626 */ 627 void 628 rtk_attach(sc) 629 struct rtk_softc *sc; 630 { 631 632 struct ifnet *ifp; 633 u_int16_t val; 634 u_int8_t eaddr[ETHER_ADDR_LEN]; 635 bus_dma_segment_t dmaseg; 636 int error,dmanseg; 637 int i,addr_len; 638 639 callout_init(&sc->rtk_tick_ch); 640 641 /* 642 * Check EEPROM type 9346 or 9356. 643 */ 644 if (rtk_read_eeprom(sc, RL_EE_ID, RL_EEADDR_LEN1) == 0x8129) 645 addr_len = RL_EEADDR_LEN1; 646 else 647 addr_len = RL_EEADDR_LEN0; 648 649 /* 650 * Get station address. 651 */ 652 val = rtk_read_eeprom(sc, RL_EE_EADDR0, addr_len); 653 eaddr[0] = val & 0xff; 654 eaddr[1] = val >> 8; 655 val = rtk_read_eeprom(sc, RL_EE_EADDR1, addr_len); 656 eaddr[2] = val & 0xff; 657 eaddr[3] = val >> 8; 658 val = rtk_read_eeprom(sc, RL_EE_EADDR2, addr_len); 659 eaddr[4] = val & 0xff; 660 eaddr[5] = val >> 8; 661 662 if ((error = bus_dmamem_alloc(sc->sc_dmat, 663 RL_RXBUFLEN + 32, NBPG, 0, &dmaseg, 1, &dmanseg, 664 BUS_DMA_NOWAIT)) != 0) { 665 printf("%s: can't allocate recv buffer, error = %d\n", 666 sc->sc_dev.dv_xname, error); 667 goto fail; 668 } 669 670 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 671 RL_RXBUFLEN + 32, (caddr_t *)&sc->rtk_cdata.rtk_rx_buf, 672 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 673 printf("%s: can't map recv buffer, error = %d\n", 674 sc->sc_dev.dv_xname, error); 675 goto fail; 676 } 677 678 /* Leave a few bytes before the start of the RX ring buffer. */ 679 sc->rtk_cdata.rtk_rx_buf_ptr = sc->rtk_cdata.rtk_rx_buf; 680 sc->rtk_cdata.rtk_rx_buf += sizeof(u_int64_t); 681 682 if ((error = bus_dmamap_create(sc->sc_dmat, 683 RL_RXBUFLEN + 32 - sizeof(u_int64_t), 1, 684 RL_RXBUFLEN + 32 - sizeof(u_int64_t), 0, BUS_DMA_NOWAIT, 685 &sc->recv_dmamap)) != 0) { 686 printf("%s: can't create recv buffer DMA map, error = %d\n", 687 sc->sc_dev.dv_xname, error); 688 goto fail; 689 } 690 691 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 692 sc->rtk_cdata.rtk_rx_buf, RL_RXBUFLEN + 32 - sizeof(u_int64_t), NULL, 693 BUS_DMA_NOWAIT)) != 0) { 694 printf("%s: can't load recv buffer DMA map, error = %d\n", 695 sc->sc_dev.dv_xname, error); 696 goto fail; 697 } 698 699 for (i = 0; i < RL_TX_LIST_CNT; i++) 700 if ((error = bus_dmamap_create(sc->sc_dmat, 701 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 702 &sc->snd_dmamap[i])) != 0) { 703 printf("%s: can't create snd buffer DMA map," 704 " error = %d\n", sc->sc_dev.dv_xname, error); 705 goto fail; 706 } 707 708 /* Reset the adapter. */ 709 rtk_reset(sc); 710 711 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 712 ether_sprintf(eaddr)); 713 714 ifp = &sc->ethercom.ec_if; 715 ifp->if_softc = sc; 716 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 717 ifp->if_mtu = ETHERMTU; 718 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 719 ifp->if_ioctl = rtk_ioctl; 720 #if 0 721 ifp->if_output = ether_output; 722 #endif 723 ifp->if_start = rtk_start; 724 ifp->if_watchdog = rtk_watchdog; 725 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 726 727 /* 728 * Do ifmedia setup. 729 */ 730 sc->mii.mii_ifp = ifp; 731 sc->mii.mii_readreg = rtk_phy_readreg; 732 sc->mii.mii_writereg = rtk_phy_writereg; 733 sc->mii.mii_statchg = rtk_phy_statchg; 734 ifmedia_init(&sc->mii.mii_media, 0, rtk_ifmedia_upd, rtk_ifmedia_sts); 735 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 736 MII_PHY_ANY, MII_OFFSET_ANY, 0); 737 738 /* Choose a default media. */ 739 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 740 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 741 0, NULL); 742 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 743 } else { 744 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 745 } 746 747 /* 748 * Call MI attach routines. 749 */ 750 if_attach(ifp); 751 ether_ifattach(ifp, eaddr); 752 753 #if NBPFILTER > 0 754 bpfattach(&sc->ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 755 sizeof(struct ether_header)); 756 #endif 757 shutdownhook_establish(rtk_shutdown, sc); 758 759 fail: 760 return; 761 } 762 763 /* 764 * Initialize the transmit descriptors. 765 */ 766 STATIC int rtk_list_tx_init(sc) 767 struct rtk_softc *sc; 768 { 769 struct rtk_chain_data *cd; 770 int i; 771 772 cd = &sc->rtk_cdata; 773 for (i = 0; i < RL_TX_LIST_CNT; i++) { 774 cd->rtk_tx_chain[i] = NULL; 775 CSR_WRITE_4(sc, 776 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 777 } 778 779 sc->rtk_cdata.cur_tx = 0; 780 sc->rtk_cdata.last_tx = 0; 781 782 return(0); 783 } 784 785 /* 786 * A frame has been uploaded: pass the resulting mbuf chain up to 787 * the higher level protocols. 788 * 789 * You know there's something wrong with a PCI bus-master chip design 790 * when you have to use m_devget(). 791 * 792 * The receive operation is badly documented in the datasheet, so I'll 793 * attempt to document it here. The driver provides a buffer area and 794 * places its base address in the RX buffer start address register. 795 * The chip then begins copying frames into the RX buffer. Each frame 796 * is preceeded by a 32-bit RX status word which specifies the length 797 * of the frame and certain other status bits. Each frame (starting with 798 * the status word) is also 32-bit aligned. The frame length is in the 799 * first 16 bits of the status word; the lower 15 bits correspond with 800 * the 'rx status register' mentioned in the datasheet. 801 * 802 * Note: to make the Alpha happy, the frame payload needs to be aligned 803 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 804 * the ring buffer starting at an address two bytes before the actual 805 * data location. We can then shave off the first two bytes using m_adj(). 806 * The reason we do this is because m_devget() doesn't let us specify an 807 * offset into the mbuf storage space, so we have to artificially create 808 * one. The ring is allocated in such a way that there are a few unused 809 * bytes of space preceecing it so that it will be safe for us to do the 810 * 2-byte backstep even if reading from the ring at offset 0. 811 */ 812 STATIC void rtk_rxeof(sc) 813 struct rtk_softc *sc; 814 { 815 struct ether_header *eh; 816 struct mbuf *m; 817 struct ifnet *ifp; 818 int total_len = 0; 819 u_int32_t rxstat; 820 caddr_t rxbufpos; 821 int wrap = 0; 822 u_int16_t cur_rx; 823 u_int16_t limit; 824 u_int16_t rx_bytes = 0, max_bytes; 825 826 ifp = &sc->ethercom.ec_if; 827 828 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 829 830 /* Do not try to read past this point. */ 831 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 832 833 if (limit < cur_rx) 834 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 835 else 836 max_bytes = limit - cur_rx; 837 838 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 839 rxbufpos = sc->rtk_cdata.rtk_rx_buf + cur_rx; 840 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 841 sizeof(u_int32_t *), BUS_DMASYNC_POSTREAD); 842 rxstat = le32toh(*(u_int32_t *)rxbufpos); 843 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 844 sizeof(u_int32_t *), BUS_DMASYNC_PREREAD); 845 846 /* 847 * Here's a totally undocumented fact for you. When the 848 * RealTek chip is in the process of copying a packet into 849 * RAM for you, the length will be 0xfff0. If you spot a 850 * packet header with this value, you need to stop. The 851 * datasheet makes absolutely no mention of this and 852 * RealTek should be shot for this. 853 */ 854 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 855 break; 856 857 if (!(rxstat & RL_RXSTAT_RXOK)) { 858 ifp->if_ierrors++; 859 860 /* 861 * submitted by:[netbsd-pcmcia:00484] 862 * Takahiro Kambe <taca (at) sky.yamashina.kyoto.jp> 863 * obtain from: 864 * FreeBSD if_rl.c rev 1.24->1.25 865 * 866 */ 867 #if 0 868 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 869 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 870 RL_RXSTAT_ALIGNERR)) { 871 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 872 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 873 RL_RXSTAT_ALIGNERR)) { 874 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB); 875 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB| 876 RL_CMD_RX_ENB); 877 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 878 CSR_WRITE_4(sc, RL_RXADDR, 879 sc->recv_dmamap->dm_segs[0].ds_addr); 880 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 881 cur_rx = 0; 882 } 883 break; 884 #else 885 rtk_init(sc); 886 return; 887 #endif 888 } 889 890 /* No errors; receive the packet. */ 891 total_len = rxstat >> 16; 892 rx_bytes += total_len + 4; 893 894 /* 895 * XXX The RealTek chip includes the CRC with every 896 * received frame, and there's no way to turn this 897 * behavior off (at least, I can't find anything in 898 * the manual that explains how to do it) so we have 899 * to trim off the CRC manually. 900 */ 901 total_len -= ETHER_CRC_LEN; 902 903 /* 904 * Avoid trying to read more bytes than we know 905 * the chip has prepared for us. 906 */ 907 if (rx_bytes > max_bytes) 908 break; 909 910 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 911 cur_rx + sizeof(u_int32_t), total_len, 912 BUS_DMASYNC_POSTREAD); 913 914 rxbufpos = sc->rtk_cdata.rtk_rx_buf + 915 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 916 917 if (rxbufpos == (sc->rtk_cdata.rtk_rx_buf + RL_RXBUFLEN)) 918 rxbufpos = sc->rtk_cdata.rtk_rx_buf; 919 920 wrap = (sc->rtk_cdata.rtk_rx_buf + RL_RXBUFLEN) - rxbufpos; 921 922 if (total_len > wrap) { 923 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 924 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 925 if (m == NULL) { 926 ifp->if_ierrors++; 927 printf("%s: out of mbufs, tried to " 928 "copy %d bytes\n", sc->sc_dev.dv_xname, 929 wrap); 930 } 931 else { 932 m_adj(m, RL_ETHER_ALIGN); 933 m_copyback(m, wrap, total_len - wrap, 934 sc->rtk_cdata.rtk_rx_buf); 935 } 936 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 937 } else { 938 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 939 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 940 if (m == NULL) { 941 ifp->if_ierrors++; 942 printf("%s: out of mbufs, tried to " 943 "copy %d bytes\n", sc->sc_dev.dv_xname, 944 total_len); 945 } else 946 m_adj(m, RL_ETHER_ALIGN); 947 cur_rx += total_len + 4 + ETHER_CRC_LEN; 948 } 949 950 /* 951 * Round up to 32-bit boundary. 952 */ 953 cur_rx = (cur_rx + 3) & ~3; 954 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 955 956 if (m == NULL) 957 continue; 958 959 eh = mtod(m, struct ether_header *); 960 ifp->if_ipackets++; 961 962 #if NBPFILTER > 0 963 /* 964 * Handle BPF listeners. Let the BPF user see the packet, but 965 * don't pass it up to the ether_input() layer unless it's 966 * a broadcast packet, multicast packet, matches our ethernet 967 * address or the interface is in promiscuous mode. 968 */ 969 if (ifp->if_bpf) { 970 bpf_mtap(ifp->if_bpf, m); 971 if ((ifp->if_flags & IFF_PROMISC) != 0 && 972 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 973 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 974 ETHER_ADDR_LEN) != 0) { 975 m_freem(m); 976 continue; 977 } 978 } 979 #endif 980 /* pass it on. */ 981 (*ifp->if_input)(ifp, m); 982 983 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 984 cur_rx + sizeof(u_int32_t), 985 total_len, BUS_DMASYNC_PREREAD); 986 } 987 988 return; 989 } 990 991 /* 992 * A frame was downloaded to the chip. It's safe for us to clean up 993 * the list buffers. 994 */ 995 STATIC void rtk_txeof(sc) 996 struct rtk_softc *sc; 997 { 998 struct ifnet *ifp; 999 u_int32_t txstat; 1000 1001 ifp = &sc->ethercom.ec_if; 1002 1003 /* Clear the timeout timer. */ 1004 ifp->if_timer = 0; 1005 1006 /* 1007 * Go through our tx list and free mbufs for those 1008 * frames that have been uploaded. 1009 */ 1010 do { 1011 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1012 if (!(txstat & (RL_TXSTAT_TX_OK| 1013 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1014 break; 1015 1016 bus_dmamap_sync(sc->sc_dmat, 1017 sc->snd_dmamap[sc->rtk_cdata.last_tx], 0, 1018 sc->snd_dmamap[sc->rtk_cdata.last_tx]->dm_mapsize, 1019 BUS_DMASYNC_POSTWRITE); 1020 bus_dmamap_unload(sc->sc_dmat, 1021 sc->snd_dmamap[sc->rtk_cdata.last_tx]); 1022 m_freem(RL_LAST_TXMBUF(sc)); 1023 RL_LAST_TXMBUF(sc) = NULL; 1024 1025 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1026 1027 if (txstat & RL_TXSTAT_TX_OK) 1028 ifp->if_opackets++; 1029 else { 1030 ifp->if_oerrors++; 1031 if ((txstat & RL_TXSTAT_TXABRT) || 1032 (txstat & RL_TXSTAT_OUTOFWIN)) 1033 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1034 } 1035 RL_INC(sc->rtk_cdata.last_tx); 1036 ifp->if_flags &= ~IFF_OACTIVE; 1037 } while (sc->rtk_cdata.last_tx != sc->rtk_cdata.cur_tx); 1038 1039 return; 1040 } 1041 1042 int rtk_intr(arg) 1043 void *arg; 1044 { 1045 struct rtk_softc *sc; 1046 struct ifnet *ifp; 1047 u_int16_t status; 1048 int handled = 0; 1049 1050 sc = arg; 1051 ifp = &sc->ethercom.ec_if; 1052 1053 /* Disable interrupts. */ 1054 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1055 1056 for (;;) { 1057 1058 status = CSR_READ_2(sc, RL_ISR); 1059 if (status) 1060 CSR_WRITE_2(sc, RL_ISR, status); 1061 1062 handled = 1; 1063 1064 if ((status & RL_INTRS) == 0) 1065 break; 1066 1067 if (status & RL_ISR_RX_OK) 1068 rtk_rxeof(sc); 1069 1070 if (status & RL_ISR_RX_ERR) 1071 rtk_rxeof(sc); 1072 1073 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1074 rtk_txeof(sc); 1075 1076 if (status & RL_ISR_SYSTEM_ERR) { 1077 rtk_reset(sc); 1078 rtk_init(sc); 1079 } 1080 1081 } 1082 1083 /* Re-enable interrupts. */ 1084 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1085 1086 if (ifp->if_snd.ifq_head != NULL) { 1087 rtk_start(ifp); 1088 } 1089 1090 return (handled); 1091 } 1092 1093 /* 1094 * Main transmit routine. 1095 */ 1096 1097 STATIC void rtk_start(ifp) 1098 struct ifnet *ifp; 1099 { 1100 struct rtk_softc *sc; 1101 struct mbuf *m_head = NULL, *m_new; 1102 int error, idx, len; 1103 1104 sc = ifp->if_softc; 1105 1106 while(RL_CUR_TXMBUF(sc) == NULL) { 1107 IF_DEQUEUE(&ifp->if_snd, m_head); 1108 if (m_head == NULL) 1109 break; 1110 1111 idx = sc->rtk_cdata.cur_tx; 1112 1113 /* 1114 * Load the DMA map. If this fails, the packet didn't 1115 * fit in one DMA segment, and we need to copy. Note, 1116 * the packet must also be aligned. 1117 */ 1118 if ((mtod(m_head, bus_addr_t) & 3) != 0 || 1119 bus_dmamap_load_mbuf(sc->sc_dmat, sc->snd_dmamap[idx], 1120 m_head, BUS_DMA_NOWAIT) != 0) { 1121 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1122 if (m_new == NULL) { 1123 printf("%s: unable to allocate Tx mbuf\n", 1124 sc->sc_dev.dv_xname); 1125 IF_PREPEND(&ifp->if_snd, m_new); 1126 break; 1127 } 1128 if (m_head->m_pkthdr.len > MHLEN) { 1129 MCLGET(m_new, M_DONTWAIT); 1130 if ((m_new->m_flags & M_EXT) == 0) { 1131 printf("%s: unable to allocate Tx " 1132 "cluster\n", sc->sc_dev.dv_xname); 1133 m_freem(m_new); 1134 IF_PREPEND(&ifp->if_snd, m_head); 1135 break; 1136 } 1137 } 1138 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1139 mtod(m_new, caddr_t)); 1140 m_new->m_pkthdr.len = m_new->m_len = 1141 m_head->m_pkthdr.len; 1142 m_freem(m_head); 1143 m_head = m_new; 1144 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1145 sc->snd_dmamap[idx], m_head, BUS_DMA_NOWAIT); 1146 if (error) { 1147 printf("%s: unable to load Tx buffer, " 1148 "error = %d\n", sc->sc_dev.dv_xname, error); 1149 IF_PREPEND(&ifp->if_snd, m_head); 1150 break; 1151 } 1152 } 1153 1154 RL_CUR_TXMBUF(sc) = m_head; 1155 1156 #if NBPFILTER > 0 1157 /* 1158 * If there's a BPF listener, bounce a copy of this frame 1159 * to him. 1160 */ 1161 if (ifp->if_bpf) 1162 bpf_mtap(ifp->if_bpf, RL_CUR_TXMBUF(sc)); 1163 #endif 1164 /* 1165 * Transmit the frame. 1166 */ 1167 bus_dmamap_sync(sc->sc_dmat, 1168 sc->snd_dmamap[idx], 0, sc->snd_dmamap[idx]->dm_mapsize, 1169 BUS_DMASYNC_PREWRITE); 1170 1171 len = sc->snd_dmamap[idx]->dm_segs[0].ds_len; 1172 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 1173 len = (ETHER_MIN_LEN - ETHER_CRC_LEN); 1174 1175 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1176 sc->snd_dmamap[idx]->dm_segs[0].ds_addr); 1177 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), RL_TX_EARLYTHRESH | len); 1178 1179 RL_INC(sc->rtk_cdata.cur_tx); 1180 } 1181 1182 /* 1183 * We broke out of the loop because all our TX slots are 1184 * full. Mark the NIC as busy until it drains some of the 1185 * packets from the queue. 1186 */ 1187 if (RL_CUR_TXMBUF(sc) != NULL) 1188 ifp->if_flags |= IFF_OACTIVE; 1189 1190 /* 1191 * Set a timeout in case the chip goes out to lunch. 1192 */ 1193 ifp->if_timer = 5; 1194 1195 return; 1196 } 1197 1198 STATIC void rtk_init(xsc) 1199 void *xsc; 1200 { 1201 struct rtk_softc *sc = xsc; 1202 struct ifnet *ifp = &sc->ethercom.ec_if; 1203 int s, i; 1204 u_int32_t rxcfg; 1205 u_int16_t phy_bmcr = 0; 1206 1207 s = splimp(); 1208 1209 /* 1210 * XXX Hack for the 8139: the built-in autoneg logic's state 1211 * gets reset by rtk_init() when we don't want it to. Try 1212 * to preserve it. 1213 */ 1214 if (sc->rtk_type == RL_8139) 1215 phy_bmcr = rtk_phy_readreg((struct device *)sc, 7, MII_BMCR); 1216 1217 /* 1218 * Cancel pending I/O and free all RX/TX buffers. 1219 */ 1220 rtk_stop(sc); 1221 1222 /* Init our MAC address */ 1223 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1224 CSR_WRITE_1(sc, RL_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1225 } 1226 1227 /* Init the RX buffer pointer register. */ 1228 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1229 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1230 CSR_WRITE_4(sc, RL_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1231 1232 /* Init TX descriptors. */ 1233 rtk_list_tx_init(sc); 1234 1235 /* 1236 * Enable transmit and receive. 1237 */ 1238 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1239 1240 /* 1241 * Set the initial TX and RX configuration. 1242 */ 1243 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1244 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1245 1246 /* Set the individual bit to receive frames for this host only. */ 1247 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1248 rxcfg |= RL_RXCFG_RX_INDIV; 1249 1250 /* If we want promiscuous mode, set the allframes bit. */ 1251 if (ifp->if_flags & IFF_PROMISC) { 1252 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1253 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1254 } else { 1255 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1256 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1257 } 1258 1259 /* 1260 * Set capture broadcast bit to capture broadcast frames. 1261 */ 1262 if (ifp->if_flags & IFF_BROADCAST) { 1263 rxcfg |= RL_RXCFG_RX_BROAD; 1264 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1265 } else { 1266 rxcfg &= ~RL_RXCFG_RX_BROAD; 1267 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1268 } 1269 1270 /* 1271 * Program the multicast filter, if necessary. 1272 */ 1273 rtk_setmulti(sc); 1274 1275 /* 1276 * Enable interrupts. 1277 */ 1278 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1279 1280 /* Start RX/TX process. */ 1281 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1282 1283 /* Enable receiver and transmitter. */ 1284 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1285 1286 /* Restore state of BMCR */ 1287 if (sc->rtk_type == RL_8139) 1288 rtk_phy_writereg((struct device *)sc, 7, MII_BMCR, phy_bmcr); 1289 1290 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1291 1292 /* 1293 * Set current media. 1294 */ 1295 mii_mediachg(&sc->mii); 1296 1297 ifp->if_flags |= IFF_RUNNING; 1298 ifp->if_flags &= ~IFF_OACTIVE; 1299 1300 (void)splx(s); 1301 1302 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1303 } 1304 1305 /* 1306 * Set media options. 1307 */ 1308 STATIC int rtk_ifmedia_upd(ifp) 1309 struct ifnet *ifp; 1310 { 1311 struct rtk_softc *sc; 1312 struct ifmedia *ifm; 1313 1314 sc = ifp->if_softc; 1315 ifm = &sc->mii.mii_media; 1316 1317 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1318 return(EINVAL); 1319 1320 return (mii_mediachg(&sc->mii)); 1321 } 1322 1323 /* 1324 * Report current media status. 1325 */ 1326 STATIC void rtk_ifmedia_sts(ifp, ifmr) 1327 struct ifnet *ifp; 1328 struct ifmediareq *ifmr; 1329 { 1330 struct rtk_softc *sc; 1331 1332 sc = ifp->if_softc; 1333 1334 mii_pollstat(&sc->mii); 1335 ifmr->ifm_status = sc->mii.mii_media_status; 1336 ifmr->ifm_active = sc->mii.mii_media_active; 1337 } 1338 1339 STATIC int 1340 rtk_ether_ioctl(ifp, cmd, data) 1341 struct ifnet *ifp; 1342 u_long cmd; 1343 caddr_t data; 1344 { 1345 struct ifaddr *ifa = (struct ifaddr *) data; 1346 struct rtk_softc *sc = ifp->if_softc; 1347 1348 switch (cmd) { 1349 case SIOCSIFADDR: 1350 ifp->if_flags |= IFF_UP; 1351 1352 switch (ifa->ifa_addr->sa_family) { 1353 #ifdef INET 1354 case AF_INET: 1355 rtk_init(sc); 1356 arp_ifinit(ifp, ifa); 1357 break; 1358 #endif 1359 #ifdef NS 1360 case AF_NS: 1361 { 1362 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1363 1364 if (ns_nullhost(*ina)) 1365 ina->x_host = *(union ns_host *) 1366 LLADDR(ifp->if_sadl); 1367 else 1368 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1369 ifp->if_addrlen); 1370 /* Set new address. */ 1371 rtk_init(sc); 1372 break; 1373 } 1374 #endif 1375 default: 1376 rtk_init(sc); 1377 break; 1378 } 1379 break; 1380 1381 default: 1382 return (EINVAL); 1383 } 1384 1385 return (0); 1386 } 1387 1388 STATIC int rtk_ioctl(ifp, command, data) 1389 struct ifnet *ifp; 1390 u_long command; 1391 caddr_t data; 1392 { 1393 struct rtk_softc *sc = ifp->if_softc; 1394 struct ifreq *ifr = (struct ifreq *) data; 1395 int s, error = 0; 1396 1397 s = splimp(); 1398 1399 switch(command) { 1400 case SIOCSIFADDR: 1401 case SIOCGIFADDR: 1402 case SIOCSIFMTU: 1403 error = rtk_ether_ioctl(ifp, command, data); 1404 break; 1405 case SIOCSIFFLAGS: 1406 if (ifp->if_flags & IFF_UP) { 1407 rtk_init(sc); 1408 } else { 1409 if (ifp->if_flags & IFF_RUNNING) 1410 rtk_stop(sc); 1411 } 1412 error = 0; 1413 break; 1414 case SIOCADDMULTI: 1415 case SIOCDELMULTI: 1416 rtk_setmulti(sc); 1417 error = 0; 1418 break; 1419 case SIOCGIFMEDIA: 1420 case SIOCSIFMEDIA: 1421 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1422 break; 1423 default: 1424 error = EINVAL; 1425 break; 1426 } 1427 1428 (void)splx(s); 1429 1430 return(error); 1431 } 1432 1433 STATIC void rtk_watchdog(ifp) 1434 struct ifnet *ifp; 1435 { 1436 struct rtk_softc *sc; 1437 1438 sc = ifp->if_softc; 1439 1440 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1441 ifp->if_oerrors++; 1442 rtk_txeof(sc); 1443 rtk_rxeof(sc); 1444 rtk_init(sc); 1445 1446 return; 1447 } 1448 1449 /* 1450 * Stop the adapter and free any mbufs allocated to the 1451 * RX and TX lists. 1452 */ 1453 STATIC void rtk_stop(sc) 1454 struct rtk_softc *sc; 1455 { 1456 int i; 1457 struct ifnet *ifp; 1458 1459 ifp = &sc->ethercom.ec_if; 1460 ifp->if_timer = 0; 1461 1462 callout_stop(&sc->rtk_tick_ch); 1463 1464 mii_down(&sc->mii); 1465 1466 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1467 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1468 1469 /* 1470 * Free the TX list buffers. 1471 */ 1472 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1473 if (sc->rtk_cdata.rtk_tx_chain[i] != NULL) { 1474 m_freem(sc->rtk_cdata.rtk_tx_chain[i]); 1475 sc->rtk_cdata.rtk_tx_chain[i] = NULL; 1476 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1477 } 1478 } 1479 1480 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1481 1482 return; 1483 } 1484 1485 /* 1486 * Stop all chip I/O so that the kernel's probe routines don't 1487 * get confused by errant DMAs when rebooting. 1488 */ 1489 STATIC void rtk_shutdown(vsc) 1490 void *vsc; 1491 { 1492 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1493 1494 rtk_stop(sc); 1495 1496 return; 1497 } 1498 1499 STATIC void 1500 rtk_tick(arg) 1501 void *arg; 1502 { 1503 struct rtk_softc *sc = arg; 1504 int s = splnet(); 1505 1506 mii_tick(&sc->mii); 1507 splx(s); 1508 1509 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1510 } 1511
Indexes created Tue Sep 23 02:09:52 GMT 2025