rtl81x9reg.h revision 1.47
1 /* $NetBSD: rtl81x9reg.h,v 1.47 2015/08/28 13:20:46 nonaka Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 register offsets 39 */ 40 #define RTK_IDR0 0x0000 /* ID register 0 (station addr) */ 41 #define RTK_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 42 #define RTK_IDR2 0x0002 43 #define RTK_IDR3 0x0003 44 #define RTK_IDR4 0x0004 45 #define RTK_IDR5 0x0005 46 /* 0006-0007 reserved */ 47 #define RTK_MAR0 0x0008 /* Multicast hash table */ 48 #define RTK_MAR1 0x0009 49 #define RTK_MAR2 0x000A 50 #define RTK_MAR3 0x000B 51 #define RTK_MAR4 0x000C 52 #define RTK_MAR5 0x000D 53 #define RTK_MAR6 0x000E 54 #define RTK_MAR7 0x000F 55 56 #define RTK_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 57 #define RTK_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 58 #define RTK_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 59 #define RTK_TXSTAT3 0x001C /* status of TX descriptor 3 */ 60 61 #define RTK_TXADDR0 0x0020 /* address of TX descriptor 0 */ 62 #define RTK_TXADDR1 0x0024 /* address of TX descriptor 1 */ 63 #define RTK_TXADDR2 0x0028 /* address of TX descriptor 2 */ 64 #define RTK_TXADDR3 0x002C /* address of TX descriptor 3 */ 65 66 #define RTK_RXADDR 0x0030 /* RX ring start address */ 67 #define RTK_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 68 #define RTK_RX_EARLY_STAT 0x0036 /* RX early status */ 69 #define RTK_COMMAND 0x0037 /* command register */ 70 #define RTK_CURRXADDR 0x0038 /* current address of packet read */ 71 #define RTK_CURRXBUF 0x003A /* current RX buffer address */ 72 #define RTK_IMR 0x003C /* interrupt mask register */ 73 #define RTK_ISR 0x003E /* interrupt status register */ 74 #define RTK_TXCFG 0x0040 /* transmit config */ 75 #define RTK_RXCFG 0x0044 /* receive config */ 76 #define RTK_TIMERCNT 0x0048 /* timer count register */ 77 #define RTK_MISSEDPKT 0x004C /* missed packet counter */ 78 #define RTK_EECMD 0x0050 /* EEPROM command register */ 79 #define RTK_CFG0 0x0051 /* config register #0 */ 80 #define RTK_CFG1 0x0052 /* config register #1 */ 81 /* 0053-0057 reserved */ 82 #define RTK_MEDIASTAT 0x0058 /* media status register (8139) */ 83 /* 0059-005A reserved */ 84 #define RTK_MII 0x005A /* 8129 chip only */ 85 #define RTK_HALTCLK 0x005B 86 #define RTK_MULTIINTR 0x005C /* multiple interrupt */ 87 #define RTK_PCIREV 0x005E /* PCI revision value */ 88 /* 005F reserved */ 89 #define RTK_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 90 91 /* Direct PHY access registers only available on 8139 */ 92 #define RTK_BMCR 0x0062 /* PHY basic mode control */ 93 #define RTK_BMSR 0x0064 /* PHY basic mode status */ 94 #define RTK_ANAR 0x0066 /* PHY autoneg advert */ 95 #define RTK_LPAR 0x0068 /* PHY link partner ability */ 96 #define RTK_ANER 0x006A /* PHY autoneg expansion */ 97 98 #define RTK_DISCCNT 0x006C /* disconnect counter */ 99 #define RTK_FALSECAR 0x006E /* false carrier counter */ 100 #define RTK_NWAYTST 0x0070 /* NWAY test register */ 101 #define RTK_RX_ER 0x0072 /* RX_ER counter */ 102 #define RTK_CSCFG 0x0074 /* CS configuration register */ 103 104 /* 105 * When operating in special C+ mode, some of the registers in an 106 * 8139C+ chip have different definitions. These are also used for 107 * the 8169 gigE chip. 108 */ 109 #define RTK_DUMPSTATS_LO 0x0010 /* counter dump command register */ 110 #define RTK_DUMPSTATS_HI 0x0014 /* counter dump command register */ 111 #define RTK_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 112 #define RTK_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 113 #define RTK_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte aligned */ 114 #define RTK_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte aligned */ 115 #define RTK_CFG2 0x0053 116 #define RTK_TIMERINT 0x0054 /* interrupt on timer expire */ 117 #define RTK_TXSTART 0x00D9 /* 8 bits */ 118 #define RTK_CPLUS_CMD 0x00E0 /* 16 bits */ 119 #define RTK_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 120 #define RTK_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 121 #define RTK_EARLY_TX_THRESH 0x00EC /* 8 bits */ 122 123 /* 124 * Registers specific to the 8169 gigE chip 125 */ 126 #define RTK_GTXSTART 0x0038 /* 8 bits */ 127 #define RTK_TIMERINT_8169 0x0058 /* different offset than 8139 */ 128 #define RTK_PHYAR 0x0060 129 #define RTK_CSIDR 0x0064 130 #define RTK_CSIAR 0x0068 131 #define RTK_TBI_LPAR 0x006A 132 #define RTK_GMEDIASTAT 0x006C /* 8 bits */ 133 #define RTK_PMCH 0x006F /* 8 bits */ 134 #define RTK_EPHYAR 0x0080 135 #define RTK_LDPS 0x0082 /* Link Down Power Saving */ 136 #define RTK_DBG_REG 0x00D1 137 #define RTK_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 138 #define RTK_IM 0x00E2 139 #define RTK_MISC 0x00F0 140 141 /* 142 * TX config register bits 143 */ 144 #define RTK_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145 #define RTK_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 146 #define RTK_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 147 #define RTK_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 148 #define RTK_TXCFG_IFG2 0x00080000 /* 8169 only */ 149 #define RTK_TXCFG_IFG 0x03000000 /* interframe gap */ 150 #define RTK_TXCFG_HWREV 0x7CC00000 151 152 #define RTK_LOOPTEST_OFF 0x00000000 153 #define RTK_LOOPTEST_ON 0x00020000 154 #define RTK_LOOPTEST_ON_CPLUS 0x00060000 155 156 /* Known revision codes. */ 157 #define RTK_HWREV_8169 0x00000000 158 #define RTK_HWREV_8110S 0x00800000 159 #define RTK_HWREV_8169S 0x04000000 160 #define RTK_HWREV_8169_8110SB 0x10000000 161 #define RTK_HWREV_8169_8110SC 0x18000000 162 #define RTK_HWREV_8102EL 0x24800000 163 #define RTK_HWREV_8103E 0x24C00000 164 #define RTK_HWREV_8168D 0x28000000 165 #define RTK_HWREV_8168DP 0x28800000 166 #define RTK_HWREV_8168E 0x2C000000 167 #define RTK_HWREV_8168E_VL 0x2C800000 168 #define RTK_HWREV_8168_SPIN1 0x30000000 169 #define RTK_HWREV_8168G 0x4c000000 170 #define RTK_HWREV_8168G_SPIN1 0x4c100000 171 #define RTK_HWREV_8168G_SPIN2 0x50900000 172 #define RTK_HWREV_8168G_SPIN4 0x5c800000 173 #define RTK_HWREV_8168GU 0x50800000 174 #define RTK_HWREV_8100E 0x30800000 175 #define RTK_HWREV_8101E 0x34000000 176 #define RTK_HWREV_8102E 0x34800000 177 #define RTK_HWREV_8168_SPIN2 0x38000000 178 #define RTK_HWREV_8168_SPIN3 0x38400000 179 #define RTK_HWREV_8100E_SPIN2 0x38800000 180 #define RTK_HWREV_8168C 0x3C000000 181 #define RTK_HWREV_8168C_SPIN2 0x3C400000 182 #define RTK_HWREV_8168CP 0x3C800000 183 #define RTK_HWREV_8168F 0x48000000 184 #define RTK_HWREV_8168H 0x54000000 185 #define RTK_HWREV_8168H_SPIN1 0x54100000 186 #define RTK_HWREV_8139 0x60000000 187 #define RTK_HWREV_8139A 0x70000000 188 #define RTK_HWREV_8139AG 0x70800000 189 #define RTK_HWREV_8139B 0x78000000 190 #define RTK_HWREV_8130 0x7C000000 191 #define RTK_HWREV_8139C 0x74000000 192 #define RTK_HWREV_8139D 0x74400000 193 #define RTK_HWREV_8139CPLUS 0x74800000 194 #define RTK_HWREV_8101 0x74c00000 195 #define RTK_HWREV_8100 0x78800000 196 #define RTK_HWREV_8169_8110SBL 0x7cc00000 197 198 #define RTK_TXDMA_16BYTES 0x00000000 199 #define RTK_TXDMA_32BYTES 0x00000100 200 #define RTK_TXDMA_64BYTES 0x00000200 201 #define RTK_TXDMA_128BYTES 0x00000300 202 #define RTK_TXDMA_256BYTES 0x00000400 203 #define RTK_TXDMA_512BYTES 0x00000500 204 #define RTK_TXDMA_1024BYTES 0x00000600 205 #define RTK_TXDMA_2048BYTES 0x00000700 206 207 /* 208 * Transmit descriptor status register bits. 209 */ 210 #define RTK_TXSTAT_LENMASK 0x00001FFF 211 #define RTK_TXSTAT_OWN 0x00002000 212 #define RTK_TXSTAT_TX_UNDERRUN 0x00004000 213 #define RTK_TXSTAT_TX_OK 0x00008000 214 #define RTK_TXSTAT_EARLY_THRESH 0x003F0000 215 #define RTK_TXSTAT_COLLCNT 0x0F000000 216 #define RTK_TXSTAT_CARR_HBEAT 0x10000000 217 #define RTK_TXSTAT_OUTOFWIN 0x20000000 218 #define RTK_TXSTAT_TXABRT 0x40000000 219 #define RTK_TXSTAT_CARRLOSS 0x80000000 220 221 #define RTK_TXSTAT_THRESH(x) (((x) << 16) & RTK_TXSTAT_EARLY_THRESH) 222 #define RTK_TXTH_256 8 /* (x) * 32 bytes */ 223 #define RTK_TXTH_1536 48 224 225 /* MISC register */ 226 #define RTK_MISC_TXPLA_RST __BIT(29) 227 #define RTK_MISC_DISABLE_LAN_EN __BIT(23) /* Enable GPIO pin */ 228 #define RTK_MISC_PWM_EN __BIT(22) 229 #define RTK_MISC_RXDV_GATED_EN __BIT(19) 230 #define RTK_MISC_EARLY_TALLY_EN __BIT(16) 231 232 233 /* 234 * Interrupt status register bits. 235 */ 236 #define RTK_ISR_RX_OK 0x0001 237 #define RTK_ISR_RX_ERR 0x0002 238 #define RTK_ISR_TX_OK 0x0004 239 #define RTK_ISR_TX_ERR 0x0008 240 #define RTK_ISR_RX_OVERRUN 0x0010 241 #define RTK_ISR_PKT_UNDERRUN 0x0020 242 #define RTK_ISR_LINKCHG 0x0020 /* 8169 only */ 243 #define RTK_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 244 #define RTK_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 245 #define RTK_ISR_SWI 0x0100 /* C+ only */ 246 #define RTK_ISR_CABLE_LEN_CHGD 0x2000 247 #define RTK_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 248 #define RTK_ISR_TIMEOUT_EXPIRED 0x4000 249 #define RTK_ISR_SYSTEM_ERR 0x8000 250 251 #define RTK_INTRS \ 252 (RTK_ISR_TX_OK|RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR| \ 253 RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \ 254 RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR) 255 256 #define RTK_INTRS_CPLUS \ 257 (RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR| \ 258 RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \ 259 RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR|RTK_ISR_TIMEOUT_EXPIRED) 260 261 262 /* 263 * Media status register. (8139 only) 264 */ 265 #define RTK_MEDIASTAT_RXPAUSE 0x01 266 #define RTK_MEDIASTAT_TXPAUSE 0x02 267 #define RTK_MEDIASTAT_LINK 0x04 268 #define RTK_MEDIASTAT_SPEED10 0x08 269 #define RTK_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 270 #define RTK_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 271 272 /* 273 * Receive config register. 274 */ 275 #define RTK_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 276 #define RTK_RXCFG_RX_INDIV 0x00000002 /* match filter */ 277 #define RTK_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 278 #define RTK_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 279 #define RTK_RXCFG_RX_RUNT 0x00000010 280 #define RTK_RXCFG_RX_ERRPKT 0x00000020 281 #define RTK_RXCFG_WRAP 0x00000080 282 #define RTK_RXCFG_MAXDMA 0x00000700 283 #define RTK_RXCFG_BUFSZ 0x00001800 284 #define RTK_RXCFG_FIFOTHRESH 0x0000E000 285 #define RTK_RXCFG_EARLYTHRESH 0x07000000 286 287 #define RTK_RXDMA_16BYTES 0x00000000 288 #define RTK_RXDMA_32BYTES 0x00000100 289 #define RTK_RXDMA_64BYTES 0x00000200 290 #define RTK_RXDMA_128BYTES 0x00000300 291 #define RTK_RXDMA_256BYTES 0x00000400 292 #define RTK_RXDMA_512BYTES 0x00000500 293 #define RTK_RXDMA_1024BYTES 0x00000600 294 #define RTK_RXDMA_UNLIMITED 0x00000700 295 296 #define RTK_RXBUF_8 0x00000000 297 #define RTK_RXBUF_16 0x00000800 298 #define RTK_RXBUF_32 0x00001000 299 #define RTK_RXBUF_64 0x00001800 300 #define RTK_RXBUF_LEN(x) (1 << (((x) >> 11) + 13)) 301 302 #define RTK_RXFIFO_16BYTES 0x00000000 303 #define RTK_RXFIFO_32BYTES 0x00002000 304 #define RTK_RXFIFO_64BYTES 0x00004000 305 #define RTK_RXFIFO_128BYTES 0x00006000 306 #define RTK_RXFIFO_256BYTES 0x00008000 307 #define RTK_RXFIFO_512BYTES 0x0000A000 308 #define RTK_RXFIFO_1024BYTES 0x0000C000 309 #define RTK_RXFIFO_NOTHRESH 0x0000E000 310 311 /* 312 * Bits in RX status header (included with RX'ed packet 313 * in ring buffer). 314 */ 315 #define RTK_RXSTAT_RXOK 0x00000001 316 #define RTK_RXSTAT_ALIGNERR 0x00000002 317 #define RTK_RXSTAT_CRCERR 0x00000004 318 #define RTK_RXSTAT_GIANT 0x00000008 319 #define RTK_RXSTAT_RUNT 0x00000010 320 #define RTK_RXSTAT_BADSYM 0x00000020 321 #define RTK_RXSTAT_BROAD 0x00002000 322 #define RTK_RXSTAT_INDIV 0x00004000 323 #define RTK_RXSTAT_MULTI 0x00008000 324 #define RTK_RXSTAT_LENMASK 0xFFFF0000 325 326 #define RTK_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 327 /* 328 * Command register. 329 */ 330 #define RTK_CMD_EMPTY_RXBUF 0x0001 331 #define RTK_CMD_TX_ENB 0x0004 332 #define RTK_CMD_RX_ENB 0x0008 333 #define RTK_CMD_RESET 0x0010 334 #define RTK_CMD_STOPREQ 0x0080 335 336 /* 337 * EEPROM control register 338 */ 339 #define RTK_EE_DATAOUT 0x01 /* Data out */ 340 #define RTK_EE_DATAIN 0x02 /* Data in */ 341 #define RTK_EE_CLK 0x04 /* clock */ 342 #define RTK_EE_SEL 0x08 /* chip select */ 343 #define RTK_EE_MODE (0x40|0x80) 344 345 #define RTK_EEMODE_OFF 0x00 346 #define RTK_EEMODE_AUTOLOAD 0x40 347 #define RTK_EEMODE_PROGRAM 0x80 348 #define RTK_EEMODE_WRITECFG (0x80|0x40) 349 350 /* 9346/9356 EEPROM commands */ 351 #define RTK_EEADDR_LEN0 6 /* 9346 */ 352 #define RTK_EEADDR_LEN1 8 /* 9356 */ 353 #define RTK_EECMD_LEN 4 354 355 #define RTK_EECMD_WRITE 0x5 /* 0101b */ 356 #define RTK_EECMD_READ 0x6 /* 0110b */ 357 #define RTK_EECMD_ERASE 0x7 /* 0111b */ 358 359 #define RTK_EE_ID 0x00 360 #define RTK_EE_PCI_VID 0x01 361 #define RTK_EE_PCI_DID 0x02 362 /* Location of station address inside EEPROM */ 363 #define RTK_EE_EADDR0 0x07 364 #define RTK_EE_EADDR1 0x08 365 #define RTK_EE_EADDR2 0x09 366 367 /* 368 * MII register (8129 only) 369 */ 370 #define RTK_MII_CLK 0x01 371 #define RTK_MII_DATAIN 0x02 372 #define RTK_MII_DATAOUT 0x04 373 #define RTK_MII_DIR 0x80 /* 0 == input, 1 == output */ 374 375 /* 376 * Config 0 register 377 */ 378 #define RTK_CFG0_ROM0 0x01 379 #define RTK_CFG0_ROM1 0x02 380 #define RTK_CFG0_ROM2 0x04 381 #define RTK_CFG0_PL0 0x08 382 #define RTK_CFG0_PL1 0x10 383 #define RTK_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 384 #define RTK_CFG0_PCS 0x40 385 #define RTK_CFG0_SCR 0x80 386 387 /* 388 * Config 1 register 389 */ 390 #define RTK_CFG1_PWRDWN 0x01 391 #define RTK_CFG1_SLEEP 0x02 392 #define RTK_CFG1_IOMAP 0x04 393 #define RTK_CFG1_MEMMAP 0x08 394 #define RTK_CFG1_RSVD 0x10 395 #define RTK_CFG1_DRVLOAD 0x20 396 #define RTK_CFG1_LED0 0x40 397 #define RTK_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 398 #define RTK_CFG1_LED1 0x80 399 400 /* 401 * 8139C+ register definitions 402 */ 403 404 /* RTK_DUMPSTATS_LO register */ 405 406 #define RTK_DUMPSTATS_START 0x00000008 407 408 /* Transmit start register */ 409 410 #define RTK_TXSTART_SWI 0x01 /* generate TX interrupt */ 411 #define RTK_TXSTART_START 0x40 /* start normal queue transmit */ 412 #define RTK_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 413 414 /* 415 * Config 2 register, 8139C+/8169/8169S/8110S only 416 */ 417 #define RTK_CFG2_BUSFREQ 0x07 418 #define RTK_CFG2_BUSWIDTH 0x08 419 #define RTK_CFG2_AUXPWRSTS 0x10 420 421 #define RTK_BUSFREQ_33MHZ 0x00 422 #define RTK_BUSFREQ_66MHZ 0x01 423 424 #define RTK_BUSWIDTH_32BITS 0x00 425 #define RTK_BUSWIDTH_64BITS 0x08 426 427 /* C+ mode command register */ 428 429 #define RE_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 430 #define RE_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 431 #define RE_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 432 #define RE_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 433 #define RE_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 434 #define RE_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 435 #define RE_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 436 #define RE_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 437 #define RE_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 438 #define RE_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 439 #define RE_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 440 #define RE_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 441 #define RE_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 442 #define RE_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 443 #define RE_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 444 445 /* C+ early transmit threshold */ 446 447 #define RTK_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 448 449 /* 450 * Gigabit PHY access register (8169 only) 451 */ 452 453 #define RTK_PHYAR_PHYDATA 0x0000FFFF 454 #define RTK_PHYAR_PHYREG 0x001F0000 455 #define RTK_PHYAR_BUSY 0x80000000 456 457 /* 458 * Gigabit media status (8169 only) 459 */ 460 #define RTK_GMEDIASTAT_FDX 0x01 /* full duplex */ 461 #define RTK_GMEDIASTAT_LINK 0x02 /* link up */ 462 #define RTK_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 463 #define RTK_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 464 #define RTK_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 465 #define RTK_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 466 #define RTK_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 467 #define RTK_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 468 469 470 #define RTK_TX_EARLYTHRESH ((256 / 32) << 16) 471 #define RTK_RX_FIFOTHRESH RTK_RXFIFO_256BYTES 472 #define RTK_RX_MAXDMA RTK_RXDMA_256BYTES 473 #define RTK_TX_MAXDMA RTK_TXDMA_256BYTES 474 475 #define RTK_RXCFG_CONFIG (RTK_RX_FIFOTHRESH|RTK_RX_MAXDMA|RTK_RX_BUF_SZ) 476 #define RTK_TXCFG_CONFIG (RTK_TXCFG_IFG|RTK_TX_MAXDMA) 477 478 #define RE_RX_FIFOTHRESH RTK_RXFIFO_NOTHRESH 479 #define RE_RX_MAXDMA RTK_RXDMA_UNLIMITED 480 #define RE_TX_MAXDMA RTK_TXDMA_2048BYTES 481 482 #define RE_RXCFG_CONFIG (RE_RX_FIFOTHRESH|RE_RX_MAXDMA|RTK_RX_BUF_SZ) 483 #define RE_TXCFG_CONFIG (RTK_TXCFG_IFG|RE_TX_MAXDMA) 484 485 /* 486 * RX/TX descriptor definition. When large send mode is enabled, the 487 * lower 11 bits of the TX rtk_cmd word are used to hold the MSS, and 488 * the checksum offload bits are disabled. The structure layout is 489 * the same for RX and TX descriptors 490 */ 491 492 struct re_desc { 493 volatile uint32_t re_cmdstat; 494 volatile uint32_t re_vlanctl; 495 volatile uint32_t re_bufaddr_lo; 496 volatile uint32_t re_bufaddr_hi; 497 }; 498 499 #define RE_TDESC_CMD_FRAGLEN 0x0000FFFF 500 #define RE_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 501 #define RE_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 502 #define RE_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 503 #define RE_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 504 #define RE_TDESC_CMD_MSSVAL_SHIFT 16 /* Shift of the above */ 505 #define RE_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 506 #define RE_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 507 #define RE_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 508 #define RE_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 509 #define RE_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 510 511 #define RE_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 512 #define RE_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 513 #define RE_TDESC_VLANCTL_UDPCSUM 0x80000000 /* DESCV2 UDP cksum enable */ 514 #define RE_TDESC_VLANCTL_TCPCSUM 0x40000000 /* DESCV2 TCP cksum enable */ 515 #define RE_TDESC_VLANCTL_IPCSUM 0x20000000 /* DESCV2 IP hdr cksum enable */ 516 517 /* 518 * Error bits are valid only on the last descriptor of a frame 519 * (i.e. RE_TDESC_CMD_EOF == 1) 520 */ 521 522 #define RE_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 523 #define RE_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 524 #define RE_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 525 #define RE_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 526 #define RE_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 527 #define RE_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occurred */ 528 #define RE_TDESC_STAT_OWN 0x80000000 529 530 /* 531 * RX descriptor cmd/vlan definitions 532 */ 533 534 #define RE_RDESC_CMD_EOR 0x40000000 535 #define RE_RDESC_CMD_OWN 0x80000000 536 #define RE_RDESC_CMD_BUFLEN 0x00001FFF 537 538 #define RE_RDESC_STAT_OWN 0x80000000 539 #define RE_RDESC_STAT_EOR 0x40000000 540 #define RE_RDESC_STAT_SOF 0x20000000 541 #define RE_RDESC_STAT_EOF 0x10000000 542 #define RE_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 543 #define RE_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 544 #define RE_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 545 #define RE_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 546 #define RE_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 547 #define RE_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 548 #define RE_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 549 #define RE_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 550 #define RE_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 551 #define RE_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 552 #define RE_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 553 #define RE_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 554 #define RE_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 555 #define RE_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 556 #define RE_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 557 #define RE_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 558 559 #define RE_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 560 (re_vlandata valid)*/ 561 #define RE_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 562 #define RE_RDESC_VLANCTL_IPV6 0x80000000 /* DESCV2 IPV6 packet */ 563 #define RE_RDESC_VLANCTL_IPV4 0x40000000 /* DESCV2 IPV4 packet */ 564 565 #define RE_PROTOID_NONIP 0x00000000 566 #define RE_PROTOID_TCPIP 0x00010000 567 #define RE_PROTOID_UDPIP 0x00020000 568 #define RE_PROTOID_IP 0x00030000 569 #define RE_TCPPKT(x) (((x) & RE_RDESC_STAT_PROTOID) == \ 570 RE_PROTOID_TCPIP) 571 #define RE_UDPPKT(x) (((x) & RE_RDESC_STAT_PROTOID) == \ 572 RE_PROTOID_UDPIP) 573 574 #define RE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) 575 #define RE_ADDR_HI(y) ((uint64_t)(y) >> 32) 576 577 /* 578 * Statistics counter structure (8139C+ and 8169 only) 579 */ 580 struct re_stats { 581 uint32_t re_tx_pkts_lo; 582 uint32_t re_tx_pkts_hi; 583 uint32_t re_tx_errs_lo; 584 uint32_t re_tx_errs_hi; 585 uint32_t re_tx_errs; 586 uint16_t re_missed_pkts; 587 uint16_t re_rx_framealign_errs; 588 uint32_t re_tx_onecoll; 589 uint32_t re_tx_multicolls; 590 uint32_t re_rx_ucasts_hi; 591 uint32_t re_rx_ucasts_lo; 592 uint32_t re_rx_bcasts_lo; 593 uint32_t re_rx_bcasts_hi; 594 uint32_t re_rx_mcasts; 595 uint16_t re_tx_aborts; 596 uint16_t re_rx_underruns; 597 }; 598 599 #define RE_IFQ_MAXLEN 512 600 601 #define RE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO 602 #define RE_JUMBO_MTU ETHERMTU_JUMBO 603
Indexes created Tue Sep 30 11:09:46 GMT 2025