rtl81x9reg.h revision 1.7
1 /* $NetBSD: rtl81x9reg.h,v 1.7 2003/10/25 23:48:45 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 register offsets 39 */ 40 #define RTK_IDR0 0x0000 /* ID register 0 (station addr) */ 41 #define RTK_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 42 #define RTK_IDR2 0x0002 43 #define RTK_IDR3 0x0003 44 #define RTK_IDR4 0x0004 45 #define RTK_IDR5 0x0005 46 /* 0006-0007 reserved */ 47 #define RTK_MAR0 0x0008 /* Multicast hash table */ 48 #define RTK_MAR1 0x0009 49 #define RTK_MAR2 0x000A 50 #define RTK_MAR3 0x000B 51 #define RTK_MAR4 0x000C 52 #define RTK_MAR5 0x000D 53 #define RTK_MAR6 0x000E 54 #define RTK_MAR7 0x000F 55 56 #define RTK_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 57 #define RTK_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 58 #define RTK_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 59 #define RTK_TXSTAT3 0x001C /* status of TX descriptor 3 */ 60 61 #define RTK_TXADDR0 0x0020 /* address of TX descriptor 0 */ 62 #define RTK_TXADDR1 0x0024 /* address of TX descriptor 1 */ 63 #define RTK_TXADDR2 0x0028 /* address of TX descriptor 2 */ 64 #define RTK_TXADDR3 0x002C /* address of TX descriptor 3 */ 65 66 #define RTK_RXADDR 0x0030 /* RX ring start address */ 67 #define RTK_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 68 #define RTK_RX_EARLY_STAT 0x0036 /* RX early status */ 69 #define RTK_COMMAND 0x0037 /* command register */ 70 #define RTK_CURRXADDR 0x0038 /* current address of packet read */ 71 #define RTK_CURRXBUF 0x003A /* current RX buffer address */ 72 #define RTK_IMR 0x003C /* interrupt mask register */ 73 #define RTK_ISR 0x003E /* interrupt status register */ 74 #define RTK_TXCFG 0x0040 /* transmit config */ 75 #define RTK_RXCFG 0x0044 /* receive config */ 76 #define RTK_TIMERCNT 0x0048 /* timer count register */ 77 #define RTK_MISSEDPKT 0x004C /* missed packet counter */ 78 #define RTK_EECMD 0x0050 /* EEPROM command register */ 79 #define RTK_CFG0 0x0051 /* config register #0 */ 80 #define RTK_CFG1 0x0052 /* config register #1 */ 81 /* 0053-0057 reserved */ 82 #define RTK_MEDIASTAT 0x0058 /* media status register (8139) */ 83 /* 0059-005A reserved */ 84 #define RTK_MII 0x005A /* 8129 chip only */ 85 #define RTK_HALTCLK 0x005B 86 #define RTK_MULTIINTR 0x005C /* multiple interrupt */ 87 #define RTK_PCIREV 0x005E /* PCI revision value */ 88 /* 005F reserved */ 89 #define RTK_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 90 91 /* Direct PHY access registers only available on 8139 */ 92 #define RTK_BMCR 0x0062 /* PHY basic mode control */ 93 #define RTK_BMSR 0x0064 /* PHY basic mode status */ 94 #define RTK_ANAR 0x0066 /* PHY autoneg advert */ 95 #define RTK_LPAR 0x0068 /* PHY link partner ability */ 96 #define RTK_ANER 0x006A /* PHY autoneg expansion */ 97 98 #define RTK_DISCCNT 0x006C /* disconnect counter */ 99 #define RTK_FALSECAR 0x006E /* false carrier counter */ 100 #define RTK_NWAYTST 0x0070 /* NWAY test register */ 101 #define RTK_RX_ER 0x0072 /* RX_ER counter */ 102 #define RTK_CSCFG 0x0074 /* CS configuration register */ 103 104 /* 105 * When operating in special C+ mode, some of the registers in an 106 * 8139C+ chip have different definitions. These are also used for 107 * the 8169 gigE chip. 108 */ 109 #define RTK_DUMPSTATS_LO 0x0010 /* counter dump command register */ 110 #define RTK_DUMPSTATS_HI 0x0014 /* counter dump command register */ 111 #define RTK_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 112 #define RTK_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 113 #define RTK_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte aligned */ 114 #define RTK_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte aligned */ 115 #define RTK_CFG2 0x0053 116 #define RTK_TIMERINT 0x0054 /* interrupt on timer expire */ 117 #define RTK_TXSTART 0x00D9 /* 8 bits */ 118 #define RTK_CPLUS_CMD 0x00E0 /* 16 bits */ 119 #define RTK_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 120 #define RTK_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 121 #define RTK_EARLY_TX_THRESH 0x00EC /* 8 bits */ 122 123 /* 124 * Registers specific to the 8169 gigE chip 125 */ 126 #define RTK_TIMERINT_8169 0x0058 /* different offset than 8139 */ 127 #define RTK_PHYAR 0x0060 128 #define RTK_TBICSR 0x0064 129 #define RTK_TBI_ANAR 0x0068 130 #define RTK_TBI_LPAR 0x006A 131 #define RTK_GMEDIASTAT 0x006C /* 8 bits */ 132 #define RTK_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 133 #define RTK_GTXSTART 0x0038 /* 16 bits */ 134 /* 135 * TX config register bits 136 */ 137 #define RTK_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 138 #define RTK_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 139 #define RTK_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 140 #define RTK_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 141 #define RTK_TXCFG_IFG2 0x00080000 /* 8169 only */ 142 #define RTK_TXCFG_IFG 0x03000000 /* interframe gap */ 143 #define RTK_TXCFG_HWREV 0x7CC00000 144 145 #define RTK_LOOPTEST_OFF 0x00000000 146 #define RTK_LOOPTEST_ON 0x00020000 147 #define RTK_LOOPTEST_ON_CPLUS 0x00060000 148 149 #define RTK_HWREV_8169 0x00000000 150 #define RTK_HWREV_8169S 0x04000000 151 #define RTK_HWREV_8110S 0x00800000 152 #define RTK_HWREV_8139 0x60000000 153 #define RTK_HWREV_8139A 0x70000000 154 #define RTK_HWREV_8139AG 0x70800000 155 #define RTK_HWREV_8139B 0x78000000 156 #define RTK_HWREV_8130 0x7C000000 157 #define RTK_HWREV_8139C 0x74000000 158 #define RTK_HWREV_8139D 0x74400000 159 #define RTK_HWREV_8139CPLUS 0x74800000 160 #define RTK_HWREV_8101 0x74c00000 161 #define RTK_HWREV_8100 0x78800000 162 163 #define RTK_TXDMA_16BYTES 0x00000000 164 #define RTK_TXDMA_32BYTES 0x00000100 165 #define RTK_TXDMA_64BYTES 0x00000200 166 #define RTK_TXDMA_128BYTES 0x00000300 167 #define RTK_TXDMA_256BYTES 0x00000400 168 #define RTK_TXDMA_512BYTES 0x00000500 169 #define RTK_TXDMA_1024BYTES 0x00000600 170 #define RTK_TXDMA_2048BYTES 0x00000700 171 172 /* 173 * Transmit descriptor status register bits. 174 */ 175 #define RTK_TXSTAT_LENMASK 0x00001FFF 176 #define RTK_TXSTAT_OWN 0x00002000 177 #define RTK_TXSTAT_TX_UNDERRUN 0x00004000 178 #define RTK_TXSTAT_TX_OK 0x00008000 179 #define RTK_TXSTAT_EARLY_THRESH 0x003F0000 180 #define RTK_TXSTAT_COLLCNT 0x0F000000 181 #define RTK_TXSTAT_CARR_HBEAT 0x10000000 182 #define RTK_TXSTAT_OUTOFWIN 0x20000000 183 #define RTK_TXSTAT_TXABRT 0x40000000 184 #define RTK_TXSTAT_CARRLOSS 0x80000000 185 186 /* 187 * Interrupt status register bits. 188 */ 189 #define RTK_ISR_RX_OK 0x0001 190 #define RTK_ISR_RX_ERR 0x0002 191 #define RTK_ISR_TX_OK 0x0004 192 #define RTK_ISR_TX_ERR 0x0008 193 #define RTK_ISR_RX_OVERRUN 0x0010 194 #define RTK_ISR_PKT_UNDERRUN 0x0020 195 #define RTK_ISR_LINKCHG 0x0020 /* 8169 only */ 196 #define RTK_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 197 #define RTK_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 198 #define RTK_ISR_SWI 0x0100 /* C+ only */ 199 #define RTK_ISR_CABLE_LEN_CHGD 0x2000 200 #define RTK_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 201 #define RTK_ISR_TIMEOUT_EXPIRED 0x4000 202 #define RTK_ISR_SYSTEM_ERR 0x8000 203 204 #define RTK_INTRS \ 205 (RTK_ISR_TX_OK|RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR| \ 206 RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \ 207 RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR) 208 209 #define RTK_INTRS_CPLUS \ 210 (RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR| \ 211 RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \ 212 RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR|RTK_ISR_TIMEOUT_EXPIRED) 213 214 215 /* 216 * Media status register. (8139 only) 217 */ 218 #define RTK_MEDIASTAT_RXPAUSE 0x01 219 #define RTK_MEDIASTAT_TXPAUSE 0x02 220 #define RTK_MEDIASTAT_LINK 0x04 221 #define RTK_MEDIASTAT_SPEED10 0x08 222 #define RTK_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 223 #define RTK_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 224 225 /* 226 * Receive config register. 227 */ 228 #define RTK_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 229 #define RTK_RXCFG_RX_INDIV 0x00000002 /* match filter */ 230 #define RTK_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 231 #define RTK_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 232 #define RTK_RXCFG_RX_RUNT 0x00000010 233 #define RTK_RXCFG_RX_ERRPKT 0x00000020 234 #define RTK_RXCFG_WRAP 0x00000080 235 #define RTK_RXCFG_MAXDMA 0x00000700 236 #define RTK_RXCFG_BUFSZ 0x00001800 237 #define RTK_RXCFG_FIFOTHRESH 0x0000E000 238 #define RTK_RXCFG_EARLYTHRESH 0x07000000 239 240 #define RTK_RXDMA_16BYTES 0x00000000 241 #define RTK_RXDMA_32BYTES 0x00000100 242 #define RTK_RXDMA_64BYTES 0x00000200 243 #define RTK_RXDMA_128BYTES 0x00000300 244 #define RTK_RXDMA_256BYTES 0x00000400 245 #define RTK_RXDMA_512BYTES 0x00000500 246 #define RTK_RXDMA_1024BYTES 0x00000600 247 #define RTK_RXDMA_UNLIMITED 0x00000700 248 249 #define RTK_RXBUF_8 0x00000000 250 #define RTK_RXBUF_16 0x00000800 251 #define RTK_RXBUF_32 0x00001000 252 #define RTK_RXBUF_64 0x00001800 253 254 #define RTK_RXFIFO_16BYTES 0x00000000 255 #define RTK_RXFIFO_32BYTES 0x00002000 256 #define RTK_RXFIFO_64BYTES 0x00004000 257 #define RTK_RXFIFO_128BYTES 0x00006000 258 #define RTK_RXFIFO_256BYTES 0x00008000 259 #define RTK_RXFIFO_512BYTES 0x0000A000 260 #define RTK_RXFIFO_1024BYTES 0x0000C000 261 #define RTK_RXFIFO_NOTHRESH 0x0000E000 262 263 /* 264 * Bits in RX status header (included with RX'ed packet 265 * in ring buffer). 266 */ 267 #define RTK_RXSTAT_RXOK 0x00000001 268 #define RTK_RXSTAT_ALIGNERR 0x00000002 269 #define RTK_RXSTAT_CRCERR 0x00000004 270 #define RTK_RXSTAT_GIANT 0x00000008 271 #define RTK_RXSTAT_RUNT 0x00000010 272 #define RTK_RXSTAT_BADSYM 0x00000020 273 #define RTK_RXSTAT_BROAD 0x00002000 274 #define RTK_RXSTAT_INDIV 0x00004000 275 #define RTK_RXSTAT_MULTI 0x00008000 276 #define RTK_RXSTAT_LENMASK 0xFFFF0000 277 278 #define RTK_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 279 /* 280 * Command register. 281 */ 282 #define RTK_CMD_EMPTY_RXBUF 0x0001 283 #define RTK_CMD_TX_ENB 0x0004 284 #define RTK_CMD_RX_ENB 0x0008 285 #define RTK_CMD_RESET 0x0010 286 287 /* 288 * EEPROM control register 289 */ 290 #define RTK_EE_DATAOUT 0x01 /* Data out */ 291 #define RTK_EE_DATAIN 0x02 /* Data in */ 292 #define RTK_EE_CLK 0x04 /* clock */ 293 #define RTK_EE_SEL 0x08 /* chip select */ 294 #define RTK_EE_MODE (0x40|0x80) 295 296 #define RTK_EEMODE_OFF 0x00 297 #define RTK_EEMODE_AUTOLOAD 0x40 298 #define RTK_EEMODE_PROGRAM 0x80 299 #define RTK_EEMODE_WRITECFG (0x80|0x40) 300 301 /* 9346/9356 EEPROM commands */ 302 #define RTK_EEADDR_LEN0 6 /* 9346 */ 303 #define RTK_EEADDR_LEN1 8 /* 9356 */ 304 #define RTK_EECMD_LEN 4 305 306 #define RTK_EECMD_WRITE 0x5 /* 0101b */ 307 #define RTK_EECMD_READ 0x6 /* 0110b */ 308 #define RTK_EECMD_ERASE 0x7 /* 0111b */ 309 310 #define RTK_EE_ID 0x00 311 #define RTK_EE_PCI_VID 0x01 312 #define RTK_EE_PCI_DID 0x02 313 /* Location of station address inside EEPROM */ 314 #define RTK_EE_EADDR0 0x07 315 #define RTK_EE_EADDR1 0x08 316 #define RTK_EE_EADDR2 0x09 317 318 /* 319 * MII register (8129 only) 320 */ 321 #define RTK_MII_CLK 0x01 322 #define RTK_MII_DATAIN 0x02 323 #define RTK_MII_DATAOUT 0x04 324 #define RTK_MII_DIR 0x80 /* 0 == input, 1 == output */ 325 326 /* 327 * Config 0 register 328 */ 329 #define RTK_CFG0_ROM0 0x01 330 #define RTK_CFG0_ROM1 0x02 331 #define RTK_CFG0_ROM2 0x04 332 #define RTK_CFG0_PL0 0x08 333 #define RTK_CFG0_PL1 0x10 334 #define RTK_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 335 #define RTK_CFG0_PCS 0x40 336 #define RTK_CFG0_SCR 0x80 337 338 /* 339 * Config 1 register 340 */ 341 #define RTK_CFG1_PWRDWN 0x01 342 #define RTK_CFG1_SLEEP 0x02 343 #define RTK_CFG1_IOMAP 0x04 344 #define RTK_CFG1_MEMMAP 0x08 345 #define RTK_CFG1_RSVD 0x10 346 #define RTK_CFG1_DRVLOAD 0x20 347 #define RTK_CFG1_LED0 0x40 348 #define RTK_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 349 #define RTK_CFG1_LED1 0x80 350 351 /* 352 * 8139C+ register definitions 353 */ 354 355 /* RTK_DUMPSTATS_LO register */ 356 357 #define RTK_DUMPSTATS_START 0x00000008 358 359 /* Transmit start register */ 360 361 #define RTK_TXSTART_SWI 0x01 /* generate TX interrupt */ 362 #define RTK_TXSTART_START 0x40 /* start normal queue transmit */ 363 #define RTK_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 364 365 /* 366 * Config 2 register, 8139C+/8169/8169S/8110S only 367 */ 368 #define RTK_CFG2_BUSFREQ 0x07 369 #define RTK_CFG2_BUSWIDTH 0x08 370 #define RTK_CFG2_AUXPWRSTS 0x10 371 372 #define RTK_BUSFREQ_33MHZ 0x00 373 #define RTK_BUSFREQ_66MHZ 0x01 374 375 #define RTK_BUSWIDTH_32BITS 0x00 376 #define RTK_BUSWIDTH_64BITS 0x08 377 378 /* C+ mode command register */ 379 380 #define RTK_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 381 #define RTK_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 382 #define RTK_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 383 #define RTK_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 384 #define RTK_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 385 #define RTK_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 386 387 /* C+ early transmit threshold */ 388 389 #define RTK_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 390 391 /* 392 * Gigabit PHY access register (8169 only) 393 */ 394 395 #define RTK_PHYAR_PHYDATA 0x0000FFFF 396 #define RTK_PHYAR_PHYREG 0x001F0000 397 #define RTK_PHYAR_BUSY 0x80000000 398 399 /* 400 * Gigabit media status (8169 only) 401 */ 402 #define RTK_GMEDIASTAT_FDX 0x01 /* full duplex */ 403 #define RTK_GMEDIASTAT_LINK 0x02 /* link up */ 404 #define RTK_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 405 #define RTK_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 406 #define RTK_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 407 #define RTK_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 408 #define RTK_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 409 #define RTK_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 410 411 /* 412 * The RealTek doesn't use a fragment-based descriptor mechanism. 413 * Instead, there are only four register sets, each or which represents 414 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 415 * packet buffer (32-bit aligned!) and we place the buffer addresses in 416 * the registers so the chip knows where they are. 417 * 418 * We can sort of kludge together the same kind of buffer management 419 * used in previous drivers, but we have to do buffer copies almost all 420 * the time, so it doesn't really buy us much. 421 * 422 * For reception, there's just one large buffer where the chip stores 423 * all received packets. 424 */ 425 426 #ifdef dreamcast 427 #define RTK_RX_BUF_SZ RTK_RXBUF_16 428 #else 429 #define RTK_RX_BUF_SZ RTK_RXBUF_64 430 #endif 431 #define RTK_RXBUFLEN (1 << ((RTK_RX_BUF_SZ >> 11) + 13)) 432 #define RTK_TX_LIST_CNT 4 433 #define RTK_TX_EARLYTHRESH ((256 / 32) << 16) 434 #define RTK_RX_FIFOTHRESH RTK_RXFIFO_256BYTES 435 #define RTK_RX_MAXDMA RTK_RXDMA_256BYTES 436 #define RTK_TX_MAXDMA RTK_TXDMA_256BYTES 437 438 #define RTK_RXCFG_CONFIG (RTK_RX_FIFOTHRESH|RTK_RX_MAXDMA|RTK_RX_BUF_SZ) 439 #define RTK_TXCFG_CONFIG (RTK_TXCFG_IFG|RTK_TX_MAXDMA) 440 441 442 /* 443 * The 8139C+ and 8160 gigE chips support descriptor-based TX 444 * and RX. In fact, they even support TCP large send. Descriptors 445 * must be allocated in contiguous blocks that are aligned on a 446 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 447 */ 448 449 /* 450 * RX/TX descriptor definition. When large send mode is enabled, the 451 * lower 11 bits of the TX rtk_cmd word are used to hold the MSS, and 452 * the checksum offload bits are disabled. The structure layout is 453 * the same for RX and TX descriptors 454 */ 455 456 struct rtk_desc { 457 u_int32_t rtk_cmdstat; 458 u_int32_t rtk_vlanctl; 459 u_int32_t rtk_bufaddr_lo; 460 u_int32_t rtk_bufaddr_hi; 461 }; 462 463 #define RTK_TDESC_CMD_FRAGLEN 0x0000FFFF 464 #define RTK_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 465 #define RTK_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 466 #define RTK_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 467 #define RTK_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 468 #define RTK_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 469 #define RTK_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 470 #define RTK_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 471 #define RTK_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 472 #define RTK_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 473 474 #define RTK_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 475 #define RTK_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 476 477 /* 478 * Error bits are valid only on the last descriptor of a frame 479 * (i.e. RTK_TDESC_CMD_EOF == 1) 480 */ 481 482 #define RTK_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 483 #define RTK_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 484 #define RTK_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 485 #define RTK_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 486 #define RTK_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 487 #define RTK_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 488 #define RTK_TDESC_STAT_OWN 0x80000000 489 490 /* 491 * RX descriptor cmd/vlan definitions 492 */ 493 494 #define RTK_RDESC_CMD_EOR 0x40000000 495 #define RTK_RDESC_CMD_OWN 0x80000000 496 #define RTK_RDESC_CMD_BUFLEN 0x00001FFF 497 498 #define RTK_RDESC_STAT_OWN 0x80000000 499 #define RTK_RDESC_STAT_EOR 0x40000000 500 #define RTK_RDESC_STAT_SOF 0x20000000 501 #define RTK_RDESC_STAT_EOF 0x10000000 502 #define RTK_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 503 #define RTK_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 504 #define RTK_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 505 #define RTK_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 506 #define RTK_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 507 #define RTK_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 508 #define RTK_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 509 #define RTK_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 510 #define RTK_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 511 #define RTK_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 512 #define RTK_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 513 #define RTK_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 514 #define RTK_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 515 #define RTK_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 516 #define RTK_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 517 #define RTK_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 518 519 #define RTK_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 520 (rtk_vlandata valid)*/ 521 #define RTK_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 522 523 #define RTK_PROTOID_NONIP 0x00000000 524 #define RTK_PROTOID_TCPIP 0x00010000 525 #define RTK_PROTOID_UDPIP 0x00020000 526 #define RTK_PROTOID_IP 0x00030000 527 #define RTK_TCPPKT(x) (((x) & RTK_RDESC_STAT_PROTOID) == \ 528 RTK_PROTOID_TCPIP) 529 #define RTK_UDPPKT(x) (((x) & RTK_RDESC_STAT_PROTOID) == \ 530 RTK_PROTOID_UDPIP) 531 532 /* 533 * Statistics counter structure (8139C+ and 8169 only) 534 */ 535 struct rtk_stats { 536 u_int32_t rtk_tx_pkts_lo; 537 u_int32_t rtk_tx_pkts_hi; 538 u_int32_t rtk_tx_errs_lo; 539 u_int32_t rtk_tx_errs_hi; 540 u_int32_t rtk_tx_errs; 541 u_int16_t rtk_missed_pkts; 542 u_int16_t rtk_rx_framealign_errs; 543 u_int32_t rtk_tx_onecoll; 544 u_int32_t rtk_tx_multicolls; 545 u_int32_t rtk_rx_ucasts_hi; 546 u_int32_t rtk_rx_ucasts_lo; 547 u_int32_t rtk_rx_bcasts_lo; 548 u_int32_t rtk_rx_bcasts_hi; 549 u_int32_t rtk_rx_mcasts; 550 u_int16_t rtk_tx_aborts; 551 u_int16_t rtk_rx_underruns; 552 }; 553 554 #define RTK_RX_DESC_CNT 64 555 #define RTK_TX_DESC_CNT 64 556 #define RTK_RX_LIST_SZ (RTK_RX_DESC_CNT * sizeof(struct rtk_desc)) 557 #define RTK_TX_LIST_SZ (RTK_TX_DESC_CNT * sizeof(struct rtk_desc)) 558 #define RTK_RING_ALIGN 256 559 #define RTK_IFQ_MAXLEN 512 560 #define RTK_DESC_INC(x) (x = (x + 1) % RTK_TX_DESC_CNT) 561 #define RTK_OWN(x) (le32toh((x)->rtk_cmdstat) & RTK_RDESC_STAT_OWN) 562 #define RTK_RXBYTES(x) (le32toh((x)->rtk_cmdstat) & sc->rtk_rxlenmask) 563 #define RTK_PKTSZ(x) ((x)/* >> 3*/) 564 565 #define RTK_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 566 #define RTK_ADDR_HI(y) ((u_int64_t) (y) >> 32) 567 568 #define RTK_JUMBO_FRAMELEN 9018 569 #define RTK_JUMBO_MTU (RTK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 570
Indexes created Sun Sep 28 07:09:56 GMT 2025