rtl81x9var.h revision 1.15
1 /* $NetBSD: rtl81x9var.h,v 1.15 2005/01/09 12:25:25 kanaoka Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp 35 */ 36 37 #define RTK_ETHER_ALIGN 2 38 #define RTK_RXSTAT_LEN 4 39 40 struct rtk_type { 41 u_int16_t rtk_vid; 42 u_int16_t rtk_did; 43 int rtk_basetype; 44 const char *rtk_name; 45 }; 46 47 struct rtk_hwrev { 48 uint32_t rtk_rev; 49 int rtk_type; 50 char *rtk_desc; 51 }; 52 53 struct rtk_mii_frame { 54 u_int8_t mii_stdelim; 55 u_int8_t mii_opcode; 56 u_int8_t mii_phyaddr; 57 u_int8_t mii_regaddr; 58 u_int8_t mii_turnaround; 59 u_int16_t mii_data; 60 }; 61 62 /* 63 * MII constants 64 */ 65 #define RTK_MII_STARTDELIM 0x01 66 #define RTK_MII_READOP 0x02 67 #define RTK_MII_WRITEOP 0x01 68 #define RTK_MII_TURNAROUND 0x02 69 70 #define RTK_8129 1 71 #define RTK_8139 2 72 #define RTK_8139CPLUS 3 73 #define RTK_8169 4 74 75 #define RTK_ISCPLUS(x) ((x)->rtk_type == RTK_8139CPLUS || \ 76 (x)->rtk_type == RTK_8169) 77 78 /* 79 * The 8139C+ and 8160 gigE chips support descriptor-based TX 80 * and RX. In fact, they even support TCP large send. Descriptors 81 * must be allocated in contiguous blocks that are aligned on a 82 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 83 */ 84 85 struct rtk_list_data { 86 struct mbuf *rtk_tx_mbuf[RTK_TX_DESC_CNT]; 87 struct mbuf *rtk_rx_mbuf[RTK_RX_DESC_CNT]; 88 int rtk_tx_prodidx; 89 int rtk_rx_prodidx; 90 int rtk_tx_considx; 91 int rtk_tx_free; 92 bus_dmamap_t rtk_tx_dmamap[RTK_TX_DESC_CNT]; 93 bus_dmamap_t rtk_rx_dmamap[RTK_RX_DESC_CNT]; 94 bus_dmamap_t rtk_rx_list_map; 95 struct rtk_desc *rtk_rx_list; 96 bus_dma_segment_t rtk_rx_listseg; 97 int rtk_rx_listnseg; 98 bus_dmamap_t rtk_tx_list_map; 99 struct rtk_desc *rtk_tx_list; 100 bus_dma_segment_t rtk_tx_listseg; 101 int rtk_tx_listnseg; 102 }; 103 struct rtk_tx_desc { 104 SIMPLEQ_ENTRY(rtk_tx_desc) txd_q; 105 struct mbuf *txd_mbuf; 106 bus_dmamap_t txd_dmamap; 107 bus_addr_t txd_txaddr; 108 bus_addr_t txd_txstat; 109 }; 110 111 struct rtk_softc { 112 struct device sc_dev; /* generic device structures */ 113 struct ethercom ethercom; /* interface info */ 114 struct mii_data mii; 115 struct callout rtk_tick_ch; /* tick callout */ 116 bus_space_handle_t rtk_bhandle; /* bus space handle */ 117 bus_space_tag_t rtk_btag; /* bus space tag */ 118 int rtk_type; 119 bus_dma_tag_t sc_dmat; 120 bus_dma_segment_t sc_dmaseg; 121 int sc_dmanseg; 122 123 bus_dmamap_t recv_dmamap; 124 caddr_t rtk_rx_buf; 125 126 struct rtk_tx_desc rtk_tx_descs[RTK_TX_LIST_CNT]; 127 SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_free; 128 SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_dirty; 129 struct rtk_list_data rtk_ldata; 130 struct mbuf *rtk_head; 131 struct mbuf *rtk_tail; 132 u_int32_t rtk_rxlenmask; 133 int rtk_testmode; 134 135 int sc_flags; /* misc flags */ 136 int sc_txthresh; /* Early tx threshold */ 137 int sc_rev; /* revision within rtk_type */ 138 139 void *sc_sdhook; /* shutdown hook */ 140 void *sc_powerhook; /* power management hook */ 141 142 /* Power management hooks. */ 143 int (*sc_enable) __P((struct rtk_softc *)); 144 void (*sc_disable) __P((struct rtk_softc *)); 145 void (*sc_power) __P((struct rtk_softc *, int)); 146 }; 147 148 #define RTK_ATTACHED 0x00000001 /* attach has succeeded */ 149 #define RTK_ENABLED 0x00000002 /* chip is enabled */ 150 151 #define RTK_IS_ENABLED(sc) ((sc)->sc_flags & RTK_ENABLED) 152 #define RTK_TX_THRESH(sc) (((sc)->sc_txthresh << 16) & 0x003F0000) 153 154 #define TXTH_256 8 155 #define TXTH_MAX 48 156 157 /* 158 * register space access macros 159 */ 160 #define CSR_WRITE_4(sc, reg, val) \ 161 bus_space_write_4(sc->rtk_btag, sc->rtk_bhandle, reg, val) 162 #define CSR_WRITE_2(sc, reg, val) \ 163 bus_space_write_2(sc->rtk_btag, sc->rtk_bhandle, reg, val) 164 #define CSR_WRITE_1(sc, reg, val) \ 165 bus_space_write_1(sc->rtk_btag, sc->rtk_bhandle, reg, val) 166 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 167 bus_space_write_stream_4(sc->rtk_btag, sc->rtk_bhandle, reg, val) 168 169 170 #define CSR_READ_4(sc, reg) \ 171 bus_space_read_4(sc->rtk_btag, sc->rtk_bhandle, reg) 172 #define CSR_READ_2(sc, reg) \ 173 bus_space_read_2(sc->rtk_btag, sc->rtk_bhandle, reg) 174 #define CSR_READ_1(sc, reg) \ 175 bus_space_read_1(sc->rtk_btag, sc->rtk_bhandle, reg) 176 177 #define RTK_TIMEOUT 1000 178 179 /* 180 * PCI low memory base and low I/O base register, and 181 * other PCI registers. 182 */ 183 184 #define RTK_PCI_LOIO 0x10 185 #define RTK_PCI_LOMEM 0x14 186 187 #define RTK_PSTATE_MASK 0x0003 188 #define RTK_PSTATE_D0 0x0000 189 #define RTK_PSTATE_D1 0x0002 190 #define RTK_PSTATE_D2 0x0002 191 #define RTK_PSTATE_D3 0x0003 192 #define RTK_PME_EN 0x0010 193 #define RTK_PME_STATUS 0x8000 194 195 #ifdef _KERNEL 196 u_int16_t rtk_read_eeprom __P((struct rtk_softc *, int, int)); 197 void rtk_setmulti __P((struct rtk_softc *)); 198 void rtk_attach __P((struct rtk_softc *)); 199 int rtk_detach __P((struct rtk_softc *)); 200 int rtk_activate __P((struct device *, enum devact)); 201 int rtk_intr __P((void *)); 202 #endif /* _KERNEL */ 203
Indexes created Mon Sep 29 21:09:56 GMT 2025