rtl81x9var.h revision 1.18
1 /* $NetBSD: rtl81x9var.h,v 1.18 2005/03/23 20:23:08 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp 35 */ 36 37 #include "rnd.h" 38 39 #if NRND > 0 40 #include <sys/rnd.h> 41 #endif 42 43 #define RTK_ETHER_ALIGN 2 44 #define RTK_RXSTAT_LEN 4 45 46 struct rtk_type { 47 u_int16_t rtk_vid; 48 u_int16_t rtk_did; 49 int rtk_basetype; 50 const char *rtk_name; 51 }; 52 53 struct rtk_hwrev { 54 uint32_t rtk_rev; 55 int rtk_type; 56 char *rtk_desc; 57 }; 58 59 struct rtk_mii_frame { 60 u_int8_t mii_stdelim; 61 u_int8_t mii_opcode; 62 u_int8_t mii_phyaddr; 63 u_int8_t mii_regaddr; 64 u_int8_t mii_turnaround; 65 u_int16_t mii_data; 66 }; 67 68 /* 69 * MII constants 70 */ 71 #define RTK_MII_STARTDELIM 0x01 72 #define RTK_MII_READOP 0x02 73 #define RTK_MII_WRITEOP 0x01 74 #define RTK_MII_TURNAROUND 0x02 75 76 #define RTK_8129 1 77 #define RTK_8139 2 78 #define RTK_8139CPLUS 3 79 #define RTK_8169 4 80 81 #define RTK_ISCPLUS(x) ((x)->rtk_type == RTK_8139CPLUS || \ 82 (x)->rtk_type == RTK_8169) 83 84 #define RTK_TX_QLEN 64 85 86 /* 87 * The 8139C+ and 8160 gigE chips support descriptor-based TX 88 * and RX. In fact, they even support TCP large send. Descriptors 89 * must be allocated in contiguous blocks that are aligned on a 90 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 91 */ 92 93 struct rtk_list_data { 94 struct rtk_txq { 95 struct mbuf *txq_mbuf; 96 bus_dmamap_t txq_dmamap; 97 int txq_descidx; 98 } rtk_txq[RTK_TX_QLEN]; 99 int rtk_txq_considx; 100 int rtk_txq_prodidx; 101 bus_dmamap_t rtk_tx_list_map; 102 struct rtk_desc *rtk_tx_list; 103 bus_dma_segment_t rtk_tx_listseg; 104 int rtk_tx_free; /* # of free descriptors */ 105 int rtk_tx_nextfree; /* next descriptor to use */ 106 int rtk_tx_desc_cnt; /* # of descriptors */ 107 int rtk_tx_listnseg; 108 109 struct mbuf *rtk_rx_mbuf[RTK_RX_DESC_CNT]; 110 bus_dmamap_t rtk_rx_dmamap[RTK_RX_DESC_CNT]; 111 bus_dmamap_t rtk_rx_list_map; 112 struct rtk_desc *rtk_rx_list; 113 bus_dma_segment_t rtk_rx_listseg; 114 int rtk_rx_prodidx; 115 int rtk_rx_listnseg; 116 }; 117 struct rtk_tx_desc { 118 SIMPLEQ_ENTRY(rtk_tx_desc) txd_q; 119 struct mbuf *txd_mbuf; 120 bus_dmamap_t txd_dmamap; 121 bus_addr_t txd_txaddr; 122 bus_addr_t txd_txstat; 123 }; 124 125 struct rtk_softc { 126 struct device sc_dev; /* generic device structures */ 127 struct ethercom ethercom; /* interface info */ 128 struct mii_data mii; 129 struct callout rtk_tick_ch; /* tick callout */ 130 bus_space_handle_t rtk_bhandle; /* bus space handle */ 131 bus_space_tag_t rtk_btag; /* bus space tag */ 132 int rtk_type; 133 bus_dma_tag_t sc_dmat; 134 bus_dma_segment_t sc_dmaseg; 135 int sc_dmanseg; 136 137 bus_dmamap_t recv_dmamap; 138 caddr_t rtk_rx_buf; 139 140 struct rtk_tx_desc rtk_tx_descs[RTK_TX_LIST_CNT]; 141 SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_free; 142 SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_dirty; 143 struct rtk_list_data rtk_ldata; 144 struct mbuf *rtk_head; 145 struct mbuf *rtk_tail; 146 u_int32_t rtk_rxlenmask; 147 int rtk_testmode; 148 149 int sc_flags; /* misc flags */ 150 int sc_txthresh; /* Early tx threshold */ 151 int sc_rev; /* revision within rtk_type */ 152 153 void *sc_sdhook; /* shutdown hook */ 154 void *sc_powerhook; /* power management hook */ 155 156 /* Power management hooks. */ 157 int (*sc_enable) (struct rtk_softc *); 158 void (*sc_disable) (struct rtk_softc *); 159 void (*sc_power) (struct rtk_softc *, int); 160 #if NRND > 0 161 rndsource_element_t rnd_source; 162 #endif 163 }; 164 165 #define RTK_TX_DESC_CNT(sc) \ 166 ((sc)->rtk_ldata.rtk_tx_desc_cnt) 167 #define RTK_TX_LIST_SZ(sc) \ 168 (RTK_TX_DESC_CNT(sc) * sizeof(struct rtk_desc)) 169 #define RTK_TX_DESC_INC(sc, x) \ 170 ((x) = ((x) + 1) % RTK_TX_DESC_CNT(sc)) 171 #define RTK_RX_DESC_INC(sc, x) \ 172 ((x) = ((x) + 1) % RTK_RX_DESC_CNT) 173 174 #define RTK_ATTACHED 0x00000001 /* attach has succeeded */ 175 #define RTK_ENABLED 0x00000002 /* chip is enabled */ 176 177 #define RTK_IS_ENABLED(sc) ((sc)->sc_flags & RTK_ENABLED) 178 #define RTK_TX_THRESH(sc) (((sc)->sc_txthresh << 16) & 0x003F0000) 179 180 #define TXTH_256 8 181 #define TXTH_MAX 48 182 183 /* 184 * register space access macros 185 */ 186 #define CSR_WRITE_4(sc, reg, val) \ 187 bus_space_write_4(sc->rtk_btag, sc->rtk_bhandle, reg, val) 188 #define CSR_WRITE_2(sc, reg, val) \ 189 bus_space_write_2(sc->rtk_btag, sc->rtk_bhandle, reg, val) 190 #define CSR_WRITE_1(sc, reg, val) \ 191 bus_space_write_1(sc->rtk_btag, sc->rtk_bhandle, reg, val) 192 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 193 bus_space_write_stream_4(sc->rtk_btag, sc->rtk_bhandle, reg, val) 194 195 196 #define CSR_READ_4(sc, reg) \ 197 bus_space_read_4(sc->rtk_btag, sc->rtk_bhandle, reg) 198 #define CSR_READ_2(sc, reg) \ 199 bus_space_read_2(sc->rtk_btag, sc->rtk_bhandle, reg) 200 #define CSR_READ_1(sc, reg) \ 201 bus_space_read_1(sc->rtk_btag, sc->rtk_bhandle, reg) 202 203 #define RTK_TIMEOUT 1000 204 205 /* 206 * PCI low memory base and low I/O base register, and 207 * other PCI registers. 208 */ 209 210 #define RTK_PCI_LOIO 0x10 211 #define RTK_PCI_LOMEM 0x14 212 213 #define RTK_PSTATE_MASK 0x0003 214 #define RTK_PSTATE_D0 0x0000 215 #define RTK_PSTATE_D1 0x0002 216 #define RTK_PSTATE_D2 0x0002 217 #define RTK_PSTATE_D3 0x0003 218 #define RTK_PME_EN 0x0010 219 #define RTK_PME_STATUS 0x8000 220 221 #ifdef _KERNEL 222 u_int16_t rtk_read_eeprom(struct rtk_softc *, int, int); 223 void rtk_setmulti(struct rtk_softc *); 224 void rtk_attach(struct rtk_softc *); 225 int rtk_detach(struct rtk_softc *); 226 int rtk_activate(struct device *, enum devact); 227 int rtk_intr(void *); 228 #endif /* _KERNEL */ 229
Indexes created Sat Sep 27 14:09:57 GMT 2025